xref: /netbsd-src/sys/arch/arm/nxp/imx6_pcie.c (revision a33a6c43803dc8b884b646dc14983a964a1581b3)
1 /*	$NetBSD: imx6_pcie.c,v 1.7 2023/05/04 13:29:33 bouyer Exp $	*/
2 
3 /*-
4  * Copyright (c) 2019 Genetec Corporation.  All rights reserved.
5  * Written by Hashimoto Kenichi for Genetec Corporation.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.7 2023/05/04 13:29:33 bouyer Exp $");
31 
32 #include "opt_pci.h"
33 #include "opt_fdt.h"
34 
35 #include "pci.h"
36 #include "locators.h"
37 
38 #define	_INTR_PRIVATE
39 
40 #include <sys/bus.h>
41 #include <sys/device.h>
42 #include <sys/intr.h>
43 #include <sys/systm.h>
44 #include <sys/param.h>
45 #include <sys/kernel.h>
46 #include <sys/queue.h>
47 #include <sys/mutex.h>
48 #include <sys/kmem.h>
49 #include <sys/gpio.h>
50 
51 #include <machine/frame.h>
52 #include <arm/cpufunc.h>
53 
54 #include <dev/fdt/fdtvar.h>
55 
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pciconf.h>
59 
60 #include <arm/imx/imxpcievar.h>
61 #include <arm/imx/imxgpioreg.h>
62 #include <arm/imx/imxgpiovar.h>
63 #include <arm/nxp/imx6_iomuxreg.h>
64 #include <arm/nxp/imx6_ccmreg.h>
65 #include <arm/nxp/imx6_ccmvar.h>
66 
67 struct imxpcie_fdt_softc {
68 	struct imxpcie_softc sc_imxpcie;
69 
70 	struct fdtbus_gpio_pin	*sc_pin_reset;
71 	struct fdtbus_regulator	*sc_reg_vpcie;
72 };
73 
74 static int imx6_pcie_match(device_t, cfdata_t, void *);
75 static void imx6_pcie_attach(device_t, device_t, void *);
76 
77 static void imx6_pcie_configure(void *);
78 static uint32_t imx6_pcie_gpr_read(void *, uint32_t);
79 static void imx6_pcie_gpr_write(void *, uint32_t, uint32_t);
80 static void imx6_pcie_reset(void *);
81 
82 #define IMX6_PCIE_MEM_BASE	0x01000000
83 #define IMX6_PCIE_MEM_SIZE	0x00f00000 /* 15MB */
84 #define IMX6_PCIE_ROOT_BASE	0x01f00000
85 #define IMX6_PCIE_ROOT_SIZE	0x00080000 /* 512KB */
86 #define IMX6_PCIE_IO_BASE	0x01f80000
87 #define IMX6_PCIE_IO_SIZE	0x00010000 /* 64KB */
88 
89 CFATTACH_DECL_NEW(imxpcie_fdt, sizeof(struct imxpcie_fdt_softc),
90     imx6_pcie_match, imx6_pcie_attach, NULL, NULL);
91 
92 static const struct device_compatible_entry compat_data[] = {
93 	{ .compat = "fsl,imx6q-pcie",	.value = false },
94 	{ .compat = "fsl,imx6qp-pcie",	.value = true },
95 	{ .compat = "fsl,imx6sx-pcie",	.value = true },
96 	DEVICE_COMPAT_EOL
97 };
98 
99 static int
imx6_pcie_match(device_t parent,cfdata_t cf,void * aux)100 imx6_pcie_match(device_t parent, cfdata_t cf, void *aux)
101 {
102 	struct fdt_attach_args * const faa = aux;
103 
104 	return of_compatible_match(faa->faa_phandle, compat_data);
105 }
106 
107 static void
imx6_pcie_attach(device_t parent,device_t self,void * aux)108 imx6_pcie_attach(device_t parent, device_t self, void *aux)
109 {
110 	struct imxpcie_fdt_softc * const ifsc = device_private(self);
111 	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
112 	struct fdt_attach_args * const faa = aux;
113 	const int phandle = faa->faa_phandle;
114 	bus_space_tag_t bst = faa->faa_bst;
115 	char intrstr[128];
116 	bus_addr_t addr;
117 	bus_size_t size;
118 
119 	aprint_naive("\n");
120 	aprint_normal(": PCI Express Controller\n");
121 
122 	sc->sc_dev = self;
123 	sc->sc_iot = bst;
124 	sc->sc_dmat = faa->faa_dmat;
125 	sc->sc_cookie = ifsc;
126 	sc->sc_pci_netbsd_configure = imx6_pcie_configure;
127 	sc->sc_gpr_read = imx6_pcie_gpr_read;
128 	sc->sc_gpr_write = imx6_pcie_gpr_write;
129 	sc->sc_reset = imx6_pcie_reset;
130 	sc->sc_have_sw_reset =
131 	    (bool)of_compatible_lookup(phandle, compat_data)->value;
132 
133 	if (fdtbus_get_reg_byname(phandle, "dbi", &addr, &size) != 0) {
134 		aprint_error(": couldn't get registers\n");
135 		return;
136 	}
137 	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) {
138 		aprint_error_dev(self, "Cannot map registers\n");
139 		return;
140 	}
141 	if (fdtbus_get_reg_byname(phandle, "config", &addr, &size) != 0) {
142 		aprint_error(": couldn't get registers\n");
143 		return;
144 	}
145 	sc->sc_root_addr = addr;
146 	sc->sc_root_size = size;
147 
148 	const int gpr_phandle = OF_finddevice("/soc/aips-bus/iomuxc-gpr");
149 	fdtbus_get_reg(gpr_phandle, 0, &addr, &size);
150 	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_gpr_ioh)) {
151 		aprint_error_dev(self, "Cannot map registers\n");
152 		return;
153 	}
154 
155 	ifsc->sc_pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpio",
156 	    GPIO_PIN_OUTPUT);
157 	if (!ifsc->sc_pin_reset) {
158 		aprint_error(": couldn't acquire reset gpio\n");
159 		return;
160 	}
161 
162 	sc->sc_clk_pcie = fdtbus_clock_get(phandle, "pcie");
163 	if (sc->sc_clk_pcie == NULL) {
164 		aprint_error(": couldn't get clock pcie_axi\n");
165 		return;
166 	}
167 	sc->sc_clk_pcie_bus = fdtbus_clock_get(phandle, "pcie_bus");
168 	if (sc->sc_clk_pcie_bus == NULL) {
169 		aprint_error(": couldn't get clock lvds1_gate\n");
170 		return;
171 	}
172 	sc->sc_clk_pcie_phy = fdtbus_clock_get(phandle, "pcie_phy");
173 	if (sc->sc_clk_pcie_phy == NULL) {
174 		aprint_error(": couldn't get clock pcie_ref\n");
175 		return;
176 	}
177 
178 	if (of_hasprop(phandle, "vpcie-supply")) {
179 		ifsc->sc_reg_vpcie = fdtbus_regulator_acquire(phandle, "vpcie-supply");
180 		if (ifsc->sc_reg_vpcie == NULL) {
181 			aprint_error(": couldn't acquire regulator\n");
182 			return;
183 		}
184 		aprint_normal_dev(self, "regulator On\n");
185 		fdtbus_regulator_enable(ifsc->sc_reg_vpcie);
186 	}
187 
188 	if (of_hasprop(phandle, "ext_osc")) {
189 		aprint_normal_dev(self, "Use external OSC\n");
190 		sc->sc_ext_osc = true;
191 
192 		sc->sc_clk_pcie_ext = fdtbus_clock_get(phandle, "pcie_ext");
193 		if (sc->sc_clk_pcie_ext == NULL) {
194 			aprint_error(": couldn't get clock pcie_ext\n");
195 			return;
196 		}
197 		sc->sc_clk_pcie_ext_src = fdtbus_clock_get(phandle, "pcie_ext_src");
198 		if (sc->sc_clk_pcie_ext_src == NULL) {
199 			aprint_error(": couldn't get clock pcie_ext_src\n");
200 			return;
201 		}
202 	} else {
203 		sc->sc_ext_osc = false;
204 		sc->sc_clk_pcie_ext = NULL;
205 		sc->sc_clk_pcie_ext_src = NULL;
206 	}
207 
208 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
209 		aprint_error_dev(self, "failed to decode interrupt\n");
210 		return;
211 	}
212 
213 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
214 	    FDT_INTR_MPSAFE, imxpcie_intr, sc, device_xname(self));
215 	if (sc->sc_ih == NULL) {
216 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
217 		    intrstr);
218 		return;
219 	}
220 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
221 
222 	imxpcie_attach_common(sc);
223 }
224 
225 static void
imx6_pcie_configure(void * cookie)226 imx6_pcie_configure(void *cookie)
227 {
228 	struct imxpcie_fdt_softc * const ifsc = cookie;
229 	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
230 
231 #ifdef PCI_NETBSD_CONFIGURE
232 	struct pciconf_resources *pcires = pciconf_resource_init();
233 
234 	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
235 	    IMX6_PCIE_IO_BASE, IMX6_PCIE_IO_SIZE);
236 	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
237 	    IMX6_PCIE_MEM_BASE, IMX6_PCIE_MEM_SIZE);
238 
239 	int error = pci_configure_bus(&sc->sc_pc, pcires, 0, arm_dcache_align);
240 
241 	pciconf_resource_fini(pcires);
242 
243 	if (error) {
244 		aprint_error_dev(sc->sc_dev, "configuration failed (%d)\n",
245 		    error);
246 	}
247 #endif
248 }
249 
250 static uint32_t
imx6_pcie_gpr_read(void * cookie,uint32_t reg)251 imx6_pcie_gpr_read(void *cookie, uint32_t reg)
252 {
253 	struct imxpcie_fdt_softc * const ifsc = cookie;
254 	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
255 	return bus_space_read_4(sc->sc_iot, sc->sc_gpr_ioh, reg);
256 }
257 
258 static void
imx6_pcie_gpr_write(void * cookie,uint32_t reg,uint32_t val)259 imx6_pcie_gpr_write(void *cookie, uint32_t reg, uint32_t val)
260 {
261 	struct imxpcie_fdt_softc * const ifsc = cookie;
262 	struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
263 	bus_space_write_4(sc->sc_iot, sc->sc_gpr_ioh, reg, val);
264 }
265 
266 static void
imx6_pcie_reset(void * cookie)267 imx6_pcie_reset(void *cookie)
268 {
269 	struct imxpcie_fdt_softc * const ifsc = cookie;
270 
271 	fdtbus_gpio_write(ifsc->sc_pin_reset, 1);
272 	delay(20 * 1000);
273 	fdtbus_gpio_write(ifsc->sc_pin_reset, 0);
274 }
275