1 /* $NetBSD: imxwdog.c,v 1.3 2014/09/25 05:05:28 ryo Exp $ */
2
3 /*
4 * Copyright (c) 2010 Genetec Corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: imxwdog.c,v 1.3 2014/09/25 05:05:28 ryo Exp $");
31
32 #include "opt_imx.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/cpu.h>
37 #include <sys/device.h>
38 #include <sys/wdog.h>
39
40 #include <prop/proplib.h>
41
42 #include <dev/sysmon/sysmonvar.h>
43
44 #include <arm/imx/imxwdogreg.h>
45 #include <arm/imx/imxwdogvar.h>
46
47 struct wdog_softc {
48 struct sysmon_wdog sc_smw;
49 device_t sc_dev;
50 bus_space_tag_t sc_iot;
51 bus_space_handle_t sc_ioh;
52
53 u_int sc_wdog_max_period;
54 u_int sc_wdog_period;
55 bool sc_wdog_armed;
56 };
57
58 #ifndef IMXWDOG_PERIOD_DEFAULT
59 #define IMXWDOG_PERIOD_DEFAULT 10
60 #endif
61
62 CFATTACH_DECL_NEW(imxwdog, sizeof(struct wdog_softc),
63 wdog_match, wdog_attach, NULL, NULL);
64
65 static inline uint16_t
wdog_read(struct wdog_softc * sc,bus_size_t o)66 wdog_read(struct wdog_softc *sc, bus_size_t o)
67 {
68 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, o);
69 }
70
71 static inline void
wdog_write(struct wdog_softc * sc,bus_size_t o,uint16_t v)72 wdog_write(struct wdog_softc *sc, bus_size_t o, uint16_t v)
73 {
74 bus_space_write_2(sc->sc_iot, sc->sc_ioh, o, v);
75 }
76
77 static int
wdog_tickle(struct sysmon_wdog * smw)78 wdog_tickle(struct sysmon_wdog *smw)
79 {
80 struct wdog_softc * const sc = smw->smw_cookie;
81
82 wdog_write(sc, IMX_WDOG_WSR, WSR_MAGIC1);
83 wdog_write(sc, IMX_WDOG_WSR, WSR_MAGIC2);
84
85 return 0;
86 }
87
88 static int
wdog_setmode(struct sysmon_wdog * smw)89 wdog_setmode(struct sysmon_wdog *smw)
90 {
91 struct wdog_softc * const sc = smw->smw_cookie;
92 uint16_t reg;
93
94 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
95 /* this chip do not support wdt disable */
96 aprint_debug_dev(sc->sc_dev, "setmode disable\n");
97 return sc->sc_wdog_armed ? EBUSY : 0;
98 }
99
100 /*
101 * If no changes, just tickle it and return.
102 */
103 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
104 wdog_tickle(smw);
105 aprint_debug_dev(sc->sc_dev, "setmode refresh\n");
106 return 0;
107 }
108
109 /* set default */
110 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
111 sc->sc_wdog_period = IMXWDOG_PERIOD_DEFAULT;
112 smw->smw_period = IMXWDOG_PERIOD_DEFAULT;
113 }
114
115 /*
116 * Make sure we don't overflow the counter.
117 */
118 if (smw->smw_period >= sc->sc_wdog_max_period)
119 return EINVAL;
120
121 sc->sc_wdog_period = smw->smw_period;
122 sc->sc_wdog_armed = true;
123
124 reg = wdog_read(sc, IMX_WDOG_WCR);
125 reg &= ~WCR_WT;
126 reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);
127 reg |= WCR_WDE;
128 wdog_write(sc, IMX_WDOG_WCR, reg);
129
130 return 0;
131 }
132
133 void
wdog_attach_common(device_t parent,device_t self,bus_space_tag_t iot,paddr_t addr,size_t size,int irq)134 wdog_attach_common(device_t parent, device_t self,
135 bus_space_tag_t iot, paddr_t addr, size_t size, int irq)
136 {
137 struct wdog_softc *sc = device_private(self);
138 uint16_t reg;
139
140 sc->sc_dev = self;
141 sc->sc_iot = iot;
142 if (bus_space_map(iot, addr, size, 0, &sc->sc_ioh)) {
143 aprint_error_dev(self, "can't map\n");
144 return;
145 }
146
147 sc->sc_wdog_armed = __SHIFTOUT(wdog_read(sc, IMX_WDOG_WCR), WCR_WDE);
148 /*
149 * Does the config file tell us to turn on the watchdog?
150 */
151 if (device_cfdata(self)->cf_flags & 1)
152 sc->sc_wdog_armed = true;
153
154 sc->sc_wdog_max_period = 0xff / 2;
155 sc->sc_wdog_period = IMXWDOG_PERIOD_DEFAULT;
156
157 reg = wdog_read(sc, IMX_WDOG_WCR);
158 reg &= ~WCR_WT;
159 reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);
160 wdog_write(sc, IMX_WDOG_WCR, reg);
161
162 aprint_naive("\n");
163 aprint_normal(": i.MX Watchdog Timer, default period is %u seconds%s\n",
164 sc->sc_wdog_period,
165 sc->sc_wdog_armed ? " (armed)" : "");
166
167 sc->sc_smw.smw_name = device_xname(self);
168 sc->sc_smw.smw_cookie = sc;
169 sc->sc_smw.smw_setmode = wdog_setmode;
170 sc->sc_smw.smw_tickle = wdog_tickle;
171 sc->sc_smw.smw_period = sc->sc_wdog_period;
172
173 if (sysmon_wdog_register(&sc->sc_smw) != 0)
174 aprint_error_dev(self, "unable to register with sysmon\n");
175
176 if (sc->sc_wdog_armed) {
177 int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
178 sc->sc_wdog_period);
179 if (error)
180 aprint_error_dev(self,
181 "failed to start kernel tickler: %d\n", error);
182 else {
183 reg = wdog_read(sc, IMX_WDOG_WCR);
184 reg |= WCR_WDE;
185 wdog_write(sc, IMX_WDOG_WCR, reg);
186 }
187 }
188 }
189