xref: /netbsd-src/sys/arch/arm/imx/imx51_ipuv3.c (revision c7fb772b85b2b5d4cfb282f868f454b4701534fd)
1*c7fb772bSthorpej /*	$NetBSD: imx51_ipuv3.c,v 1.11 2021/08/07 16:18:44 thorpej Exp $	*/
2456cfa81Sbsh 
3456cfa81Sbsh /*
4456cfa81Sbsh  * Copyright (c) 2011, 2012  Genetec Corporation.  All rights reserved.
5456cfa81Sbsh  * Written by Hashimoto Kenichi for Genetec Corporation.
6456cfa81Sbsh  *
7456cfa81Sbsh  * Redistribution and use in source and binary forms, with or without
8456cfa81Sbsh  * modification, are permitted provided that the following conditions
9456cfa81Sbsh  * are met:
10456cfa81Sbsh  * 1. Redistributions of source code must retain the above copyright
11456cfa81Sbsh  *    notice, this list of conditions and the following disclaimer.
12456cfa81Sbsh  * 2. Redistributions in binary form must reproduce the above copyright
13456cfa81Sbsh  *    notice, this list of conditions and the following disclaimer in the
14456cfa81Sbsh  *    documentation and/or other materials provided with the distribution.
15456cfa81Sbsh  *
16456cfa81Sbsh  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17456cfa81Sbsh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18456cfa81Sbsh  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19456cfa81Sbsh  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
20456cfa81Sbsh  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21456cfa81Sbsh  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22456cfa81Sbsh  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23456cfa81Sbsh  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24456cfa81Sbsh  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25456cfa81Sbsh  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26456cfa81Sbsh  * POSSIBILITY OF SUCH DAMAGE.
27456cfa81Sbsh  */
28456cfa81Sbsh 
29456cfa81Sbsh #include <sys/cdefs.h>
30*c7fb772bSthorpej __KERNEL_RCSID(0, "$NetBSD: imx51_ipuv3.c,v 1.11 2021/08/07 16:18:44 thorpej Exp $");
317bb55e03Shkenken 
327bb55e03Shkenken #include "opt_imx51_ipuv3.h"
33456cfa81Sbsh 
34456cfa81Sbsh #include <sys/param.h>
35456cfa81Sbsh #include <sys/systm.h>
36456cfa81Sbsh #include <sys/conf.h>
37456cfa81Sbsh #include <sys/uio.h>
3845a935baSthorpej #include <sys/kmem.h>
39456cfa81Sbsh #include <sys/kernel.h>			/* for cold */
40456cfa81Sbsh 
41456cfa81Sbsh #include <sys/bus.h>
42456cfa81Sbsh #include <machine/cpu.h>
43456cfa81Sbsh #include <arm/cpufunc.h>
44456cfa81Sbsh 
45456cfa81Sbsh #include <arm/imx/imx51var.h>
46456cfa81Sbsh #include <arm/imx/imx51reg.h>
47456cfa81Sbsh #include <arm/imx/imx51_ipuv3var.h>
48456cfa81Sbsh #include <arm/imx/imx51_ipuv3reg.h>
49456cfa81Sbsh #include <arm/imx/imx51_ccmvar.h>
50456cfa81Sbsh #include <arm/imx/imx51_ccmreg.h>
51456cfa81Sbsh 
52456cfa81Sbsh #include "imxccm.h"	/* if CCM driver is configured into the kernel */
53456cfa81Sbsh 
54456cfa81Sbsh #define	IPUV3_READ(ipuv3, module, reg)					      \
55456cfa81Sbsh 	bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
56456cfa81Sbsh #define	IPUV3_WRITE(ipuv3, module, reg, val)				      \
57456cfa81Sbsh 	bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
58456cfa81Sbsh 
59456cfa81Sbsh #ifdef IPUV3_DEBUG
60456cfa81Sbsh int ipuv3_debug = IPUV3_DEBUG;
61456cfa81Sbsh #define	DPRINTFN(n,x)   if (ipuv3_debug>(n)) printf x; else
62456cfa81Sbsh #else
63456cfa81Sbsh #define	DPRINTFN(n,x)
64456cfa81Sbsh #endif
65456cfa81Sbsh 
66456cfa81Sbsh int ipuv3intr(void *);
67456cfa81Sbsh 
68456cfa81Sbsh static void imx51_ipuv3_initialize(struct imx51_ipuv3_softc *,
69456cfa81Sbsh     const struct lcd_panel_geometry *);
70456cfa81Sbsh static void imx51_ipuv3_set_idma_param(uint32_t *, uint32_t, uint32_t);
71456cfa81Sbsh 
72456cfa81Sbsh #ifdef IPUV3_DEBUG
73456cfa81Sbsh static void
imx51_ipuv3_dump(struct imx51_ipuv3_softc * sc)74456cfa81Sbsh imx51_ipuv3_dump(struct imx51_ipuv3_softc *sc)
75456cfa81Sbsh {
76456cfa81Sbsh 	int i;
77456cfa81Sbsh 
78456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
79456cfa81Sbsh 
80456cfa81Sbsh #define	__DUMP(grp, reg)						\
81456cfa81Sbsh 	DPRINTFN(4, ("%-16s = 0x%08X\n", #reg, IPUV3_READ(sc, grp, IPU_##reg)))
82456cfa81Sbsh 
83456cfa81Sbsh 	__DUMP(cm, CM_CONF);
84456cfa81Sbsh 	__DUMP(cm, CM_DISP_GEN);
85456cfa81Sbsh 	__DUMP(idmac, IDMAC_CONF);
86456cfa81Sbsh 	__DUMP(idmac, IDMAC_CH_EN_1);
87456cfa81Sbsh 	__DUMP(idmac, IDMAC_CH_EN_2);
88456cfa81Sbsh 	__DUMP(idmac, IDMAC_CH_PRI_1);
89456cfa81Sbsh 	__DUMP(idmac, IDMAC_CH_PRI_2);
90456cfa81Sbsh 	__DUMP(idmac, IDMAC_BNDM_EN_1);
91456cfa81Sbsh 	__DUMP(idmac, IDMAC_BNDM_EN_2);
92456cfa81Sbsh 	__DUMP(cm, CM_CH_DB_MODE_SEL_0);
93456cfa81Sbsh 	__DUMP(cm, CM_CH_DB_MODE_SEL_1);
94456cfa81Sbsh 	__DUMP(dmfc, DMFC_WR_CHAN);
95456cfa81Sbsh 	__DUMP(dmfc, DMFC_WR_CHAN_DEF);
96456cfa81Sbsh 	__DUMP(dmfc, DMFC_DP_CHAN);
97456cfa81Sbsh 	__DUMP(dmfc, DMFC_DP_CHAN_DEF);
98456cfa81Sbsh 	__DUMP(dmfc, DMFC_IC_CTRL);
99456cfa81Sbsh 	__DUMP(cm, CM_FS_PROC_FLOW1);
100456cfa81Sbsh 	__DUMP(cm, CM_FS_PROC_FLOW2);
101456cfa81Sbsh 	__DUMP(cm, CM_FS_PROC_FLOW3);
102456cfa81Sbsh 	__DUMP(cm, CM_FS_DISP_FLOW1);
103456cfa81Sbsh 	__DUMP(dc, DC_DISP_CONF1_0);
104456cfa81Sbsh 	__DUMP(dc, DC_DISP_CONF2_0);
105456cfa81Sbsh 	__DUMP(dc, DC_WR_CH_CONF_5);
106456cfa81Sbsh 
107456cfa81Sbsh 	printf("*** IPU ***\n");
108456cfa81Sbsh 	for (i = 0; i <= 0x17c; i += 4)
109456cfa81Sbsh 		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cm, i)));
110456cfa81Sbsh 	printf("*** IDMAC ***\n");
111456cfa81Sbsh 	for (i = 0; i <= 0x104; i += 4)
112456cfa81Sbsh 		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, idmac, i)));
113456cfa81Sbsh 	printf("*** CPMEM ***\n");
114456cfa81Sbsh 	for (i = 0x5c0; i <= 0x600; i += 4)
115456cfa81Sbsh 		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cpmem, i)));
116456cfa81Sbsh 
117456cfa81Sbsh #undef __DUMP
118456cfa81Sbsh 
119456cfa81Sbsh }
120456cfa81Sbsh #endif
121456cfa81Sbsh 
122456cfa81Sbsh static void
imx51_ipuv3_enable_display(struct imx51_ipuv3_softc * sc)123456cfa81Sbsh imx51_ipuv3_enable_display(struct imx51_ipuv3_softc *sc)
124456cfa81Sbsh {
125456cfa81Sbsh 	uint32_t reg = 0;
126456cfa81Sbsh 
127456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
128456cfa81Sbsh 
129456cfa81Sbsh 	/* enable sub modules */
130456cfa81Sbsh 	reg = IPUV3_READ(sc, cm, IPU_CM_CONF);
131456cfa81Sbsh 	reg |= CM_CONF_DP_EN |
132456cfa81Sbsh 	    CM_CONF_DC_EN |
133456cfa81Sbsh 	    CM_CONF_DMFC_EN |
134456cfa81Sbsh 	    CM_CONF_DI0_EN;
135456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_CONF, reg);
136456cfa81Sbsh }
137456cfa81Sbsh 
138456cfa81Sbsh static void
imx51_ipuv3_dmfc_init(struct imx51_ipuv3_softc * sc)139456cfa81Sbsh imx51_ipuv3_dmfc_init(struct imx51_ipuv3_softc *sc)
140456cfa81Sbsh {
141456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
142456cfa81Sbsh 
143456cfa81Sbsh 	/* IC channel is disabled */
144456cfa81Sbsh 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_IC_CTRL,
145456cfa81Sbsh 	    IC_IN_PORT_DISABLE);
146456cfa81Sbsh 
147456cfa81Sbsh 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN, 0x00000000);
148456cfa81Sbsh 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN_DEF, 0x20202020);
149456cfa81Sbsh 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN, 0x00000094);
150456cfa81Sbsh 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN_DEF, 0x202020F6);
151456cfa81Sbsh 
152456cfa81Sbsh 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_GENERAL1,
153456cfa81Sbsh 	    DCDP_SYNC_PR_ROUNDROBIN);
154456cfa81Sbsh 
155456cfa81Sbsh #ifdef IPUV3_DEBUG
156456cfa81Sbsh 	int i;
157456cfa81Sbsh 	printf("*** DMFC ***\n");
158456cfa81Sbsh 	for (i = 0; i <= 0x34; i += 4)
159456cfa81Sbsh 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dmfc, i));
160456cfa81Sbsh 
161456cfa81Sbsh 	printf("%s: DMFC_IC_CTRL         0x%08X\n", __func__,
162456cfa81Sbsh 	    IPUV3_READ(sc, dmfc, IPU_DMFC_IC_CTRL));
163456cfa81Sbsh 	printf("%s: IPU_DMFC_WR_CHAN     0x%08X\n", __func__,
164456cfa81Sbsh 	    IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN));
165456cfa81Sbsh 	printf("%s: IPU_DMFC_WR_CHAN_DEF 0x%08X\n", __func__,
166456cfa81Sbsh 	    IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN_DEF));
167456cfa81Sbsh 	printf("%s: IPU_DMFC_GENERAL1    0x%08X\n", __func__,
168456cfa81Sbsh 	    IPUV3_READ(sc, dmfc, IPU_DMFC_GENERAL1));
169456cfa81Sbsh #endif
170456cfa81Sbsh }
171456cfa81Sbsh 
172456cfa81Sbsh static void
imx51_ipuv3_dc_map_clear(struct imx51_ipuv3_softc * sc,int map)173456cfa81Sbsh imx51_ipuv3_dc_map_clear(struct imx51_ipuv3_softc *sc, int map)
174456cfa81Sbsh {
175456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
176456cfa81Sbsh 
177456cfa81Sbsh 	uint32_t reg;
178456cfa81Sbsh 	uint32_t addr;
179456cfa81Sbsh 
180456cfa81Sbsh 	addr = IPU_DC_MAP_CONF_PNTR(map / 2);
181456cfa81Sbsh 	reg = IPUV3_READ(sc, dc, addr);
182456cfa81Sbsh 	reg &= ~(0xFFFF << (16 * (map & 0x1)));
183456cfa81Sbsh 	IPUV3_WRITE(sc, dc, addr, reg);
184456cfa81Sbsh }
185456cfa81Sbsh 
186456cfa81Sbsh static void
imx51_ipuv3_dc_map_conf(struct imx51_ipuv3_softc * sc,int map,int byte,int offset,uint8_t mask)187456cfa81Sbsh imx51_ipuv3_dc_map_conf(struct imx51_ipuv3_softc *sc,
188456cfa81Sbsh     int map, int byte, int offset, uint8_t mask)
189456cfa81Sbsh {
190456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
191456cfa81Sbsh 
192456cfa81Sbsh 	uint32_t reg;
193456cfa81Sbsh 	uint32_t addr;
194456cfa81Sbsh 
195456cfa81Sbsh 	addr = IPU_DC_MAP_CONF_MASK((map * 3 + byte) / 2);
196456cfa81Sbsh 	reg = IPUV3_READ(sc, dc, addr);
197456cfa81Sbsh 	reg &= ~(0xFFFF << (16 * ((map * 3 + byte) & 0x1)));
198456cfa81Sbsh 	reg |= ((offset << 8) | mask) << (16 * ((map * 3 + byte) & 0x1));
199456cfa81Sbsh 	IPUV3_WRITE(sc, dc, addr, reg);
200456cfa81Sbsh #ifdef IPUV3_DEBUG
201456cfa81Sbsh 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);
202456cfa81Sbsh #endif
203456cfa81Sbsh 
204456cfa81Sbsh 	addr = IPU_DC_MAP_CONF_PNTR(map / 2);
205456cfa81Sbsh 	reg = IPUV3_READ(sc, dc, addr);
206456cfa81Sbsh 	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte)));
207456cfa81Sbsh 	reg |= ((map * 3) + byte) << ((16 * (map & 0x1)) + (5 * byte));
208456cfa81Sbsh 	IPUV3_WRITE(sc, dc, addr, reg);
209456cfa81Sbsh #ifdef IPUV3_DEBUG
210456cfa81Sbsh 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);
211456cfa81Sbsh #endif
212456cfa81Sbsh }
213456cfa81Sbsh 
214456cfa81Sbsh static void
imx51_ipuv3_dc_template_command(struct imx51_ipuv3_softc * sc,int index,int sync,int gluelogic,int waveform,int mapping,int operand,int opecode,int stop)215456cfa81Sbsh imx51_ipuv3_dc_template_command(struct imx51_ipuv3_softc *sc,
216456cfa81Sbsh     int index, int sync, int gluelogic, int waveform, int mapping,
217456cfa81Sbsh     int operand, int opecode, int stop)
218456cfa81Sbsh {
219456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
220456cfa81Sbsh 
221456cfa81Sbsh 	uint32_t reg;
222456cfa81Sbsh 
223456cfa81Sbsh 	reg = (sync << 0) |
224456cfa81Sbsh 	    (gluelogic << 4) |
225456cfa81Sbsh 	    (waveform << 11) |
226456cfa81Sbsh 	    (mapping << 15) |
227456cfa81Sbsh 	    (operand << 20);
228456cfa81Sbsh 	IPUV3_WRITE(sc, dctmpl, index * 8, reg);
229456cfa81Sbsh #ifdef IPUV3_DEBUG
230456cfa81Sbsh 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8, reg);
231456cfa81Sbsh #endif
232456cfa81Sbsh 	reg = (opecode << 0) |
233456cfa81Sbsh 	    (stop << 9);
234456cfa81Sbsh 	IPUV3_WRITE(sc, dctmpl, index * 8 + 4, reg);
235456cfa81Sbsh #ifdef IPUV3_DEBUG
236456cfa81Sbsh 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8 + 4, reg);
237456cfa81Sbsh #endif
238456cfa81Sbsh }
239456cfa81Sbsh 
240456cfa81Sbsh static void
imx51_ipuv3_set_routine_link(struct imx51_ipuv3_softc * sc,int base,int evt,int addr,int pri)241456cfa81Sbsh imx51_ipuv3_set_routine_link(struct imx51_ipuv3_softc *sc,
242456cfa81Sbsh     int base, int evt, int addr, int pri)
243456cfa81Sbsh {
244456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
245456cfa81Sbsh 
246456cfa81Sbsh 	uint32_t reg;
247456cfa81Sbsh 
248456cfa81Sbsh 	reg = IPUV3_READ(sc, dc, IPU_DC_RL(base, evt));
249456cfa81Sbsh 	reg &= ~(0xFFFF << (16 * (evt & 0x1)));
250456cfa81Sbsh 	reg |= ((addr << 8) | pri) << (16 * (evt & 0x1));
251456cfa81Sbsh 	IPUV3_WRITE(sc, dc, IPU_DC_RL(base, evt), reg);
252456cfa81Sbsh #ifdef IPUV3_DEBUG
253456cfa81Sbsh 	printf("%s: event %d addr %d priority %d\n", __func__,
254456cfa81Sbsh 	    evt, addr, pri);
255456cfa81Sbsh 	printf("%s: %p = 0x%08X\n", __func__,
256456cfa81Sbsh 	    (void *)IPU_DC_RL(base, evt), reg);
257456cfa81Sbsh #endif
258456cfa81Sbsh }
259456cfa81Sbsh 
260456cfa81Sbsh static void
imx51_ipuv3_dc_init(struct imx51_ipuv3_softc * sc)261456cfa81Sbsh imx51_ipuv3_dc_init(struct imx51_ipuv3_softc *sc)
262456cfa81Sbsh {
263456cfa81Sbsh 	uint32_t reg;
264456cfa81Sbsh 
265456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
266456cfa81Sbsh 
267456cfa81Sbsh 	imx51_ipuv3_dc_map_clear(sc, 0);
268456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 0, 0,  7, 0xff);
269456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 0, 1, 15, 0xff);
270456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 0, 2, 23, 0xff);
271456cfa81Sbsh 	imx51_ipuv3_dc_map_clear(sc, 1);
272456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 1, 0,  5, 0xfc);
273456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 1, 1, 11, 0xfc);
274456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 1, 2, 17, 0xfc);
275456cfa81Sbsh 	imx51_ipuv3_dc_map_clear(sc, 2);
276456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 2, 0, 15, 0xff);
277456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 2, 1, 23, 0xff);
278456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 2, 2,  7, 0xff);
279456cfa81Sbsh 	imx51_ipuv3_dc_map_clear(sc, 3);
280456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 3, 0,  4, 0xf8);
281456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 3, 1, 10, 0xfc);
282456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 3, 2, 15, 0xf8);
283456cfa81Sbsh 	imx51_ipuv3_dc_map_clear(sc, 4);
284456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 4, 0,  5, 0xfc);
285456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 4, 1, 13, 0xfc);
286456cfa81Sbsh 	imx51_ipuv3_dc_map_conf(sc, 4, 2, 21, 0xfc);
287456cfa81Sbsh 
288456cfa81Sbsh 	/* microcode */
289456cfa81Sbsh 	imx51_ipuv3_dc_template_command(sc,
290456cfa81Sbsh 	    5, 5, 8, 1, 5, 0, 0x180, 1);
291456cfa81Sbsh 	imx51_ipuv3_dc_template_command(sc,
292456cfa81Sbsh 	    6, 5, 4, 1, 5, 0, 0x180, 1);
293456cfa81Sbsh 	imx51_ipuv3_dc_template_command(sc,
294456cfa81Sbsh 	    7, 5, 0, 1, 5, 0, 0x180, 1);
295456cfa81Sbsh 
296456cfa81Sbsh 	reg = (4 << 5) | 0x2;
297456cfa81Sbsh 	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_5, reg);
298456cfa81Sbsh 	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_1, 0x4);
299456cfa81Sbsh 	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_ADDR_5, 0x0);
300456cfa81Sbsh 	IPUV3_WRITE(sc, dc, IPU_DC_GEN, 0x44);
301456cfa81Sbsh 
302456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NL, 5, 3);
303456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOL, 6, 2);
304456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_DATA, 7, 1);
305456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NF, 0, 0);
306456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NFIELD, 0, 0);
307456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOF, 0, 0);
308456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOFIELD, 0, 0);
309456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_CHAN, 0, 0);
310456cfa81Sbsh 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_ADDR, 0, 0);
311456cfa81Sbsh 
312456cfa81Sbsh #ifdef IPUV3_DEBUG
313456cfa81Sbsh 	int i;
314456cfa81Sbsh 	printf("*** DC ***\n");
315456cfa81Sbsh 	for (i = 0; i <= 0x1C8; i += 4)
316456cfa81Sbsh 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dc, i));
317456cfa81Sbsh 	printf("*** DCTEMPL ***\n");
318456cfa81Sbsh 	for (i = 0; i <= 0x100; i += 4)
319456cfa81Sbsh 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dctmpl, i));
320456cfa81Sbsh #endif
321456cfa81Sbsh }
322456cfa81Sbsh 
323456cfa81Sbsh static void
imx51_ipuv3_dc_display_config(struct imx51_ipuv3_softc * sc,int width)324456cfa81Sbsh imx51_ipuv3_dc_display_config(struct imx51_ipuv3_softc *sc, int width)
325456cfa81Sbsh {
326456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
327456cfa81Sbsh 
328456cfa81Sbsh 	IPUV3_WRITE(sc, dc, IPU_DC_DISP_CONF2_0, width);
329456cfa81Sbsh }
330456cfa81Sbsh 
331456cfa81Sbsh static void
imx51_ipuv3_di_sync_conf(struct imx51_ipuv3_softc * sc,int no,uint32_t reg_gen0,uint32_t reg_gen1,uint32_t repeat)332456cfa81Sbsh imx51_ipuv3_di_sync_conf(struct imx51_ipuv3_softc *sc, int no,
333456cfa81Sbsh     uint32_t reg_gen0, uint32_t reg_gen1, uint32_t repeat)
334456cfa81Sbsh {
335456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
336456cfa81Sbsh 
337456cfa81Sbsh 	uint32_t reg;
338456cfa81Sbsh 
339456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(no), reg_gen0);
340456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(no), reg_gen1);
341456cfa81Sbsh 	reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(no));
342a656470bShkenken 	reg &= ~DI_STP_REP(no);
343a656470bShkenken 	reg |= __SHIFTIN(repeat, DI_STP_REP(no));
344456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg);
345456cfa81Sbsh 
346456cfa81Sbsh #ifdef IPUV3_DEBUG
347456cfa81Sbsh 	printf("%s: no %d\n", __func__, no);
348456cfa81Sbsh 	printf("%s: addr 0x%08X reg_gen0   0x%08X\n", __func__,
349456cfa81Sbsh 	    IPU_DI_SW_GEN0(no), reg_gen0);
350456cfa81Sbsh 	printf("%s: addr 0x%08X reg_gen1   0x%08X\n", __func__,
351456cfa81Sbsh 	    IPU_DI_SW_GEN1(no), reg_gen1);
352456cfa81Sbsh 	printf("%s: addr 0x%08X DI_STP_REP 0x%08X\n", __func__,
353456cfa81Sbsh 	    IPU_DI_STP_REP(no), reg);
354456cfa81Sbsh #endif
355456cfa81Sbsh }
356456cfa81Sbsh 
357456cfa81Sbsh static void
imx51_ipuv3_di_init(struct imx51_ipuv3_softc * sc)358456cfa81Sbsh imx51_ipuv3_di_init(struct imx51_ipuv3_softc *sc)
359456cfa81Sbsh {
360456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
361456cfa81Sbsh 
362456cfa81Sbsh 	uint32_t reg;
363456cfa81Sbsh 	uint32_t div;
364456cfa81Sbsh 	u_int ipuclk;
365456cfa81Sbsh 	const struct lcd_panel_geometry *geom = sc->geometry;
366456cfa81Sbsh 
367456cfa81Sbsh #if NIMXCCM > 0
368456cfa81Sbsh 	ipuclk = imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT);
369456cfa81Sbsh #elif !defined(IMX51_IPU_HSP_CLOCK)
370456cfa81Sbsh #error	IMX51_CPU_HSP_CLOCK need to be defined.
371456cfa81Sbsh #else
372456cfa81Sbsh 	ipuclk = IMX51_IPU_HSP_CLOCK;
373456cfa81Sbsh #endif
374456cfa81Sbsh 	DPRINTFN(3, ("IPU HSP clock = %d\n", ipuclk));
375456cfa81Sbsh 	div = (ipuclk * 16) / geom->pixel_clk;
376456cfa81Sbsh 	div = div < 16 ? 16 : div & 0xff8;
377456cfa81Sbsh 
378456cfa81Sbsh 	/* DI counter */
379456cfa81Sbsh 	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
380456cfa81Sbsh 	reg &= ~(CM_DISP_GEN_DI1_COUNTER_RELEASE |
381456cfa81Sbsh 	    CM_DISP_GEN_DI0_COUNTER_RELEASE);
382456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
383456cfa81Sbsh 
384456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div);
385456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN1,
386a656470bShkenken 	    __SHIFTIN(div / 16, DI_BS_CLKGEN1_DOWN));
387456cfa81Sbsh #ifdef IPUV3_DEBUG
388456cfa81Sbsh 	printf("%s: IPU_DI_BS_CLKGEN0 = 0x%08X\n", __func__,
389456cfa81Sbsh 	    IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN0));
390456cfa81Sbsh 	printf("%s: IPU_DI_BS_CLKGEN1 = 0x%08X\n", __func__,
391456cfa81Sbsh 	    IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN1));
392456cfa81Sbsh #endif
393456cfa81Sbsh 	/* Display Time settings */
394a656470bShkenken 	reg = __SHIFTIN(div / 16 - 1, DI_DW_GEN_ACCESS_SIZE) |
395a656470bShkenken 	    __SHIFTIN(div / 16 - 1, DI_DW_GEN_COMPONNENT_SIZE) |
396a656470bShkenken 	    __SHIFTIN(3, DI_DW_GEN_PIN(15));
397456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg);
398456cfa81Sbsh #ifdef IPUV3_DEBUG
399456cfa81Sbsh 	printf("%s: div = %d\n", __func__, div);
400456cfa81Sbsh 	printf("%s: IPU_DI_DW_GEN(0) 0x%08X = 0x%08X\n", __func__,
401456cfa81Sbsh 	    IPU_DI_DW_GEN(0), reg);
402456cfa81Sbsh #endif
403456cfa81Sbsh 
404456cfa81Sbsh 	/* Up & Down Data Wave Set */
405a656470bShkenken 	reg = __SHIFTIN(div / 16 * 2, DI_DW_SET_DOWN);
406456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg);
407456cfa81Sbsh #ifdef IPUV3_DEBUG
408456cfa81Sbsh 	printf("%s: IPU_DI_DW_SET(0, 3) 0x%08X = 0x%08X\n", __func__,
409456cfa81Sbsh 	    IPU_DI_DW_SET(0, 3), reg);
410456cfa81Sbsh #endif
411456cfa81Sbsh 
412456cfa81Sbsh 	/* internal HSCYNC */
413456cfa81Sbsh 	imx51_ipuv3_di_sync_conf(sc, 1,
414456cfa81Sbsh 	    __DI_SW_GEN0(geom->panel_width + geom->hsync_width +
415456cfa81Sbsh 		geom->left + geom->right - 1, 1, 0, 0),
416456cfa81Sbsh 	    __DI_SW_GEN1(0, 1, 0, 0, 0, 0, 0),
417456cfa81Sbsh 	    0);
418456cfa81Sbsh 
419456cfa81Sbsh 	/* HSYNC */
420456cfa81Sbsh 	imx51_ipuv3_di_sync_conf(sc, 2,
421456cfa81Sbsh 	    __DI_SW_GEN0(geom->panel_width + geom->hsync_width +
422456cfa81Sbsh 		geom->left + geom->right - 1, 1, 0, 1),
423456cfa81Sbsh 	    __DI_SW_GEN1(1, 1, 0, geom->hsync_width * 2, 1, 0, 0),
424456cfa81Sbsh 	    0);
425456cfa81Sbsh 
426456cfa81Sbsh 	/* VSYNC */
427456cfa81Sbsh 	imx51_ipuv3_di_sync_conf(sc, 3,
428456cfa81Sbsh 	    __DI_SW_GEN0(geom->panel_height + geom->vsync_width +
429456cfa81Sbsh 		geom->upper + geom->lower - 1, 2, 0, 0),
430456cfa81Sbsh 	    __DI_SW_GEN1(1, 1, 0, geom->vsync_width * 2, 2, 0, 0),
431456cfa81Sbsh 	    0);
432456cfa81Sbsh 
433456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SCR_CONF,
434456cfa81Sbsh 	    geom->panel_height + geom->vsync_width + geom->upper +
435456cfa81Sbsh 	    geom->lower - 1);
436456cfa81Sbsh 
437456cfa81Sbsh 	/* Active Lines Start */
438456cfa81Sbsh 	imx51_ipuv3_di_sync_conf(sc, 4,
439456cfa81Sbsh 	    __DI_SW_GEN0(0, 3, geom->vsync_width + geom->upper, 3),
440456cfa81Sbsh 	    __DI_SW_GEN1(0, 0, 4, 0, 0, 0, 0),
441456cfa81Sbsh 	    geom->panel_height);
442456cfa81Sbsh 
443456cfa81Sbsh 	/* Active Clock Start */
444456cfa81Sbsh 	imx51_ipuv3_di_sync_conf(sc, 5,
445456cfa81Sbsh 	    __DI_SW_GEN0(0, 1, geom->hsync_width + geom->left, 1),
446456cfa81Sbsh 	    __DI_SW_GEN1(0, 0, 5, 0, 0, 0, 0),
447456cfa81Sbsh 	    geom->panel_width);
448456cfa81Sbsh 
449456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(6), 0);
450456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(6), 0);
451456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(7), 0);
452456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(7), 0);
453456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(8), 0);
454456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(8), 0);
455456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(9), 0);
456456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(9), 0);
457456cfa81Sbsh 
458456cfa81Sbsh 	reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(6));
459a656470bShkenken 	reg &= ~DI_STP_REP(6);
460456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg);
461456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(7), 0);
462456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(9), 0);
463456cfa81Sbsh 
464456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_GENERAL, 0);
465a656470bShkenken 	reg = __SHIFTIN(3 - 1, DI_SYNC_AS_GEN_VSYNC_SEL) |
466a656470bShkenken 	    __SHIFTIN(0x2, DI_SYNC_AS_GEN_SYNC_START);
467456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg);
468456cfa81Sbsh 	IPUV3_WRITE(sc, di0, IPU_DI_POL, DI_POL_DRDY_POLARITY_15);
469456cfa81Sbsh 
470456cfa81Sbsh 	/* release DI counter */
471456cfa81Sbsh 	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
472456cfa81Sbsh 	reg |= CM_DISP_GEN_DI0_COUNTER_RELEASE;
473456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
474456cfa81Sbsh 
475456cfa81Sbsh #ifdef IPUV3_DEBUG
476456cfa81Sbsh 	int i;
477456cfa81Sbsh 	printf("*** DI0 ***\n");
478456cfa81Sbsh 	for (i = 0; i <= 0x174; i += 4)
479456cfa81Sbsh 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, di0, i));
480456cfa81Sbsh 
481456cfa81Sbsh 	printf("%s: IPU_CM_DISP_GEN    : 0x%08X\n", __func__,
482456cfa81Sbsh 	    IPUV3_READ(sc, cm, IPU_CM_DISP_GEN));
483456cfa81Sbsh 	printf("%s: IPU_DI_SYNC_AS_GEN : 0x%08X\n", __func__,
484456cfa81Sbsh 	    IPUV3_READ(sc, di0, IPU_DI_SYNC_AS_GEN));
485456cfa81Sbsh 	printf("%s: IPU_DI_GENERAL     : 0x%08X\n", __func__,
486456cfa81Sbsh 	    IPUV3_READ(sc, di0, IPU_DI_GENERAL));
487456cfa81Sbsh 	printf("%s: IPU_DI_POL         : 0x%08X\n", __func__,
488456cfa81Sbsh 	    IPUV3_READ(sc, di0, IPU_DI_POL));
489456cfa81Sbsh #endif
490456cfa81Sbsh }
491456cfa81Sbsh 
492456cfa81Sbsh 
493456cfa81Sbsh void
imx51_ipuv3_geometry(struct imx51_ipuv3_softc * sc,const struct lcd_panel_geometry * geom)494456cfa81Sbsh imx51_ipuv3_geometry(struct imx51_ipuv3_softc *sc,
495456cfa81Sbsh     const struct lcd_panel_geometry *geom)
496456cfa81Sbsh {
497456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
498456cfa81Sbsh 
499456cfa81Sbsh 	sc->geometry = geom;
500456cfa81Sbsh 
501456cfa81Sbsh #ifdef IPUV3_DEBUG
502456cfa81Sbsh 	printf("%s: screen height = %d\n",__func__ , geom->panel_height);
503456cfa81Sbsh 	printf("%s:        width  = %d\n",__func__ , geom->panel_width);
504456cfa81Sbsh 	printf("%s: IPU Clock = %d\n", __func__,
505456cfa81Sbsh 	    imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT));
506456cfa81Sbsh 	printf("%s: Pixel Clock = %d\n", __func__, geom->pixel_clk);
507456cfa81Sbsh #endif
508456cfa81Sbsh 
509456cfa81Sbsh 	imx51_ipuv3_di_init(sc);
510456cfa81Sbsh 
511456cfa81Sbsh #ifdef IPUV3_DEBUG
512456cfa81Sbsh 	printf("%s: IPU_CM_DISP_GEN    : 0x%08X\n", __func__,
513456cfa81Sbsh 	    IPUV3_READ(sc, cm, IPU_CM_DISP_GEN));
514456cfa81Sbsh #endif
515456cfa81Sbsh 
516456cfa81Sbsh 	imx51_ipuv3_dc_display_config(sc, geom->panel_width);
517456cfa81Sbsh 
518456cfa81Sbsh 	return;
519456cfa81Sbsh }
520456cfa81Sbsh 
521456cfa81Sbsh /*
522456cfa81Sbsh  * Initialize the IPUV3 controller.
523456cfa81Sbsh  */
524456cfa81Sbsh static void
imx51_ipuv3_initialize(struct imx51_ipuv3_softc * sc,const struct lcd_panel_geometry * geom)525456cfa81Sbsh imx51_ipuv3_initialize(struct imx51_ipuv3_softc *sc,
526456cfa81Sbsh     const struct lcd_panel_geometry *geom)
527456cfa81Sbsh {
528456cfa81Sbsh 	uint32_t reg;
529456cfa81Sbsh 
530456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
531456cfa81Sbsh 
532456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_CONF, 0);
533456cfa81Sbsh 
534456cfa81Sbsh 	/* reset */
535456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_MEM_RST, CM_MEM_START | CM_MEM_EN);
536456cfa81Sbsh 	while (IPUV3_READ(sc, cm, IPU_CM_MEM_RST) & CM_MEM_START)
537456cfa81Sbsh 		; /* wait */
538456cfa81Sbsh 
539456cfa81Sbsh 	imx51_ipuv3_dmfc_init(sc);
540456cfa81Sbsh 	imx51_ipuv3_dc_init(sc);
541456cfa81Sbsh 
542456cfa81Sbsh 	imx51_ipuv3_geometry(sc, geom);
543456cfa81Sbsh 
544456cfa81Sbsh 	/* set global alpha */
545456cfa81Sbsh 	IPUV3_WRITE(sc, dp, IPU_DP_GRAPH_WIND_CTRL_SYNC, 0x80 << 24);
546456cfa81Sbsh 	IPUV3_WRITE(sc, dp, IPU_DP_COM_CONF_SYNC, DP_DP_GWAM_SYNC);
547456cfa81Sbsh 
548456cfa81Sbsh 	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
549456cfa81Sbsh 	reg |= CM_DISP_GEN_MCU_MAX_BURST_STOP |
550a656470bShkenken 	    __SHIFTIN(0x8, CM_DISP_GEN_MCU_T);
551456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
552456cfa81Sbsh }
553456cfa81Sbsh 
5547bb55e03Shkenken static int
imx51_ipuv3_print(void * aux,const char * pnp)5557bb55e03Shkenken imx51_ipuv3_print(void *aux, const char *pnp)
556456cfa81Sbsh {
5577bb55e03Shkenken 	const struct imxfb_attach_args * const ifb = aux;
558456cfa81Sbsh 
5597bb55e03Shkenken 	aprint_normal(" output %s", device_xname(ifb->ifb_outputdev));
560456cfa81Sbsh 
5617bb55e03Shkenken 	return UNCONF;
562456cfa81Sbsh }
563456cfa81Sbsh 
564456cfa81Sbsh /*
565456cfa81Sbsh  * Common driver attachment code.
566456cfa81Sbsh  */
567456cfa81Sbsh void
imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc * sc,struct axi_attach_args * axia,const struct lcd_panel_geometry * geom)568456cfa81Sbsh imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc *sc,
569456cfa81Sbsh     struct axi_attach_args *axia, const struct lcd_panel_geometry *geom)
570456cfa81Sbsh {
571456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
572456cfa81Sbsh 
573456cfa81Sbsh 	bus_space_tag_t iot = axia->aa_iot;
574456cfa81Sbsh 	int error;
575456cfa81Sbsh 
576456cfa81Sbsh 	aprint_normal(": i.MX51 IPUV3 controller\n");
577456cfa81Sbsh 
578456cfa81Sbsh 	sc->n_screens = 0;
579456cfa81Sbsh 	LIST_INIT(&sc->screens);
580456cfa81Sbsh 
581456cfa81Sbsh 	sc->iot = iot;
582eabbe28cSryo 	sc->dma_tag = &arm_generic_dma_tag;
583456cfa81Sbsh 
584456cfa81Sbsh 	/* map controller registers */
5857bb55e03Shkenken 	error = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &sc->cm_ioh);
586456cfa81Sbsh 	if (error)
587456cfa81Sbsh 		goto fail_retarn_cm;
588456cfa81Sbsh 
589456cfa81Sbsh 	/* map Display Multi FIFO Controller registers */
5907bb55e03Shkenken 	error = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &sc->dmfc_ioh);
591456cfa81Sbsh 	if (error)
592456cfa81Sbsh 		goto fail_retarn_dmfc;
593456cfa81Sbsh 
594456cfa81Sbsh 	/* map Display Interface registers */
5957bb55e03Shkenken 	error = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &sc->di0_ioh);
596456cfa81Sbsh 	if (error)
597456cfa81Sbsh 		goto fail_retarn_di0;
598456cfa81Sbsh 
599456cfa81Sbsh 	/* map Display Processor registers */
6007bb55e03Shkenken 	error = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &sc->dp_ioh);
601456cfa81Sbsh 	if (error)
602456cfa81Sbsh 		goto fail_retarn_dp;
603456cfa81Sbsh 
604456cfa81Sbsh 	/* map Display Controller registers */
6057bb55e03Shkenken 	error = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &sc->dc_ioh);
606456cfa81Sbsh 	if (error)
607456cfa81Sbsh 		goto fail_retarn_dc;
608456cfa81Sbsh 
609456cfa81Sbsh 	/* map Image DMA Controller registers */
6107bb55e03Shkenken 	error = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &sc->idmac_ioh);
611456cfa81Sbsh 	if (error)
612456cfa81Sbsh 		goto fail_retarn_idmac;
613456cfa81Sbsh 
614456cfa81Sbsh 	/* map CPMEM registers */
6157bb55e03Shkenken 	error = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &sc->cpmem_ioh);
616456cfa81Sbsh 	if (error)
617456cfa81Sbsh 		goto fail_retarn_cpmem;
618456cfa81Sbsh 
619456cfa81Sbsh 	/* map DCTEMPL registers */
6207bb55e03Shkenken 	error = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &sc->dctmpl_ioh);
621456cfa81Sbsh 	if (error)
622456cfa81Sbsh 		goto fail_retarn_dctmpl;
623456cfa81Sbsh 
624456cfa81Sbsh #ifdef notyet
625456cfa81Sbsh 	sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
626456cfa81Sbsh 	    ipuv3intr, sc);
627456cfa81Sbsh 	if (sc->ih == NULL) {
628456cfa81Sbsh 		aprint_error_dev(sc->dev,
629456cfa81Sbsh 		    "unable to establish interrupt at irq %d\n",
630456cfa81Sbsh 		    IMX51_INT_IPUV3);
631456cfa81Sbsh 		return;
632456cfa81Sbsh 	}
633456cfa81Sbsh #endif
634456cfa81Sbsh 
635456cfa81Sbsh 	imx51_ipuv3_initialize(sc, geom);
636456cfa81Sbsh 
637456cfa81Sbsh 	struct imx51_ipuv3_screen *scr;
6387bb55e03Shkenken 	error = imx51_ipuv3_new_screen(sc, &scr);
639456cfa81Sbsh 	if (error) {
640456cfa81Sbsh 		aprint_error_dev(sc->dev,
641456cfa81Sbsh 		    "unable to create new screen (errno=%d)", error);
642456cfa81Sbsh 		return;
643456cfa81Sbsh 	}
644456cfa81Sbsh 	sc->active = scr;
645456cfa81Sbsh 
646456cfa81Sbsh 	imx51_ipuv3_start_dma(sc, scr);
647456cfa81Sbsh 
6487bb55e03Shkenken 	struct imxfb_attach_args ifb = {
6497bb55e03Shkenken 		.ifb_dmat      = sc->dma_tag,
6507bb55e03Shkenken 		.ifb_dmamap    = scr->dma,
6517bb55e03Shkenken 		.ifb_dmasegs   = scr->segs,
6527bb55e03Shkenken 		.ifb_ndmasegs  = scr->nsegs,
6537bb55e03Shkenken 		.ifb_fb	       = scr->buf_va,
6547bb55e03Shkenken 		.ifb_width     = geom->panel_width,
6557bb55e03Shkenken 		.ifb_height    = geom->panel_height,
6567bb55e03Shkenken 		.ifb_depth     = scr->depth,
6577bb55e03Shkenken 		.ifb_stride    = geom->panel_width * (scr->depth / 8),
6587bb55e03Shkenken 		.ifb_outputdev = sc->dev,
6597bb55e03Shkenken 	};
6607bb55e03Shkenken 
661*c7fb772bSthorpej 	sc->fbdev = config_found(sc->dev, &ifb, imx51_ipuv3_print, CFARGS_NONE);
662b9040788Shkenken 
663456cfa81Sbsh 	return;
664456cfa81Sbsh 
665456cfa81Sbsh fail_retarn_dctmpl:
666456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
667456cfa81Sbsh fail_retarn_cpmem:
668456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
669456cfa81Sbsh fail_retarn_idmac:
670456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
671456cfa81Sbsh fail_retarn_dp:
672456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
673456cfa81Sbsh fail_retarn_dc:
674456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
675456cfa81Sbsh fail_retarn_di0:
676456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
677456cfa81Sbsh fail_retarn_dmfc:
678456cfa81Sbsh 	bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
679456cfa81Sbsh fail_retarn_cm:
680456cfa81Sbsh 	aprint_error_dev(sc->dev,
681456cfa81Sbsh 	    "failed to map registers (errno=%d)\n", error);
682456cfa81Sbsh 	return;
683456cfa81Sbsh }
684456cfa81Sbsh 
685456cfa81Sbsh #ifdef notyet
686456cfa81Sbsh /*
687456cfa81Sbsh  * Interrupt handler.
688456cfa81Sbsh  */
689456cfa81Sbsh int
ipuv3intr(void * arg)690456cfa81Sbsh ipuv3intr(void *arg)
691456cfa81Sbsh {
692456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
693456cfa81Sbsh 
694456cfa81Sbsh 	struct imx51_ipuv3_softc *sc = (struct imx51_ipuv3_softc *)arg;
695456cfa81Sbsh 	bus_space_tag_t iot = sc->iot;
696456cfa81Sbsh 	bus_space_handle_t ioh = sc->dc_ioh;
697456cfa81Sbsh 	uint32_t status;
698456cfa81Sbsh 
699456cfa81Sbsh 	status = IPUV3_READ(ioh, V3CR);
700456cfa81Sbsh 	/* Clear stickey status bits */
701456cfa81Sbsh 	IPUV3_WRITE(ioh, V3CR, status);
702456cfa81Sbsh 
703456cfa81Sbsh 	return 1;
704456cfa81Sbsh }
705456cfa81Sbsh #endif
706456cfa81Sbsh 
707456cfa81Sbsh static void
imx51_ipuv3_write_dmaparam(struct imx51_ipuv3_softc * sc,int ch,uint32_t * value,int size)708456cfa81Sbsh imx51_ipuv3_write_dmaparam(struct imx51_ipuv3_softc *sc,
709456cfa81Sbsh     int ch, uint32_t *value, int size)
710456cfa81Sbsh {
711456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
712456cfa81Sbsh 
713456cfa81Sbsh 	int i;
714456cfa81Sbsh 	uint32_t addr = ch * 0x40;
715456cfa81Sbsh 
716456cfa81Sbsh 	for (i = 0; i < size; i++) {
717456cfa81Sbsh 		IPUV3_WRITE(sc, cpmem, addr + ((i % 5) * 0x4) +
718456cfa81Sbsh 		    ((i / 5) * 0x20), value[i]);
719456cfa81Sbsh #ifdef IPUV3_DEBUG
720456cfa81Sbsh 		printf("%s: addr = 0x%08X, val = 0x%08X\n", __func__,
721456cfa81Sbsh 		    addr + ((i % 5) * 0x4) + ((i / 5) * 0x20),
722456cfa81Sbsh 		    IPUV3_READ(sc, cpmem, addr + ((i % 5) * 0x4) +
723456cfa81Sbsh 			((i / 5) * 0x20)));
724456cfa81Sbsh #endif
725456cfa81Sbsh 	}
726456cfa81Sbsh }
727456cfa81Sbsh 
728456cfa81Sbsh static void
imx51_ipuv3_build_param(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen * scr,uint32_t * params)729456cfa81Sbsh imx51_ipuv3_build_param(struct imx51_ipuv3_softc *sc,
730456cfa81Sbsh     struct imx51_ipuv3_screen *scr,
731456cfa81Sbsh     uint32_t *params)
732456cfa81Sbsh {
733456cfa81Sbsh 	const struct lcd_panel_geometry *geom = sc->geometry;
734456cfa81Sbsh 
735456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
736456cfa81Sbsh 
737456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FW,
738456cfa81Sbsh 	    (geom->panel_width - 1));
739456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FH,
740456cfa81Sbsh 	    (geom->panel_height - 1));
741456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA0,
742456cfa81Sbsh 	    scr->segs[0].ds_addr >> 3);
743456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA1,
744456cfa81Sbsh 	    scr->segs[0].ds_addr >> 3);
745456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_SL,
746456cfa81Sbsh 	    (scr->stride - 1));
747456cfa81Sbsh 
748456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_PFS, 0x7);
749456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_NPB, 32 - 1);
750456cfa81Sbsh 
751456cfa81Sbsh 	switch (scr->depth) {
752456cfa81Sbsh 	case 32:
753456cfa81Sbsh 		/* ARBG888 */
754456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x0);
755456cfa81Sbsh 
756456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
757456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8);
758456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16);
759456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24);
760456cfa81Sbsh 
761456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1);
762456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1);
763456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1);
764456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 8 - 1);
765456cfa81Sbsh 		break;
766456cfa81Sbsh 	case 24:
767456cfa81Sbsh 		/* RBG888 */
768456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x1);
769456cfa81Sbsh 
770456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
771456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8);
772456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16);
773456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24);
774456cfa81Sbsh 
775456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1);
776456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1);
777456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1);
778456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0);
779456cfa81Sbsh 		break;
780456cfa81Sbsh 	case 16:
781456cfa81Sbsh 		/* RBG565 */
782456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x3);
783456cfa81Sbsh 
784456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
785456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 5);
786456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 11);
787456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 16);
788456cfa81Sbsh 
789456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 5 - 1);
790456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 6 - 1);
791456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 5 - 1);
792456cfa81Sbsh 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0);
793456cfa81Sbsh 		break;
794456cfa81Sbsh 	default:
795456cfa81Sbsh 		panic("%s: unsupported depth %d\n", __func__, scr->depth);
796456cfa81Sbsh 		break;
797456cfa81Sbsh 	}
798456cfa81Sbsh 
799456cfa81Sbsh 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_ID, 1);
800456cfa81Sbsh }
801456cfa81Sbsh 
802456cfa81Sbsh static void
imx51_ipuv3_set_idma_param(uint32_t * params,uint32_t name,uint32_t val)803456cfa81Sbsh imx51_ipuv3_set_idma_param(uint32_t *params, uint32_t name, uint32_t val)
804456cfa81Sbsh {
805456cfa81Sbsh 	int word = (name >> 16) & 0xff;
806456cfa81Sbsh 	int shift = (name >> 8) & 0xff;
807456cfa81Sbsh 	int width = name & 0xff;
808456cfa81Sbsh 	int index;
809456cfa81Sbsh 
810456cfa81Sbsh 	index = word * 5;
811456cfa81Sbsh 	index += shift / 32;
812456cfa81Sbsh 	shift = shift % 32;
813456cfa81Sbsh 
814456cfa81Sbsh 	params[index] |= val << shift;
815456cfa81Sbsh 	shift = 32 - shift;
816456cfa81Sbsh 
817456cfa81Sbsh 	if (width > shift)
818456cfa81Sbsh 		params[index+1] |= val >> shift;
819456cfa81Sbsh }
820456cfa81Sbsh 
821456cfa81Sbsh /*
822456cfa81Sbsh  * Enable DMA to cause the display to be refreshed periodically.
823456cfa81Sbsh  * This brings the screen to life...
824456cfa81Sbsh  */
825456cfa81Sbsh void
imx51_ipuv3_start_dma(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen * scr)826456cfa81Sbsh imx51_ipuv3_start_dma(struct imx51_ipuv3_softc *sc,
827456cfa81Sbsh     struct imx51_ipuv3_screen *scr)
828456cfa81Sbsh {
829456cfa81Sbsh 	int save;
830456cfa81Sbsh 	uint32_t params[10];
831456cfa81Sbsh 	uint32_t reg;
832456cfa81Sbsh 
833456cfa81Sbsh 	DPRINTFN(3, ("%s: Pixel depth = %d\n", __func__, scr->depth));
834456cfa81Sbsh 
835456cfa81Sbsh 	reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);
836456cfa81Sbsh 	reg &= ~__BIT(CH_PANNEL_BG);
837456cfa81Sbsh 	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
838456cfa81Sbsh 
839456cfa81Sbsh 	memset(params, 0, sizeof(params));
840456cfa81Sbsh 	imx51_ipuv3_build_param(sc, scr, params);
841456cfa81Sbsh 
842456cfa81Sbsh 	save = disable_interrupts(I32_bit);
843456cfa81Sbsh 
844456cfa81Sbsh 	/* IDMAC configuration */
845456cfa81Sbsh 	imx51_ipuv3_write_dmaparam(sc, CH_PANNEL_BG, params,
846456cfa81Sbsh 	    sizeof(params) / sizeof(params[0]));
847456cfa81Sbsh 
848456cfa81Sbsh 	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_PRI_1, __BIT(CH_PANNEL_BG));
849456cfa81Sbsh 
850456cfa81Sbsh 	/* double buffer */
851456cfa81Sbsh 	reg = IPUV3_READ(sc, cm, IPU_CM_CH_DB_MODE_SEL_0);
852456cfa81Sbsh 	reg |= __BIT(CH_PANNEL_BG);
853456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_CH_DB_MODE_SEL_0, reg);
854456cfa81Sbsh 
855456cfa81Sbsh 	reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);
856456cfa81Sbsh 	reg |= __BIT(CH_PANNEL_BG);
857456cfa81Sbsh 	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
858456cfa81Sbsh 
859456cfa81Sbsh 	reg = IPUV3_READ(sc, cm, IPU_CM_GPR);
860456cfa81Sbsh 	reg &= ~CM_GPR_IPU_CH_BUF0_RDY0_CLR;
861456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_GPR, reg);
862456cfa81Sbsh 
863456cfa81Sbsh 	IPUV3_WRITE(sc, cm, IPU_CM_CUR_BUF_0, __BIT(CH_PANNEL_BG));
864456cfa81Sbsh 
865456cfa81Sbsh 	restore_interrupts(save);
866456cfa81Sbsh 
867456cfa81Sbsh 	imx51_ipuv3_enable_display(sc);
868456cfa81Sbsh 
869456cfa81Sbsh #ifdef IPUV3_DEBUG
870456cfa81Sbsh 	imx51_ipuv3_dump(sc);
871456cfa81Sbsh #endif
872456cfa81Sbsh }
873456cfa81Sbsh 
8747bb55e03Shkenken static int
imx51_ipuv3_allocmem(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen * scr)8757bb55e03Shkenken imx51_ipuv3_allocmem(struct imx51_ipuv3_softc *sc,
8767bb55e03Shkenken     struct imx51_ipuv3_screen *scr)
877456cfa81Sbsh {
8787bb55e03Shkenken 	int error;
879456cfa81Sbsh 
8807bb55e03Shkenken 	error = bus_dmamem_alloc(sc->dma_tag, scr->buf_size, PAGE_SIZE, 0,
8817bb55e03Shkenken 	    scr->segs, 1, &scr->nsegs, BUS_DMA_WAITOK);
8827bb55e03Shkenken 	if (error)
8837bb55e03Shkenken 		return error;
8847bb55e03Shkenken 	error = bus_dmamem_map(sc->dma_tag, scr->segs, scr->nsegs, scr->buf_size,
8857bb55e03Shkenken 	    (void **)&scr->buf_va, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
8867bb55e03Shkenken 	if (error)
8877bb55e03Shkenken 		goto free;
8887bb55e03Shkenken 	/* map memory for DMA */
8897bb55e03Shkenken 	error = bus_dmamap_create(sc->dma_tag, scr->buf_size, 1, scr->buf_size, 0,
8907bb55e03Shkenken 	    BUS_DMA_WAITOK, &scr->dma);
8917bb55e03Shkenken 	if (error)
8927bb55e03Shkenken 		goto unmap;
8937bb55e03Shkenken 	error = bus_dmamap_load(sc->dma_tag, scr->dma, scr->buf_va, scr->buf_size,
8947bb55e03Shkenken 	    NULL, BUS_DMA_WAITOK);
8957bb55e03Shkenken 	if (error)
8967bb55e03Shkenken 		goto destroy;
8977bb55e03Shkenken 
8987bb55e03Shkenken 	memset(scr->buf_va, 0, scr->buf_size);
8997bb55e03Shkenken 
9007bb55e03Shkenken 	return 0;
9017bb55e03Shkenken 
9027bb55e03Shkenken destroy:
9037bb55e03Shkenken 	bus_dmamap_destroy(sc->dma_tag, scr->dma);
9047bb55e03Shkenken unmap:
9057bb55e03Shkenken 	bus_dmamem_unmap(sc->dma_tag, scr->buf_va, scr->buf_size);
9067bb55e03Shkenken free:
9077bb55e03Shkenken 	bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs);
9087bb55e03Shkenken 
9097bb55e03Shkenken 	scr->buf_size = 0;
9107bb55e03Shkenken 	scr->buf_va = NULL;
9117bb55e03Shkenken 
9127bb55e03Shkenken 	return error;
913456cfa81Sbsh }
914456cfa81Sbsh 
915456cfa81Sbsh /*
916456cfa81Sbsh  * Create and initialize a new screen buffer.
917456cfa81Sbsh  */
918456cfa81Sbsh int
imx51_ipuv3_new_screen(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen ** scrpp)9197bb55e03Shkenken imx51_ipuv3_new_screen(struct imx51_ipuv3_softc *sc,
920456cfa81Sbsh     struct imx51_ipuv3_screen **scrpp)
921456cfa81Sbsh {
922456cfa81Sbsh 	const struct lcd_panel_geometry *geometry;
923456cfa81Sbsh 	struct imx51_ipuv3_screen *scr = NULL;
9247bb55e03Shkenken 	int depth, width, height;
925456cfa81Sbsh 	int error;
926456cfa81Sbsh 
927456cfa81Sbsh 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
928456cfa81Sbsh 
929456cfa81Sbsh 	geometry = sc->geometry;
930456cfa81Sbsh 
9317bb55e03Shkenken 	depth = geometry->depth;
932456cfa81Sbsh 	width = geometry->panel_width;
933456cfa81Sbsh 	height = geometry->panel_height;
934456cfa81Sbsh 
93545a935baSthorpej 	scr = kmem_zalloc(sizeof(*scr), KM_SLEEP);
936456cfa81Sbsh 	scr->nsegs = 0;
937456cfa81Sbsh 	scr->depth = depth;
938456cfa81Sbsh 	scr->stride = width * depth / 8;
9397bb55e03Shkenken 	scr->buf_size = scr->stride * height;
940456cfa81Sbsh 	scr->buf_va = NULL;
941456cfa81Sbsh 
9427bb55e03Shkenken 	error = imx51_ipuv3_allocmem(sc, scr);
9437bb55e03Shkenken 	if (error) {
9447bb55e03Shkenken 		aprint_error_dev(sc->dev,
9457bb55e03Shkenken 		    "failed to allocate %u bytes of video memory: %d\n",
9467bb55e03Shkenken 		    scr->stride * height, error);
94745a935baSthorpej 		kmem_free(scr, sizeof(*scr));
9487bb55e03Shkenken 		return error;
949456cfa81Sbsh 	}
950456cfa81Sbsh 
951456cfa81Sbsh 	LIST_INSERT_HEAD(&sc->screens, scr, link);
952456cfa81Sbsh 	sc->n_screens++;
953456cfa81Sbsh 
954456cfa81Sbsh #ifdef IPUV3_DEBUG
955456cfa81Sbsh 	printf("%s: screen buffer width  %d\n", __func__, width);
956456cfa81Sbsh 	printf("%s: screen buffer height %d\n", __func__, height);
957456cfa81Sbsh 	printf("%s: screen buffer depth  %d\n", __func__, depth);
958456cfa81Sbsh 	printf("%s: screen buffer stride %d\n", __func__, scr->stride);
959456cfa81Sbsh 	printf("%s: screen buffer size   0x%08X\n", __func__,
960456cfa81Sbsh 	    (uint32_t)scr->buf_size);
961456cfa81Sbsh 	printf("%s: screen buffer addr virtual  %p\n", __func__, scr->buf_va);
962456cfa81Sbsh 	printf("%s: screen buffer addr physical %p\n", __func__,
963456cfa81Sbsh 	    (void *)scr->segs[0].ds_addr);
964456cfa81Sbsh #endif
965456cfa81Sbsh 
9667bb55e03Shkenken 	scr->map_size = scr->buf_size;		/* used when unmap this. */
967456cfa81Sbsh 
968456cfa81Sbsh 	*scrpp = scr;
969456cfa81Sbsh 
970456cfa81Sbsh 	return 0;
971456cfa81Sbsh }
972