xref: /netbsd-src/sys/arch/arm/imx/imx51_ipuv3.c (revision c7fb772b85b2b5d4cfb282f868f454b4701534fd)
1 /*	$NetBSD: imx51_ipuv3.c,v 1.11 2021/08/07 16:18:44 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2011, 2012  Genetec Corporation.  All rights reserved.
5  * Written by Hashimoto Kenichi for Genetec Corporation.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: imx51_ipuv3.c,v 1.11 2021/08/07 16:18:44 thorpej Exp $");
31 
32 #include "opt_imx51_ipuv3.h"
33 
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/conf.h>
37 #include <sys/uio.h>
38 #include <sys/kmem.h>
39 #include <sys/kernel.h>			/* for cold */
40 
41 #include <sys/bus.h>
42 #include <machine/cpu.h>
43 #include <arm/cpufunc.h>
44 
45 #include <arm/imx/imx51var.h>
46 #include <arm/imx/imx51reg.h>
47 #include <arm/imx/imx51_ipuv3var.h>
48 #include <arm/imx/imx51_ipuv3reg.h>
49 #include <arm/imx/imx51_ccmvar.h>
50 #include <arm/imx/imx51_ccmreg.h>
51 
52 #include "imxccm.h"	/* if CCM driver is configured into the kernel */
53 
54 #define	IPUV3_READ(ipuv3, module, reg)					      \
55 	bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
56 #define	IPUV3_WRITE(ipuv3, module, reg, val)				      \
57 	bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
58 
59 #ifdef IPUV3_DEBUG
60 int ipuv3_debug = IPUV3_DEBUG;
61 #define	DPRINTFN(n,x)   if (ipuv3_debug>(n)) printf x; else
62 #else
63 #define	DPRINTFN(n,x)
64 #endif
65 
66 int ipuv3intr(void *);
67 
68 static void imx51_ipuv3_initialize(struct imx51_ipuv3_softc *,
69     const struct lcd_panel_geometry *);
70 static void imx51_ipuv3_set_idma_param(uint32_t *, uint32_t, uint32_t);
71 
72 #ifdef IPUV3_DEBUG
73 static void
imx51_ipuv3_dump(struct imx51_ipuv3_softc * sc)74 imx51_ipuv3_dump(struct imx51_ipuv3_softc *sc)
75 {
76 	int i;
77 
78 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
79 
80 #define	__DUMP(grp, reg)						\
81 	DPRINTFN(4, ("%-16s = 0x%08X\n", #reg, IPUV3_READ(sc, grp, IPU_##reg)))
82 
83 	__DUMP(cm, CM_CONF);
84 	__DUMP(cm, CM_DISP_GEN);
85 	__DUMP(idmac, IDMAC_CONF);
86 	__DUMP(idmac, IDMAC_CH_EN_1);
87 	__DUMP(idmac, IDMAC_CH_EN_2);
88 	__DUMP(idmac, IDMAC_CH_PRI_1);
89 	__DUMP(idmac, IDMAC_CH_PRI_2);
90 	__DUMP(idmac, IDMAC_BNDM_EN_1);
91 	__DUMP(idmac, IDMAC_BNDM_EN_2);
92 	__DUMP(cm, CM_CH_DB_MODE_SEL_0);
93 	__DUMP(cm, CM_CH_DB_MODE_SEL_1);
94 	__DUMP(dmfc, DMFC_WR_CHAN);
95 	__DUMP(dmfc, DMFC_WR_CHAN_DEF);
96 	__DUMP(dmfc, DMFC_DP_CHAN);
97 	__DUMP(dmfc, DMFC_DP_CHAN_DEF);
98 	__DUMP(dmfc, DMFC_IC_CTRL);
99 	__DUMP(cm, CM_FS_PROC_FLOW1);
100 	__DUMP(cm, CM_FS_PROC_FLOW2);
101 	__DUMP(cm, CM_FS_PROC_FLOW3);
102 	__DUMP(cm, CM_FS_DISP_FLOW1);
103 	__DUMP(dc, DC_DISP_CONF1_0);
104 	__DUMP(dc, DC_DISP_CONF2_0);
105 	__DUMP(dc, DC_WR_CH_CONF_5);
106 
107 	printf("*** IPU ***\n");
108 	for (i = 0; i <= 0x17c; i += 4)
109 		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cm, i)));
110 	printf("*** IDMAC ***\n");
111 	for (i = 0; i <= 0x104; i += 4)
112 		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, idmac, i)));
113 	printf("*** CPMEM ***\n");
114 	for (i = 0x5c0; i <= 0x600; i += 4)
115 		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cpmem, i)));
116 
117 #undef __DUMP
118 
119 }
120 #endif
121 
122 static void
imx51_ipuv3_enable_display(struct imx51_ipuv3_softc * sc)123 imx51_ipuv3_enable_display(struct imx51_ipuv3_softc *sc)
124 {
125 	uint32_t reg = 0;
126 
127 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
128 
129 	/* enable sub modules */
130 	reg = IPUV3_READ(sc, cm, IPU_CM_CONF);
131 	reg |= CM_CONF_DP_EN |
132 	    CM_CONF_DC_EN |
133 	    CM_CONF_DMFC_EN |
134 	    CM_CONF_DI0_EN;
135 	IPUV3_WRITE(sc, cm, IPU_CM_CONF, reg);
136 }
137 
138 static void
imx51_ipuv3_dmfc_init(struct imx51_ipuv3_softc * sc)139 imx51_ipuv3_dmfc_init(struct imx51_ipuv3_softc *sc)
140 {
141 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
142 
143 	/* IC channel is disabled */
144 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_IC_CTRL,
145 	    IC_IN_PORT_DISABLE);
146 
147 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN, 0x00000000);
148 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN_DEF, 0x20202020);
149 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN, 0x00000094);
150 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN_DEF, 0x202020F6);
151 
152 	IPUV3_WRITE(sc, dmfc, IPU_DMFC_GENERAL1,
153 	    DCDP_SYNC_PR_ROUNDROBIN);
154 
155 #ifdef IPUV3_DEBUG
156 	int i;
157 	printf("*** DMFC ***\n");
158 	for (i = 0; i <= 0x34; i += 4)
159 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dmfc, i));
160 
161 	printf("%s: DMFC_IC_CTRL         0x%08X\n", __func__,
162 	    IPUV3_READ(sc, dmfc, IPU_DMFC_IC_CTRL));
163 	printf("%s: IPU_DMFC_WR_CHAN     0x%08X\n", __func__,
164 	    IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN));
165 	printf("%s: IPU_DMFC_WR_CHAN_DEF 0x%08X\n", __func__,
166 	    IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN_DEF));
167 	printf("%s: IPU_DMFC_GENERAL1    0x%08X\n", __func__,
168 	    IPUV3_READ(sc, dmfc, IPU_DMFC_GENERAL1));
169 #endif
170 }
171 
172 static void
imx51_ipuv3_dc_map_clear(struct imx51_ipuv3_softc * sc,int map)173 imx51_ipuv3_dc_map_clear(struct imx51_ipuv3_softc *sc, int map)
174 {
175 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
176 
177 	uint32_t reg;
178 	uint32_t addr;
179 
180 	addr = IPU_DC_MAP_CONF_PNTR(map / 2);
181 	reg = IPUV3_READ(sc, dc, addr);
182 	reg &= ~(0xFFFF << (16 * (map & 0x1)));
183 	IPUV3_WRITE(sc, dc, addr, reg);
184 }
185 
186 static void
imx51_ipuv3_dc_map_conf(struct imx51_ipuv3_softc * sc,int map,int byte,int offset,uint8_t mask)187 imx51_ipuv3_dc_map_conf(struct imx51_ipuv3_softc *sc,
188     int map, int byte, int offset, uint8_t mask)
189 {
190 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
191 
192 	uint32_t reg;
193 	uint32_t addr;
194 
195 	addr = IPU_DC_MAP_CONF_MASK((map * 3 + byte) / 2);
196 	reg = IPUV3_READ(sc, dc, addr);
197 	reg &= ~(0xFFFF << (16 * ((map * 3 + byte) & 0x1)));
198 	reg |= ((offset << 8) | mask) << (16 * ((map * 3 + byte) & 0x1));
199 	IPUV3_WRITE(sc, dc, addr, reg);
200 #ifdef IPUV3_DEBUG
201 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);
202 #endif
203 
204 	addr = IPU_DC_MAP_CONF_PNTR(map / 2);
205 	reg = IPUV3_READ(sc, dc, addr);
206 	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte)));
207 	reg |= ((map * 3) + byte) << ((16 * (map & 0x1)) + (5 * byte));
208 	IPUV3_WRITE(sc, dc, addr, reg);
209 #ifdef IPUV3_DEBUG
210 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);
211 #endif
212 }
213 
214 static void
imx51_ipuv3_dc_template_command(struct imx51_ipuv3_softc * sc,int index,int sync,int gluelogic,int waveform,int mapping,int operand,int opecode,int stop)215 imx51_ipuv3_dc_template_command(struct imx51_ipuv3_softc *sc,
216     int index, int sync, int gluelogic, int waveform, int mapping,
217     int operand, int opecode, int stop)
218 {
219 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
220 
221 	uint32_t reg;
222 
223 	reg = (sync << 0) |
224 	    (gluelogic << 4) |
225 	    (waveform << 11) |
226 	    (mapping << 15) |
227 	    (operand << 20);
228 	IPUV3_WRITE(sc, dctmpl, index * 8, reg);
229 #ifdef IPUV3_DEBUG
230 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8, reg);
231 #endif
232 	reg = (opecode << 0) |
233 	    (stop << 9);
234 	IPUV3_WRITE(sc, dctmpl, index * 8 + 4, reg);
235 #ifdef IPUV3_DEBUG
236 	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8 + 4, reg);
237 #endif
238 }
239 
240 static void
imx51_ipuv3_set_routine_link(struct imx51_ipuv3_softc * sc,int base,int evt,int addr,int pri)241 imx51_ipuv3_set_routine_link(struct imx51_ipuv3_softc *sc,
242     int base, int evt, int addr, int pri)
243 {
244 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
245 
246 	uint32_t reg;
247 
248 	reg = IPUV3_READ(sc, dc, IPU_DC_RL(base, evt));
249 	reg &= ~(0xFFFF << (16 * (evt & 0x1)));
250 	reg |= ((addr << 8) | pri) << (16 * (evt & 0x1));
251 	IPUV3_WRITE(sc, dc, IPU_DC_RL(base, evt), reg);
252 #ifdef IPUV3_DEBUG
253 	printf("%s: event %d addr %d priority %d\n", __func__,
254 	    evt, addr, pri);
255 	printf("%s: %p = 0x%08X\n", __func__,
256 	    (void *)IPU_DC_RL(base, evt), reg);
257 #endif
258 }
259 
260 static void
imx51_ipuv3_dc_init(struct imx51_ipuv3_softc * sc)261 imx51_ipuv3_dc_init(struct imx51_ipuv3_softc *sc)
262 {
263 	uint32_t reg;
264 
265 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
266 
267 	imx51_ipuv3_dc_map_clear(sc, 0);
268 	imx51_ipuv3_dc_map_conf(sc, 0, 0,  7, 0xff);
269 	imx51_ipuv3_dc_map_conf(sc, 0, 1, 15, 0xff);
270 	imx51_ipuv3_dc_map_conf(sc, 0, 2, 23, 0xff);
271 	imx51_ipuv3_dc_map_clear(sc, 1);
272 	imx51_ipuv3_dc_map_conf(sc, 1, 0,  5, 0xfc);
273 	imx51_ipuv3_dc_map_conf(sc, 1, 1, 11, 0xfc);
274 	imx51_ipuv3_dc_map_conf(sc, 1, 2, 17, 0xfc);
275 	imx51_ipuv3_dc_map_clear(sc, 2);
276 	imx51_ipuv3_dc_map_conf(sc, 2, 0, 15, 0xff);
277 	imx51_ipuv3_dc_map_conf(sc, 2, 1, 23, 0xff);
278 	imx51_ipuv3_dc_map_conf(sc, 2, 2,  7, 0xff);
279 	imx51_ipuv3_dc_map_clear(sc, 3);
280 	imx51_ipuv3_dc_map_conf(sc, 3, 0,  4, 0xf8);
281 	imx51_ipuv3_dc_map_conf(sc, 3, 1, 10, 0xfc);
282 	imx51_ipuv3_dc_map_conf(sc, 3, 2, 15, 0xf8);
283 	imx51_ipuv3_dc_map_clear(sc, 4);
284 	imx51_ipuv3_dc_map_conf(sc, 4, 0,  5, 0xfc);
285 	imx51_ipuv3_dc_map_conf(sc, 4, 1, 13, 0xfc);
286 	imx51_ipuv3_dc_map_conf(sc, 4, 2, 21, 0xfc);
287 
288 	/* microcode */
289 	imx51_ipuv3_dc_template_command(sc,
290 	    5, 5, 8, 1, 5, 0, 0x180, 1);
291 	imx51_ipuv3_dc_template_command(sc,
292 	    6, 5, 4, 1, 5, 0, 0x180, 1);
293 	imx51_ipuv3_dc_template_command(sc,
294 	    7, 5, 0, 1, 5, 0, 0x180, 1);
295 
296 	reg = (4 << 5) | 0x2;
297 	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_5, reg);
298 	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_1, 0x4);
299 	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_ADDR_5, 0x0);
300 	IPUV3_WRITE(sc, dc, IPU_DC_GEN, 0x44);
301 
302 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NL, 5, 3);
303 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOL, 6, 2);
304 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_DATA, 7, 1);
305 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NF, 0, 0);
306 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NFIELD, 0, 0);
307 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOF, 0, 0);
308 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOFIELD, 0, 0);
309 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_CHAN, 0, 0);
310 	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_ADDR, 0, 0);
311 
312 #ifdef IPUV3_DEBUG
313 	int i;
314 	printf("*** DC ***\n");
315 	for (i = 0; i <= 0x1C8; i += 4)
316 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dc, i));
317 	printf("*** DCTEMPL ***\n");
318 	for (i = 0; i <= 0x100; i += 4)
319 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dctmpl, i));
320 #endif
321 }
322 
323 static void
imx51_ipuv3_dc_display_config(struct imx51_ipuv3_softc * sc,int width)324 imx51_ipuv3_dc_display_config(struct imx51_ipuv3_softc *sc, int width)
325 {
326 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
327 
328 	IPUV3_WRITE(sc, dc, IPU_DC_DISP_CONF2_0, width);
329 }
330 
331 static void
imx51_ipuv3_di_sync_conf(struct imx51_ipuv3_softc * sc,int no,uint32_t reg_gen0,uint32_t reg_gen1,uint32_t repeat)332 imx51_ipuv3_di_sync_conf(struct imx51_ipuv3_softc *sc, int no,
333     uint32_t reg_gen0, uint32_t reg_gen1, uint32_t repeat)
334 {
335 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
336 
337 	uint32_t reg;
338 
339 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(no), reg_gen0);
340 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(no), reg_gen1);
341 	reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(no));
342 	reg &= ~DI_STP_REP(no);
343 	reg |= __SHIFTIN(repeat, DI_STP_REP(no));
344 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg);
345 
346 #ifdef IPUV3_DEBUG
347 	printf("%s: no %d\n", __func__, no);
348 	printf("%s: addr 0x%08X reg_gen0   0x%08X\n", __func__,
349 	    IPU_DI_SW_GEN0(no), reg_gen0);
350 	printf("%s: addr 0x%08X reg_gen1   0x%08X\n", __func__,
351 	    IPU_DI_SW_GEN1(no), reg_gen1);
352 	printf("%s: addr 0x%08X DI_STP_REP 0x%08X\n", __func__,
353 	    IPU_DI_STP_REP(no), reg);
354 #endif
355 }
356 
357 static void
imx51_ipuv3_di_init(struct imx51_ipuv3_softc * sc)358 imx51_ipuv3_di_init(struct imx51_ipuv3_softc *sc)
359 {
360 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
361 
362 	uint32_t reg;
363 	uint32_t div;
364 	u_int ipuclk;
365 	const struct lcd_panel_geometry *geom = sc->geometry;
366 
367 #if NIMXCCM > 0
368 	ipuclk = imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT);
369 #elif !defined(IMX51_IPU_HSP_CLOCK)
370 #error	IMX51_CPU_HSP_CLOCK need to be defined.
371 #else
372 	ipuclk = IMX51_IPU_HSP_CLOCK;
373 #endif
374 	DPRINTFN(3, ("IPU HSP clock = %d\n", ipuclk));
375 	div = (ipuclk * 16) / geom->pixel_clk;
376 	div = div < 16 ? 16 : div & 0xff8;
377 
378 	/* DI counter */
379 	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
380 	reg &= ~(CM_DISP_GEN_DI1_COUNTER_RELEASE |
381 	    CM_DISP_GEN_DI0_COUNTER_RELEASE);
382 	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
383 
384 	IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div);
385 	IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN1,
386 	    __SHIFTIN(div / 16, DI_BS_CLKGEN1_DOWN));
387 #ifdef IPUV3_DEBUG
388 	printf("%s: IPU_DI_BS_CLKGEN0 = 0x%08X\n", __func__,
389 	    IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN0));
390 	printf("%s: IPU_DI_BS_CLKGEN1 = 0x%08X\n", __func__,
391 	    IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN1));
392 #endif
393 	/* Display Time settings */
394 	reg = __SHIFTIN(div / 16 - 1, DI_DW_GEN_ACCESS_SIZE) |
395 	    __SHIFTIN(div / 16 - 1, DI_DW_GEN_COMPONNENT_SIZE) |
396 	    __SHIFTIN(3, DI_DW_GEN_PIN(15));
397 	IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg);
398 #ifdef IPUV3_DEBUG
399 	printf("%s: div = %d\n", __func__, div);
400 	printf("%s: IPU_DI_DW_GEN(0) 0x%08X = 0x%08X\n", __func__,
401 	    IPU_DI_DW_GEN(0), reg);
402 #endif
403 
404 	/* Up & Down Data Wave Set */
405 	reg = __SHIFTIN(div / 16 * 2, DI_DW_SET_DOWN);
406 	IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg);
407 #ifdef IPUV3_DEBUG
408 	printf("%s: IPU_DI_DW_SET(0, 3) 0x%08X = 0x%08X\n", __func__,
409 	    IPU_DI_DW_SET(0, 3), reg);
410 #endif
411 
412 	/* internal HSCYNC */
413 	imx51_ipuv3_di_sync_conf(sc, 1,
414 	    __DI_SW_GEN0(geom->panel_width + geom->hsync_width +
415 		geom->left + geom->right - 1, 1, 0, 0),
416 	    __DI_SW_GEN1(0, 1, 0, 0, 0, 0, 0),
417 	    0);
418 
419 	/* HSYNC */
420 	imx51_ipuv3_di_sync_conf(sc, 2,
421 	    __DI_SW_GEN0(geom->panel_width + geom->hsync_width +
422 		geom->left + geom->right - 1, 1, 0, 1),
423 	    __DI_SW_GEN1(1, 1, 0, geom->hsync_width * 2, 1, 0, 0),
424 	    0);
425 
426 	/* VSYNC */
427 	imx51_ipuv3_di_sync_conf(sc, 3,
428 	    __DI_SW_GEN0(geom->panel_height + geom->vsync_width +
429 		geom->upper + geom->lower - 1, 2, 0, 0),
430 	    __DI_SW_GEN1(1, 1, 0, geom->vsync_width * 2, 2, 0, 0),
431 	    0);
432 
433 	IPUV3_WRITE(sc, di0, IPU_DI_SCR_CONF,
434 	    geom->panel_height + geom->vsync_width + geom->upper +
435 	    geom->lower - 1);
436 
437 	/* Active Lines Start */
438 	imx51_ipuv3_di_sync_conf(sc, 4,
439 	    __DI_SW_GEN0(0, 3, geom->vsync_width + geom->upper, 3),
440 	    __DI_SW_GEN1(0, 0, 4, 0, 0, 0, 0),
441 	    geom->panel_height);
442 
443 	/* Active Clock Start */
444 	imx51_ipuv3_di_sync_conf(sc, 5,
445 	    __DI_SW_GEN0(0, 1, geom->hsync_width + geom->left, 1),
446 	    __DI_SW_GEN1(0, 0, 5, 0, 0, 0, 0),
447 	    geom->panel_width);
448 
449 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(6), 0);
450 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(6), 0);
451 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(7), 0);
452 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(7), 0);
453 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(8), 0);
454 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(8), 0);
455 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(9), 0);
456 	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(9), 0);
457 
458 	reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(6));
459 	reg &= ~DI_STP_REP(6);
460 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg);
461 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(7), 0);
462 	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(9), 0);
463 
464 	IPUV3_WRITE(sc, di0, IPU_DI_GENERAL, 0);
465 	reg = __SHIFTIN(3 - 1, DI_SYNC_AS_GEN_VSYNC_SEL) |
466 	    __SHIFTIN(0x2, DI_SYNC_AS_GEN_SYNC_START);
467 	IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg);
468 	IPUV3_WRITE(sc, di0, IPU_DI_POL, DI_POL_DRDY_POLARITY_15);
469 
470 	/* release DI counter */
471 	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
472 	reg |= CM_DISP_GEN_DI0_COUNTER_RELEASE;
473 	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
474 
475 #ifdef IPUV3_DEBUG
476 	int i;
477 	printf("*** DI0 ***\n");
478 	for (i = 0; i <= 0x174; i += 4)
479 		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, di0, i));
480 
481 	printf("%s: IPU_CM_DISP_GEN    : 0x%08X\n", __func__,
482 	    IPUV3_READ(sc, cm, IPU_CM_DISP_GEN));
483 	printf("%s: IPU_DI_SYNC_AS_GEN : 0x%08X\n", __func__,
484 	    IPUV3_READ(sc, di0, IPU_DI_SYNC_AS_GEN));
485 	printf("%s: IPU_DI_GENERAL     : 0x%08X\n", __func__,
486 	    IPUV3_READ(sc, di0, IPU_DI_GENERAL));
487 	printf("%s: IPU_DI_POL         : 0x%08X\n", __func__,
488 	    IPUV3_READ(sc, di0, IPU_DI_POL));
489 #endif
490 }
491 
492 
493 void
imx51_ipuv3_geometry(struct imx51_ipuv3_softc * sc,const struct lcd_panel_geometry * geom)494 imx51_ipuv3_geometry(struct imx51_ipuv3_softc *sc,
495     const struct lcd_panel_geometry *geom)
496 {
497 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
498 
499 	sc->geometry = geom;
500 
501 #ifdef IPUV3_DEBUG
502 	printf("%s: screen height = %d\n",__func__ , geom->panel_height);
503 	printf("%s:        width  = %d\n",__func__ , geom->panel_width);
504 	printf("%s: IPU Clock = %d\n", __func__,
505 	    imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT));
506 	printf("%s: Pixel Clock = %d\n", __func__, geom->pixel_clk);
507 #endif
508 
509 	imx51_ipuv3_di_init(sc);
510 
511 #ifdef IPUV3_DEBUG
512 	printf("%s: IPU_CM_DISP_GEN    : 0x%08X\n", __func__,
513 	    IPUV3_READ(sc, cm, IPU_CM_DISP_GEN));
514 #endif
515 
516 	imx51_ipuv3_dc_display_config(sc, geom->panel_width);
517 
518 	return;
519 }
520 
521 /*
522  * Initialize the IPUV3 controller.
523  */
524 static void
imx51_ipuv3_initialize(struct imx51_ipuv3_softc * sc,const struct lcd_panel_geometry * geom)525 imx51_ipuv3_initialize(struct imx51_ipuv3_softc *sc,
526     const struct lcd_panel_geometry *geom)
527 {
528 	uint32_t reg;
529 
530 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
531 
532 	IPUV3_WRITE(sc, cm, IPU_CM_CONF, 0);
533 
534 	/* reset */
535 	IPUV3_WRITE(sc, cm, IPU_CM_MEM_RST, CM_MEM_START | CM_MEM_EN);
536 	while (IPUV3_READ(sc, cm, IPU_CM_MEM_RST) & CM_MEM_START)
537 		; /* wait */
538 
539 	imx51_ipuv3_dmfc_init(sc);
540 	imx51_ipuv3_dc_init(sc);
541 
542 	imx51_ipuv3_geometry(sc, geom);
543 
544 	/* set global alpha */
545 	IPUV3_WRITE(sc, dp, IPU_DP_GRAPH_WIND_CTRL_SYNC, 0x80 << 24);
546 	IPUV3_WRITE(sc, dp, IPU_DP_COM_CONF_SYNC, DP_DP_GWAM_SYNC);
547 
548 	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
549 	reg |= CM_DISP_GEN_MCU_MAX_BURST_STOP |
550 	    __SHIFTIN(0x8, CM_DISP_GEN_MCU_T);
551 	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
552 }
553 
554 static int
imx51_ipuv3_print(void * aux,const char * pnp)555 imx51_ipuv3_print(void *aux, const char *pnp)
556 {
557 	const struct imxfb_attach_args * const ifb = aux;
558 
559 	aprint_normal(" output %s", device_xname(ifb->ifb_outputdev));
560 
561 	return UNCONF;
562 }
563 
564 /*
565  * Common driver attachment code.
566  */
567 void
imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc * sc,struct axi_attach_args * axia,const struct lcd_panel_geometry * geom)568 imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc *sc,
569     struct axi_attach_args *axia, const struct lcd_panel_geometry *geom)
570 {
571 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
572 
573 	bus_space_tag_t iot = axia->aa_iot;
574 	int error;
575 
576 	aprint_normal(": i.MX51 IPUV3 controller\n");
577 
578 	sc->n_screens = 0;
579 	LIST_INIT(&sc->screens);
580 
581 	sc->iot = iot;
582 	sc->dma_tag = &arm_generic_dma_tag;
583 
584 	/* map controller registers */
585 	error = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &sc->cm_ioh);
586 	if (error)
587 		goto fail_retarn_cm;
588 
589 	/* map Display Multi FIFO Controller registers */
590 	error = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &sc->dmfc_ioh);
591 	if (error)
592 		goto fail_retarn_dmfc;
593 
594 	/* map Display Interface registers */
595 	error = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &sc->di0_ioh);
596 	if (error)
597 		goto fail_retarn_di0;
598 
599 	/* map Display Processor registers */
600 	error = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &sc->dp_ioh);
601 	if (error)
602 		goto fail_retarn_dp;
603 
604 	/* map Display Controller registers */
605 	error = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &sc->dc_ioh);
606 	if (error)
607 		goto fail_retarn_dc;
608 
609 	/* map Image DMA Controller registers */
610 	error = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &sc->idmac_ioh);
611 	if (error)
612 		goto fail_retarn_idmac;
613 
614 	/* map CPMEM registers */
615 	error = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &sc->cpmem_ioh);
616 	if (error)
617 		goto fail_retarn_cpmem;
618 
619 	/* map DCTEMPL registers */
620 	error = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &sc->dctmpl_ioh);
621 	if (error)
622 		goto fail_retarn_dctmpl;
623 
624 #ifdef notyet
625 	sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
626 	    ipuv3intr, sc);
627 	if (sc->ih == NULL) {
628 		aprint_error_dev(sc->dev,
629 		    "unable to establish interrupt at irq %d\n",
630 		    IMX51_INT_IPUV3);
631 		return;
632 	}
633 #endif
634 
635 	imx51_ipuv3_initialize(sc, geom);
636 
637 	struct imx51_ipuv3_screen *scr;
638 	error = imx51_ipuv3_new_screen(sc, &scr);
639 	if (error) {
640 		aprint_error_dev(sc->dev,
641 		    "unable to create new screen (errno=%d)", error);
642 		return;
643 	}
644 	sc->active = scr;
645 
646 	imx51_ipuv3_start_dma(sc, scr);
647 
648 	struct imxfb_attach_args ifb = {
649 		.ifb_dmat      = sc->dma_tag,
650 		.ifb_dmamap    = scr->dma,
651 		.ifb_dmasegs   = scr->segs,
652 		.ifb_ndmasegs  = scr->nsegs,
653 		.ifb_fb	       = scr->buf_va,
654 		.ifb_width     = geom->panel_width,
655 		.ifb_height    = geom->panel_height,
656 		.ifb_depth     = scr->depth,
657 		.ifb_stride    = geom->panel_width * (scr->depth / 8),
658 		.ifb_outputdev = sc->dev,
659 	};
660 
661 	sc->fbdev = config_found(sc->dev, &ifb, imx51_ipuv3_print, CFARGS_NONE);
662 
663 	return;
664 
665 fail_retarn_dctmpl:
666 	bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
667 fail_retarn_cpmem:
668 	bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
669 fail_retarn_idmac:
670 	bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
671 fail_retarn_dp:
672 	bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
673 fail_retarn_dc:
674 	bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
675 fail_retarn_di0:
676 	bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
677 fail_retarn_dmfc:
678 	bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
679 fail_retarn_cm:
680 	aprint_error_dev(sc->dev,
681 	    "failed to map registers (errno=%d)\n", error);
682 	return;
683 }
684 
685 #ifdef notyet
686 /*
687  * Interrupt handler.
688  */
689 int
ipuv3intr(void * arg)690 ipuv3intr(void *arg)
691 {
692 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
693 
694 	struct imx51_ipuv3_softc *sc = (struct imx51_ipuv3_softc *)arg;
695 	bus_space_tag_t iot = sc->iot;
696 	bus_space_handle_t ioh = sc->dc_ioh;
697 	uint32_t status;
698 
699 	status = IPUV3_READ(ioh, V3CR);
700 	/* Clear stickey status bits */
701 	IPUV3_WRITE(ioh, V3CR, status);
702 
703 	return 1;
704 }
705 #endif
706 
707 static void
imx51_ipuv3_write_dmaparam(struct imx51_ipuv3_softc * sc,int ch,uint32_t * value,int size)708 imx51_ipuv3_write_dmaparam(struct imx51_ipuv3_softc *sc,
709     int ch, uint32_t *value, int size)
710 {
711 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
712 
713 	int i;
714 	uint32_t addr = ch * 0x40;
715 
716 	for (i = 0; i < size; i++) {
717 		IPUV3_WRITE(sc, cpmem, addr + ((i % 5) * 0x4) +
718 		    ((i / 5) * 0x20), value[i]);
719 #ifdef IPUV3_DEBUG
720 		printf("%s: addr = 0x%08X, val = 0x%08X\n", __func__,
721 		    addr + ((i % 5) * 0x4) + ((i / 5) * 0x20),
722 		    IPUV3_READ(sc, cpmem, addr + ((i % 5) * 0x4) +
723 			((i / 5) * 0x20)));
724 #endif
725 	}
726 }
727 
728 static void
imx51_ipuv3_build_param(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen * scr,uint32_t * params)729 imx51_ipuv3_build_param(struct imx51_ipuv3_softc *sc,
730     struct imx51_ipuv3_screen *scr,
731     uint32_t *params)
732 {
733 	const struct lcd_panel_geometry *geom = sc->geometry;
734 
735 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
736 
737 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FW,
738 	    (geom->panel_width - 1));
739 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FH,
740 	    (geom->panel_height - 1));
741 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA0,
742 	    scr->segs[0].ds_addr >> 3);
743 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA1,
744 	    scr->segs[0].ds_addr >> 3);
745 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_SL,
746 	    (scr->stride - 1));
747 
748 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_PFS, 0x7);
749 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_NPB, 32 - 1);
750 
751 	switch (scr->depth) {
752 	case 32:
753 		/* ARBG888 */
754 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x0);
755 
756 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
757 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8);
758 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16);
759 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24);
760 
761 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1);
762 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1);
763 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1);
764 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 8 - 1);
765 		break;
766 	case 24:
767 		/* RBG888 */
768 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x1);
769 
770 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
771 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8);
772 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16);
773 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24);
774 
775 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1);
776 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1);
777 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1);
778 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0);
779 		break;
780 	case 16:
781 		/* RBG565 */
782 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x3);
783 
784 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
785 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 5);
786 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 11);
787 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 16);
788 
789 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 5 - 1);
790 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 6 - 1);
791 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 5 - 1);
792 		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0);
793 		break;
794 	default:
795 		panic("%s: unsupported depth %d\n", __func__, scr->depth);
796 		break;
797 	}
798 
799 	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_ID, 1);
800 }
801 
802 static void
imx51_ipuv3_set_idma_param(uint32_t * params,uint32_t name,uint32_t val)803 imx51_ipuv3_set_idma_param(uint32_t *params, uint32_t name, uint32_t val)
804 {
805 	int word = (name >> 16) & 0xff;
806 	int shift = (name >> 8) & 0xff;
807 	int width = name & 0xff;
808 	int index;
809 
810 	index = word * 5;
811 	index += shift / 32;
812 	shift = shift % 32;
813 
814 	params[index] |= val << shift;
815 	shift = 32 - shift;
816 
817 	if (width > shift)
818 		params[index+1] |= val >> shift;
819 }
820 
821 /*
822  * Enable DMA to cause the display to be refreshed periodically.
823  * This brings the screen to life...
824  */
825 void
imx51_ipuv3_start_dma(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen * scr)826 imx51_ipuv3_start_dma(struct imx51_ipuv3_softc *sc,
827     struct imx51_ipuv3_screen *scr)
828 {
829 	int save;
830 	uint32_t params[10];
831 	uint32_t reg;
832 
833 	DPRINTFN(3, ("%s: Pixel depth = %d\n", __func__, scr->depth));
834 
835 	reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);
836 	reg &= ~__BIT(CH_PANNEL_BG);
837 	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
838 
839 	memset(params, 0, sizeof(params));
840 	imx51_ipuv3_build_param(sc, scr, params);
841 
842 	save = disable_interrupts(I32_bit);
843 
844 	/* IDMAC configuration */
845 	imx51_ipuv3_write_dmaparam(sc, CH_PANNEL_BG, params,
846 	    sizeof(params) / sizeof(params[0]));
847 
848 	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_PRI_1, __BIT(CH_PANNEL_BG));
849 
850 	/* double buffer */
851 	reg = IPUV3_READ(sc, cm, IPU_CM_CH_DB_MODE_SEL_0);
852 	reg |= __BIT(CH_PANNEL_BG);
853 	IPUV3_WRITE(sc, cm, IPU_CM_CH_DB_MODE_SEL_0, reg);
854 
855 	reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);
856 	reg |= __BIT(CH_PANNEL_BG);
857 	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
858 
859 	reg = IPUV3_READ(sc, cm, IPU_CM_GPR);
860 	reg &= ~CM_GPR_IPU_CH_BUF0_RDY0_CLR;
861 	IPUV3_WRITE(sc, cm, IPU_CM_GPR, reg);
862 
863 	IPUV3_WRITE(sc, cm, IPU_CM_CUR_BUF_0, __BIT(CH_PANNEL_BG));
864 
865 	restore_interrupts(save);
866 
867 	imx51_ipuv3_enable_display(sc);
868 
869 #ifdef IPUV3_DEBUG
870 	imx51_ipuv3_dump(sc);
871 #endif
872 }
873 
874 static int
imx51_ipuv3_allocmem(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen * scr)875 imx51_ipuv3_allocmem(struct imx51_ipuv3_softc *sc,
876     struct imx51_ipuv3_screen *scr)
877 {
878 	int error;
879 
880 	error = bus_dmamem_alloc(sc->dma_tag, scr->buf_size, PAGE_SIZE, 0,
881 	    scr->segs, 1, &scr->nsegs, BUS_DMA_WAITOK);
882 	if (error)
883 		return error;
884 	error = bus_dmamem_map(sc->dma_tag, scr->segs, scr->nsegs, scr->buf_size,
885 	    (void **)&scr->buf_va, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
886 	if (error)
887 		goto free;
888 	/* map memory for DMA */
889 	error = bus_dmamap_create(sc->dma_tag, scr->buf_size, 1, scr->buf_size, 0,
890 	    BUS_DMA_WAITOK, &scr->dma);
891 	if (error)
892 		goto unmap;
893 	error = bus_dmamap_load(sc->dma_tag, scr->dma, scr->buf_va, scr->buf_size,
894 	    NULL, BUS_DMA_WAITOK);
895 	if (error)
896 		goto destroy;
897 
898 	memset(scr->buf_va, 0, scr->buf_size);
899 
900 	return 0;
901 
902 destroy:
903 	bus_dmamap_destroy(sc->dma_tag, scr->dma);
904 unmap:
905 	bus_dmamem_unmap(sc->dma_tag, scr->buf_va, scr->buf_size);
906 free:
907 	bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs);
908 
909 	scr->buf_size = 0;
910 	scr->buf_va = NULL;
911 
912 	return error;
913 }
914 
915 /*
916  * Create and initialize a new screen buffer.
917  */
918 int
imx51_ipuv3_new_screen(struct imx51_ipuv3_softc * sc,struct imx51_ipuv3_screen ** scrpp)919 imx51_ipuv3_new_screen(struct imx51_ipuv3_softc *sc,
920     struct imx51_ipuv3_screen **scrpp)
921 {
922 	const struct lcd_panel_geometry *geometry;
923 	struct imx51_ipuv3_screen *scr = NULL;
924 	int depth, width, height;
925 	int error;
926 
927 	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
928 
929 	geometry = sc->geometry;
930 
931 	depth = geometry->depth;
932 	width = geometry->panel_width;
933 	height = geometry->panel_height;
934 
935 	scr = kmem_zalloc(sizeof(*scr), KM_SLEEP);
936 	scr->nsegs = 0;
937 	scr->depth = depth;
938 	scr->stride = width * depth / 8;
939 	scr->buf_size = scr->stride * height;
940 	scr->buf_va = NULL;
941 
942 	error = imx51_ipuv3_allocmem(sc, scr);
943 	if (error) {
944 		aprint_error_dev(sc->dev,
945 		    "failed to allocate %u bytes of video memory: %d\n",
946 		    scr->stride * height, error);
947 		kmem_free(scr, sizeof(*scr));
948 		return error;
949 	}
950 
951 	LIST_INSERT_HEAD(&sc->screens, scr, link);
952 	sc->n_screens++;
953 
954 #ifdef IPUV3_DEBUG
955 	printf("%s: screen buffer width  %d\n", __func__, width);
956 	printf("%s: screen buffer height %d\n", __func__, height);
957 	printf("%s: screen buffer depth  %d\n", __func__, depth);
958 	printf("%s: screen buffer stride %d\n", __func__, scr->stride);
959 	printf("%s: screen buffer size   0x%08X\n", __func__,
960 	    (uint32_t)scr->buf_size);
961 	printf("%s: screen buffer addr virtual  %p\n", __func__, scr->buf_va);
962 	printf("%s: screen buffer addr physical %p\n", __func__,
963 	    (void *)scr->segs[0].ds_addr);
964 #endif
965 
966 	scr->map_size = scr->buf_size;		/* used when unmap this. */
967 
968 	*scrpp = scr;
969 
970 	return 0;
971 }
972