1 /* $NetBSD: gemini_pci.c,v 1.19 2018/11/16 15:06:22 jmcneill Exp $ */ 2 3 /* adapted from: 4 * NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp 5 */ 6 7 /* 8 * Copyright (c) 2001 Wasabi Systems, Inc. 9 * All rights reserved. 10 * 11 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed for the NetBSD Project by 24 * Wasabi Systems, Inc. 25 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 26 * or promote products derived from this software without specific prior 27 * written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * PCI configuration support for i80312 Companion I/O chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.19 2018/11/16 15:06:22 jmcneill Exp $"); 48 49 #include "opt_gemini.h" 50 #include "opt_pci.h" 51 #include "pci.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/extent.h> 57 #include <sys/malloc.h> 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 #include <dev/pci/pciconf.h> 66 67 #include <arm/locore.h> 68 69 #include <arm/pic/picvar.h> 70 71 #include <arm/gemini/gemini_reg.h> 72 #include <arm/gemini/gemini_pcivar.h> 73 #include <arm/gemini/gemini_obiovar.h> 74 75 void gemini_pci_attach_hook(device_t, device_t, 76 struct pcibus_attach_args *); 77 int gemini_pci_bus_maxdevs(void *, int); 78 pcitag_t gemini_pci_make_tag(void *, int, int, int); 79 void gemini_pci_decompose_tag(void *, pcitag_t, int *, int *, 80 int *); 81 pcireg_t gemini_pci_conf_read(void *, pcitag_t, int); 82 void gemini_pci_conf_write(void *, pcitag_t, int, pcireg_t); 83 int gemini_pci_conf_hook(void *, int, int, int, pcireg_t); 84 void gemini_pci_conf_interrupt(void *, int, int, int, int, int *); 85 86 int gemini_pci_intr_map(const struct pci_attach_args *, 87 pci_intr_handle_t *); 88 const char *gemini_pci_intr_string(void *, pci_intr_handle_t, 89 char *, size_t); 90 const struct evcnt *gemini_pci_intr_evcnt(void *, pci_intr_handle_t); 91 void *gemini_pci_intr_establish(void *, pci_intr_handle_t, 92 int, int (*)(void *), void *, const char *); 93 void gemini_pci_intr_disestablish(void *, void *); 94 int gemini_pci_intr_handler(void *v); 95 96 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 97 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 98 99 struct gemini_pci_intrq { 100 SIMPLEQ_ENTRY(gemini_pci_intrq) iq_q; 101 int (*iq_func)(void *); 102 void *iq_arg; 103 void *iq_ih; 104 }; 105 106 static SIMPLEQ_HEAD(, gemini_pci_intrq) gemini_pci_intrq = 107 SIMPLEQ_HEAD_INITIALIZER(gemini_pci_intrq); 108 109 static inline int 110 gemini_pci_intrq_empty(void) 111 { 112 return SIMPLEQ_EMPTY(&gemini_pci_intrq); 113 } 114 115 static inline void * 116 gemini_pci_intrq_insert(void *ih, int (*func)(void *), void *arg) 117 { 118 struct gemini_pci_intrq *iqp; 119 120 iqp = malloc(sizeof(*iqp), M_DEVBUF, M_NOWAIT|M_ZERO); 121 if (iqp == NULL) { 122 printf("gemini_pci_intrq_insert: malloc failed\n"); 123 return NULL; 124 } 125 126 iqp->iq_func = func; 127 iqp->iq_arg = arg; 128 iqp->iq_ih = ih; 129 SIMPLEQ_INSERT_TAIL(&gemini_pci_intrq, iqp, iq_q); 130 131 return (void *)iqp; 132 } 133 134 static inline void 135 gemini_pci_intrq_remove(void *cookie) 136 { 137 struct gemini_pci_intrq *iqp; 138 139 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 140 if ((void *)iqp == cookie) { 141 SIMPLEQ_REMOVE(&gemini_pci_intrq, 142 iqp, gemini_pci_intrq, iq_q); 143 free(iqp, M_DEVBUF); 144 return; 145 } 146 } 147 } 148 149 static inline int 150 gemini_pci_intrq_dispatch(void) 151 { 152 struct gemini_pci_intrq *iqp; 153 154 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) { 155 (*iqp->iq_func)(iqp->iq_arg); 156 } 157 158 return 1; 159 } 160 161 void 162 gemini_pci_init(pci_chipset_tag_t pc, void *cookie) 163 { 164 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 165 struct obio_softc *sc = cookie; 166 struct extent *ioext, *memext; 167 #endif 168 169 pc->pc_conf_v = cookie; 170 pc->pc_attach_hook = gemini_pci_attach_hook; 171 pc->pc_bus_maxdevs = gemini_pci_bus_maxdevs; 172 pc->pc_make_tag = gemini_pci_make_tag; 173 pc->pc_decompose_tag = gemini_pci_decompose_tag; 174 pc->pc_conf_read = gemini_pci_conf_read; 175 pc->pc_conf_write = gemini_pci_conf_write; 176 177 pc->pc_intr_v = cookie; 178 pc->pc_intr_map = gemini_pci_intr_map; 179 pc->pc_intr_string = gemini_pci_intr_string; 180 pc->pc_intr_evcnt = gemini_pci_intr_evcnt; 181 pc->pc_intr_establish = gemini_pci_intr_establish; 182 pc->pc_intr_disestablish = gemini_pci_intr_disestablish; 183 184 pc->pc_conf_hook = gemini_pci_conf_hook; 185 pc->pc_conf_interrupt = gemini_pci_conf_interrupt; 186 187 /* 188 * initialize copy of CFG_CMD 189 */ 190 sc->sc_pci_chipset.pc_cfg_cmd = 191 gemini_pci_conf_read(sc, 0, GEMINI_PCI_CFG_CMD); 192 193 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 194 /* 195 * Configure the PCI bus. 196 * 197 * XXX We need to revisit this. We only configure the Secondary 198 * bus (and its children). The bus configure code needs changes 199 * to support how the busses are arranged on this chip. We also 200 * need to only configure devices in the private device space on 201 * the Secondary bus. 202 */ 203 204 aprint_normal("%s: configuring Secondary PCI bus\n", 205 device_xname(sc->sc_dev)); 206 207 /* 208 * XXX PCI IO addr should be inherited ? 209 */ 210 ioext = extent_create("pciio", 211 GEMINI_PCIIO_BASE, 212 GEMINI_PCIIO_BASE + GEMINI_PCIIO_SIZE - 1, 213 NULL, 0, EX_NOWAIT); 214 215 /* 216 * XXX PCI mem addr should be inherited ? 217 */ 218 memext = extent_create("pcimem", 219 GEMINI_PCIMEM_BASE, 220 GEMINI_PCIMEM_BASE + GEMINI_PCIMEM_SIZE - 1, 221 NULL, 0, EX_NOWAIT); 222 223 pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align); 224 225 gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1, 226 PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024))) 227 | gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024)); 228 229 extent_destroy(ioext); 230 extent_destroy(memext); 231 #endif 232 } 233 234 void 235 gemini_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 236 { 237 } 238 239 int 240 gemini_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id) 241 { 242 int rv; 243 244 rv = PCI_CONF_ALL; 245 246 return rv; 247 } 248 249 void 250 gemini_pci_attach_hook(device_t parent, device_t self, 251 struct pcibus_attach_args *pba) 252 { 253 /* Nothing to do. */ 254 } 255 256 int 257 gemini_pci_bus_maxdevs(void *v, int busno) 258 { 259 return (32); 260 } 261 262 pcitag_t 263 gemini_pci_make_tag(void *v, int b, int d, int f) 264 { 265 return ((b << 16) | (d << 11) | (f << 8)); 266 } 267 268 void 269 gemini_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 270 { 271 if (bp != NULL) 272 *bp = (tag >> 16) & 0xff; 273 if (dp != NULL) 274 *dp = (tag >> 11) & 0x1f; 275 if (fp != NULL) 276 *fp = (tag >> 8) & 0x7; 277 } 278 279 struct pciconf_state { 280 uint32_t ps_addr_val; 281 int ps_b, ps_d, ps_f; 282 }; 283 284 static int 285 gemini_pci_conf_setup(struct obio_softc *sc, pcitag_t tag, int offset, 286 struct pciconf_state *ps) 287 { 288 289 if ((unsigned int)offset >= PCI_CONF_SIZE) 290 return (1); 291 292 gemini_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 293 294 ps->ps_addr_val = 295 PCI_CFG_CMD_ENB 296 | PCI_CFG_CMD_BUSn(ps->ps_b) 297 | PCI_CFG_CMD_DEVn(ps->ps_d) 298 | PCI_CFG_CMD_FUNCn(ps->ps_f) 299 | PCI_CFG_CMD_REGn(offset); 300 301 return (0); 302 } 303 304 pcireg_t 305 gemini_pci_conf_read(void *v, pcitag_t tag, int offset) 306 { 307 struct obio_softc *sc = v; 308 struct pciconf_state ps; 309 vaddr_t va; 310 pcireg_t rv; 311 u_int s; 312 313 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 314 return ((pcireg_t) -1); 315 316 PCI_CONF_LOCK(s); 317 318 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 319 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 320 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 321 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 322 } 323 324 va = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_pcicfg_ioh); 325 if (badaddr_read((void *) (va + GEMINI_PCI_CFG_DATA), sizeof(rv), &rv)) { 326 /* 327 * XXX Clear the Master Abort 328 */ 329 #if 1 330 printf("conf_read: %d/%d/%d bad address\n", 331 ps.ps_b, ps.ps_d, ps.ps_f); 332 #endif 333 rv = (pcireg_t) -1; 334 } 335 336 PCI_CONF_UNLOCK(s); 337 338 return (rv); 339 } 340 341 void 342 gemini_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 343 { 344 struct obio_softc *sc = v; 345 struct pciconf_state ps; 346 u_int s; 347 348 if (gemini_pci_conf_setup(sc, tag, offset, &ps)) 349 return; 350 351 PCI_CONF_LOCK(s); 352 353 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) { 354 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val; 355 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 356 GEMINI_PCI_CFG_CMD, ps.ps_addr_val); 357 } 358 359 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh, 360 GEMINI_PCI_CFG_DATA, val); 361 362 PCI_CONF_UNLOCK(s); 363 } 364 365 int 366 gemini_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 367 { 368 int irq; 369 370 irq = 8; 371 372 *ihp = irq; 373 return 0; 374 } 375 376 const char * 377 gemini_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 378 { 379 strlcpy(buf, "pci", len); 380 return buf; 381 } 382 383 const struct evcnt * 384 gemini_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 385 { 386 return NULL; 387 } 388 389 void * 390 gemini_pci_intr_establish(void *v, pci_intr_handle_t pci_ih, int ipl, 391 int (*func)(void *), void *arg, const char *xname) 392 { 393 pcireg_t r; 394 void *ih=NULL; 395 int irq; 396 void *cookie; 397 398 irq = (int)pci_ih; 399 400 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 401 r |= CFG_REG_CTL2_INTMASK_INT_ABCD; 402 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 403 404 if (gemini_pci_intrq_empty()) 405 ih = intr_establish_xname(irq, ipl, IST_LEVEL_HIGH, 406 gemini_pci_intr_handler, v, xname); 407 408 cookie = gemini_pci_intrq_insert(ih, func, arg); 409 if (cookie == NULL) { 410 if (gemini_pci_intrq_empty()) 411 intr_disestablish(ih); 412 } 413 414 return cookie; 415 } 416 417 void 418 gemini_pci_intr_disestablish(void *v, void *cookie) 419 { 420 pcireg_t r; 421 struct gemini_pci_intrq *iqp = (struct gemini_pci_intrq *)cookie; 422 void *ih = iqp->iq_ih; 423 424 gemini_pci_intrq_remove(cookie); 425 if (gemini_pci_intrq_empty()) { 426 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 427 r &= ~CFG_REG_CTL2_INTMASK_INT_ABCD; 428 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 429 intr_disestablish(ih); 430 } 431 } 432 433 int 434 gemini_pci_intr_handler(void *v) 435 { 436 pcireg_t r; 437 int rv; 438 439 /* 440 * dispatch PCI device interrupt handlers 441 */ 442 rv = gemini_pci_intrq_dispatch(); 443 444 /* 445 * ack Gemini PCI interrupts 446 */ 447 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2); 448 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r); 449 450 return rv; 451 } 452