1 /* $NetBSD: gemini_pci.c,v 1.23 2020/11/20 18:10:07 thorpej Exp $ */
2
3 /* adapted from:
4 * NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp
5 */
6
7 /*
8 * Copyright (c) 2001 Wasabi Systems, Inc.
9 * All rights reserved.
10 *
11 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed for the NetBSD Project by
24 * Wasabi Systems, Inc.
25 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
26 * or promote products derived from this software without specific prior
27 * written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42 /*
43 * PCI configuration support for i80312 Companion I/O chip.
44 */
45
46 #include <sys/cdefs.h>
47 __KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.23 2020/11/20 18:10:07 thorpej Exp $");
48
49 #include "opt_gemini.h"
50 #include "opt_pci.h"
51 #include "pci.h"
52
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/device.h>
56 #include <sys/kmem.h>
57 #include <sys/bus.h>
58 #include <sys/intr.h>
59
60 #include <uvm/uvm_extern.h>
61
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pcidevs.h>
64 #include <dev/pci/pciconf.h>
65
66 #include <arm/locore.h>
67
68 #include <arm/pic/picvar.h>
69
70 #include <arm/gemini/gemini_reg.h>
71 #include <arm/gemini/gemini_pcivar.h>
72 #include <arm/gemini/gemini_obiovar.h>
73
74 void gemini_pci_attach_hook(device_t, device_t,
75 struct pcibus_attach_args *);
76 int gemini_pci_bus_maxdevs(void *, int);
77 pcitag_t gemini_pci_make_tag(void *, int, int, int);
78 void gemini_pci_decompose_tag(void *, pcitag_t, int *, int *,
79 int *);
80 pcireg_t gemini_pci_conf_read(void *, pcitag_t, int);
81 void gemini_pci_conf_write(void *, pcitag_t, int, pcireg_t);
82 int gemini_pci_conf_hook(void *, int, int, int, pcireg_t);
83 void gemini_pci_conf_interrupt(void *, int, int, int, int, int *);
84
85 int gemini_pci_intr_map(const struct pci_attach_args *,
86 pci_intr_handle_t *);
87 const char *gemini_pci_intr_string(void *, pci_intr_handle_t,
88 char *, size_t);
89 const struct evcnt *gemini_pci_intr_evcnt(void *, pci_intr_handle_t);
90 void *gemini_pci_intr_establish(void *, pci_intr_handle_t,
91 int, int (*)(void *), void *, const char *);
92 void gemini_pci_intr_disestablish(void *, void *);
93 int gemini_pci_intr_handler(void *v);
94
95 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
96 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
97
98 struct gemini_pci_intrq {
99 SIMPLEQ_ENTRY(gemini_pci_intrq) iq_q;
100 int (*iq_func)(void *);
101 void *iq_arg;
102 void *iq_ih;
103 };
104
105 static SIMPLEQ_HEAD(, gemini_pci_intrq) gemini_pci_intrq =
106 SIMPLEQ_HEAD_INITIALIZER(gemini_pci_intrq);
107
108 static inline int
gemini_pci_intrq_empty(void)109 gemini_pci_intrq_empty(void)
110 {
111 return SIMPLEQ_EMPTY(&gemini_pci_intrq);
112 }
113
114 static inline void *
gemini_pci_intrq_insert(void * ih,int (* func)(void *),void * arg)115 gemini_pci_intrq_insert(void *ih, int (*func)(void *), void *arg)
116 {
117 struct gemini_pci_intrq *iqp;
118
119 iqp = kmem_zalloc(sizeof(*iqp), KM_SLEEP);
120 iqp->iq_func = func;
121 iqp->iq_arg = arg;
122 iqp->iq_ih = ih;
123 SIMPLEQ_INSERT_TAIL(&gemini_pci_intrq, iqp, iq_q);
124
125 return (void *)iqp;
126 }
127
128 static inline void
gemini_pci_intrq_remove(void * cookie)129 gemini_pci_intrq_remove(void *cookie)
130 {
131 struct gemini_pci_intrq *iqp;
132
133 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) {
134 if ((void *)iqp == cookie) {
135 SIMPLEQ_REMOVE(&gemini_pci_intrq,
136 iqp, gemini_pci_intrq, iq_q);
137 kmem_free(iqp, sizeof(*iqp));
138 return;
139 }
140 }
141 }
142
143 static inline int
gemini_pci_intrq_dispatch(void)144 gemini_pci_intrq_dispatch(void)
145 {
146 struct gemini_pci_intrq *iqp;
147
148 SIMPLEQ_FOREACH(iqp, &gemini_pci_intrq, iq_q) {
149 (*iqp->iq_func)(iqp->iq_arg);
150 }
151
152 return 1;
153 }
154
155 void
gemini_pci_init(pci_chipset_tag_t pc,void * cookie)156 gemini_pci_init(pci_chipset_tag_t pc, void *cookie)
157 {
158 struct obio_softc *sc = cookie;
159
160 pc->pc_conf_v = cookie;
161 pc->pc_attach_hook = gemini_pci_attach_hook;
162 pc->pc_bus_maxdevs = gemini_pci_bus_maxdevs;
163 pc->pc_make_tag = gemini_pci_make_tag;
164 pc->pc_decompose_tag = gemini_pci_decompose_tag;
165 pc->pc_conf_read = gemini_pci_conf_read;
166 pc->pc_conf_write = gemini_pci_conf_write;
167
168 pc->pc_intr_v = cookie;
169 pc->pc_intr_map = gemini_pci_intr_map;
170 pc->pc_intr_string = gemini_pci_intr_string;
171 pc->pc_intr_evcnt = gemini_pci_intr_evcnt;
172 pc->pc_intr_establish = gemini_pci_intr_establish;
173 pc->pc_intr_disestablish = gemini_pci_intr_disestablish;
174
175 pc->pc_conf_hook = gemini_pci_conf_hook;
176 pc->pc_conf_interrupt = gemini_pci_conf_interrupt;
177
178 /*
179 * initialize copy of CFG_CMD
180 */
181 sc->sc_pci_chipset.pc_cfg_cmd =
182 gemini_pci_conf_read(sc, 0, GEMINI_PCI_CFG_CMD);
183
184 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
185 /*
186 * Configure the PCI bus.
187 *
188 * XXX We need to revisit this. We only configure the Secondary
189 * bus (and its children). The bus configure code needs changes
190 * to support how the busses are arranged on this chip. We also
191 * need to only configure devices in the private device space on
192 * the Secondary bus.
193 */
194
195 aprint_normal("%s: configuring Secondary PCI bus\n",
196 device_xname(sc->sc_dev));
197
198 struct pciconf_resources *pcires = pciconf_resource_init();
199
200 /*
201 * XXX PCI IO addr should be inherited ?
202 */
203 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
204 GEMINI_PCIIO_BASE, GEMINI_PCIIO_SIZE);
205
206 /*
207 * XXX PCI mem addr should be inherited ?
208 */
209 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
210 GEMINI_PCIMEM_BASE, GEMINI_PCIMEM_SIZE);
211
212 pci_configure_bus(pc, pcires, 0, arm_dcache_align);
213
214 gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1,
215 PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024)))
216 | gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024));
217
218 pciconf_resource_fini(pcires);
219 #endif
220 }
221
222 void
gemini_pci_conf_interrupt(void * v,int a,int b,int c,int d,int * p)223 gemini_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p)
224 {
225 }
226
227 int
gemini_pci_conf_hook(void * v,int bus,int device,int function,pcireg_t id)228 gemini_pci_conf_hook(void *v, int bus, int device, int function, pcireg_t id)
229 {
230 int rv;
231
232 rv = PCI_CONF_ALL;
233
234 return rv;
235 }
236
237 void
gemini_pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)238 gemini_pci_attach_hook(device_t parent, device_t self,
239 struct pcibus_attach_args *pba)
240 {
241 /* Nothing to do. */
242 }
243
244 int
gemini_pci_bus_maxdevs(void * v,int busno)245 gemini_pci_bus_maxdevs(void *v, int busno)
246 {
247 return (32);
248 }
249
250 pcitag_t
gemini_pci_make_tag(void * v,int b,int d,int f)251 gemini_pci_make_tag(void *v, int b, int d, int f)
252 {
253 return ((b << 16) | (d << 11) | (f << 8));
254 }
255
256 void
gemini_pci_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)257 gemini_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
258 {
259 if (bp != NULL)
260 *bp = (tag >> 16) & 0xff;
261 if (dp != NULL)
262 *dp = (tag >> 11) & 0x1f;
263 if (fp != NULL)
264 *fp = (tag >> 8) & 0x7;
265 }
266
267 struct pciconf_state {
268 uint32_t ps_addr_val;
269 int ps_b, ps_d, ps_f;
270 };
271
272 static int
gemini_pci_conf_setup(struct obio_softc * sc,pcitag_t tag,int offset,struct pciconf_state * ps)273 gemini_pci_conf_setup(struct obio_softc *sc, pcitag_t tag, int offset,
274 struct pciconf_state *ps)
275 {
276
277 if ((unsigned int)offset >= PCI_CONF_SIZE)
278 return (1);
279
280 gemini_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
281
282 ps->ps_addr_val =
283 PCI_CFG_CMD_ENB
284 | PCI_CFG_CMD_BUSn(ps->ps_b)
285 | PCI_CFG_CMD_DEVn(ps->ps_d)
286 | PCI_CFG_CMD_FUNCn(ps->ps_f)
287 | PCI_CFG_CMD_REGn(offset);
288
289 return (0);
290 }
291
292 pcireg_t
gemini_pci_conf_read(void * v,pcitag_t tag,int offset)293 gemini_pci_conf_read(void *v, pcitag_t tag, int offset)
294 {
295 struct obio_softc *sc = v;
296 struct pciconf_state ps;
297 vaddr_t va;
298 pcireg_t rv;
299 u_int s;
300
301 if (gemini_pci_conf_setup(sc, tag, offset, &ps))
302 return ((pcireg_t) -1);
303
304 PCI_CONF_LOCK(s);
305
306 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) {
307 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val;
308 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh,
309 GEMINI_PCI_CFG_CMD, ps.ps_addr_val);
310 }
311
312 va = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_pcicfg_ioh);
313 if (badaddr_read((void *) (va + GEMINI_PCI_CFG_DATA), sizeof(rv), &rv)) {
314 /*
315 * XXX Clear the Master Abort
316 */
317 #if 1
318 printf("conf_read: %d/%d/%d bad address\n",
319 ps.ps_b, ps.ps_d, ps.ps_f);
320 #endif
321 rv = (pcireg_t) -1;
322 }
323
324 PCI_CONF_UNLOCK(s);
325
326 return (rv);
327 }
328
329 void
gemini_pci_conf_write(void * v,pcitag_t tag,int offset,pcireg_t val)330 gemini_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
331 {
332 struct obio_softc *sc = v;
333 struct pciconf_state ps;
334 u_int s;
335
336 if (gemini_pci_conf_setup(sc, tag, offset, &ps))
337 return;
338
339 PCI_CONF_LOCK(s);
340
341 if (sc->sc_pci_chipset.pc_cfg_cmd != ps.ps_addr_val) {
342 sc->sc_pci_chipset.pc_cfg_cmd = ps.ps_addr_val;
343 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh,
344 GEMINI_PCI_CFG_CMD, ps.ps_addr_val);
345 }
346
347 bus_space_write_4(sc->sc_iot, sc->sc_pcicfg_ioh,
348 GEMINI_PCI_CFG_DATA, val);
349
350 PCI_CONF_UNLOCK(s);
351 }
352
353 int
gemini_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)354 gemini_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
355 {
356 int irq;
357
358 irq = 8;
359
360 *ihp = irq;
361 return 0;
362 }
363
364 const char *
gemini_pci_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)365 gemini_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
366 {
367 strlcpy(buf, "pci", len);
368 return buf;
369 }
370
371 const struct evcnt *
gemini_pci_intr_evcnt(void * v,pci_intr_handle_t ih)372 gemini_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
373 {
374 return NULL;
375 }
376
377 void *
gemini_pci_intr_establish(void * v,pci_intr_handle_t pci_ih,int ipl,int (* func)(void *),void * arg,const char * xname)378 gemini_pci_intr_establish(void *v, pci_intr_handle_t pci_ih, int ipl,
379 int (*func)(void *), void *arg, const char *xname)
380 {
381 pcireg_t r;
382 void *ih=NULL;
383 int irq;
384 void *cookie;
385
386 irq = (int)pci_ih;
387
388 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2);
389 r |= CFG_REG_CTL2_INTMASK_INT_ABCD;
390 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r);
391
392 if (gemini_pci_intrq_empty())
393 ih = intr_establish_xname(irq, ipl, IST_LEVEL_HIGH,
394 gemini_pci_intr_handler, v, xname);
395
396 cookie = gemini_pci_intrq_insert(ih, func, arg);
397 return cookie;
398 }
399
400 void
gemini_pci_intr_disestablish(void * v,void * cookie)401 gemini_pci_intr_disestablish(void *v, void *cookie)
402 {
403 pcireg_t r;
404 struct gemini_pci_intrq *iqp = (struct gemini_pci_intrq *)cookie;
405 void *ih = iqp->iq_ih;
406
407 gemini_pci_intrq_remove(cookie);
408 if (gemini_pci_intrq_empty()) {
409 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2);
410 r &= ~CFG_REG_CTL2_INTMASK_INT_ABCD;
411 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r);
412 intr_disestablish(ih);
413 }
414 }
415
416 int
gemini_pci_intr_handler(void * v)417 gemini_pci_intr_handler(void *v)
418 {
419 pcireg_t r;
420 int rv;
421
422 /*
423 * dispatch PCI device interrupt handlers
424 */
425 rv = gemini_pci_intrq_dispatch();
426
427 /*
428 * ack Gemini PCI interrupts
429 */
430 r = gemini_pci_conf_read(v, 0, GEMINI_PCI_CFG_REG_CTL2);
431 gemini_pci_conf_write(v, 0, GEMINI_PCI_CFG_REG_CTL2, r);
432
433 return rv;
434 }
435