1 /* $NetBSD: epe.c,v 1.51 2024/07/05 04:31:49 rin Exp $ */
2
3 /*
4 * Copyright (c) 2004 Jesse Off
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.51 2024/07/05 04:31:49 rin Exp $");
31
32 #include <sys/types.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/ioctl.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/time.h>
39 #include <sys/device.h>
40 #include <uvm/uvm_extern.h>
41
42 #include <sys/bus.h>
43 #include <machine/intr.h>
44
45 #include <arm/cpufunc.h>
46
47 #include <arm/ep93xx/epsocvar.h>
48 #include <arm/ep93xx/ep93xxvar.h>
49
50 #include <net/if.h>
51 #include <net/if_dl.h>
52 #include <net/if_types.h>
53 #include <net/if_media.h>
54 #include <net/if_ether.h>
55 #include <net/bpf.h>
56
57 #include <dev/mii/mii.h>
58 #include <dev/mii/miivar.h>
59
60 #ifdef INET
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #include <netinet/if_inarp.h>
66 #endif
67
68 #include <arm/ep93xx/ep93xxreg.h>
69 #include <arm/ep93xx/epereg.h>
70 #include <arm/ep93xx/epevar.h>
71
72 #define DEFAULT_MDCDIV 32
73
74 #ifndef EPE_FAST
75 #define EPE_FAST
76 #endif
77
78 #ifndef EPE_FAST
79 #define EPE_READ(x) \
80 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x))
81 #define EPE_WRITE(x, y) \
82 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y))
83 #define CTRLPAGE_DMASYNC(x, y, z) \
84 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z))
85 #else
86 #define EPE_READ(x) *(volatile uint32_t *) \
87 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x))
88 #define EPE_WRITE(x, y) *(volatile uint32_t *) \
89 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y
90 #define CTRLPAGE_DMASYNC(x, y, z)
91 #endif /* ! EPE_FAST */
92
93 static int epe_match(device_t , cfdata_t, void *);
94 static void epe_attach(device_t, device_t, void *);
95 static void epe_init(struct epe_softc *);
96 static int epe_intr(void* arg);
97 static int epe_gctx(struct epe_softc *);
98 int epe_mii_readreg (device_t, int, int, uint16_t *);
99 int epe_mii_writereg (device_t, int, int, uint16_t);
100 void epe_statchg (struct ifnet *);
101 void epe_tick (void *);
102 static int epe_ifioctl (struct ifnet *, u_long, void *);
103 static void epe_ifstart (struct ifnet *);
104 static void epe_ifwatchdog (struct ifnet *);
105 static int epe_ifinit (struct ifnet *);
106 static void epe_ifstop (struct ifnet *, int);
107 static void epe_setaddr (struct ifnet *);
108
109 CFATTACH_DECL_NEW(epe, sizeof(struct epe_softc),
110 epe_match, epe_attach, NULL, NULL);
111
112 static int
epe_match(device_t parent,cfdata_t match,void * aux)113 epe_match(device_t parent, cfdata_t match, void *aux)
114 {
115 return 2;
116 }
117
118 static void
epe_attach(device_t parent,device_t self,void * aux)119 epe_attach(device_t parent, device_t self, void *aux)
120 {
121 struct epe_softc *sc = device_private(self);
122 struct epsoc_attach_args *sa;
123 prop_data_t enaddr;
124
125 aprint_normal("\n");
126 sa = aux;
127 sc->sc_dev = self;
128 sc->sc_iot = sa->sa_iot;
129 sc->sc_intr = sa->sa_intr;
130 sc->sc_dmat = sa->sa_dmat;
131
132 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size,
133 0, &sc->sc_ioh))
134 panic("%s: Cannot map registers", device_xname(self));
135
136 /* Fetch the Ethernet address from property if set. */
137 enaddr = prop_dictionary_get(device_properties(self), "mac-address");
138 if (enaddr != NULL) {
139 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA);
140 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN);
141 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr),
142 ETHER_ADDR_LEN);
143 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0);
144 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
145 sc->sc_enaddr, ETHER_ADDR_LEN);
146 }
147
148 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc);
149 epe_init(sc);
150 }
151
152 static int
epe_gctx(struct epe_softc * sc)153 epe_gctx(struct epe_softc *sc)
154 {
155 struct ifnet * ifp = &sc->sc_ec.ec_if;
156 uint32_t *cur, ndq = 0;
157
158 /* Handle transmit completions */
159 cur = (uint32_t *)(EPE_READ(TXStsQCurAdd) -
160 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage);
161
162 if (sc->TXStsQ_cur != cur) {
163 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(uint32_t),
164 TX_QLEN * sizeof(uint32_t), BUS_DMASYNC_PREREAD);
165 } else
166 return 0;
167
168 do {
169 uint32_t tbi = *sc->TXStsQ_cur & 0x7fff;
170 struct mbuf *m = sc->txq[tbi].m;
171
172 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0)
173 if_statinc(ifp, if_oerrors);
174
175 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap);
176 m_freem(m);
177 do {
178 sc->txq[tbi].m = NULL;
179 ndq++;
180 tbi = (tbi + 1) % TX_QLEN;
181 } while (sc->txq[tbi].m == m);
182
183 if_statinc(ifp, if_opackets);
184 sc->TXStsQ_cur++;
185 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) {
186 sc->TXStsQ_cur = sc->TXStsQ;
187 }
188 } while (sc->TXStsQ_cur != cur);
189
190 sc->TXDQ_avail += ndq;
191 if (sc->tx_busy) {
192 sc->tx_busy = false;
193 /* Disable end-of-tx-chain interrupt */
194 EPE_WRITE(IntEn, IntEn_REOFIE);
195 }
196 return ndq;
197 }
198
199 static int
epe_intr(void * arg)200 epe_intr(void *arg)
201 {
202 struct epe_softc *sc = (struct epe_softc *)arg;
203 struct ifnet * ifp = &sc->sc_ec.ec_if;
204 uint32_t ndq = 0, irq, *cur;
205
206 irq = EPE_READ(IntStsC);
207 begin:
208 cur = (uint32_t *)(EPE_READ(RXStsQCurAdd) -
209 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage);
210 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t),
211 RX_QLEN * 4 * sizeof(uint32_t),
212 BUS_DMASYNC_PREREAD);
213 while (sc->RXStsQ_cur != cur) {
214 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE | RXStsQ_RFP |RXStsQ_EOB))
215 == (RXStsQ_RWE | RXStsQ_RFP | RXStsQ_EOB)) {
216 uint32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff;
217 uint32_t fl = sc->RXStsQ_cur[1] & 0xffff;
218 struct mbuf *m;
219
220 MGETHDR(m, M_DONTWAIT, MT_DATA);
221 if (m != NULL) MCLGET(m, M_DONTWAIT);
222 if (m != NULL && (m->m_flags & M_EXT)) {
223 bus_dmamap_unload(sc->sc_dmat,
224 sc->rxq[bi].m_dmamap);
225 m_set_rcvif(sc->rxq[bi].m, ifp);
226 sc->rxq[bi].m->m_pkthdr.len =
227 sc->rxq[bi].m->m_len = fl;
228 if_percpuq_enqueue(ifp->if_percpuq,
229 sc->rxq[bi].m);
230 sc->rxq[bi].m = m;
231 bus_dmamap_load(sc->sc_dmat,
232 sc->rxq[bi].m_dmamap,
233 m->m_ext.ext_buf, MCLBYTES,
234 NULL, BUS_DMA_NOWAIT);
235 sc->RXDQ[bi * 2] =
236 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr;
237 } else {
238 /* Drop packets until we can get replacement
239 * empty mbufs for the RXDQ.
240 */
241 m_freem(m);
242
243 if_statinc(ifp, if_ierrors);
244 }
245 } else
246 if_statinc(ifp, if_ierrors);
247
248 ndq++;
249
250 sc->RXStsQ_cur += 2;
251 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2))
252 sc->RXStsQ_cur = sc->RXStsQ;
253 }
254
255 if (ndq > 0) {
256 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t),
257 RX_QLEN * 4 * sizeof(uint32_t),
258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
259 EPE_WRITE(RXStsEnq, ndq);
260 EPE_WRITE(RXDEnq, ndq);
261 ndq = 0;
262 }
263
264 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
265 if_schedule_deferred_start(ifp);
266 }
267
268 irq = EPE_READ(IntStsC);
269 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0)
270 goto begin;
271
272 return 1;
273 }
274
275
276 static void
epe_init(struct epe_softc * sc)277 epe_init(struct epe_softc *sc)
278 {
279 bus_dma_segment_t segs;
280 char *addr;
281 int rsegs, err, i;
282 struct ifnet * ifp = &sc->sc_ec.ec_if;
283 struct mii_data *mii = &sc->sc_mii;
284 int mdcdiv = DEFAULT_MDCDIV;
285
286 callout_init(&sc->epe_tick_ch, 0);
287
288 /* Select primary Individual Address in Address Filter Pointer */
289 EPE_WRITE(AFP, 0);
290 /* Read ethernet MAC, should already be set by bootrom */
291 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
292 sc->sc_enaddr, ETHER_ADDR_LEN);
293 aprint_normal_dev(sc->sc_dev, "MAC address %s\n",
294 ether_sprintf(sc->sc_enaddr));
295
296 /* Soft Reset the MAC */
297 EPE_WRITE(SelfCtl, SelfCtl_RESET);
298 while (EPE_READ(SelfCtl) & SelfCtl_RESET)
299 ;
300
301 /* suggested magic initialization values from datasheet */
302 EPE_WRITE(RXBufThrshld, 0x800040);
303 EPE_WRITE(TXBufThrshld, 0x200010);
304 EPE_WRITE(RXStsThrshld, 0x40002);
305 EPE_WRITE(TXStsThrshld, 0x40002);
306 EPE_WRITE(RXDThrshld, 0x40002);
307 EPE_WRITE(TXDThrshld, 0x40002);
308
309 /* Allocate a page of memory for descriptor and status queues */
310 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE,
311 &segs, 1, &rsegs, BUS_DMA_WAITOK);
312 if (err == 0) {
313 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE,
314 &sc->ctrlpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT));
315 }
316 if (err == 0) {
317 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE,
318 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap);
319 }
320 if (err == 0) {
321 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap,
322 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK);
323 }
324 if (err != 0) {
325 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev));
326 }
327 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr;
328 memset(sc->ctrlpage, 0, PAGE_SIZE);
329
330 /* Set up pointers to start of each queue in kernel addr space.
331 * Each descriptor queue or status queue entry uses 2 words
332 */
333 sc->TXDQ = (uint32_t *)sc->ctrlpage;
334 sc->TXDQ_cur = sc->TXDQ;
335 sc->TXDQ_avail = TX_QLEN - 1;
336 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2];
337 sc->TXStsQ_cur = sc->TXStsQ;
338 sc->RXDQ = &sc->TXStsQ[TX_QLEN];
339 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2];
340 sc->RXStsQ_cur = sc->RXStsQ;
341
342 /* Program each queue's start addr, cur addr, and len registers
343 * with the physical addresses.
344 */
345 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr;
346 EPE_WRITE(TXDQBAdd, (uint32_t)addr);
347 EPE_WRITE(TXDQCurAdd, (uint32_t)addr);
348 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(uint32_t));
349
350 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(uint32_t);
351 EPE_WRITE(TXStsQBAdd, (uint32_t)addr);
352 EPE_WRITE(TXStsQCurAdd, (uint32_t)addr);
353 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(uint32_t));
354
355 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(uint32_t);
356 EPE_WRITE(RXDQBAdd, (uint32_t)addr);
357 EPE_WRITE(RXDCurAdd, (uint32_t)addr);
358 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(uint32_t));
359
360 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(uint32_t);
361 EPE_WRITE(RXStsQBAdd, (uint32_t)addr);
362 EPE_WRITE(RXStsQCurAdd, (uint32_t)addr);
363 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(uint32_t));
364
365 /* Populate the RXDQ with mbufs */
366 for (i = 0; i < RX_QLEN; i++) {
367 struct mbuf *m;
368
369 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES,
370 0, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap);
371 MGETHDR(m, M_WAIT, MT_DATA);
372 MCLGET(m, M_WAIT);
373 sc->rxq[i].m = m;
374 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap,
375 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_WAITOK);
376
377 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr;
378 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES;
379 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0,
380 MCLBYTES, BUS_DMASYNC_PREREAD);
381 }
382
383 for (i = 0; i < TX_QLEN; i++) {
384 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
385 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW),
386 &sc->txq[i].m_dmamap);
387 sc->txq[i].m = NULL;
388 sc->TXDQ[i * 2 + 1] = (i << 16);
389 }
390
391 /* Divide HCLK by 32 for MDC clock */
392 if (device_cfdata(sc->sc_dev)->cf_flags)
393 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags;
394 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv) | SelfCtl_PSPRS));
395
396 mii->mii_ifp = ifp;
397 mii->mii_readreg = epe_mii_readreg;
398 mii->mii_writereg = epe_mii_writereg;
399 mii->mii_statchg = epe_statchg;
400 sc->sc_ec.ec_mii = mii;
401 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
402 ether_mediastatus);
403 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
404 MII_OFFSET_ANY, 0);
405 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
406
407 EPE_WRITE(BMCtl, BMCtl_RxEn | BMCtl_TxEn);
408 EPE_WRITE(IntEn, IntEn_REOFIE);
409 /* maximum valid max frame length */
410 EPE_WRITE(MaxFrmLen, (0x7ff << 16) | MHLEN);
411 /* wait for receiver ready */
412 while ((EPE_READ(BMSts) & BMSts_RxAct) == 0)
413 continue;
414 /* enqueue the entries in RXStsQ and RXDQ */
415 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize,
416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
417 EPE_WRITE(RXDEnq, RX_QLEN - 1);
418 EPE_WRITE(RXStsEnq, RX_QLEN - 1);
419
420 /*
421 * We can support 802.1Q VLAN-sized frames.
422 */
423 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
424
425 strcpy(ifp->if_xname, device_xname(sc->sc_dev));
426 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
427 ifp->if_ioctl = epe_ifioctl;
428 ifp->if_start = epe_ifstart;
429 ifp->if_watchdog = epe_ifwatchdog;
430 ifp->if_init = epe_ifinit;
431 ifp->if_stop = epe_ifstop;
432 ifp->if_timer = 0;
433 ifp->if_softc = sc;
434 IFQ_SET_READY(&ifp->if_snd);
435 if_attach(ifp);
436 if_deferred_start_init(ifp, NULL);
437 ether_ifattach(ifp, (sc)->sc_enaddr);
438 }
439
440 int
epe_mii_readreg(device_t self,int phy,int reg,uint16_t * val)441 epe_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
442 {
443 uint32_t d;
444
445 d = EPE_READ(SelfCtl);
446 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
447 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg));
448 while (EPE_READ(MIISts) & MIISts_BUSY)
449 ;
450 *val = EPE_READ(MIIData) & 0xffff;
451 EPE_WRITE(SelfCtl, d); /* restore old value */
452 return 0;
453 }
454
455 int
epe_mii_writereg(device_t self,int phy,int reg,uint16_t val)456 epe_mii_writereg(device_t self, int phy, int reg, uint16_t val)
457 {
458 uint32_t d;
459
460 d = EPE_READ(SelfCtl);
461 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
462 EPE_WRITE(MIIData, val);
463 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg));
464 while (EPE_READ(MIISts) & MIISts_BUSY)
465 ;
466 EPE_WRITE(SelfCtl, d); /* restore old value */
467
468 return 0;
469 }
470
471 void
epe_statchg(struct ifnet * ifp)472 epe_statchg(struct ifnet *ifp)
473 {
474 struct epe_softc *sc = ifp->if_softc;
475 uint32_t reg;
476
477 /*
478 * We must keep the MAC and the PHY in sync as
479 * to the status of full-duplex!
480 */
481 reg = EPE_READ(TestCtl);
482 if (sc->sc_mii.mii_media_active & IFM_FDX)
483 reg |= TestCtl_MFDX;
484 else
485 reg &= ~TestCtl_MFDX;
486 EPE_WRITE(TestCtl, reg);
487 }
488
489 void
epe_tick(void * arg)490 epe_tick(void *arg)
491 {
492 struct epe_softc* sc = (struct epe_softc *)arg;
493 struct ifnet * ifp = &sc->sc_ec.ec_if;
494 int s;
495 uint32_t misses;
496
497 if_statadd(ifp, if_collisions, EPE_READ(TXCollCnt));
498 /* These misses are ok, they will happen if the RAM/CPU can't keep up */
499 misses = EPE_READ(RXMissCnt);
500 if (misses > 0)
501 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses);
502
503 s = splnet();
504 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
505 epe_ifstart(ifp);
506 }
507 splx(s);
508
509 mii_tick(&sc->sc_mii);
510 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc);
511 }
512
513
514 static int
epe_ifioctl(struct ifnet * ifp,u_long cmd,void * data)515 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data)
516 {
517 int s, error;
518
519 s = splnet();
520 error = ether_ioctl(ifp, cmd, data);
521 if (error == ENETRESET) {
522 if (ifp->if_flags & IFF_RUNNING)
523 epe_setaddr(ifp);
524 error = 0;
525 }
526 splx(s);
527 return error;
528 }
529
530 static void
epe_ifstart(struct ifnet * ifp)531 epe_ifstart(struct ifnet *ifp)
532 {
533 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc;
534 struct mbuf *m;
535 bus_dma_segment_t *segs;
536 int s, bi, err, nsegs, ndq;
537
538 s = splnet();
539 start:
540 ndq = 0;
541 if (sc->TXDQ_avail == 0) {
542 if (epe_gctx(sc) == 0) {
543 /* Enable End-Of-TX-Chain interrupt */
544 EPE_WRITE(IntEn, IntEn_REOFIE | IntEn_ECIE);
545 sc->tx_busy = true;
546 ifp->if_timer = 10;
547 splx(s);
548 return;
549 }
550 }
551
552 bi = sc->TXDQ_cur - sc->TXDQ;
553
554 IFQ_POLL(&ifp->if_snd, m);
555 if (m == NULL) {
556 splx(s);
557 return;
558 }
559 more:
560 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
561 BUS_DMA_NOWAIT)) ||
562 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 ||
563 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) {
564 /* Copy entire mbuf chain to new and 32-bit aligned storage */
565 struct mbuf *mn;
566
567 if (err == 0)
568 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap);
569
570 MGETHDR(mn, M_DONTWAIT, MT_DATA);
571 if (mn == NULL) goto stop;
572 if (m->m_pkthdr.len > (MHLEN & (~0x3))) {
573 MCLGET(mn, M_DONTWAIT);
574 if ((mn->m_flags & M_EXT) == 0) {
575 m_freem(mn);
576 goto stop;
577 }
578 }
579 mn->m_data = (void *)(((uint32_t)mn->m_data + 0x3) & (~0x3));
580 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *));
581 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len;
582 IFQ_DEQUEUE(&ifp->if_snd, m);
583 m_freem(m);
584 m = mn;
585 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
586 BUS_DMA_NOWAIT);
587 } else {
588 IFQ_DEQUEUE(&ifp->if_snd, m);
589 }
590
591 bpf_mtap(ifp, m, BPF_D_OUT);
592
593 nsegs = sc->txq[bi].m_dmamap->dm_nsegs;
594 segs = sc->txq[bi].m_dmamap->dm_segs;
595 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0,
596 sc->txq[bi].m_dmamap->dm_mapsize,
597 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
598
599 /* XXX: This driver hasn't been tested w/nsegs > 1 */
600 while (nsegs > 0) {
601 nsegs--;
602 sc->txq[bi].m = m;
603 sc->TXDQ[bi * 2] = segs->ds_addr;
604 if (nsegs == 0)
605 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) |
606 (1 << 31);
607 else
608 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16);
609 segs++;
610 bi = (bi + 1) % TX_QLEN;
611 ndq++;
612 }
613
614
615 /*
616 * Enqueue another. Don't do more than half the available
617 * descriptors before telling the MAC about them
618 */
619 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) {
620 IFQ_POLL(&ifp->if_snd, m);
621 if (m != NULL)
622 goto more;
623 }
624 stop:
625 if (ndq > 0) {
626 sc->TXDQ_avail -= ndq;
627 sc->TXDQ_cur = &sc->TXDQ[bi];
628 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(uint32_t),
629 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
630 EPE_WRITE(TXDEnq, ndq);
631 }
632
633 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
634 goto start;
635
636 splx(s);
637 return;
638 }
639
640 static void
epe_ifwatchdog(struct ifnet * ifp)641 epe_ifwatchdog(struct ifnet *ifp)
642 {
643 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc;
644
645 if ((ifp->if_flags & IFF_RUNNING) == 0)
646 return;
647 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n",
648 device_xname(sc->sc_dev), EPE_READ(BMCtl), EPE_READ(BMSts));
649 }
650
651 static int
epe_ifinit(struct ifnet * ifp)652 epe_ifinit(struct ifnet *ifp)
653 {
654 struct epe_softc *sc = ifp->if_softc;
655 int rc, s = splnet();
656
657 callout_stop(&sc->epe_tick_ch);
658 EPE_WRITE(RXCtl, RXCtl_IA0 | RXCtl_BA | RXCtl_RCRCA | RXCtl_SRxON);
659 EPE_WRITE(TXCtl, TXCtl_STxON);
660 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */
661
662 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
663 rc = 0;
664 else if (rc != 0)
665 goto out;
666
667 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc);
668 ifp->if_flags |= IFF_RUNNING;
669 out:
670 splx(s);
671 return 0;
672 }
673
674 static void
epe_ifstop(struct ifnet * ifp,int disable)675 epe_ifstop(struct ifnet *ifp, int disable)
676 {
677 struct epe_softc *sc = ifp->if_softc;
678
679
680 EPE_WRITE(RXCtl, 0);
681 EPE_WRITE(TXCtl, 0);
682 EPE_WRITE(GIIntMsk, 0);
683 callout_stop(&sc->epe_tick_ch);
684
685 /* Down the MII. */
686 mii_down(&sc->sc_mii);
687
688 ifp->if_flags &= ~IFF_RUNNING;
689 ifp->if_timer = 0;
690 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE;
691 }
692
693 static void
epe_setaddr(struct ifnet * ifp)694 epe_setaddr(struct ifnet *ifp)
695 {
696 struct epe_softc *sc = ifp->if_softc;
697 struct ethercom *ec = &sc->sc_ec;
698 struct ether_multi *enm;
699 struct ether_multistep step;
700 uint8_t ias[2][ETHER_ADDR_LEN];
701 uint32_t h, nma = 0, hashes[2] = { 0, 0 };
702 uint32_t rxctl = EPE_READ(RXCtl);
703
704 /* disable receiver temporarily */
705 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON);
706
707 rxctl &= ~(RXCtl_MA | RXCtl_PA | RXCtl_IA2 | RXCtl_IA3);
708
709 if (ifp->if_flags & IFF_PROMISC)
710 rxctl |= RXCtl_PA;
711
712 ifp->if_flags &= ~IFF_ALLMULTI;
713
714 ETHER_LOCK(ec);
715 ETHER_FIRST_MULTI(step, ec, enm);
716 while (enm != NULL) {
717 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
718 /*
719 * We must listen to a range of multicast addresses.
720 * For now, just accept all multicasts, rather than
721 * trying to set only those filter bits needed to match
722 * the range. (At this time, the only use of address
723 * ranges is for IP multicast routing, for which the
724 * range is big enough to require all bits set.)
725 */
726 rxctl &= ~(RXCtl_IA2 | RXCtl_IA3);
727 rxctl |= RXCtl_MA;
728 hashes[0] = 0xffffffffUL;
729 hashes[1] = 0xffffffffUL;
730 ifp->if_flags |= IFF_ALLMULTI;
731 break;
732 }
733
734 if (nma < 2) {
735 /* We can program 2 perfect address filters for mcast */
736 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN);
737 rxctl |= (1 << (nma + 2));
738 } else {
739 /*
740 * XXX: Datasheet is not very clear here, I'm not sure
741 * if I'm doing this right. --joff
742 */
743 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
744
745 /* Just want the 6 most-significant bits. */
746 h = h >> 26;
747
748 hashes[ h / 32 ] |= (1 << (h % 32));
749 rxctl |= RXCtl_MA;
750 }
751 ETHER_NEXT_MULTI(step, enm);
752 nma++;
753 }
754 ETHER_UNLOCK(ec);
755
756 EPE_WRITE(AFP, 0);
757 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
758 sc->sc_enaddr, ETHER_ADDR_LEN);
759 if (rxctl & RXCtl_IA2) {
760 EPE_WRITE(AFP, 2);
761 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
762 ias[0], ETHER_ADDR_LEN);
763 }
764 if (rxctl & RXCtl_IA3) {
765 EPE_WRITE(AFP, 3);
766 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
767 ias[1], ETHER_ADDR_LEN);
768 }
769 if (hashes[0] != 0 && hashes[1] != 0) {
770 EPE_WRITE(AFP, 7);
771 EPE_WRITE(HashTbl, hashes[0]);
772 EPE_WRITE(HashTbl + 4, hashes[1]);
773 }
774 EPE_WRITE(RXCtl, rxctl);
775 }
776