xref: /netbsd-src/sys/arch/arm/at91/at91sam9261reg.h (revision c46bd13f4407f0d4766ba7a791a8cbf22ba5d45f)
1 /*	$Id: at91sam9261reg.h,v 1.4 2021/09/17 08:13:06 andvar Exp $	*/
2 /*	$NetBSD: at91sam9261reg.h,v 1.4 2021/09/17 08:13:06 andvar Exp $	*/
3 
4 /*
5  * Copyright (c) 2007 Embedtronics Oy
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #ifndef _AT91SAM9261REG_H_
31 #define _AT91SAM9261REG_H_
32 
33 #include <arm/at91/at91reg.h>
34 
35 /*
36  * Physical memory map for the AT91SAM9261
37  */
38 
39 /*
40  * ffff ffff ---------------------------
41  *	      System Controller
42  * ffff c000 ---------------------------
43  *	      Peripherals
44  * fffa 0000 ---------------------------
45  *	      (not used)
46  * 9000 0000 ---------------------------
47  *	      EBI Chip Select 7
48  * 8000 0000 ---------------------------
49  *	      EBI Chip Select 6 / CF logic
50  * 7000 0000 ---------------------------
51  *	      EBI Chip Select 5 / CF logic
52  * 6000 0000 ---------------------------
53  *	      EBI Chip Select 4 / CF logic
54  * 5000 0000 ---------------------------
55  *	      EBI Chip Select 3 / NANDFlash
56  * 4000 0000 ---------------------------
57  *	      EBI Chip Select 2
58  * 3000 0000 ---------------------------
59  *	      EBI Chip Select 1 / SDRAM
60  * 2000 0000 ---------------------------
61  *	      EBI Chip Select 0 / BFC
62  * 1000 0000 ---------------------------
63  *	      Reserved
64  * 0070 0000 ---------------------------
65  *	      LCD User Interface
66  * 0060 0000 ---------------------------
67  *	      UHP User Interface
68  * 0050 0000 ---------------------------
69  *	      Reserved
70  * 0040 0000 ---------------------------
71  *	      SRAM
72  * 0030 0000 ---------------------------
73  *	      DTCM
74  * 0020 0000 ---------------------------
75  *	      ITCM
76  * 0010 0000 ---------------------------
77  *	      Boot memory
78  * 0000 0000 ---------------------------
79  */
80 
81 
82 /*
83  * Virtual memory map for the AT91SAM9261 integrated devices
84  *
85  * Some device registers are statically mapped on upper address region.
86  * because we have to access them before bus_space is initialized.
87  * Most devices are dynamically mapped by bus_space_map(). In this case,
88  * the actual mapped (virtual) address are not cared by device drivers.
89  */
90 
91 /*
92  * FFFF FFFF ---------------------------
93  *            APB bus (1 MB)
94  * FFF0 0000 ---------------------------
95  *	      (not used)
96  * E000 0000 ---------------------------
97  *            Kernel text and data
98  * C000 0000 ---------------------------
99  *	      (not used)
100  * 0000 0000 ---------------------------
101  *
102  */
103 
104 #define	AT91SAM9261_BOOTMEM_BASE	0x00000000U
105 #define	AT91SAM9261_BOOTMEM_SIZE	0x00100000U
106 
107 #define	AT91SAM9261_ROM_BASE	0x00100000U
108 #define	AT91SAM9261_ROM_SIZE	0x00100000U
109 
110 #define	AT91SAM9261_SRAM_BASE	0x00300000U
111 #define	AT91SAM9261_SRAM_SIZE	0x00028000U
112 
113 #define	AT91SAM9261_UHP_BASE	0x00500000U
114 #define	AT91SAM9261_UHP_SIZE	0x00100000U
115 
116 #define	AT91SAM9261_LCD_BASE	0x00600000U
117 #define	AT91SAM9261_LCD_SIZE	0x00100000U
118 
119 #define	AT91SAM9261_CS0_BASE	0x10000000U
120 #define	AT91SAM9261_CS0_SIZE	0x10000000U
121 
122 #define	AT91SAM9261_CS1_BASE	0x20000000U
123 #define	AT91SAM9261_CS1_SIZE	0x10000000U
124 
125 #define	AT91SAM9261_SDRAM_BASE	AT91SAM9261_CS1_BASE
126 
127 #define	AT91SAM9261_CS2_BASE	0x30000000U
128 #define	AT91SAM9261_CS2_SIZE	0x10000000U
129 
130 #define	AT91SAM9261_CS3_BASE	0x40000000U
131 #define	AT91SAM9261_CS3_SIZE	0x10000000U
132 
133 #define	AT91SAM9261_CS4_BASE	0x50000000U
134 #define	AT91SAM9261_CS4_SIZE	0x10000000U
135 
136 #define	AT91SAM9261_CS5_BASE	0x60000000U
137 #define	AT91SAM9261_CS5_SIZE	0x10000000U
138 
139 #define	AT91SAM9261_CS6_BASE	0x70000000U
140 #define	AT91SAM9261_CS6_SIZE	0x10000000U
141 
142 #define	AT91SAM9261_CS7_BASE	0x80000000U
143 #define	AT91SAM9261_CS7_SIZE	0x10000000U
144 
145 /* Virtual address for I/O space */
146 #define	AT91SAM9261_APB_VBASE	0xfff00000U
147 #define	AT91SAM9261_APB_HWBASE	0xfff00000U
148 #define	AT91SAM9261_APB_SIZE	0x00100000U
149 
150 /* Peripherals: */
151 #include <arm/at91/at91pdcreg.h>
152 
153 #define	AT91SAM9261_TC0_BASE	0xFFFA0000U
154 #define	AT91SAM9261_TC1_BASE	0xFFFA0040U
155 #define	AT91SAM9261_TC2_BASE	0xFFFA0080U
156 #define	AT91SAM9261_TCB012_BASE	0xFFFA00C0U
157 #define	AT91SAM9261_TC_SIZE	0x4000U
158 //#include <arm/at91/at91tcreg.h>
159 
160 #define	AT91SAM9261_UDP_BASE	0xFFFA4000U
161 #define	AT91SAM9261_UDP_SIZE	0x4000U
162 //#include <arm/at91/at91udpreg.h>
163 
164 #define	AT91SAM9261_MCI_BASE	0xFFFA8000U
165 
166 #define	AT91SAM9261_TWI_BASE	0xFFFAC000U
167 #include <arm/at91/at91twireg.h>
168 
169 #define	AT91SAM9261_USART0_BASE	0xFFFB0000U
170 #define	AT91SAM9261_USART1_BASE	0xFFFB4000U
171 #define	AT91SAM9261_USART2_BASE	0xFFFB8000U
172 #define	AT91SAM9261_USART_SIZE	0x4000U
173 #include <arm/at91/at91usartreg.h>
174 
175 #define	AT91SAM9261_SSC0_BASE	0xFFFBC000U
176 #define	AT91SAM9261_SSC1_BASE	0xFFFC0000U
177 #define	AT91SAM9261_SSC2_BASE	0xFFFC4000U
178 #define	AT91SAM9261_SSC_SIZE	0x4000U
179 //#include <arm/at91/at91sscreg.h>
180 
181 #define	AT91SAM9261_SPI0_BASE	0xFFFC8000U
182 #define	AT91SAM9261_SPI1_BASE	0xFFFCC000U
183 #define	AT91SAM9261_SPI_SIZE	0x4000U
184 #include <arm/at91/at91spireg.h>
185 
186 /* system controller: */
187 #define	AT91SAM9261_SDRAMC_BASE	0xFFFFEA00U
188 #define	AT91SAM9261_SDRAMC_SIZE	0x200U
189 
190 #define	AT91SAM9261_SMC_BASE	0xFFFFEC00U
191 #define	AT91SAM9261_SMC_SIZE	0x200U
192 
193 #define	AT91SAM9261_MATRIX_BASE	0xFFFFEE00U
194 #define	AT91SAM9216_MATRIX_SIZE	0x200U
195 
196 #define	AT91SAM9261_AIC_BASE	0xFFFFF000U
197 #define	AT91SAM9261_AIC_SIZE	0x200U
198 #include <arm/at91/at91aicreg.h>
199 
200 #define	AT91SAM9261_DBGU_BASE	0xFFFFF200U
201 #define	AT91SAM9261_DBGU_SIZE	0x200U
202 #include <arm/at91/at91dbgureg.h>
203 
204 #define	AT91SAM9261_PIOA_BASE	0xFFFFF400U
205 #define	AT91SAM9261_PIOB_BASE	0xFFFFF600U
206 #define	AT91SAM9261_PIOC_BASE	0xFFFFF800U
207 #define	AT91SAM9261_PIO_SIZE	0x200U
208 #define	AT91_PIO_SIZE		AT91SAM9261_PIO_SIZE	// for generic AT91 code
209 #include <arm/at91/at91pioreg.h>
210 
211 #define	PIOA_READ(_reg)		*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg)))
212 #define	PIOA_WRITE(_reg, _val)	do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val);} while (0)
213 #define	PIOB_READ(_reg)		*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg)))
214 #define	PIOB_WRITE(_reg, _val)	do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val);} while (0)
215 #define	PIOC_READ(_reg)		*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg)))
216 #define	PIOC_WRITE(_reg, _val)	do {*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) = (_val);} while (0)
217 
218 #define	AT91SAM9261_PMC_BASE	0xFFFFFC00U
219 #define	AT91SAM9261_PMC_SIZE	0x100U
220 #include <arm/at91/at91pmcreg.h>
221 
222 #define	AT91SAM9261_RSTC_BASE	0xFFFFFD00U
223 #define	AT91SAM9261_RSTC_SIZE	0x10U
224 
225 #define	AT91SAM9261_SHDWC_BASE	0xFFFFFD10U
226 #define	AT91SAM9261_SHDWC_SIZE	0x10U
227 
228 #define	AT91SAM9261_RTT_BASE	0xFFFFFD20U
229 #define	AT91SAM9261_RTT_SIZE	0x10U
230 
231 #define	AT91SAM9261_PIT_BASE	0xFFFFFD30U
232 #define	AT91SAM9261_PIT_SIZE	0x10U
233 
234 #define	AT91SAM9261_WDT_BASE	0xFFFFFD40U
235 #define	AT91SAM9261_WDTC_SIZE	0x10U
236 
237 #define	AT91SAM9261_GPBR_BASE	0xFFFFFD50U
238 #define	AT91SAM9261_GPBR_SIZE	0x10U
239 
240 
241 // peripheral identifiers:
242 /* peripheral identifiers: */
243 enum {
244   PID_FIQ = 0,			/* 0 */
245   PID_SYSIRQ,			/* 1 */
246   PID_PIOA,			/* 2 */
247   PID_PIOB,			/* 3 */
248   PID_PIOC,			/* 4 */
249 
250   PID_US0 = 6,			/* 6 */
251   PID_US1,			/* 7 */
252   PID_US2,			/* 8 */
253   PID_MCI,			/* 9 */
254   PID_UDP,			/* 10 */
255   PID_TWI,			/* 11 */
256   PID_SPI0,			/* 12 */
257   PID_SPI1,			/* 13 */
258   PID_SSC0,			/* 14 */
259   PID_SSC1,			/* 15 */
260   PID_SSC2,			/* 16 */
261   PID_TC0,			/* 17 */
262   PID_TC1,			/* 18 */
263   PID_TC2,			/* 19 */
264   PID_UHP,			/* 20 */
265   PID_LCDC,			/* 21 */
266 
267   PID_IRQ0 = 29,		/* 29 */
268   PID_IRQ1,			/* 30 */
269   PID_IRQ2,			/* 31 */
270 };
271 
272 #endif /* _AT91SAM9261REG_H_ */
273