1 /* $NetBSD: mesong12_clkc.c,v 1.6 2021/02/04 22:55:36 joerg Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: mesong12_clkc.c,v 1.6 2021/02/04 22:55:36 joerg Exp $");
31
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36
37 #include <dev/fdt/fdtvar.h>
38
39 #include <arm/amlogic/meson_clk.h>
40 #include <arm/amlogic/mesong12_clkc.h>
41
42 #define CBUS_REG(x) ((x) << 2)
43
44 #define HHI_GP0_PLL_CNTL0 CBUS_REG(0x10)
45 #define HHI_GP0_PLL_CNTL1 CBUS_REG(0x11)
46 #define HHI_GP0_PLL_CNTL2 CBUS_REG(0x12)
47 #define HHI_GP0_PLL_CNTL3 CBUS_REG(0x13)
48 #define HHI_GP0_PLL_CNTL4 CBUS_REG(0x14)
49 #define HHI_GP0_PLL_CNTL5 CBUS_REG(0x15)
50 #define HHI_GP0_PLL_CNTL6 CBUS_REG(0x16)
51 #define HHI_GP1_PLL_CNTL0 CBUS_REG(0x18)
52 #define HHI_GP1_PLL_CNTL1 CBUS_REG(0x19)
53 #define HHI_PCIE_PLL_CNTL0 CBUS_REG(0x26)
54 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_LOCK __BIT(31)
55 #define HHI_PCIE_PLL_CNTL0_PCIE_HCSL_CAL_DONE __BIT(30)
56 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_RESET __BIT(29)
57 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_EN __BIT(28)
58 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_VCO_DIV_SEL __BIT(27)
59 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_AFC_START __BIT(26)
60 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_OD __BITS(20,16)
61 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_PREDIV_SEL __BITS(14,10)
62 #define HHI_PCIE_PLL_CNTL0_PCIE_APLL_FBKDIV __BITS(7,0)
63 #define HHI_PCIE_PLL_CNTL1 CBUS_REG(0x27)
64 #define HHI_PCIE_PLL_CNTL1_PCIE_APLL_SDM_EN __BIT(12)
65 #define HHI_PCIE_PLL_CNTL1_PCIE_APLL_SDM_FRAC __BITS(11,0)
66 #define HHI_PCIE_PLL_CNTL2 CBUS_REG(0x28)
67 #define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_DEP_SEL __BITS(31,28)
68 #define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_FREF_SEL __BITS(25,24)
69 #define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_MODE __BITS(23,22)
70 #define HHI_PCIE_PLL_CNTL2_PCIE_APLL_SSC_OFFSET __BITS(21,20)
71 #define HHI_PCIE_PLL_CNTL2_PCIE_APLL_STR_M __BITS(19,18)
72 #define HHI_PCIE_PLL_CNTL2_PCIE_APLL_RESERVE __BITS(15,0)
73 #define HHI_PCIE_PLL_CNTL3 CBUS_REG(0x29)
74 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_BYPASS_EN __BIT(31)
75 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_HOLD_T __BITS(29,28)
76 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_IN __BITS(26,20)
77 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_NT __BIT(19)
78 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_DIV __BITS(18,17)
79 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_BIAS_LPF_EN __BIT(16)
80 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_ICAP __BITS(15,12)
81 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_IRES __BITS(11,8)
82 #define HHI_PCIE_PLL_CNTL3_PCIE_APLL_CPI __BITS(5,4)
83 #define HHI_PCIE_PLL_CNTL4 CBUS_REG(0x2a)
84 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_SHIFT_EN __BIT(31)
85 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_SHIFT_T __BITS(27,26)
86 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_SHIFT_V __BITS(25,24)
87 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_VCTRL_MON_EN __BIT(23)
88 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_CAP __BITS(21,20)
89 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_CAPADJ __BITS(19,16)
90 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_RES __BITS(13,12)
91 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_SF __BIT(11)
92 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LVR_OD_EN __BIT(10)
93 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_REFCLK_MON_EN __BIT(9)
94 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_FBKCLK_MON_EN __BIT(8)
95 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LOAD __BIT(7)
96 #define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LOAD_EN __BIT(6)
97 #define HHI_PCIE_PLL_CNTL5 CBUS_REG(0x2b)
98 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_ADJ_LDO __BITS(30,28)
99 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGP_EN __BIT(27)
100 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGR_ADJ __BITS(24,20)
101 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGR_START __BIT(19)
102 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGR_VREF __BITS(16,12)
103 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BY_IMP_IN __BITS(11,8)
104 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BY_IMP __BIT(7)
105 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_CAL_EN __BIT(6)
106 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_CAL_RSTN __BIT(5)
107 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_EDGEDRV_EN __BIT(4)
108 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_EN0 __BIT(3)
109 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_IN_EN __BIT(2)
110 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_SEL_PW __BIT(1)
111 #define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_SEL_STR __BIT(0)
112
113 #define HHI_HIFI_PLL_CNTL0 CBUS_REG(0x36)
114 #define HHI_HIFI_PLL_CNTL1 CBUS_REG(0x37)
115 #define HHI_HIFI_PLL_CNTL2 CBUS_REG(0x38)
116 #define HHI_HIFI_PLL_CNTL3 CBUS_REG(0x39)
117 #define HHI_HIFI_PLL_CNTL4 CBUS_REG(0x3a)
118 #define HHI_HIFI_PLL_CNTL5 CBUS_REG(0x3b)
119 #define HHI_HIFI_PLL_CNTL6 CBUS_REG(0x3c)
120 #define HHI_MEM_PD_REG0 CBUS_REG(0x40)
121 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
122 #define HHI_GCLK_MPEG1 CBUS_REG(0x51)
123 #define HHI_GCLK_MPEG2 CBUS_REG(0x52)
124 #define HHI_GCLK_OTHER CBUS_REG(0x54)
125 #define HHI_GCLK_OTHER2 CBUS_REG(0x55)
126 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
127 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
128 #define HHI_TS_CLK_CNTL CBUS_REG(0x64)
129 #define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67)
130 #define HHI_VID_PLL_CLK_DIV CBUS_REG(0x68)
131 #define HHI_SYS_CPUB_CLK_CNTL1 CBUS_REG(0x80)
132 #define HHI_SYS_CPUB_CLK_CNTL CBUS_REG(0x82)
133 #define HHI_NAND_CLK_CNTL CBUS_REG(0x97)
134 #define HHI_SD_EMMC_CLK_CNTL CBUS_REG(0x99)
135 #define HHI_MPLL_CNTL0 CBUS_REG(0x9e)
136 #define HHI_MPLL_CNTL1 CBUS_REG(0x9f)
137 #define HHI_MPLL_CNTL2 CBUS_REG(0xa0)
138 #define HHI_MPLL_CNTL3 CBUS_REG(0xa1)
139 #define HHI_MPLL_CNTL4 CBUS_REG(0xa2)
140 #define HHI_MPLL_CNTL5 CBUS_REG(0xa3)
141 #define HHI_MPLL_CNTL6 CBUS_REG(0xa4)
142 #define HHI_MPLL_CNTL7 CBUS_REG(0xa5)
143 #define HHI_MPLL_CNTL8 CBUS_REG(0xa6)
144 #define HHI_FIX_PLL_CNTL0 CBUS_REG(0xa8)
145 #define HHI_FIX_PLL_CNTL1 CBUS_REG(0xa9)
146 #define HHI_FIX_PLL_CNTL2 CBUS_REG(0xaa)
147 #define HHI_FIX_PLL_CNTL3 CBUS_REG(0xab)
148 #define HHI_SYS_PLL_CNTL0 CBUS_REG(0xbd)
149 #define HHI_SYS_PLL_CNTL1 CBUS_REG(0xbe)
150 #define HHI_SYS_PLL_CNTL2 CBUS_REG(0xbf)
151 #define HHI_SYS_PLL_CNTL3 CBUS_REG(0xc0)
152 #define HHI_SYS_PLL_CNTL4 CBUS_REG(0xc1)
153 #define HHI_SYS_PLL_CNTL5 CBUS_REG(0xc2)
154 #define HHI_SYS_PLL_CNTL6 CBUS_REG(0xc3)
155 #define HHI_HDMI_PLL_CNTL0 CBUS_REG(0xc8)
156 #define HHI_HDMI_PLL_CNTL1 CBUS_REG(0xc9)
157 #define HHI_SYS1_PLL_CNTL0 CBUS_REG(0xe0)
158 #define HHI_SYS1_PLL_CNTL1 CBUS_REG(0xe1)
159 #define HHI_SYS1_PLL_CNTL2 CBUS_REG(0xe2)
160 #define HHI_SYS1_PLL_CNTL3 CBUS_REG(0xe3)
161 #define HHI_SYS1_PLL_CNTL4 CBUS_REG(0xe4)
162 #define HHI_SYS1_PLL_CNTL5 CBUS_REG(0xe5)
163 #define HHI_SYS1_PLL_CNTL6 CBUS_REG(0xe6)
164
165 static int mesong12_clkc_match(device_t, cfdata_t, void *);
166 static void mesong12_clkc_attach(device_t, device_t, void *);
167
168 static u_int mesong12_cpuclk_get_rate(struct meson_clk_softc *,
169 struct meson_clk_clk *);
170 static int mesong12_cpuclk_set_rate(struct meson_clk_softc *,
171 struct meson_clk_clk *, u_int);
172 static int mesong12_clk_pcie_pll_set_rate(struct meson_clk_softc *,
173 struct meson_clk_clk *, u_int);
174
175 struct mesong12_clkc_config {
176 const char *name;
177 struct meson_clk_clk *clks;
178 int nclks;
179 };
180
181 #define PARENTS(args...) ((const char *[]){ args })
182
183 /* fixed pll */
184 #define G12_CLK_fixed_pll_dco \
185 MESON_CLK_PLL(MESONG12_CLOCK_FIXED_PLL_DCO, "fixed_pll_dco", \
186 "xtal", /* parent */ \
187 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(28)), /* enable */ \
188 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(7,0)), /* m */ \
189 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(14,10)),/* n */ \
190 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL1, __BITS(16,0)), /* frac */ \
191 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(31)), /* l */ \
192 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(29)), /* reset */ \
193 0)
194 #define G12_CLK_fixed_pll \
195 MESON_CLK_DIV(MESONG12_CLOCK_FIXED_PLL, "fixed_pll", \
196 "fixed_pll_dco", /* parent */ \
197 HHI_FIX_PLL_CNTL0, /* reg */ \
198 __BITS(17,16), /* div */ \
199 MESON_CLK_DIV_POWER_OF_TWO)
200
201 /* sys pll */
202 #define G12_CLK_sys_pll_dco \
203 MESON_CLK_PLL(MESONG12_CLOCK_SYS_PLL_DCO, "sys_pll_dco", \
204 "xtal", /* parent */ \
205 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(28)), /* enable */ \
206 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(7,0)), /* m */ \
207 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(14,10)),/* n */ \
208 MESON_CLK_PLL_REG_INVALID, /* frac */ \
209 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(31)), /* l */ \
210 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(29)), /* reset */ \
211 0)
212 #define G12_CLK_sys_pll \
213 MESON_CLK_DIV(MESONG12_CLOCK_SYS_PLL, "sys_pll", \
214 "sys_pll_dco", /* parent */ \
215 HHI_SYS_PLL_CNTL0, /* reg */ \
216 __BITS(18,16), /* div */ \
217 MESON_CLK_DIV_POWER_OF_TWO | MESON_CLK_DIV_SET_RATE_PARENT)
218
219 /* sys1 pll */
220 #define G12B_CLK_sys1_pll_dco \
221 MESON_CLK_PLL(MESONG12_CLOCK_SYS1_PLL_DCO, "sys1_pll_dco", \
222 "xtal", /* parent */ \
223 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(28)), /* enable */ \
224 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(7,0)), /* m */ \
225 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(14,10)),/* n */ \
226 MESON_CLK_PLL_REG_INVALID, /* frac */ \
227 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(31)), /* l */ \
228 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(29)), /* reset */ \
229 0)
230 #define G12B_CLK_sys1_pll \
231 MESON_CLK_DIV(MESONG12_CLOCK_SYS1_PLL, "sys1_pll", \
232 "sys1_pll_dco", /* parent */ \
233 HHI_SYS1_PLL_CNTL0, /* reg */ \
234 __BITS(18,16), /* div */ \
235 MESON_CLK_DIV_POWER_OF_TWO | MESON_CLK_DIV_SET_RATE_PARENT)
236
237 /* fclk div */
238 #define G12_CLK_fclk_div2_div \
239 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", \
240 "fixed_pll", /* parent */ \
241 2, /* div */ \
242 1) /* mult */
243 #define G12_CLK_fclk_div2 \
244 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV2, "fclk_div2", \
245 "fclk_div2_div", /* parent */ \
246 HHI_FIX_PLL_CNTL1, /* reg */ \
247 24) /* bit */
248 #define G12_CLK_fclk_div2p5_div \
249 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV2P5_DIV, \
250 "fclk_div2p5_div", \
251 "fixed_pll_dco", /* parent */ \
252 5, /* div */ \
253 1) /* mult */
254 #define G12_CLK_fclk_div3_div \
255 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV3_DIV, \
256 "fclk_div3_div", \
257 "fixed_pll", /* parent */ \
258 3, /* div */ \
259 1) /* mult */
260 #define G12_CLK_fclk_div3 \
261 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV3, "fclk_div3", \
262 "fclk_div3_div", /* parent */ \
263 HHI_FIX_PLL_CNTL1, /* reg */ \
264 20) /* bit */
265 #define G12_CLK_fclk_div4_div \
266 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", \
267 "fixed_pll", /* parent */ \
268 4, /* div */ \
269 1) /* mult */
270 #define G12_CLK_fclk_div4 \
271 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV4, "fclk_div4", \
272 "fclk_div4_div", /* parent */ \
273 HHI_FIX_PLL_CNTL1, /* reg */ \
274 21) /* bit */
275 #define G12_CLK_fclk_div5_div \
276 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", \
277 "fixed_pll", /* parent */ \
278 5, /* div */ \
279 1) /* mult */
280 #define G12_CLK_fclk_div5 \
281 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV5, "fclk_div5", \
282 "fclk_div5_div", /* parent */ \
283 HHI_FIX_PLL_CNTL1, /* reg */ \
284 22) /* bit */
285 #define G12_CLK_fclk_div7_div \
286 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", \
287 "fixed_pll", /* parent */ \
288 7, /* div */ \
289 1) /* mult */
290 #define G12_CLK_fclk_div7 \
291 MESON_CLK_GATE(MESONG12_CLOCK_FCLK_DIV7, "fclk_div7", \
292 "fclk_div7_div", /* parent */ \
293 HHI_FIX_PLL_CNTL1, /* reg */ \
294 23) /* bit */
295
296 /* mpll */
297 #define G12_CLK_mpll_prediv \
298 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_MPLL_PREDIV, "mpll_prediv", \
299 "fixed_pll_dco", /* parent */ \
300 2, /* div */ \
301 1) /* mult */
302 #define G12_CLK_mpll0_div \
303 MESON_CLK_MPLL(MESONG12_CLOCK_MPLL0_DIV, "mpll0_div", \
304 "mpll_prediv", /* parent */ \
305 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(13,0)), /* sdm */ \
306 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(30)), /* sdm_enable */ \
307 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(28,20)), /* n2 */ \
308 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(29)), /* ssen */ \
309 0)
310 #define G12_CLK_mpll1_div \
311 MESON_CLK_MPLL(MESONG12_CLOCK_MPLL1_DIV, "mpll1_div", \
312 "mpll_prediv", /* parent */ \
313 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(13,0)), /* sdm */ \
314 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(30)), /* sdm_enable */ \
315 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(28,20)), /* n2 */ \
316 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(29)), /* ssen */ \
317 0)
318 #define G12_CLK_mpll2_div \
319 MESON_CLK_MPLL(MESONG12_CLOCK_MPLL2_DIV, "mpll2_div", \
320 "mpll_prediv", /* parent */ \
321 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(13,0)), /* sdm */ \
322 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(30)), /* sdm_enable */ \
323 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(28,20)), /* n2 */ \
324 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(29)), /* ssen */ \
325 0)
326 #define G12_CLK_mpll0 \
327 MESON_CLK_GATE(MESONG12_CLOCK_MPLL0, "mpll0", \
328 "mpll0_div", /* parent */ \
329 HHI_MPLL_CNTL1, /* reg */ \
330 31) /* bit */
331 #define G12_CLK_mpll1 \
332 MESON_CLK_GATE(MESONG12_CLOCK_MPLL1, "mpll1", \
333 "mpll1_div", /* parent */ \
334 HHI_MPLL_CNTL3, /* reg */ \
335 31) /* bit */
336 #define G12_CLK_mpll2 \
337 MESON_CLK_GATE(MESONG12_CLOCK_MPLL2, "mpll2", \
338 "mpll2_div", /* parent */ \
339 HHI_MPLL_CNTL5, /* reg */ \
340 31) /* bit */
341 #define G12_CLK_mpll_50m_div \
342 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_MPLL_50M_DIV, "mpll_50m_div", \
343 "fixed_pll_dco", /* parent */ \
344 80, /* div */ \
345 1) /* mult */
346 #define G12_CLK_mpll_50m \
347 MESON_CLK_MUX(MESONG12_CLOCK_MPLL_50M, "mpll_50m", \
348 PARENTS("mpll_50m_div", "xtal"), \
349 HHI_FIX_PLL_CNTL3, /* reg */ \
350 __BIT(5), /* sel */ \
351 0)
352
353 /* sd/emmc */
354 #define G12_CLK_sd_emmc_a_clk0_sel \
355 MESON_CLK_MUX(MESONG12_CLOCK_SD_EMMC_A_CLK0_SEL, "sd_emmc_a_clk0_sel", \
356 PARENTS("xtal", "fclk_div2", "fclk_div3", \
357 "fclk_div5", "fclk_div7"), \
358 HHI_SD_EMMC_CLK_CNTL, /* reg */ \
359 __BITS(11,9), /* sel */ \
360 0)
361 #define G12_CLK_sd_emmc_b_clk0_sel \
362 MESON_CLK_MUX(MESONG12_CLOCK_SD_EMMC_B_CLK0_SEL, "sd_emmc_b_clk0_sel", \
363 PARENTS("xtal", "fclk_div2", "fclk_div3", \
364 "fclk_div5", "fclk_div7"), \
365 HHI_SD_EMMC_CLK_CNTL, /* reg */ \
366 __BITS(27,25), /* sel */ \
367 0)
368 #define G12_CLK_sd_emmc_c_clk0_sel \
369 MESON_CLK_MUX(MESONG12_CLOCK_SD_EMMC_C_CLK0_SEL, "sd_emmc_c_clk0_sel", \
370 PARENTS("xtal", "fclk_div2", "fclk_div3", \
371 "fclk_div5", "fclk_div7"), \
372 HHI_NAND_CLK_CNTL, /* reg */ \
373 __BITS(11,9), /* sel */ \
374 0)
375 #define G12_CLK_sd_emmc_a_clk0_div \
376 MESON_CLK_DIV(MESONG12_CLOCK_SD_EMMC_A_CLK0_DIV, "sd_emmc_a_clk0_div", \
377 "sd_emmc_a_clk0_sel", /* parent */ \
378 HHI_SD_EMMC_CLK_CNTL, /* reg */ \
379 __BITS(6,0), /* div */ \
380 0)
381 #define G12_CLK_sd_emmc_b_clk0_div \
382 MESON_CLK_DIV(MESONG12_CLOCK_SD_EMMC_B_CLK0_DIV, "sd_emmc_b_clk0_div", \
383 "sd_emmc_b_clk0_sel", /* parent */ \
384 HHI_SD_EMMC_CLK_CNTL, /* reg */ \
385 __BITS(22,16), /* div */ \
386 0)
387 #define G12_CLK_sd_emmc_c_clk0_div \
388 MESON_CLK_DIV(MESONG12_CLOCK_SD_EMMC_C_CLK0_DIV, "sd_emmc_c_clk0_div", \
389 "sd_emmc_c_clk0_sel", /* parent */ \
390 HHI_NAND_CLK_CNTL, /* reg */ \
391 __BITS(6,0), /* div */ \
392 0)
393 #define G12_CLK_sd_emmc_a_clk0 \
394 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_A_CLK0, "sd_emmc_a_clk0", \
395 "sd_emmc_a_clk0_div", /* parent */ \
396 HHI_SD_EMMC_CLK_CNTL, /* reg */ \
397 7) /* bit */
398 #define G12_CLK_sd_emmc_b_clk0 \
399 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_B_CLK0, "sd_emmc_b_clk0", \
400 "sd_emmc_b_clk0_div", /* parent */ \
401 HHI_SD_EMMC_CLK_CNTL, /* reg */ \
402 23) /* bit */
403 #define G12_CLK_sd_emmc_c_clk0 \
404 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_C_CLK0, "sd_emmc_c_clk0", \
405 "sd_emmc_c_clk0_div", /* parent */ \
406 HHI_NAND_CLK_CNTL, /* reg */ \
407 7) /* bit */
408
409 /* source as mpeg_clk */
410 #define G12_CLK_mpeg_sel \
411 MESON_CLK_MUX(MESONG12_CLOCK_MPEG_SEL, "mpeg_sel", \
412 PARENTS("xtal", NULL, "fclk_div7", "mpll1", \
413 "mpll2", "fclk_div4", "fclk_div3", "fclk_div5"), \
414 HHI_MPEG_CLK_CNTL, /* reg */ \
415 __BITS(14,12), /* sel */ \
416 0)
417 #define G12_CLK_mpeg_clk_div \
418 MESON_CLK_DIV(MESONG12_CLOCK_MPEG_DIV, "mpeg_clk_div", \
419 "mpeg_sel", /* parent */ \
420 HHI_MPEG_CLK_CNTL, /* reg */ \
421 __BITS(6,0), /* div */ \
422 MESON_CLK_DIV_SET_RATE_PARENT)
423 #define G12_CLK_clk81 \
424 MESON_CLK_GATE(MESONG12_CLOCK_CLK81, "clk81", \
425 "mpeg_clk_div", /* parent */ \
426 HHI_MPEG_CLK_CNTL, /* reg */ \
427 7) /* bit */
428 #define G12_CLK_ddr \
429 MESON_CLK_GATE(MESONG12_CLOCK_DDR, "ddr", \
430 "clk81", /* parent */ \
431 HHI_GCLK_MPEG0, /* reg */ \
432 0) /* bit */
433 #define G12_CLK_dos \
434 MESON_CLK_GATE(MESONG12_CLOCK_DOS, "dos", \
435 "clk81", /* parent */ \
436 HHI_GCLK_MPEG0, /* reg */ \
437 1) /* bit */
438 #define G12_CLK_audio_locker \
439 MESON_CLK_GATE(MESONG12_CLOCK_AUDIO_LOCKER, "audio_locker", \
440 "clk81", /* parent */ \
441 HHI_GCLK_MPEG0, /* reg */ \
442 2) /* bit */
443 #define G12_CLK_mipi_dsi_host \
444 MESON_CLK_GATE(MESONG12_CLOCK_MIPI_DSI_HOST, "mipi_dsi_host", \
445 "clk81", /* parent */ \
446 HHI_GCLK_MPEG0, /* reg */ \
447 3) /* bit */
448 #define G12_CLK_eth_phy \
449 MESON_CLK_GATE(MESONG12_CLOCK_ETH_PHY, "eth_phy", \
450 "clk81", /* parent */ \
451 HHI_GCLK_MPEG0, /* reg */ \
452 4) /* bit */
453 #define G12_CLK_isa \
454 MESON_CLK_GATE(MESONG12_CLOCK_ISA, "isa", \
455 "clk81", /* parent */ \
456 HHI_GCLK_MPEG0, /* reg */ \
457 5) /* bit */
458 #define G12_CLK_pl301 \
459 MESON_CLK_GATE(MESONG12_CLOCK_PL301, "pl301", \
460 "clk81", /* parent */ \
461 HHI_GCLK_MPEG0, /* reg */ \
462 6) /* bit */
463 #define G12_CLK_periphs \
464 MESON_CLK_GATE(MESONG12_CLOCK_PERIPHS, "periphs", \
465 "clk81", /* parent */ \
466 HHI_GCLK_MPEG0, /* reg */ \
467 7) /* bit */
468 #define G12_CLK_spicc0 \
469 MESON_CLK_GATE(MESONG12_CLOCK_SPICC0, "spicc0", \
470 "clk81", /* parent */ \
471 HHI_GCLK_MPEG0, /* reg */ \
472 8) /* bit */
473 #define G12_CLK_i2c \
474 MESON_CLK_GATE(MESONG12_CLOCK_I2C, "i2c", \
475 "clk81", /* parent */ \
476 HHI_GCLK_MPEG0, /* reg */ \
477 9) /* bit */
478 #define G12_CLK_sana \
479 MESON_CLK_GATE(MESONG12_CLOCK_SANA, "sana", \
480 "clk81", /* parent */ \
481 HHI_GCLK_MPEG0, /* reg */ \
482 10) /* bit */
483 #define G12_CLK_sd \
484 MESON_CLK_GATE(MESONG12_CLOCK_SD, "sd", \
485 "clk81", /* parent */ \
486 HHI_GCLK_MPEG0, /* reg */ \
487 11) /* bit */
488 #define G12_CLK_rng0 \
489 MESON_CLK_GATE(MESONG12_CLOCK_RNG0, "rng0", \
490 "clk81", /* parent */ \
491 HHI_GCLK_MPEG0, /* reg */ \
492 12) /* bit */
493 #define G12_CLK_uart0 \
494 MESON_CLK_GATE(MESONG12_CLOCK_UART0, "uart0", \
495 "clk81", /* parent */ \
496 HHI_GCLK_MPEG0, /* reg */ \
497 13) /* bit */
498 #define G12_CLK_spicc1 \
499 MESON_CLK_GATE(MESONG12_CLOCK_SPICC1, "spicc1", \
500 "clk81", /* parent */ \
501 HHI_GCLK_MPEG0, /* reg */ \
502 14) /* bit */
503 #define G12_CLK_hiu_iface \
504 MESON_CLK_GATE(MESONG12_CLOCK_HIU_IFACE, "hiu_iface", \
505 "clk81", /* parent */ \
506 HHI_GCLK_MPEG0, /* reg */ \
507 19) /* bit */
508 #define G12_CLK_mipi_dsi_phy \
509 MESON_CLK_GATE(MESONG12_CLOCK_MIPI_DSI_PHY, "mipi_dsi_phy", \
510 "clk81", /* parent */ \
511 HHI_GCLK_MPEG0, /* reg */ \
512 20) /* bit */
513 #define G12_CLK_assist_misc \
514 MESON_CLK_GATE(MESONG12_CLOCK_ASSIST_MISC, "assist_misc", \
515 "clk81", /* parent */ \
516 HHI_GCLK_MPEG0, /* reg */ \
517 23) /* bit */
518 #define G12_CLK_sd_emmc_a \
519 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_A, "sd_emmc_a", \
520 "clk81", /* parent */ \
521 HHI_GCLK_MPEG0, /* reg */ \
522 4) /* bit */
523 #define G12_CLK_sd_emmc_b \
524 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_B, "sd_emmc_b", \
525 "clk81", /* parent */ \
526 HHI_GCLK_MPEG0, /* reg */ \
527 25) /* bit */
528 #define G12_CLK_sd_emmc_c \
529 MESON_CLK_GATE(MESONG12_CLOCK_SD_EMMC_C, "sd_emmc_c", \
530 "clk81", /* parent */ \
531 HHI_GCLK_MPEG0, /* reg */ \
532 26) /* bit */
533 #define G12_CLK_audio_codec \
534 MESON_CLK_GATE(MESONG12_CLOCK_AUDIO_CODEC, "audio_codec", \
535 "clk81", /* parent */ \
536 HHI_GCLK_MPEG0, /* reg */ \
537 28) /* bit */
538 #define G12_CLK_audio \
539 MESON_CLK_GATE(MESONG12_CLOCK_AUDIO, "audio", \
540 "clk81", /* parent */ \
541 HHI_GCLK_MPEG1, /* reg */ \
542 0) /* bit */
543 #define G12_CLK_eth \
544 MESON_CLK_GATE(MESONG12_CLOCK_ETH, "eth", \
545 "clk81", /* parent */ \
546 HHI_GCLK_MPEG1, /* reg */ \
547 3) /* bit */
548 #define G12_CLK_demux \
549 MESON_CLK_GATE(MESONG12_CLOCK_DEMUX, "demux", \
550 "clk81", /* parent */ \
551 HHI_GCLK_MPEG1, /* reg */ \
552 4) /* bit */
553 #define G12_CLK_audio_ififo \
554 MESON_CLK_GATE(MESONG12_CLOCK_AUDIO_IFIFO, "audio_ififo", \
555 "clk81", /* parent */ \
556 HHI_GCLK_MPEG1, /* reg */ \
557 11) /* bit */
558 #define G12_CLK_adc \
559 MESON_CLK_GATE(MESONG12_CLOCK_ADC, "adc", \
560 "clk81", /* parent */ \
561 HHI_GCLK_MPEG1, /* reg */ \
562 13) /* bit */
563 #define G12_CLK_uart1 \
564 MESON_CLK_GATE(MESONG12_CLOCK_UART1, "uart1", \
565 "clk81", /* parent */ \
566 HHI_GCLK_MPEG1, /* reg */ \
567 16) /* bit */
568 #define G12_CLK_g2d \
569 MESON_CLK_GATE(MESONG12_CLOCK_G2D, "g2d", \
570 "clk81", /* parent */ \
571 HHI_GCLK_MPEG1, /* reg */ \
572 20) /* bit */
573 #define G12_CLK_reset \
574 MESON_CLK_GATE(MESONG12_CLOCK_RESET, "reset", \
575 "clk81", /* parent */ \
576 HHI_GCLK_MPEG1, /* reg */ \
577 23) /* bit */
578 #define G12_CLK_pcie_comb \
579 MESON_CLK_GATE(MESONG12_CLOCK_PCIE_COMB, "pcie_comb", \
580 "clk81", /* parent */ \
581 HHI_GCLK_MPEG1, /* reg */ \
582 24) /* bit */
583 #define G12_CLK_parser \
584 MESON_CLK_GATE(MESONG12_CLOCK_PARSER, "parser", \
585 "clk81", /* parent */ \
586 HHI_GCLK_MPEG1, /* reg */ \
587 25) /* bit */
588 #define G12_CLK_usb \
589 MESON_CLK_GATE(MESONG12_CLOCK_USB, "usb", \
590 "clk81", /* parent */ \
591 HHI_GCLK_MPEG1, /* reg */ \
592 26) /* bit */
593 #define G12_CLK_pcie_phy \
594 MESON_CLK_GATE(MESONG12_CLOCK_PCIE_PHY, "pcie_phy", \
595 "clk81", /* parent */ \
596 HHI_GCLK_MPEG1, /* reg */ \
597 27) /* bit */
598 #define G12_CLK_ahb_arb0 \
599 MESON_CLK_GATE(MESONG12_CLOCK_AHB_ARB0, "ahb_arb0", \
600 "clk81", /* parent */ \
601 HHI_GCLK_MPEG1, /* reg */ \
602 29) /* bit */
603 #define G12_CLK_ahb_data_bus \
604 MESON_CLK_GATE(MESONG12_CLOCK_AHB_DATA_BUS, "ahb_data_bus", \
605 "clk81", /* parent */ \
606 HHI_GCLK_MPEG2, /* reg */ \
607 1) /* bit */
608 #define G12_CLK_ahb_ctrl_bus \
609 MESON_CLK_GATE(MESONG12_CLOCK_AHB_CTRL_BUS, "ahb_ctrl_bus", \
610 "clk81", /* parent */ \
611 HHI_GCLK_MPEG2, /* reg */ \
612 2) /* bit */
613 #define G12_CLK_htx_hdcp22 \
614 MESON_CLK_GATE(MESONG12_CLOCK_HTX_HDCP22, "htx_hdcp22", \
615 "clk81", /* parent */ \
616 HHI_GCLK_MPEG2, /* reg */ \
617 3) /* bit */
618 #define G12_CLK_htx_pclk \
619 MESON_CLK_GATE(MESONG12_CLOCK_HTX_PCLK, "htx_pclk", \
620 "clk81", /* parent */ \
621 HHI_GCLK_MPEG2, /* reg */ \
622 4) /* bit */
623 #define G12_CLK_bt656 \
624 MESON_CLK_GATE(MESONG12_CLOCK_BT656, "bt656", \
625 "clk81", /* parent */ \
626 HHI_GCLK_MPEG2, /* reg */ \
627 6) /* bit */
628 #define G12_CLK_usb1_ddr_bridge \
629 MESON_CLK_GATE(MESONG12_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", \
630 "clk81", /* parent */ \
631 HHI_GCLK_MPEG2, /* reg */ \
632 8) /* bit */
633 #define G12_CLK_mmc_pclk \
634 MESON_CLK_GATE(MESONG12_CLOCK_MMC_PCLK, "mmc_pclk", \
635 "clk81", /* parent */ \
636 HHI_GCLK_MPEG2, /* reg */ \
637 11) /* bit */
638 #define G12_CLK_uart2 \
639 MESON_CLK_GATE(MESONG12_CLOCK_UART2, "uart2", \
640 "clk81", /* parent */ \
641 HHI_GCLK_MPEG2, /* reg */ \
642 15) /* bit */
643 #define G12_CLK_vpu_intr \
644 MESON_CLK_GATE(MESONG12_CLOCK_VPU_INTR, "vpu_intr", \
645 "clk81", /* parent */ \
646 HHI_GCLK_MPEG2, /* reg */ \
647 25) /* bit */
648 #define G12_CLK_gic \
649 MESON_CLK_GATE(MESONG12_CLOCK_GIC, "gic", \
650 "clk81", /* parent */ \
651 HHI_GCLK_MPEG2, /* reg */ \
652 30) /* bit */
653 #define G12_CLK_vclk2_venci0 \
654 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCI0, "vclk2_venci0", \
655 "clk81", /* parent */ \
656 HHI_GCLK_OTHER, /* reg */ \
657 1) /* bit */
658 #define G12_CLK_vclk2_venci1 \
659 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCI1, "vclk2_venci1", \
660 "clk81", /* parent */ \
661 HHI_GCLK_OTHER, /* reg */ \
662 2) /* bit */
663 #define G12_CLK_vclk2_vencp0 \
664 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCP0, "vclk2_vencp0", \
665 "clk81", /* parent */ \
666 HHI_GCLK_OTHER, /* reg */ \
667 3) /* bit */
668 #define G12_CLK_vclk2_vencp1 \
669 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCP1, "vclk2_vencp1", \
670 "clk81", /* parent */ \
671 HHI_GCLK_OTHER, /* reg */ \
672 4) /* bit */
673 #define G12_CLK_vclk2_venct0 \
674 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCT0, "vclk2_venct0", \
675 "clk81", /* parent */ \
676 HHI_GCLK_OTHER, /* reg */ \
677 5) /* bit */
678 #define G12_CLK_vclk2_venct1 \
679 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCT1, "vclk2_venct1", \
680 "clk81", /* parent */ \
681 HHI_GCLK_OTHER, /* reg */ \
682 6) /* bit */
683 #define G12_CLK_vclk2_other \
684 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_OTHER, "vclk2_other", \
685 "clk81", /* parent */ \
686 HHI_GCLK_OTHER, /* reg */ \
687 7) /* bit */
688 #define G12_CLK_vclk2_enci \
689 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCI, "vclk2_enci", \
690 "clk81", /* parent */ \
691 HHI_GCLK_OTHER, /* reg */ \
692 8) /* bit */
693 #define G12_CLK_vclk2_encp \
694 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCP, "vclk2_encp", \
695 "clk81", /* parent */ \
696 HHI_GCLK_OTHER, /* reg */ \
697 9) /* bit */
698 #define G12_CLK_dac_clk \
699 MESON_CLK_GATE(MESONG12_CLOCK_DAC_CLK, "dac_clk", \
700 "clk81", /* parent */ \
701 HHI_GCLK_OTHER, /* reg */ \
702 10) /* bit */
703 #define G12_CLK_aoclk \
704 MESON_CLK_GATE(MESONG12_CLOCK_AOCLK, "aoclk", \
705 "clk81", /* parent */ \
706 HHI_GCLK_OTHER, /* reg */ \
707 14) /* bit */
708 #define G12_CLK_iec958 \
709 MESON_CLK_GATE(MESONG12_CLOCK_IEC958, "iec958", \
710 "clk81", /* parent */ \
711 HHI_GCLK_OTHER, /* reg */ \
712 16) /* bit */
713 #define G12_CLK_enc480p \
714 MESON_CLK_GATE(MESONG12_CLOCK_ENC480P, "enc480p", \
715 "clk81", /* parent */ \
716 HHI_GCLK_OTHER, /* reg */ \
717 20) /* bit */
718 #define G12_CLK_rng1 \
719 MESON_CLK_GATE(MESONG12_CLOCK_RNG1, "rng1", \
720 "clk81", /* parent */ \
721 HHI_GCLK_OTHER, /* reg */ \
722 21) /* bit */
723 #define G12_CLK_vclk2_enct \
724 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCT, "vclk2_enct", \
725 "clk81", /* parent */ \
726 HHI_GCLK_OTHER, /* reg */ \
727 22) /* bit */
728 #define G12_CLK_vclk2_encl \
729 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_ENCL, "vclk2_encl", \
730 "clk81", /* parent */ \
731 HHI_GCLK_OTHER, /* reg */ \
732 23) /* bit */
733 #define G12_CLK_vclk2_venclmmc \
734 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCLMMC, "vclk2_venclmmc", \
735 "clk81", /* parent */ \
736 HHI_GCLK_OTHER, /* reg */ \
737 24) /* bit */
738 #define G12_CLK_vclk2_vencl \
739 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_VENCL, "vclk2_vencl", \
740 "clk81", /* parent */ \
741 HHI_GCLK_OTHER, /* reg */ \
742 25) /* bit */
743 #define G12_CLK_vclk2_other1 \
744 MESON_CLK_GATE(MESONG12_CLOCK_VCLK2_OTHER1, "vclk2_other1", \
745 "clk81", /* parent */ \
746 HHI_GCLK_OTHER, /* reg */ \
747 26) /* bit */
748 #define G12_CLK_dma \
749 MESON_CLK_GATE(MESONG12_CLOCK_DMA, "dma", \
750 "clk81", /* parent */ \
751 HHI_GCLK_OTHER2, /* reg */ \
752 0) /* bit */
753 #define G12_CLK_efuse \
754 MESON_CLK_GATE(MESONG12_CLOCK_EFUSE, "efuse", \
755 "clk81", /* parent */ \
756 HHI_GCLK_OTHER2, /* reg */ \
757 1) /* bit */
758 #define G12_CLK_rom_boot \
759 MESON_CLK_GATE(MESONG12_CLOCK_ROM_BOOT, "rom_boot", \
760 "clk81", /* parent */ \
761 HHI_GCLK_OTHER2, /* reg */ \
762 2) /* bit */
763 #define G12_CLK_reset_sec \
764 MESON_CLK_GATE(MESONG12_CLOCK_RESET_SEC, "reset_sec", \
765 "clk81", /* parent */ \
766 HHI_GCLK_OTHER2, /* reg */ \
767 3) /* bit */
768 #define G12_CLK_sec_ahb_apb3 \
769 MESON_CLK_GATE(MESONG12_CLOCK_SEC_AHB_APB3, "sec_ahb_apb3", \
770 "clk81", /* parent */ \
771 HHI_GCLK_OTHER2, /* reg */ \
772 4) /* bit */
773
774 /* little cpu cluster */
775 #define G12_CLK_cpu_clk_dyn0_sel \
776 MESON_CLK_MUX(MESONG12_CLOCK_CPU_CLK_DYN0_SEL, "cpu_clk_dyn0_sel", \
777 PARENTS("fclk_div2", "fclk_div3", "xtal"), \
778 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
779 __BITS(1,0), /* sel */ \
780 0)
781 #define G12_CLK_cpu_clk_dyn1_sel \
782 MESON_CLK_MUX(MESONG12_CLOCK_CPU_CLK_DYN1_SEL, "cpu_clk_dyn1_sel", \
783 PARENTS("fclk_div2", "fclk_div3", "xtal"), \
784 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
785 __BITS(17,16), /* sel */ \
786 0)
787 #define G12_CLK_cpu_clk_dyn0_div \
788 MESON_CLK_DIV(MESONG12_CLOCK_CPU_CLK_DYN0_DIV, "cpu_clk_dyn0_div", \
789 "cpu_clk_dyn0_sel", /* parent */ \
790 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
791 __BIT(26), /* div */ \
792 0)
793 #define G12_CLK_cpu_clk_dyn1_div \
794 MESON_CLK_DIV(MESONG12_CLOCK_CPU_CLK_DYN1_DIV, "cpu_clk_dyn1_div", \
795 "cpu_clk_dyn1_sel", /* parent */ \
796 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
797 __BITS(25,20), /* div */ \
798 0)
799 #define G12_CLK_cpu_clk_dyn0 \
800 MESON_CLK_MUX(MESONG12_CLOCK_CPU_CLK_DYN0, "cpu_clk_dyn0", \
801 PARENTS("cpu_clk_dyn0_div", "cpu_clk_dyn0_sel"), \
802 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
803 __BIT(2), /* sel */ \
804 0)
805 #define G12_CLK_cpu_clk_dyn1 \
806 MESON_CLK_MUX(MESONG12_CLOCK_CPU_CLK_DYN1, "cpu_clk_dyn1", \
807 PARENTS("cpu_clk_dyn1_div", "cpu_clk_dyn1_sel"), \
808 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
809 __BIT(18), /* sel */ \
810 0)
811 #define G12_CLK_cpu_clk_dyn \
812 MESON_CLK_MUX(MESONG12_CLOCK_CPU_CLK_DYN, "cpu_clk_dyn", \
813 PARENTS("cpu_clk_dyn0", "cpu_clk_dyn1"), \
814 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
815 __BIT(10), /* sel */ \
816 0)
817 #define G12A_CLK_cpu_clk \
818 MESON_CLK_MUX_RATE(MESONG12_CLOCK_CPU_CLK, "cpu_clk", \
819 PARENTS("cpu_clk_dyn", "sys_pll"), \
820 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
821 __BIT(11), /* sel */ \
822 mesong12_cpuclk_get_rate, \
823 mesong12_cpuclk_set_rate, \
824 0)
825 #define G12B_CLK_cpu_clk \
826 MESON_CLK_MUX_RATE(MESONG12_CLOCK_CPU_CLK, "cpu_clk", \
827 PARENTS("cpu_clk_dyn", "sys1_pll"), \
828 HHI_SYS_CPU_CLK_CNTL0, /* reg */ \
829 __BIT(11), /* sel */ \
830 mesong12_cpuclk_get_rate, \
831 mesong12_cpuclk_set_rate, \
832 0)
833
834 /* big cpu cluster */
835 #define G12_CLK_cpub_clk_dyn0_sel \
836 MESON_CLK_MUX(MESONG12_CLOCK_CPUB_CLK_DYN0_SEL, "cpub_clk_dyn0_sel", \
837 PARENTS("fclk_div2", "fclk_div3", "xtal"), \
838 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
839 __BITS(1,0), /* sel */ \
840 0)
841 #define G12_CLK_cpub_clk_dyn0_div \
842 MESON_CLK_DIV(MESONG12_CLOCK_CPUB_CLK_DYN0_DIV, "cpub_clk_dyn0_div", \
843 "cpub_clk_dyn0_sel", /* parent */ \
844 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
845 __BITS(9,4), /* div */ \
846 0)
847 #define G12_CLK_cpub_clk_dyn0 \
848 MESON_CLK_MUX(MESONG12_CLOCK_CPUB_CLK_DYN0, "cpub_clk_dyn0", \
849 PARENTS("cpub_clk_dyn0_div", "cpub_clk_dyn0_sel"), \
850 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
851 __BIT(2), /* sel */ \
852 0)
853 #define G12_CLK_cpub_clk_dyn1_sel \
854 MESON_CLK_MUX(MESONG12_CLOCK_CPUB_CLK_DYN1_SEL, "cpub_clk_dyn1_sel", \
855 PARENTS("fclk_div2", "fclk_div3", "xtal", "xtal"), \
856 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
857 __BITS(17,16), /* sel */ \
858 0)
859 #define G12_CLK_cpub_clk_dyn1_div \
860 MESON_CLK_DIV(MESONG12_CLOCK_CPUB_CLK_DYN1_DIV, "cpub_clk_dyn1_div", \
861 "cpub_clk_dyn1_sel", /* parent */ \
862 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
863 __BITS(25,20), /* div */ \
864 0)
865 #define G12_CLK_cpub_clk_dyn1 \
866 MESON_CLK_MUX(MESONG12_CLOCK_CPUB_CLK_DYN1, "cpub_clk_dyn1", \
867 PARENTS("cpub_clk_dyn1_div", "cpub_clk_dyn1_sel"), \
868 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
869 __BIT(18), /* sel */ \
870 0)
871 #define G12_CLK_cpub_clk_dyn \
872 MESON_CLK_MUX(MESONG12_CLOCK_CPUB_CLK_DYN, "cpub_clk_dyn", \
873 PARENTS("cpub_clk_dyn0", "cpub_clk_dyn1"), \
874 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
875 __BIT(10), /* sel */ \
876 0)
877 #define G12_CLK_cpub_clk \
878 MESON_CLK_MUX_RATE(MESONG12_CLOCK_CPUB_CLK, "cpub_clk", \
879 PARENTS("cpub_clk_dyn", "sys_pll"), \
880 HHI_SYS_CPUB_CLK_CNTL, /* reg */ \
881 __BIT(11), /* sel */ \
882 mesong12_cpuclk_get_rate, \
883 mesong12_cpuclk_set_rate, \
884 0)
885
886 /* ts */
887 #define G12_CLK_ts_div \
888 MESON_CLK_DIV(MESONG12_CLOCK_TS_DIV, "ts_div", \
889 "xtal", /* parent */ \
890 HHI_TS_CLK_CNTL, /* reg */ \
891 __BITS(7,0), /* div */ \
892 0)
893 #define G12_CLK_ts \
894 MESON_CLK_GATE(MESONG12_CLOCK_TS, "ts", \
895 "ts_div", /* parent */ \
896 HHI_TS_CLK_CNTL, /* ret */ \
897 8) /* bit */
898
899 /* hdmi */
900 #define G12_CLK_hdmi_pll_dco \
901 MESON_CLK_PLL(MESONG12_CLOCK_HDMI_PLL_DCO, "hdmi_pll_dco", \
902 "xtal", /* parent */ \
903 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(28)), /* enable */ \
904 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(7,0)), /* m */ \
905 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(14,10)),/* n */ \
906 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL1, __BITS(15,0)),/* frac */ \
907 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(30)), /* l */ \
908 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(29)), /* reset */ \
909 0)
910 #define G12_CLK_hdmi_pll_od \
911 MESON_CLK_DIV(MESONG12_CLOCK_HDMI_PLL_OD, "hdmi_pll_od", \
912 "hdmi_pll_dco", /* parent */ \
913 HHI_HDMI_PLL_CNTL0, /* reg */ \
914 __BITS(17,16), /* div */ \
915 MESON_CLK_DIV_POWER_OF_TWO)
916 #define G12_CLK_hdmi_pll_od2 \
917 MESON_CLK_DIV(MESONG12_CLOCK_HDMI_PLL_OD2, "hdmi_pll_od2", \
918 "hdmi_pll_od", /* parent */ \
919 HHI_HDMI_PLL_CNTL0, /* reg */ \
920 __BITS(19,18), /* div */ \
921 MESON_CLK_DIV_POWER_OF_TWO)
922 #define G12_CLK_hdmi_pll \
923 MESON_CLK_DIV(MESONG12_CLOCK_HDMI_PLL, "hdmi_pll", \
924 "hdmi_pll_od2", /* parent */ \
925 HHI_HDMI_PLL_CNTL0, /* reg */ \
926 __BITS(21,20), /* div */ \
927 MESON_CLK_DIV_POWER_OF_TWO)
928
929 #define G12_CLK_vid_pll_div \
930 MESON_CLK_DIV(MESONG12_CLOCK_VID_PLL_DIV, "vid_pll_div", \
931 "hdmi_pll", /* parent */ \
932 HHI_FIX_PLL_CNTL0, /* reg */ \
933 __BITS(17,16), /* div */ \
934 0)
935 #define G12_CLK_vid_pll_sel \
936 MESON_CLK_MUX(MESONG12_CLOCK_VID_PLL_SEL, "vid_pll_sel", \
937 PARENTS("vid_pll_div", "hdmi_pll"), \
938 HHI_VID_PLL_CLK_DIV, /* reg */ \
939 __BIT(18), /* sel */ \
940 0)
941 #define G12_CLK_vid_pll \
942 MESON_CLK_GATE(MESONG12_CLOCK_VID_PLL, "vid_pll", \
943 "vid_pll_sel", /* parent */ \
944 HHI_VID_PLL_CLK_DIV, /* reg */ \
945 19) /* bit */
946
947 /* USB3/PCIe */
948 #define G12_CLK_pcie_pll_dco \
949 MESON_CLK_PLL_RATE(MESONG12_CLOCK_PCIE_PLL_DCO, "pcie_pll_dco", \
950 "xtal", /* parent */ \
951 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(28)), /* enable */ \
952 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(7,0)), /* m */ \
953 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(14,10)),/* n */ \
954 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL1, __BITS(11,0)),/* frac */ \
955 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(31)), /* l */ \
956 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(29)), /* reset */ \
957 mesong12_clk_pcie_pll_set_rate, \
958 0)
959 #define G12_CLK_pcie_pll_dco_div2 \
960 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_PCIE_PLL_DCO_DIV2, \
961 "pcie_pll_dco_div2", \
962 "pcie_pll_dco", /* parent */ \
963 2, /* div */ \
964 1) /* mult */
965 #define G12_CLK_pcie_pll_od \
966 MESON_CLK_DIV(MESONG12_CLOCK_PCIE_PLL_OD, "pcie_pll_od", \
967 "pcie_pll_dco_div2", /* parent */ \
968 HHI_PCIE_PLL_CNTL0, /* reg */ \
969 __BITS(20,16), /* div */ \
970 MESON_CLK_DIV_SET_RATE_PARENT)
971 #define G12_CLK_pcie_pll_pll \
972 MESON_CLK_FIXED_FACTOR(MESONG12_CLOCK_PCIE_PLL, "pcie_pll_pll", \
973 "pcie_pll_od", /* parent */ \
974 2, /* div */ \
975 1) /* mult */
976
977 /* not all clocks are defined */
978 static struct meson_clk_clk mesong12a_clkc_clks[] = {
979 G12_CLK_fixed_pll_dco,
980 G12_CLK_fixed_pll,
981 G12_CLK_sys_pll_dco,
982 G12_CLK_sys_pll,
983 G12_CLK_fclk_div2_div,
984 G12_CLK_fclk_div2,
985 G12_CLK_fclk_div2p5_div,
986 G12_CLK_fclk_div3_div,
987 G12_CLK_fclk_div3,
988 G12_CLK_fclk_div4_div,
989 G12_CLK_fclk_div4,
990 G12_CLK_fclk_div5_div,
991 G12_CLK_fclk_div5,
992 G12_CLK_fclk_div7_div,
993 G12_CLK_fclk_div7,
994 G12_CLK_mpll_prediv,
995 G12_CLK_mpll0_div,
996 G12_CLK_mpll1_div,
997 G12_CLK_mpll2_div,
998 G12_CLK_mpll0,
999 G12_CLK_mpll1,
1000 G12_CLK_mpll2,
1001 G12_CLK_mpeg_sel,
1002 G12_CLK_mpeg_clk_div,
1003 G12_CLK_clk81,
1004 G12_CLK_mpll_50m_div,
1005 G12_CLK_mpll_50m,
1006 G12_CLK_sd_emmc_a_clk0_sel,
1007 G12_CLK_sd_emmc_b_clk0_sel,
1008 G12_CLK_sd_emmc_c_clk0_sel,
1009 G12_CLK_sd_emmc_a_clk0_div,
1010 G12_CLK_sd_emmc_b_clk0_div,
1011 G12_CLK_sd_emmc_c_clk0_div,
1012 G12_CLK_sd_emmc_a_clk0,
1013 G12_CLK_sd_emmc_b_clk0,
1014 G12_CLK_sd_emmc_c_clk0,
1015 G12_CLK_ddr,
1016 G12_CLK_dos,
1017 G12_CLK_audio_locker,
1018 G12_CLK_mipi_dsi_host,
1019 G12_CLK_eth_phy,
1020 G12_CLK_isa,
1021 G12_CLK_pl301,
1022 G12_CLK_periphs,
1023 G12_CLK_spicc0,
1024 G12_CLK_i2c,
1025 G12_CLK_sana,
1026 G12_CLK_sd,
1027 G12_CLK_rng0,
1028 G12_CLK_uart0,
1029 G12_CLK_spicc1,
1030 G12_CLK_hiu_iface,
1031 G12_CLK_mipi_dsi_phy,
1032 G12_CLK_assist_misc,
1033 G12_CLK_sd_emmc_a,
1034 G12_CLK_sd_emmc_b,
1035 G12_CLK_sd_emmc_c,
1036 G12_CLK_audio_codec,
1037 G12_CLK_audio,
1038 G12_CLK_eth,
1039 G12_CLK_demux,
1040 G12_CLK_audio_ififo,
1041 G12_CLK_adc,
1042 G12_CLK_uart1,
1043 G12_CLK_g2d,
1044 G12_CLK_reset,
1045 G12_CLK_pcie_comb,
1046 G12_CLK_parser,
1047 G12_CLK_usb,
1048 G12_CLK_pcie_phy,
1049 G12_CLK_ahb_arb0,
1050 G12_CLK_ahb_data_bus,
1051 G12_CLK_ahb_ctrl_bus,
1052 G12_CLK_htx_hdcp22,
1053 G12_CLK_htx_pclk,
1054 G12_CLK_bt656,
1055 G12_CLK_usb1_ddr_bridge,
1056 G12_CLK_mmc_pclk,
1057 G12_CLK_uart2,
1058 G12_CLK_vpu_intr,
1059 G12_CLK_gic,
1060 G12_CLK_vclk2_venci0,
1061 G12_CLK_vclk2_venci1,
1062 G12_CLK_vclk2_vencp0,
1063 G12_CLK_vclk2_vencp1,
1064 G12_CLK_vclk2_venct0,
1065 G12_CLK_vclk2_venct1,
1066 G12_CLK_vclk2_other,
1067 G12_CLK_vclk2_enci,
1068 G12_CLK_vclk2_encp,
1069 G12_CLK_dac_clk,
1070 G12_CLK_aoclk,
1071 G12_CLK_iec958,
1072 G12_CLK_enc480p,
1073 G12_CLK_rng1,
1074 G12_CLK_vclk2_enct,
1075 G12_CLK_vclk2_encl,
1076 G12_CLK_vclk2_venclmmc,
1077 G12_CLK_vclk2_vencl,
1078 G12_CLK_vclk2_other1,
1079 G12_CLK_dma,
1080 G12_CLK_efuse,
1081 G12_CLK_rom_boot,
1082 G12_CLK_reset_sec,
1083 G12_CLK_sec_ahb_apb3,
1084 G12_CLK_cpu_clk_dyn0_sel,
1085 G12_CLK_cpu_clk_dyn1_sel,
1086 G12_CLK_cpu_clk_dyn0_div,
1087 G12_CLK_cpu_clk_dyn1_div,
1088 G12_CLK_cpu_clk_dyn0,
1089 G12_CLK_cpu_clk_dyn1,
1090 G12_CLK_cpu_clk_dyn,
1091 G12A_CLK_cpu_clk,
1092 G12_CLK_ts_div,
1093 G12_CLK_ts,
1094 G12_CLK_hdmi_pll_dco,
1095 G12_CLK_hdmi_pll_od,
1096 G12_CLK_hdmi_pll_od2,
1097 G12_CLK_hdmi_pll,
1098 G12_CLK_vid_pll_div,
1099 G12_CLK_vid_pll_sel,
1100 G12_CLK_vid_pll,
1101 G12_CLK_pcie_pll_dco,
1102 G12_CLK_pcie_pll_dco_div2,
1103 G12_CLK_pcie_pll_od,
1104 G12_CLK_pcie_pll_pll
1105 };
1106
1107 static struct meson_clk_clk mesong12b_clkc_clks[] = {
1108 G12_CLK_fixed_pll_dco,
1109 G12_CLK_fixed_pll,
1110 G12_CLK_sys_pll_dco,
1111 G12_CLK_sys_pll,
1112 G12B_CLK_sys1_pll_dco,
1113 G12B_CLK_sys1_pll,
1114 G12_CLK_fclk_div2_div,
1115 G12_CLK_fclk_div2,
1116 G12_CLK_fclk_div2p5_div,
1117 G12_CLK_fclk_div3_div,
1118 G12_CLK_fclk_div3,
1119 G12_CLK_fclk_div4_div,
1120 G12_CLK_fclk_div4,
1121 G12_CLK_fclk_div5_div,
1122 G12_CLK_fclk_div5,
1123 G12_CLK_fclk_div7_div,
1124 G12_CLK_fclk_div7,
1125 G12_CLK_mpll_prediv,
1126 G12_CLK_mpll0_div,
1127 G12_CLK_mpll1_div,
1128 G12_CLK_mpll2_div,
1129 G12_CLK_mpll0,
1130 G12_CLK_mpll1,
1131 G12_CLK_mpll2,
1132 G12_CLK_mpeg_sel,
1133 G12_CLK_mpeg_clk_div,
1134 G12_CLK_clk81,
1135 G12_CLK_mpll_50m_div,
1136 G12_CLK_mpll_50m,
1137 G12_CLK_sd_emmc_a_clk0_sel,
1138 G12_CLK_sd_emmc_b_clk0_sel,
1139 G12_CLK_sd_emmc_c_clk0_sel,
1140 G12_CLK_sd_emmc_a_clk0_div,
1141 G12_CLK_sd_emmc_b_clk0_div,
1142 G12_CLK_sd_emmc_c_clk0_div,
1143 G12_CLK_sd_emmc_a_clk0,
1144 G12_CLK_sd_emmc_b_clk0,
1145 G12_CLK_sd_emmc_c_clk0,
1146 G12_CLK_ddr,
1147 G12_CLK_dos,
1148 G12_CLK_audio_locker,
1149 G12_CLK_mipi_dsi_host,
1150 G12_CLK_eth_phy,
1151 G12_CLK_isa,
1152 G12_CLK_pl301,
1153 G12_CLK_periphs,
1154 G12_CLK_spicc0,
1155 G12_CLK_i2c,
1156 G12_CLK_sana,
1157 G12_CLK_sd,
1158 G12_CLK_rng0,
1159 G12_CLK_uart0,
1160 G12_CLK_spicc1,
1161 G12_CLK_hiu_iface,
1162 G12_CLK_mipi_dsi_phy,
1163 G12_CLK_assist_misc,
1164 G12_CLK_sd_emmc_a,
1165 G12_CLK_sd_emmc_b,
1166 G12_CLK_sd_emmc_c,
1167 G12_CLK_audio_codec,
1168 G12_CLK_audio,
1169 G12_CLK_eth,
1170 G12_CLK_demux,
1171 G12_CLK_audio_ififo,
1172 G12_CLK_adc,
1173 G12_CLK_uart1,
1174 G12_CLK_g2d,
1175 G12_CLK_reset,
1176 G12_CLK_pcie_comb,
1177 G12_CLK_parser,
1178 G12_CLK_usb,
1179 G12_CLK_pcie_phy,
1180 G12_CLK_ahb_arb0,
1181 G12_CLK_ahb_data_bus,
1182 G12_CLK_ahb_ctrl_bus,
1183 G12_CLK_htx_hdcp22,
1184 G12_CLK_htx_pclk,
1185 G12_CLK_bt656,
1186 G12_CLK_usb1_ddr_bridge,
1187 G12_CLK_mmc_pclk,
1188 G12_CLK_uart2,
1189 G12_CLK_vpu_intr,
1190 G12_CLK_gic,
1191 G12_CLK_vclk2_venci0,
1192 G12_CLK_vclk2_venci1,
1193 G12_CLK_vclk2_vencp0,
1194 G12_CLK_vclk2_vencp1,
1195 G12_CLK_vclk2_venct0,
1196 G12_CLK_vclk2_venct1,
1197 G12_CLK_vclk2_other,
1198 G12_CLK_vclk2_enci,
1199 G12_CLK_vclk2_encp,
1200 G12_CLK_dac_clk,
1201 G12_CLK_aoclk,
1202 G12_CLK_iec958,
1203 G12_CLK_enc480p,
1204 G12_CLK_rng1,
1205 G12_CLK_vclk2_enct,
1206 G12_CLK_vclk2_encl,
1207 G12_CLK_vclk2_venclmmc,
1208 G12_CLK_vclk2_vencl,
1209 G12_CLK_vclk2_other1,
1210 G12_CLK_dma,
1211 G12_CLK_efuse,
1212 G12_CLK_rom_boot,
1213 G12_CLK_reset_sec,
1214 G12_CLK_sec_ahb_apb3,
1215 G12_CLK_cpu_clk_dyn0_sel,
1216 G12_CLK_cpu_clk_dyn1_sel,
1217 G12_CLK_cpu_clk_dyn0_div,
1218 G12_CLK_cpu_clk_dyn1_div,
1219 G12_CLK_cpu_clk_dyn0,
1220 G12_CLK_cpu_clk_dyn1,
1221 G12_CLK_cpu_clk_dyn,
1222 G12B_CLK_cpu_clk,
1223 G12_CLK_cpub_clk_dyn0_sel,
1224 G12_CLK_cpub_clk_dyn0_div,
1225 G12_CLK_cpub_clk_dyn0,
1226 G12_CLK_cpub_clk_dyn1_sel,
1227 G12_CLK_cpub_clk_dyn1_div,
1228 G12_CLK_cpub_clk_dyn1,
1229 G12_CLK_cpub_clk_dyn,
1230 G12_CLK_cpub_clk,
1231 G12_CLK_ts_div,
1232 G12_CLK_ts,
1233 G12_CLK_hdmi_pll_dco,
1234 G12_CLK_hdmi_pll_od,
1235 G12_CLK_hdmi_pll_od2,
1236 G12_CLK_hdmi_pll,
1237 G12_CLK_vid_pll_div,
1238 G12_CLK_vid_pll_sel,
1239 G12_CLK_vid_pll,
1240 G12_CLK_pcie_pll_dco,
1241 G12_CLK_pcie_pll_dco_div2,
1242 G12_CLK_pcie_pll_od,
1243 G12_CLK_pcie_pll_pll
1244 };
1245
1246 /*
1247 * XXX:
1248 * mesong12_cpuclk_get_rate() is needed because the source clock exceeds 32bit
1249 * and sys/dev/clk cannot handle it.
1250 * By modifying sys/dev/clk to be able to handle 64-bit clocks, this function
1251 * will no longer be needed.
1252 */
1253 static u_int
mesong12_cpuclk_get_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk)1254 mesong12_cpuclk_get_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk)
1255 {
1256 bus_size_t reg_cntl0;
1257 uint64_t freq;
1258 uint32_t val, m, n, div_shift, div;
1259 uint64_t xtal_clock = clk_get_rate(fdtbus_clock_byname("xtal"));
1260
1261 KASSERT(clk->type == MESON_CLK_MUX);
1262 if (sc->sc_clks == mesong12a_clkc_clks) {
1263 reg_cntl0 = HHI_SYS_PLL_CNTL0;
1264 } else {
1265 switch (clk->u.mux.reg) {
1266 case HHI_SYS_CPU_CLK_CNTL0:
1267 reg_cntl0 = HHI_SYS1_PLL_CNTL0;
1268 break;
1269 case HHI_SYS_CPUB_CLK_CNTL:
1270 reg_cntl0 = HHI_SYS_PLL_CNTL0;
1271 break;
1272 default:
1273 panic("%s: illegal clk table\n", __func__);
1274 }
1275 }
1276 CLK_LOCK(sc);
1277
1278 if ((CLK_READ(sc, clk->u.mux.reg) & __BIT(11)) == 0) {
1279 CLK_UNLOCK(sc);
1280
1281 /* use dyn clock instead of sys1?_pll */
1282 struct clk *clkp;
1283
1284 switch (clk->u.mux.reg) {
1285 case HHI_SYS_CPU_CLK_CNTL0:
1286 clkp = (struct clk *)meson_clk_clock_find(sc,
1287 "cpu_clk_dyn");
1288 freq = clk_get_rate(clkp);
1289 break;
1290 case HHI_SYS_CPUB_CLK_CNTL:
1291 clkp = (struct clk *)meson_clk_clock_find(sc,
1292 "cpub_clk_dyn");
1293 freq = clk_get_rate(clkp);
1294 break;
1295 default:
1296 freq = 0;
1297 break;
1298 }
1299 return freq;
1300 }
1301 val = CLK_READ(sc, reg_cntl0);
1302 m = __SHIFTOUT(val, __BITS(7,0));
1303 n = __SHIFTOUT(val, __BITS(14,10));
1304 div_shift = __SHIFTOUT(val, __BITS(18,16));
1305 div = 1 << div_shift;
1306 CLK_UNLOCK(sc);
1307
1308 freq = xtal_clock * m / n / div;
1309 return freq;
1310 }
1311
1312 static int
mesong12_cpuclk_set_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk,u_int rate)1313 mesong12_cpuclk_set_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk,
1314 u_int rate)
1315 {
1316 bus_size_t reg_cntl0;
1317 uint32_t val;
1318 uint64_t xtal_clock = clk_get_rate(fdtbus_clock_byname("xtal"));
1319 int new_m, new_n, new_div, i, error;
1320
1321 KASSERT(clk->type == MESON_CLK_MUX);
1322 if (sc->sc_clks == mesong12a_clkc_clks) {
1323 reg_cntl0 = HHI_SYS_PLL_CNTL0;
1324 } else {
1325 switch (clk->u.mux.reg) {
1326 case HHI_SYS_CPU_CLK_CNTL0:
1327 reg_cntl0 = HHI_SYS1_PLL_CNTL0;
1328 break;
1329 case HHI_SYS_CPUB_CLK_CNTL:
1330 reg_cntl0 = HHI_SYS_PLL_CNTL0;
1331 break;
1332 default:
1333 panic("%s: illegal clk table\n", __func__);
1334 }
1335 }
1336
1337 new_div = 7;
1338 new_n = 1;
1339 new_m = (uint64_t)rate * (1 << new_div) / xtal_clock;
1340 while (new_m >= 250 && (new_div > 0)) {
1341 new_div--;
1342 new_m /= 2;
1343 }
1344
1345 if (new_m >= 256)
1346 return EINVAL;
1347
1348 CLK_LOCK(sc);
1349
1350 /* use cpub?_clk_dyn temporary */
1351 val = CLK_READ(sc, clk->u.mux.reg);
1352 CLK_WRITE(sc, clk->u.mux.reg, val & ~__BIT(11));
1353 DELAY(100);
1354
1355 #define MESON_PLL_CNTL_REG_LOCK __BIT(31)
1356 #define MESON_PLL_CNTL_REG_RST __BIT(29)
1357 #define MESON_PLL_CNTL_REG_EN __BIT(28)
1358 /* disable */
1359 val = CLK_READ(sc, reg_cntl0);
1360 CLK_WRITE(sc, reg_cntl0, val | MESON_PLL_CNTL_REG_RST);
1361 val = CLK_READ(sc, reg_cntl0);
1362 CLK_WRITE(sc, reg_cntl0, val & ~MESON_PLL_CNTL_REG_EN);
1363
1364 /* HHI_SYS{,1}_PLL_CNTL{1,2,3,4,5} */
1365 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(1), 0x00000000);
1366 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(2), 0x00000000);
1367 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(3), 0x48681c00);
1368 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(4), 0x88770290);
1369 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(5), 0x39272000);
1370 DELAY(100);
1371
1372 /* write new M, N, and DIV */
1373 val = CLK_READ(sc, reg_cntl0);
1374 val &= ~__BITS(7,0);
1375 val |= __SHIFTIN(new_m, __BITS(7,0));
1376 val &= ~__BITS(14,10);
1377 val |= __SHIFTIN(new_n, __BITS(14,10));
1378 val &= ~__BITS(18,16);
1379 val |= __SHIFTIN(new_div, __BITS(18,16));
1380 CLK_WRITE(sc, reg_cntl0, val);
1381
1382 /* enable */
1383 val = CLK_READ(sc, reg_cntl0);
1384 CLK_WRITE(sc, reg_cntl0, val | MESON_PLL_CNTL_REG_RST);
1385 val = CLK_READ(sc, reg_cntl0);
1386 CLK_WRITE(sc, reg_cntl0, val | MESON_PLL_CNTL_REG_EN);
1387 DELAY(1000);
1388 val = CLK_READ(sc, reg_cntl0);
1389 CLK_WRITE(sc, reg_cntl0, val & ~MESON_PLL_CNTL_REG_RST);
1390
1391 error = ETIMEDOUT;
1392 for (i = 24000000; i > 0; i--) {
1393 if ((CLK_READ(sc, reg_cntl0) & MESON_PLL_CNTL_REG_LOCK) != 0) {
1394 error = 0;
1395 break;
1396 }
1397 }
1398
1399 /* XXX: always use sys1?_pll. cpub?_clk_dyn should be used for <1GHz */
1400 val = CLK_READ(sc, clk->u.mux.reg);
1401 CLK_WRITE(sc, clk->u.mux.reg, val | __BIT(11));
1402 DELAY(100);
1403
1404 CLK_UNLOCK(sc);
1405
1406 return error;
1407 }
1408
1409 static int
mesong12_clk_pcie_pll_set_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk,u_int new_rate)1410 mesong12_clk_pcie_pll_set_rate(struct meson_clk_softc *sc,
1411 struct meson_clk_clk *clk, u_int new_rate)
1412 {
1413 struct meson_clk_pll *pll = &clk->u.pll;
1414
1415 KASSERT(clk->type == MESON_CLK_PLL);
1416
1417 /*
1418 * A strict register sequence is required to set the PLL to the
1419 * fine-tuned 100MHz for PCIe
1420 */
1421 if (new_rate == (100000000 * 2 * 2)) { /* "2*2" is fixed factor */
1422 uint32_t cntl0, cntl4, cntl3, cntl5;
1423
1424 cntl0 = __SHIFTIN(9, HHI_PCIE_PLL_CNTL0_PCIE_APLL_OD) |
1425 __SHIFTIN(1, HHI_PCIE_PLL_CNTL0_PCIE_APLL_PREDIV_SEL) |
1426 __SHIFTIN(150, HHI_PCIE_PLL_CNTL0_PCIE_APLL_FBKDIV);
1427 cntl4 = __SHIFTIN(1, HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_CAPADJ) |
1428 HHI_PCIE_PLL_CNTL4_PCIE_APLL_LOAD |
1429 HHI_PCIE_PLL_CNTL4_PCIE_APLL_LOAD_EN;
1430 cntl3 = __SHIFTIN(1, HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_HOLD_T) |
1431 __SHIFTIN(2, HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_DIV) |
1432 HHI_PCIE_PLL_CNTL3_PCIE_APLL_BIAS_LPF_EN |
1433 __SHIFTIN(8, HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_ICAP) |
1434 __SHIFTIN(14, HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_IRES);
1435 cntl5 = __SHIFTIN(6, HHI_PCIE_PLL_CNTL5_PCIE_HCSL_ADJ_LDO) |
1436 HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGP_EN |
1437 HHI_PCIE_PLL_CNTL5_PCIE_HCSL_CAL_EN |
1438 HHI_PCIE_PLL_CNTL5_PCIE_HCSL_EN0;
1439
1440 CLK_LOCK(sc);
1441 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
1442 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1443 HHI_PCIE_PLL_CNTL0_PCIE_APLL_RESET);
1444 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1445 HHI_PCIE_PLL_CNTL0_PCIE_APLL_RESET |
1446 HHI_PCIE_PLL_CNTL0_PCIE_APLL_EN);
1447 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL1, 0);
1448 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL2,
1449 __SHIFTIN(0x1100, HHI_PCIE_PLL_CNTL2_PCIE_APLL_RESERVE));
1450 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL3, cntl3);
1451 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL4, cntl4);
1452 delay(20);
1453 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL5, cntl5);
1454 delay(10);
1455 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL5, cntl5 |
1456 HHI_PCIE_PLL_CNTL5_PCIE_HCSL_CAL_RSTN);
1457 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL4, cntl4 |
1458 HHI_PCIE_PLL_CNTL4_PCIE_APLL_VCTRL_MON_EN);
1459 delay(10);
1460 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1461 HHI_PCIE_PLL_CNTL0_PCIE_APLL_RESET |
1462 HHI_PCIE_PLL_CNTL0_PCIE_APLL_EN |
1463 HHI_PCIE_PLL_CNTL0_PCIE_APLL_AFC_START);
1464 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1465 HHI_PCIE_PLL_CNTL0_PCIE_APLL_EN |
1466 HHI_PCIE_PLL_CNTL0_PCIE_APLL_AFC_START);
1467 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL2,
1468 __SHIFTIN(0x1000, HHI_PCIE_PLL_CNTL2_PCIE_APLL_RESERVE));
1469
1470 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);
1471 /* XXX: pll_wait_lock() sometimes times out? but ignore it */
1472 meson_clk_pll_wait_lock(sc, pll);
1473 CLK_UNLOCK(sc);
1474 return 0;
1475 }
1476
1477 return meson_clk_pll_set_rate(sc, clk, new_rate);
1478 }
1479
1480 static const struct mesong12_clkc_config g12a_config = {
1481 .name = "Meson G12A",
1482 .clks = mesong12a_clkc_clks,
1483 .nclks = __arraycount(mesong12a_clkc_clks),
1484 };
1485
1486 static const struct mesong12_clkc_config g12b_config = {
1487 .name = "Meson G12B",
1488 .clks = mesong12b_clkc_clks,
1489 .nclks = __arraycount(mesong12b_clkc_clks),
1490 };
1491
1492 static const struct device_compatible_entry compat_data[] = {
1493 { .compat = "amlogic,g12a-clkc", .data = &g12a_config },
1494 { .compat = "amlogic,g12b-clkc", .data = &g12b_config },
1495 DEVICE_COMPAT_EOL
1496 };
1497
1498 CFATTACH_DECL_NEW(mesong12_clkc, sizeof(struct meson_clk_softc),
1499 mesong12_clkc_match, mesong12_clkc_attach, NULL, NULL);
1500
1501 static int
mesong12_clkc_match(device_t parent,cfdata_t cf,void * aux)1502 mesong12_clkc_match(device_t parent, cfdata_t cf, void *aux)
1503 {
1504 struct fdt_attach_args * const faa = aux;
1505
1506 return of_compatible_match(faa->faa_phandle, compat_data);
1507 }
1508
1509 static void
mesong12_clkc_attach(device_t parent,device_t self,void * aux)1510 mesong12_clkc_attach(device_t parent, device_t self, void *aux)
1511 {
1512 struct meson_clk_softc * const sc = device_private(self);
1513 struct fdt_attach_args * const faa = aux;
1514 const struct mesong12_clkc_config *conf;
1515 const int phandle = faa->faa_phandle;
1516
1517 sc->sc_dev = self;
1518 sc->sc_phandle = faa->faa_phandle;
1519 sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
1520 if (sc->sc_syscon == NULL) {
1521 aprint_error(": couldn't get syscon registers\n");
1522 return;
1523 }
1524
1525 conf = of_compatible_lookup(phandle, compat_data)->data;
1526 sc->sc_clks = conf->clks;
1527 sc->sc_nclks = conf->nclks;
1528
1529 aprint_naive("\n");
1530 aprint_normal(": %s clock controller\n", conf->name);
1531
1532 meson_clk_attach(sc);
1533 meson_clk_print(sc);
1534 }
1535