1 /* $NetBSD: meson_platform.c,v 1.21 2023/04/07 08:55:29 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_soc.h"
30 #include "opt_multiprocessor.h"
31 #include "opt_console.h"
32
33 #include "arml2cc.h"
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.21 2023/04/07 08:55:29 skrll Exp $");
37
38 #include <sys/param.h>
39 #include <sys/bus.h>
40 #include <sys/cpu.h>
41 #include <sys/device.h>
42 #include <sys/termios.h>
43
44 #include <dev/fdt/fdtvar.h>
45
46 #include <arm/fdt/arm_fdtvar.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <machine/bootconfig.h>
51 #include <arm/cpufunc.h>
52
53 #include <arm/cortex/a9tmr_var.h>
54 #include <arm/cortex/gtmr_var.h>
55 #include <arm/cortex/pl310_var.h>
56 #include <arm/cortex/scu_reg.h>
57
58 #include <arm/amlogic/meson_uart.h>
59
60 #include <evbarm/fdt/platform.h>
61 #include <evbarm/fdt/machdep.h>
62
63 #include <net/if_ether.h>
64
65 #include <libfdt.h>
66
67 #define MESON_CORE_APB3_VBASE KERNEL_IO_VBASE
68 #define MESON_CORE_APB3_PBASE 0xc0000000
69 #define MESON_CORE_APB3_SIZE 0x01400000
70
71 #define MESON_CBUS_OFFSET 0x01100000
72
73 #define MESON8B_WATCHDOG_BASE 0xc1109900
74 #define MESON8B_WATCHDOG_SIZE 0x8
75 #define MESON8B_WATCHDOG_TC 0x00
76 #define MESON8B_WATCHDOG_TC_CPUS __BITS(27,24)
77 #define MESON8B_WATCHDOG_TC_ENABLE __BIT(19)
78 #define MESON8B_WATCHDOG_TC_TCNT __BITS(15,0)
79 #define MESON8B_WATCHDOG_RESET 0x04
80 #define MESON8B_WATCHDOG_RESET_COUNT __BITS(15,0)
81
82 #define MESONGX_WATCHDOG_BASE 0xc11098d0
83 #define MESONGX_WATCHDOG_SIZE 0x10
84 #define MESONGX_WATCHDOG_CNTL 0x00
85 #define MESONGX_WATCHDOG_CNTL_CLK_EN __BIT(24)
86 #define MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN __BIT(21)
87 #define MESONGX_WATCHDOG_CNTL_WDOG_EN __BIT(18)
88 #define MESONGX_WATCHDOG_CNTL1 0x04
89 #define MESONGX_WATCHDOG_TCNT 0x08
90 #define MESONGX_WATCHDOG_TCNT_COUNT __BITS(15,0)
91 #define MESONGX_WATCHDOG_RESET 0x0c
92
93 #define MESON8B_ARM_VBASE (MESON_CORE_APB3_VBASE + MESON_CORE_APB3_SIZE)
94 #define MESON8B_ARM_PBASE 0xc4200000
95 #define MESON8B_ARM_SIZE 0x00200000
96 #define MESON8B_ARM_PL310_BASE 0x00000000
97 #define MESON8B_ARM_SCU_BASE 0x00100000
98
99 #define MESON8B_AOBUS_VBASE (MESON8B_ARM_VBASE + MESON8B_ARM_SIZE)
100 #define MESON8B_AOBUS_PBASE 0xc8000000
101 #define MESON8B_AOBUS_SIZE 0x00200000
102 #define MESON8B_AOBUS_RTI_OFFSET 0x00100000
103
104 #define MESON_AOBUS_PWR_CTRL0_REG 0xe0
105 #define MESON_AOBUS_PWR_CTRL1_REG 0xe4
106 #define MESON_AOBUS_PWR_MEM_PD0_REG 0xf4
107
108 #define MESON_CBUS_CPU_CLK_CNTL_REG 0x419c
109
110
111 #define MESON8B_SRAM_VBASE (MESON8B_AOBUS_VBASE + MESON8B_AOBUS_SIZE)
112 #define MESON8B_SRAM_PBASE 0xd9000000
113 #define MESON8B_SRAM_SIZE 0x00200000 /* 0x10000 rounded up */
114
115 #define MESON8B_SRAM_CPUCONF_OFFSET 0x1ff80
116 #define MESON8B_SRAM_CPUCONF_CTRL_REG 0x00
117 #define MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(n) (0x04 * (n))
118
119
120 extern struct arm32_bus_dma_tag arm_generic_dma_tag;
121 extern struct bus_space arm_generic_bs_tag;
122
123 #define meson_dma_tag arm_generic_dma_tag
124 #define meson_bs_tag arm_generic_bs_tag
125
126 static const struct pmap_devmap *
meson_platform_devmap(void)127 meson_platform_devmap(void)
128 {
129 static const struct pmap_devmap devmap[] = {
130 DEVMAP_ENTRY(MESON_CORE_APB3_VBASE,
131 MESON_CORE_APB3_PBASE,
132 MESON_CORE_APB3_SIZE),
133 DEVMAP_ENTRY(MESON8B_ARM_VBASE,
134 MESON8B_ARM_PBASE,
135 MESON8B_ARM_SIZE),
136 DEVMAP_ENTRY(MESON8B_AOBUS_VBASE,
137 MESON8B_AOBUS_PBASE,
138 MESON8B_AOBUS_SIZE),
139 DEVMAP_ENTRY(MESON8B_SRAM_VBASE,
140 MESON8B_SRAM_PBASE,
141 MESON8B_SRAM_SIZE),
142 DEVMAP_ENTRY_END
143 };
144
145 return devmap;
146 }
147
148 static void
meson_platform_init_attach_args(struct fdt_attach_args * faa)149 meson_platform_init_attach_args(struct fdt_attach_args *faa)
150 {
151 faa->faa_bst = &meson_bs_tag;
152 faa->faa_dmat = &meson_dma_tag;
153 }
154
155 void meson_platform_early_putchar(char);
156
157 void __noasan
meson_platform_early_putchar(char c)158 meson_platform_early_putchar(char c)
159 {
160 #ifdef CONSADDR
161 #define CONSADDR_VA ((CONSADDR - MESON8B_AOBUS_PBASE) + MESON8B_AOBUS_VBASE)
162 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
163 (volatile uint32_t *)CONSADDR_VA :
164 (volatile uint32_t *)CONSADDR;
165 int timo = 150000;
166
167 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) {
168 if (--timo == 0)
169 break;
170 }
171
172 uartaddr[UART_WFIFO_REG/4] = c;
173
174 while ((uartaddr[UART_STATUS_REG/4] & UART_STATUS_TX_EMPTY) == 0) {
175 if (--timo == 0)
176 break;
177 }
178 #endif
179 }
180
181 static void
meson_platform_device_register(device_t self,void * aux)182 meson_platform_device_register(device_t self, void *aux)
183 {
184 prop_dictionary_t dict = device_properties(self);
185
186 if (device_is_a(self, "awge") && device_unit(self) == 0) {
187 uint8_t enaddr[ETHER_ADDR_LEN];
188 if (get_bootconf_option(boot_args, "awge0.mac-address",
189 BOOTOPT_TYPE_MACADDR, enaddr)) {
190 prop_dictionary_set_data(dict, "mac-address", enaddr,
191 sizeof(enaddr));
192 }
193 }
194
195 if (device_is_a(self, "mesonfb")) {
196 int scale, depth;
197
198 if (get_bootconf_option(boot_args, "fb.scale",
199 BOOTOPT_TYPE_INT, &scale) && scale > 0) {
200 prop_dictionary_set_uint32(dict, "scale", scale);
201 }
202 if (get_bootconf_option(boot_args, "fb.depth",
203 BOOTOPT_TYPE_INT, &depth)) {
204 prop_dictionary_set_uint32(dict, "depth", depth);
205 }
206 }
207 }
208
209 #if defined(SOC_MESON8B)
210 #define MESON8B_BOOTINFO_REG 0xd901ff04
211 static int
meson8b_get_boot_id(void)212 meson8b_get_boot_id(void)
213 {
214 static int boot_id = -1;
215 bus_space_tag_t bst = &arm_generic_bs_tag;
216 bus_space_handle_t bsh;
217
218 if (boot_id == -1) {
219 if (bus_space_map(bst, MESON8B_BOOTINFO_REG, 4, 0, &bsh) != 0)
220 return -1;
221
222 boot_id = (int)bus_space_read_4(bst, bsh, 0);
223
224 bus_space_unmap(bst, bsh, 4);
225 }
226
227 return boot_id;
228 }
229
230 static void
meson8b_platform_device_register(device_t self,void * aux)231 meson8b_platform_device_register(device_t self, void *aux)
232 {
233 device_t parent = device_parent(self);
234 char *ptr;
235
236 if (device_is_a(self, "ld") &&
237 device_is_a(parent, "sdmmc") &&
238 (device_is_a(device_parent(parent), "mesonsdhc") ||
239 device_is_a(device_parent(parent), "mesonsdio"))) {
240
241 const int boot_id = meson8b_get_boot_id();
242 const bool has_rootdev = get_bootconf_option(boot_args, "root", BOOTOPT_TYPE_STRING, &ptr) != 0;
243
244 if (!has_rootdev) {
245 char rootarg[64];
246 snprintf(rootarg, sizeof(rootarg), " root=%sa", device_xname(self));
247
248 /* Assume that SDIO is used for SD cards and SDHC is used for eMMC */
249 if (device_is_a(device_parent(parent), "mesonsdhc") && boot_id == 0)
250 strcat(boot_args, rootarg);
251 else if (device_is_a(device_parent(parent), "mesonsdio") && boot_id != 0)
252 strcat(boot_args, rootarg);
253 }
254 }
255
256 meson_platform_device_register(self, aux);
257 }
258 #endif
259
260 static u_int
meson_platform_uart_freq(void)261 meson_platform_uart_freq(void)
262 {
263 return 0;
264 }
265
266 static void
meson_platform_bootstrap(void)267 meson_platform_bootstrap(void)
268 {
269 arm_fdt_cpu_bootstrap();
270
271 void *fdt_data = __UNCONST(fdtbus_get_data());
272 const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
273 if (chosen_off < 0)
274 return;
275
276 if (match_bootconf_option(boot_args, "console", "fb")) {
277 const int framebuffer_off =
278 fdt_path_offset(fdt_data, "/chosen/framebuffer");
279 if (framebuffer_off >= 0) {
280 const char *status = fdt_getprop(fdt_data,
281 framebuffer_off, "status", NULL);
282 if (status == NULL || strncmp(status, "ok", 2) == 0) {
283 fdt_setprop_string(fdt_data, chosen_off,
284 "stdout-path", "/chosen/framebuffer");
285 }
286 }
287 } else if (match_bootconf_option(boot_args, "console", "serial")) {
288 fdt_setprop_string(fdt_data, chosen_off,
289 "stdout-path", "serial0:115200n8");
290 }
291 }
292
293 #if defined(SOC_MESON8B)
294 static void
meson8b_platform_bootstrap(void)295 meson8b_platform_bootstrap(void)
296 {
297
298 #if NARML2CC > 0
299 const bus_space_handle_t pl310_bh = MESON8B_ARM_VBASE + MESON8B_ARM_PL310_BASE;
300 arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0);
301 #endif
302
303 meson_platform_bootstrap();
304 }
305
306 static void
meson8b_platform_reset(void)307 meson8b_platform_reset(void)
308 {
309 bus_space_tag_t bst = &meson_bs_tag;
310 bus_space_handle_t bsh;
311
312 bus_space_map(bst, MESON8B_WATCHDOG_BASE, MESON8B_WATCHDOG_SIZE, 0, &bsh);
313
314 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_TC,
315 MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT));
316 bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_RESET, 0);
317
318 for (;;) {
319 __asm("wfi");
320 }
321 }
322
323 #ifdef MULTIPROCESSOR
324 static void
meson8b_mpinit_delay(u_int n)325 meson8b_mpinit_delay(u_int n)
326 {
327 for (volatile int i = 0; i < n; i++)
328 ;
329 }
330 #endif
331
332 static int
cpu_enable_meson8b(int phandle)333 cpu_enable_meson8b(int phandle)
334 {
335 #ifdef MULTIPROCESSOR
336 const bus_addr_t cbar = armreg_cbar_read();
337 bus_space_tag_t bst = &arm_generic_bs_tag;
338
339 const bus_space_handle_t scu_bsh =
340 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE;
341 const bus_space_handle_t cpuconf_bsh =
342 MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET;
343 const bus_space_handle_t ao_bsh =
344 MESON8B_AOBUS_VBASE + MESON8B_AOBUS_RTI_OFFSET;
345 const bus_space_handle_t cbus_bsh =
346 MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET;
347 uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0;
348 uint64_t mpidr;
349
350 fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
351
352 const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);
353
354 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno),
355 KERN_VTOPHYS((vaddr_t)cpu_mpstart));
356
357 pwr_sts = bus_space_read_4(bst, scu_bsh, SCU_CPU_PWR_STS);
358 pwr_sts &= ~(3 << (8 * cpuno));
359 bus_space_write_4(bst, scu_bsh, SCU_CPU_PWR_STS, pwr_sts);
360
361 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG);
362 pwr_cntl0 &= ~((3 << 18) << ((cpuno - 1) * 2));
363 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
364
365 meson8b_mpinit_delay(5000);
366
367 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG);
368 cpuclk |= (1 << (24 + cpuno));
369 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk);
370
371 mempd0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG);
372 mempd0 &= ~((uint32_t)(0xf << 28) >> ((cpuno - 1) * 4));
373 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_MEM_PD0_REG, mempd0);
374
375 pwr_cntl1 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG);
376 pwr_cntl1 &= ~((3 << 4) << ((cpuno - 1) * 2));
377 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL1_REG, pwr_cntl1);
378
379 meson8b_mpinit_delay(10000);
380
381 for (;;) {
382 pwr_cntl1 = bus_space_read_4(bst, ao_bsh,
383 MESON_AOBUS_PWR_CTRL1_REG) & ((1 << 17) << (cpuno - 1));
384 if (pwr_cntl1)
385 break;
386 meson8b_mpinit_delay(10000);
387 }
388
389 pwr_cntl0 = bus_space_read_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG);
390 pwr_cntl0 &= ~(1 << cpuno);
391 bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
392
393 cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG);
394 cpuclk &= ~(1 << (24 + cpuno));
395 bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk);
396
397 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno),
398 KERN_VTOPHYS((vaddr_t)cpu_mpstart));
399
400 uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG);
401 ctrl |= __BITS(cpuno,0);
402 bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl);
403 #endif
404
405 return 0;
406 }
407
408 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b);
409
410 static int
meson8b_mpstart(void)411 meson8b_mpstart(void)
412 {
413 int ret = 0;
414 const bus_addr_t cbar = armreg_cbar_read();
415 bus_space_tag_t bst = &arm_generic_bs_tag;
416
417 if (cbar == 0)
418 return ret;
419
420 const bus_space_handle_t scu_bsh =
421 cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE;
422
423 const uint32_t scu_cfg = bus_space_read_4(bst, scu_bsh, SCU_CFG);
424 const u_int ncpus = (scu_cfg & SCU_CFG_CPUMAX) + 1;
425
426 if (ncpus < 2)
427 return ret;
428
429 /*
430 * Invalidate all SCU cache tags. That is, for all cores (0-3)
431 */
432 bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff);
433
434 uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL);
435 scu_ctl |= SCU_CTL_SCU_ENA;
436 bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl);
437
438 armv7_dcache_wbinv_all();
439
440 ret = arm_fdt_cpu_mpstart();
441 return ret;
442 }
443
444 static const struct fdt_platform meson8b_platform = {
445 .fp_devmap = meson_platform_devmap,
446 .fp_bootstrap = meson8b_platform_bootstrap,
447 .fp_init_attach_args = meson_platform_init_attach_args,
448 .fp_device_register = meson8b_platform_device_register,
449 .fp_reset = meson8b_platform_reset,
450 .fp_delay = a9ptmr_delay,
451 .fp_uart_freq = meson_platform_uart_freq,
452 .fp_mpstart = meson8b_mpstart,
453 };
454
455 FDT_PLATFORM(meson8b, "amlogic,meson8b", &meson8b_platform);
456 #endif /* SOC_MESON8B */
457
458 #if defined(SOC_MESONGX)
459 static void
mesongx_platform_reset(void)460 mesongx_platform_reset(void)
461 {
462 bus_space_tag_t bst = &meson_bs_tag;
463 bus_space_handle_t bsh;
464 uint32_t val;
465
466 bus_space_map(bst, MESONGX_WATCHDOG_BASE, MESONGX_WATCHDOG_SIZE, 0, &bsh);
467
468 val = MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN |
469 MESONGX_WATCHDOG_CNTL_WDOG_EN |
470 MESONGX_WATCHDOG_CNTL_CLK_EN;
471 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_CNTL, val);
472
473 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_TCNT, 1);
474
475 bus_space_write_4(bst, bsh, MESONGX_WATCHDOG_RESET, 0);
476
477 for (;;) {
478 __asm("wfi");
479 }
480 }
481
482 static const struct fdt_platform mesongx_platform = {
483 .fp_devmap = meson_platform_devmap,
484 .fp_bootstrap = meson_platform_bootstrap,
485 .fp_init_attach_args = meson_platform_init_attach_args,
486 .fp_device_register = meson_platform_device_register,
487 .fp_reset = mesongx_platform_reset,
488 .fp_delay = gtmr_delay,
489 .fp_uart_freq = meson_platform_uart_freq,
490 .fp_mpstart = arm_fdt_cpu_mpstart,
491 };
492
493 #if defined(SOC_MESONGXBB)
494 FDT_PLATFORM(mesongxbb, "amlogic,meson-gxbb", &mesongx_platform);
495 #endif /* SOC_MESONGXBB */
496 #if defined(SOC_MESONGXL)
497 FDT_PLATFORM(mesongxl, "amlogic,meson-gxl", &mesongx_platform);
498 #endif /* SOC_MESONGXL */
499 #endif /* SOC_MESONGX */
500