xref: /netbsd-src/sys/arch/arm/amlogic/meson_clk_div.c (revision 7e38c880e6b36d84c377184be7355e456c934ffd)
1 /* $NetBSD: meson_clk_div.c,v 1.3 2019/02/25 19:30:17 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2017-2019 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: meson_clk_div.c,v 1.3 2019/02/25 19:30:17 jmcneill Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 
35 #include <dev/clk/clk_backend.h>
36 
37 #include <arm/amlogic/meson_clk.h>
38 
39 u_int
meson_clk_div_get_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk)40 meson_clk_div_get_rate(struct meson_clk_softc *sc,
41     struct meson_clk_clk *clk)
42 {
43 	struct meson_clk_div *div = &clk->u.div;
44 	struct clk *clkp, *clkp_parent;
45 	u_int rate, ratio;
46 	uint32_t val;
47 
48 	KASSERT(clk->type == MESON_CLK_DIV);
49 
50 	clkp = &clk->base;
51 	clkp_parent = clk_get_parent(clkp);
52 	if (clkp_parent == NULL)
53 		return 0;
54 
55 	rate = clk_get_rate(clkp_parent);
56 	if (rate == 0)
57 		return 0;
58 
59 	CLK_LOCK(sc);
60 	val = CLK_READ(sc, div->reg);
61 	CLK_UNLOCK(sc);
62 
63 	if (div->div)
64 		ratio = __SHIFTOUT(val, div->div);
65 	else
66 		ratio = 0;
67 
68 	if (div->flags & MESON_CLK_DIV_POWER_OF_TWO) {
69 		return rate >> ratio;
70 	} else if (div->flags & MESON_CLK_DIV_CPU_SCALE_TABLE) {
71 		if (ratio < 1 || ratio > 8)
72 			return 0;
73 		return rate / ((ratio + 1) * 2);
74 	} else {
75 		return rate / (ratio + 1);
76 	}
77 }
78 
79 int
meson_clk_div_set_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk,u_int new_rate)80 meson_clk_div_set_rate(struct meson_clk_softc *sc,
81     struct meson_clk_clk *clk, u_int new_rate)
82 {
83 	struct meson_clk_div *div = &clk->u.div;
84 	struct clk *clkp, *clkp_parent;
85 	int parent_rate;
86 	uint32_t val, raw_div;
87 	int ratio, error;
88 
89 	KASSERT(clk->type == MESON_CLK_DIV);
90 
91 	clkp = &clk->base;
92 	clkp_parent = clk_get_parent(clkp);
93 	if (clkp_parent == NULL)
94 		return ENXIO;
95 
96 	if ((div->flags & MESON_CLK_DIV_SET_RATE_PARENT) != 0)
97 		return clk_set_rate(clkp_parent, new_rate);
98 
99 	if (div->div == 0)
100 		return ENXIO;
101 
102 	CLK_LOCK(sc);
103 
104 	val = CLK_READ(sc, div->reg);
105 
106 	parent_rate = clk_get_rate(clkp_parent);
107 	if (parent_rate == 0) {
108 		error = (new_rate == 0) ? 0 : ERANGE;
109 		goto done;
110 	}
111 
112 	ratio = howmany(parent_rate, new_rate);
113 	if ((div->flags & MESON_CLK_DIV_POWER_OF_TWO) != 0) {
114 		error = EINVAL;
115 		goto done;
116 	} else if ((div->flags & MESON_CLK_DIV_CPU_SCALE_TABLE) != 0) {
117 		error = EINVAL;
118 		goto done;
119 	} else {
120 		raw_div = (ratio > 0) ? ratio - 1 : 0;
121 	}
122 	if (raw_div > __SHIFTOUT_MASK(div->div)) {
123 		error = ERANGE;
124 		goto done;
125 	}
126 
127 	val &= ~div->div;
128 	val |= __SHIFTIN(raw_div, div->div);
129 	CLK_WRITE(sc, div->reg, val);
130 
131 	error = 0;
132 
133 done:
134 	CLK_UNLOCK(sc);
135 
136 	return error;
137 }
138 
139 const char *
meson_clk_div_get_parent(struct meson_clk_softc * sc,struct meson_clk_clk * clk)140 meson_clk_div_get_parent(struct meson_clk_softc *sc,
141     struct meson_clk_clk *clk)
142 {
143 	struct meson_clk_div *div = &clk->u.div;
144 
145 	KASSERT(clk->type == MESON_CLK_DIV);
146 
147 	return div->parent;
148 }
149