1 /* $NetBSD: cycv_platform.c,v 1.19 2023/04/07 08:55:29 skrll Exp $ */
2
3 /* This file is in the public domain. */
4
5 #include "arml2cc.h"
6 #include "opt_console.h"
7 #include "opt_multiprocessor.h"
8
9 #include <sys/cdefs.h>
10 __KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.19 2023/04/07 08:55:29 skrll Exp $");
11
12 #define _ARM32_BUS_DMA_PRIVATE
13 #include <sys/param.h>
14 #include <sys/bus.h>
15 #include <sys/cpu.h>
16 #include <sys/device.h>
17
18 #include <uvm/uvm_extern.h>
19
20 #include <arm/arm32/machdep.h>
21
22 #include <arm/altera/cycv_reg.h>
23 #include <arm/altera/cycv_var.h>
24 #include <arm/cortex/a9tmr_var.h>
25 #include <arm/cortex/pl310_var.h>
26 #include <arm/cortex/scu_reg.h>
27
28 #include <arm/bootconfig.h>
29 #include <arm/cpufunc.h>
30
31 #include <dev/fdt/fdtvar.h>
32
33 #include <arm/fdt/arm_fdtvar.h>
34 #include <dev/ic/comreg.h>
35
36 void cycv_platform_early_putchar(char);
37
38 void __noasan
cycv_platform_early_putchar(char c)39 cycv_platform_early_putchar(char c) {
40 #ifdef CONSADDR
41 #define CONSADDR_VA (CONSADDR - CYCV_PERIPHERAL_BASE + CYCV_PERIPHERAL_VBASE)
42 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
43 (volatile uint32_t *) CONSADDR_VA :
44 (volatile uint32_t *) CONSADDR;
45
46 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0)
47 ;
48
49 uartaddr[com_data] = htole32(c);
50 #endif
51 }
52
53 static const struct pmap_devmap *
cycv_platform_devmap(void)54 cycv_platform_devmap(void) {
55 static const struct pmap_devmap devmap[] = {
56 DEVMAP_ENTRY(CYCV_PERIPHERAL_VBASE,
57 CYCV_PERIPHERAL_BASE,
58 CYCV_PERIPHERAL_SIZE),
59 DEVMAP_ENTRY_END
60 };
61
62 return devmap;
63 }
64
65 static void
cycv_platform_bootstrap(void)66 cycv_platform_bootstrap(void)
67 {
68 bus_space_tag_t bst = &armv7_generic_bs_tag;
69 bus_space_handle_t bsh_l2c;
70
71 bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c);
72
73 #if NARML2CC > 0
74 arml2cc_init(bst, bsh_l2c, 0);
75 #endif
76
77 arm_fdt_cpu_bootstrap();
78 }
79
80 static int
cycv_mpstart(void)81 cycv_mpstart(void)
82 {
83 int ret = 0;
84
85 #ifdef MULTIPROCESSOR
86 bus_space_tag_t bst = &armv7_generic_bs_tag;
87 bus_space_handle_t bsh_rst;
88 bus_space_handle_t bsh_scu;
89
90 bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst);
91 bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu);
92
93 /* Enable Snoop Control Unit */
94 bus_space_write_4(bst, bsh_scu, SCU_INV_ALL_REG, 0xff);
95 bus_space_write_4(bst, bsh_scu, SCU_CTL,
96 bus_space_read_4(bst, bsh_scu, SCU_CTL) | SCU_CTL_SCU_ENA);
97
98 const uint32_t startfunc =
99 (uint32_t) KERN_VTOPHYS((vaddr_t) cpu_mpstart);
100
101 /*
102 * We place a "LDR PC, =cpu_mpstart" at address 0 in order to bootstrap
103 * CPU 1. We can't use the similar feature of the Boot ROM because
104 * it was unmapped by u-boot in favor of the SDRAM.
105 */
106 pmap_map_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, CYCV_SDRAM_BASE,
107 L1_S_SIZE, VM_PROT_READ|VM_PROT_WRITE, PMAP_NOCACHE);
108
109 /* 0: LDR PC, [PC, #0x18] -> loads address at 0x20 into PC */
110 *(volatile uint32_t *) CYCV_SDRAM_VBASE = htole32(0xe59ff018);
111 *(volatile uint32_t *) (CYCV_SDRAM_VBASE + 0x20) = startfunc;
112
113 pmap_unmap_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, L1_S_SIZE);
114
115 bus_space_write_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST,
116 bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) &
117 ~CYCV_RSTMGR_MPUMODRST_CPU1);
118
119 /* Wait for secondary processor to start */
120 int i;
121 for (i = 0x10000000; i > 0; i--) {
122 if (cpu_hatched_p(1))
123 break;
124 }
125 if (i == 0) {
126 aprint_error("cpu%d: WARNING: AP failed to start\n", 1);
127 ret++;
128 }
129 #endif
130
131 return ret;
132 }
133
134 static void
cycv_platform_init_attach_args(struct fdt_attach_args * faa)135 cycv_platform_init_attach_args(struct fdt_attach_args *faa) {
136 faa->faa_bst = &armv7_generic_bs_tag;
137 faa->faa_dmat = &arm_generic_dma_tag;
138 }
139
140 static void
cycv_platform_device_register(device_t dev,void * aux)141 cycv_platform_device_register(device_t dev, void *aux)
142 {
143 prop_dictionary_t dict = device_properties(dev);
144
145 if (device_is_a(dev, "arma9tmr")) {
146 prop_dictionary_set_uint32(dict, "frequency",
147 cycv_clkmgr_early_get_mpu_clk() / 4);
148 }
149 }
150
151 static void
cycv_platform_reset(void)152 cycv_platform_reset(void) {
153 bus_space_tag_t bst = &armv7_generic_bs_tag;
154 bus_space_handle_t bsh;
155 uint32_t val;
156
157 bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh);
158 val = bus_space_read_4(bst, bsh, CYCV_RSTMGR_CTRL);
159 bus_space_write_4(bst, bsh, CYCV_RSTMGR_CTRL,
160 val | CYCV_RSTMGR_CTRL_SWCOLDRSTREQ);
161 }
162
163 static u_int
cycv_platform_uart_freq(void)164 cycv_platform_uart_freq(void) {
165 return cycv_clkmgr_early_get_l4_sp_clk();
166 }
167
168 static const struct fdt_platform cycv_platform = {
169 .fp_devmap = cycv_platform_devmap,
170 .fp_bootstrap = cycv_platform_bootstrap,
171 .fp_init_attach_args = cycv_platform_init_attach_args,
172 .fp_device_register = cycv_platform_device_register,
173 .fp_reset = cycv_platform_reset,
174 .fp_delay = a9tmr_delay,
175 .fp_uart_freq = cycv_platform_uart_freq,
176 .fp_mpstart = cycv_mpstart,
177 };
178
179 FDT_PLATFORM(cycv, "altr,socfpga-cyclone5", &cycv_platform);
180