1 /* $NetBSD: pci_6600.c,v 1.33 2021/07/04 22:42:36 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1999 by Ross Harvey. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Ross Harvey.
17 * 4. The name of Ross Harvey may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 */
33
34 #include <sys/cdefs.h>
35
36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.33 2021/07/04 22:42:36 thorpej Exp $");
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/device.h>
42 #include <sys/cpu.h>
43
44 #include <machine/autoconf.h>
45 #define _ALPHA_BUS_DMA_PRIVATE
46 #include <sys/bus.h>
47 #include <machine/rpb.h>
48 #include <machine/alpha.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pciidereg.h>
53 #include <dev/pci/pciidevar.h>
54
55 #include <alpha/pci/tsreg.h>
56 #include <alpha/pci/tsvar.h>
57
58 #define pci_6600() { Generate ctags(1) key. }
59
60 #include "sio.h"
61 #if NSIO
62 #include <alpha/pci/siovar.h>
63 #endif
64
65 #define PCI_NIRQ 64
66 #define PCI_SIO_IRQ 55
67 #define PCI_STRAY_MAX 5
68
69 /*
70 * Some Tsunami models have a PCI device (the USB controller) with interrupts
71 * tied to ISA IRQ lines. The IRQ is encoded as:
72 *
73 * line = 0xe0 | isa_irq;
74 */
75 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef)
76 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f)
77
78 static struct tsp_config *sioprimary;
79
80 static void dec_6600_intr_disestablish(pci_chipset_tag_t, void *);
81 static void *dec_6600_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
82 int, int (*func)(void *), void *);
83 static const char *dec_6600_intr_string(pci_chipset_tag_t, pci_intr_handle_t,
84 char *, size_t);
85 static const struct evcnt *dec_6600_intr_evcnt(pci_chipset_tag_t,
86 pci_intr_handle_t);
87 static int dec_6600_intr_map(const struct pci_attach_args *,
88 pci_intr_handle_t *);
89
90 static void *dec_6600_pciide_compat_intr_establish(device_t,
91 const struct pci_attach_args *, int,
92 int (*)(void *), void *);
93
94 static void dec_6600_intr_enable(pci_chipset_tag_t, int irq);
95 static void dec_6600_intr_disable(pci_chipset_tag_t, int irq);
96 static void dec_6600_intr_set_affinity(pci_chipset_tag_t, int,
97 struct cpu_info *);
98 static void dec_6600_intr_program(pci_chipset_tag_t);
99
100 static void dec_6600_intr_redistribute(void);
101
102 /*
103 * We keep 2 software copies of the interrupt enables: one global one,
104 * and one per-CPU for setting the interrupt affinity.
105 */
106 static uint64_t dec_6600_intr_enables __read_mostly;
107 static uint64_t dec_6600_cpu_intr_enables[4] __read_mostly;
108
109 static void
pci_6600_pickintr(void * core,bus_space_tag_t iot,bus_space_tag_t memt,pci_chipset_tag_t pc)110 pci_6600_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt,
111 pci_chipset_tag_t pc)
112 {
113 struct cpu_info *ci;
114 CPU_INFO_ITERATOR cii;
115
116 pc->pc_intr_v = core;
117 pc->pc_intr_map = dec_6600_intr_map;
118 pc->pc_intr_string = dec_6600_intr_string;
119 pc->pc_intr_evcnt = dec_6600_intr_evcnt;
120 pc->pc_intr_establish = dec_6600_intr_establish;
121 pc->pc_intr_disestablish = dec_6600_intr_disestablish;
122
123 pc->pc_pciide_compat_intr_establish = NULL;
124
125 pc->pc_intr_desc = "dec 6600";
126 pc->pc_vecbase = 0x900;
127 pc->pc_nirq = PCI_NIRQ;
128
129 pc->pc_intr_enable = dec_6600_intr_enable;
130 pc->pc_intr_disable = dec_6600_intr_disable;
131 pc->pc_intr_set_affinity = dec_6600_intr_set_affinity;
132
133 alpha_intr_redistribute = dec_6600_intr_redistribute;
134
135 /* Note eligible CPUs for interrupt routing purposes. */
136 for (CPU_INFO_FOREACH(cii, ci)) {
137 KASSERT(ci->ci_cpuid < 4);
138 pc->pc_eligible_cpus |= __BIT(ci->ci_cpuid);
139 }
140
141 /*
142 * System-wide and Pchip-0-only logic...
143 */
144 if (sioprimary == NULL) {
145 sioprimary = core;
146 /*
147 * Unless explicitly routed, all interrupts go to the
148 * primary CPU.
149 */
150 dec_6600_cpu_intr_enables[cpu_info_primary.ci_cpuid] =
151 __BITS(0,63);
152 pc->pc_pciide_compat_intr_establish =
153 dec_6600_pciide_compat_intr_establish;
154
155 KASSERT(dec_6600_intr_enables == 0);
156 dec_6600_intr_program(pc);
157
158 alpha_pci_intr_alloc(pc, PCI_STRAY_MAX);
159 #if NSIO
160 sio_intr_setup(pc, iot);
161
162 mutex_enter(&cpu_lock);
163 dec_6600_intr_enable(pc, PCI_SIO_IRQ);
164 mutex_exit(&cpu_lock);
165 #endif
166 } else {
167 pc->pc_shared_intrs = sioprimary->pc_pc.pc_shared_intrs;
168 }
169 }
ALPHA_PCI_INTR_INIT(ST_DEC_6600,pci_6600_pickintr)170 ALPHA_PCI_INTR_INIT(ST_DEC_6600, pci_6600_pickintr)
171 ALPHA_PCI_INTR_INIT(ST_DEC_TITAN, pci_6600_pickintr)
172
173 static int
174 dec_6600_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
175 {
176 pcitag_t bustag = pa->pa_intrtag;
177 int buspin = pa->pa_intrpin, line = pa->pa_intrline;
178 pci_chipset_tag_t pc = pa->pa_pc;
179 int bus, device, function;
180
181 if (buspin == 0) {
182 /* No IRQ used. */
183 return 1;
184 }
185 if (buspin < 0 || buspin > 4) {
186 printf("intr_map: bad interrupt pin %d\n", buspin);
187 return 1;
188 }
189
190 pci_decompose_tag(pc, bustag, &bus, &device, &function);
191
192 /*
193 * The console places the interrupt mapping in the "line" value.
194 * A value of (char)-1 indicates there is no mapping.
195 */
196 if (line == 0xff) {
197 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n",
198 bus, device, function);
199 return (1);
200 }
201
202 #if NSIO == 0
203 if (DEC_6600_LINE_IS_ISA(line)) {
204 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n",
205 DEC_6600_LINE_ISA_IRQ(line), bus, device, function);
206 return (1);
207 }
208 #endif
209
210 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ)
211 panic("dec_6600_intr_map: dec 6600 irq too large (%d)",
212 line);
213
214 alpha_pci_intr_handle_init(ihp, line, 0);
215 return (0);
216 }
217
218 static const char *
dec_6600_intr_string(pci_chipset_tag_t const pc,pci_intr_handle_t const ih,char * const buf,size_t const len)219 dec_6600_intr_string(pci_chipset_tag_t const pc, pci_intr_handle_t const ih,
220 char * const buf, size_t const len)
221 {
222 #if NSIO
223 const u_int irq = alpha_pci_intr_handle_get_irq(&ih);
224
225 if (DEC_6600_LINE_IS_ISA(irq))
226 return (sio_intr_string(NULL /*XXX*/,
227 DEC_6600_LINE_ISA_IRQ(irq), buf, len));
228 #endif
229
230 return alpha_pci_generic_intr_string(pc, ih, buf, len);
231 }
232
233 static const struct evcnt *
dec_6600_intr_evcnt(pci_chipset_tag_t const pc,pci_intr_handle_t const ih)234 dec_6600_intr_evcnt(pci_chipset_tag_t const pc, pci_intr_handle_t const ih)
235 {
236 #if NSIO
237 const u_int irq = alpha_pci_intr_handle_get_irq(&ih);
238
239 if (DEC_6600_LINE_IS_ISA(irq))
240 return (sio_intr_evcnt(NULL /*XXX*/,
241 DEC_6600_LINE_ISA_IRQ(irq)));
242 #endif
243
244 return alpha_pci_generic_intr_evcnt(pc, ih);
245 }
246
247 static void *
dec_6600_intr_establish(pci_chipset_tag_t const pc,pci_intr_handle_t const ih,int const level,int (* func)(void *),void * arg)248 dec_6600_intr_establish(pci_chipset_tag_t const pc, pci_intr_handle_t const ih,
249 int const level, int (*func)(void *), void *arg)
250 {
251 #if NSIO
252 const u_int irq = alpha_pci_intr_handle_get_irq(&ih);
253 const u_int flags = alpha_pci_intr_handle_get_flags(&ih);
254
255 if (DEC_6600_LINE_IS_ISA(irq))
256 return (sio_intr_establish(NULL /*XXX*/,
257 DEC_6600_LINE_ISA_IRQ(irq), IST_LEVEL, level, flags,
258 func, arg));
259 #endif
260
261 return alpha_pci_generic_intr_establish(pc, ih, level, func, arg);
262 }
263
264 static void
dec_6600_intr_disestablish(pci_chipset_tag_t const pc,void * const cookie)265 dec_6600_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie)
266 {
267 #if NSIO
268 struct alpha_shared_intrhand * const ih = cookie;
269
270 /*
271 * We have to determine if this is an ISA IRQ or not! We do this
272 * by checking to see if the intrhand points back to an intrhead
273 * that points to the sioprimary TSP. If not, it's an ISA IRQ.
274 * Pretty disgusting, eh?
275 */
276 if (ih->ih_intrhead->intr_private != sioprimary) {
277 sio_intr_disestablish(NULL /*XXX*/, cookie);
278 return;
279 }
280 #endif
281
282 return alpha_pci_generic_intr_disestablish(pc, cookie);
283 }
284
285 static void
dec_6600_intr_program(pci_chipset_tag_t const pc)286 dec_6600_intr_program(pci_chipset_tag_t const pc)
287 {
288 unsigned int irq, cpuno, cnt;
289
290 /*
291 * Validate the configuration before we program it: each enabled
292 * IRQ must be routed to exactly one CPU.
293 */
294 for (irq = 0; irq < PCI_NIRQ; irq++) {
295 if ((dec_6600_intr_enables & __BIT(irq)) == 0)
296 continue;
297 for (cpuno = 0, cnt = 0; cpuno < 4; cpuno++) {
298 if (dec_6600_cpu_intr_enables[cpuno] != 0 &&
299 (pc->pc_eligible_cpus & __BIT(cpuno)) == 0)
300 panic("%s: interrupts enabled on non-existent CPU %u",
301 __func__, cpuno);
302 if (dec_6600_cpu_intr_enables[cpuno] & __BIT(irq))
303 cnt++;
304 }
305 if (cnt != 1) {
306 panic("%s: irq %u enabled on %u CPUs", __func__,
307 irq, cnt);
308 }
309 }
310
311 const uint64_t enab0 =
312 dec_6600_intr_enables & dec_6600_cpu_intr_enables[0];
313 const uint64_t enab1 =
314 dec_6600_intr_enables & dec_6600_cpu_intr_enables[1];
315 const uint64_t enab2 =
316 dec_6600_intr_enables & dec_6600_cpu_intr_enables[2];
317 const uint64_t enab3 =
318 dec_6600_intr_enables & dec_6600_cpu_intr_enables[3];
319
320 /* Don't touch DIMx registers for non-existent CPUs. */
321 uint64_t black_hole;
322 volatile uint64_t * const dim0 = (pc->pc_eligible_cpus & __BIT(0)) ?
323 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM0) : &black_hole;
324 volatile uint64_t * const dim1 = (pc->pc_eligible_cpus & __BIT(1)) ?
325 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM1) : &black_hole;
326 volatile uint64_t * const dim2 = (pc->pc_eligible_cpus & __BIT(2)) ?
327 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM2) : &black_hole;
328 volatile uint64_t * const dim3 = (pc->pc_eligible_cpus & __BIT(3)) ?
329 (void *)ALPHA_PHYS_TO_K0SEG(TS_C_DIM3) : &black_hole;
330
331 const unsigned long psl = alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH);
332
333 alpha_mb();
334 *dim0 = enab0;
335 *dim1 = enab1;
336 *dim2 = enab2;
337 *dim3 = enab3;
338 alpha_mb();
339 (void) *dim0;
340 (void) *dim1;
341 (void) *dim2;
342 (void) *dim3;
343 alpha_mb();
344
345 alpha_pal_swpipl(psl);
346 }
347
348 static void
dec_6600_intr_enable(pci_chipset_tag_t const pc,int const irq)349 dec_6600_intr_enable(pci_chipset_tag_t const pc, int const irq)
350 {
351
352 KASSERT(mutex_owned(&cpu_lock));
353
354 dec_6600_intr_enables |= __BIT(irq);
355 dec_6600_intr_program(pc);
356 }
357
358 static void
dec_6600_intr_disable(pci_chipset_tag_t const pc,int const irq)359 dec_6600_intr_disable(pci_chipset_tag_t const pc, int const irq)
360 {
361
362 KASSERT(mutex_owned(&cpu_lock));
363
364 dec_6600_intr_enables &= ~__BIT(irq);
365 dec_6600_intr_program(pc);
366 }
367
368 static void
dec_6600_intr_set_affinity(pci_chipset_tag_t const pc,int const irq,struct cpu_info * const ci)369 dec_6600_intr_set_affinity(pci_chipset_tag_t const pc, int const irq,
370 struct cpu_info * const ci)
371 {
372 const uint64_t intr_bit = __BIT(irq);
373 cpuid_t cpuno;
374
375 KASSERT(mutex_owned(&cpu_lock));
376 KASSERT(ci->ci_cpuid < 4);
377 KASSERT(pc->pc_eligible_cpus & __BIT(ci->ci_cpuid));
378
379 for (cpuno = 0; cpuno < 4; cpuno++) {
380 if (cpuno == ci->ci_cpuid)
381 dec_6600_cpu_intr_enables[cpuno] |= intr_bit;
382 else
383 dec_6600_cpu_intr_enables[cpuno] &= ~intr_bit;
384 }
385
386 /* Only program the hardware if the irq is enabled. */
387 if (dec_6600_intr_enables & intr_bit)
388 dec_6600_intr_program(pc);
389 }
390
391 static void
dec_6600_intr_redistribute(void)392 dec_6600_intr_redistribute(void)
393 {
394 KASSERT(sioprimary != NULL);
395
396 pci_chipset_tag_t const pc = &sioprimary->pc_pc;
397
398 /* ISA interrupts always stay on primary. Shuffle PCI interrupts. */
399 alpha_pci_generic_intr_redistribute(pc);
400 }
401
402 static void *
dec_6600_pciide_compat_intr_establish(device_t dev,const struct pci_attach_args * pa,int chan,int (* func)(void *),void * arg)403 dec_6600_pciide_compat_intr_establish(device_t dev,
404 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
405 {
406 pci_chipset_tag_t const pc = pa->pa_pc;
407
408 /*
409 * If this isn't the TSP that holds the PCI-ISA bridge,
410 * all bets are off.
411 */
412 if (pc->pc_intr_v != sioprimary)
413 return (NULL);
414
415 return sio_pciide_compat_intr_establish(dev, pa, chan, func, arg);
416 }
417