1 /* $NetBSD: cia.c,v 1.81 2023/12/04 00:32:10 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
35 * All rights reserved.
36 *
37 * Author: Chris G. Demetriou
38 *
39 * Permission to use, copy, modify and distribute this software and
40 * its documentation is hereby granted, provided that both the copyright
41 * notice and this permission notice appear in all copies of the
42 * software, derivative works or modified versions, and any portions
43 * thereof, and that both notices appear in supporting documentation.
44 *
45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
48 *
49 * Carnegie Mellon requests users of this software to return to
50 *
51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
52 * School of Computer Science
53 * Carnegie Mellon University
54 * Pittsburgh PA 15213-3890
55 *
56 * any improvements or extensions that they make and grant Carnegie the
57 * rights to redistribute these changes.
58 */
59
60 #include "opt_dec_550.h"
61
62 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
63
64 __KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.81 2023/12/04 00:32:10 thorpej Exp $");
65
66 #include <sys/param.h>
67 #include <sys/systm.h>
68 #include <sys/kernel.h>
69 #include <sys/device.h>
70
71 #include <machine/autoconf.h>
72 #include <machine/rpb.h>
73 #include <machine/sysarch.h>
74 #include <machine/alpha.h>
75
76 #include <dev/isa/isareg.h>
77 #include <dev/isa/isavar.h>
78
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <alpha/pci/ciareg.h>
82 #include <alpha/pci/ciavar.h>
83
84 static int ciamatch(device_t, cfdata_t, void *);
85 static void ciaattach(device_t, device_t, void *);
86
87 CFATTACH_DECL_NEW(cia, sizeof(struct cia_softc),
88 ciamatch, ciaattach, NULL, NULL);
89
90 extern struct cfdriver cia_cd;
91
92 static int cia_bus_get_window(int, int,
93 struct alpha_bus_space_translation *);
94
95 /* There can be only one. */
96 static int ciafound;
97 struct cia_config cia_configuration;
98
99 /*
100 * This determines if we attempt to use BWX for PCI bus and config space
101 * access. Some systems, notably with Pyxis, don't fare so well unless
102 * BWX is used.
103 *
104 * EXCEPT! Some devices have a really hard time if BWX is used (WHY?!).
105 * So, we decouple the uses for PCI config space and PCI bus space.
106 *
107 * FURTHERMORE! The Pyxis, most notably earlier revs, really don't
108 * do so well if you don't use BWX for bus access. So we default to
109 * forcing BWX on those chips.
110 *
111 * Geez.
112 */
113
114 #ifndef CIA_PCI_USE_BWX
115 #define CIA_PCI_USE_BWX 1
116 #endif
117
118 #ifndef CIA_BUS_USE_BWX
119 #define CIA_BUS_USE_BWX 0
120 #endif
121
122 #ifndef CIA_PYXIS_FORCE_BWX
123 #define CIA_PYXIS_FORCE_BWX 0
124 #endif
125
126 int cia_pci_use_bwx = CIA_PCI_USE_BWX;
127 int cia_bus_use_bwx = CIA_BUS_USE_BWX;
128 int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX;
129
130 static int
ciamatch(device_t parent,cfdata_t match,void * aux)131 ciamatch(device_t parent, cfdata_t match, void *aux)
132 {
133 struct mainbus_attach_args *ma = aux;
134
135 /* Make sure that we're looking for a CIA. */
136 if (strcmp(ma->ma_name, cia_cd.cd_name) != 0)
137 return (0);
138
139 if (ciafound)
140 return (0);
141
142 return (1);
143 }
144
145 /*
146 * Set up the chipset's function pointers.
147 */
148 void
cia_init(struct cia_config * ccp)149 cia_init(struct cia_config *ccp)
150 {
151 int pci_use_bwx = cia_pci_use_bwx;
152 int bus_use_bwx = cia_bus_use_bwx;
153
154 ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
155 ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
156 ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
157
158 /*
159 * Determine if we have a Pyxis. Only two systypes can
160 * have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
161 * and the DEC_550 systype (Miata).
162 */
163 if ((cputype == ST_EB164 &&
164 (hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
165 cputype == ST_DEC_550) {
166 ccp->cc_flags |= CCF_ISPYXIS;
167 if (cia_pyxis_force_bwx)
168 pci_use_bwx = bus_use_bwx = 1;
169 }
170
171 /*
172 * ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
173 */
174 if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0)
175 ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
176 else
177 ccp->cc_cnfg = 0;
178
179 /*
180 * Use BWX iff:
181 *
182 * - It hasn't been disabled by the user,
183 * - it's enabled in CNFG,
184 * - we're implementation version ev5,
185 * - BWX is enabled in the CPU's capabilities mask
186 */
187 if ((pci_use_bwx || bus_use_bwx) &&
188 (ccp->cc_cnfg & CNFG_BWEN) != 0 &&
189 (cpu_amask & ALPHA_AMASK_BWX) != 0) {
190 uint32_t ctrl;
191
192 if (pci_use_bwx)
193 ccp->cc_flags |= CCF_PCI_USE_BWX;
194 if (bus_use_bwx)
195 ccp->cc_flags |= CCF_BUS_USE_BWX;
196
197 /*
198 * For whatever reason, the firmware seems to enable PCI
199 * loopback mode if it also enables BWX. Make sure it's
200 * enabled if we have an old, buggy firmware rev.
201 */
202 alpha_mb();
203 ctrl = REGVAL(CIA_CSR_CTRL);
204 if ((ctrl & CTRL_PCI_LOOP_EN) == 0) {
205 REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
206 alpha_mb();
207 }
208 }
209
210 if (!ccp->cc_initted) {
211 /* don't do these twice since they set up extents */
212 if (ccp->cc_flags & CCF_BUS_USE_BWX) {
213 cia_bwx_bus_io_init(&ccp->cc_iot, ccp);
214 cia_bwx_bus_mem_init(&ccp->cc_memt, ccp);
215
216 /*
217 * We have one window for both PCI I/O and MEM
218 * in BWX mode.
219 */
220 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
221 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
222 } else {
223 cia_swiz_bus_io_init(&ccp->cc_iot, ccp);
224 cia_swiz_bus_mem_init(&ccp->cc_memt, ccp);
225
226 /*
227 * We have two I/O windows and 4 MEM windows in
228 * SWIZ mode.
229 */
230 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2;
231 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4;
232 }
233 alpha_bus_get_window = cia_bus_get_window;
234 }
235
236 cia_pci_init(&ccp->cc_pc, ccp);
237 alpha_pci_chipset = &ccp->cc_pc;
238
239 ccp->cc_initted = 1;
240 }
241
242 static void
ciaattach(device_t parent,device_t self,void * aux)243 ciaattach(device_t parent, device_t self, void *aux)
244 {
245 struct cia_softc *sc = device_private(self);
246 struct cia_config *ccp;
247 struct pcibus_attach_args pba;
248 char bits[64];
249 const char *name;
250
251 /* note that we've attached the chipset; can't have 2 CIAs. */
252 ciafound = 1;
253 sc->sc_dev = self;
254
255 /*
256 * set up the chipset's info; done once at console init time
257 * (maybe), but we must do it here as well to take care of things
258 * that need to use memory allocation.
259 */
260 ccp = sc->sc_ccp = &cia_configuration;
261 cia_init(ccp);
262
263 if (ccp->cc_flags & CCF_ISPYXIS) {
264 name = "Pyxis";
265 } else {
266 name = "ALCOR/ALCOR2";
267 }
268
269 aprint_normal(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
270 name, ccp->cc_rev + 1);
271 if (ccp->cc_cnfg) {
272 snprintb(bits, sizeof(bits), CIA_CSR_CNFG_BITS, ccp->cc_cnfg);
273 aprint_normal_dev(self, "extended capabilities: %s\n", bits);
274 }
275
276 switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) {
277 case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX:
278 name = "PCI config and bus";
279 break;
280 case CCF_PCI_USE_BWX:
281 name = "PCI config";
282 break;
283 case CCF_BUS_USE_BWX:
284 name = "bus";
285 break;
286 default:
287 name = NULL;
288 break;
289 }
290 if (name != NULL)
291 aprint_normal_dev(self, "using BWX for %s access\n", name);
292
293 #ifdef DEC_550
294 if (cputype == ST_DEC_550 &&
295 (hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
296 /*
297 * Miata 1 systems have a bug: DMA cannot cross
298 * an 8k boundary! Make sure PCI read prefetching
299 * is disabled on these chips. Note that secondary
300 * PCI busses don't have this problem, because of
301 * the way PPBs handle PCI read requests.
302 *
303 * In the 21174 Technical Reference Manual, this is
304 * actually documented as "Pyxis Pass 1", but apparently
305 * there are chips that report themselves as "Pass 1"
306 * which do not have the bug! Miatas with the Cypress
307 * PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
308 * have the bug, so we use this check.
309 *
310 * NOTE: This bug is actually worked around in cia_dma.c,
311 * when direct-mapped DMA maps are created.
312 *
313 * XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR
314 * XXX SGMAP DMA MAPPINGS!
315 */
316 uint32_t ctrl;
317
318 /* XXX no bets... */
319 aprint_error_dev(self,
320 "WARNING: Pyxis pass 1 DMA bug; no bets...\n");
321
322 ccp->cc_flags |= CCF_PYXISBUG;
323
324 alpha_mb();
325 ctrl = REGVAL(CIA_CSR_CTRL);
326 ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
327 REGVAL(CIA_CSR_CTRL) = ctrl;
328 alpha_mb();
329 }
330 #endif /* DEC_550 */
331
332 cia_dma_init(ccp);
333
334 alpha_pci_intr_init(ccp, &ccp->cc_iot, &ccp->cc_memt, &ccp->cc_pc);
335
336 pba.pba_iot = &ccp->cc_iot;
337 pba.pba_memt = &ccp->cc_memt;
338 pba.pba_dmat =
339 alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
340 pba.pba_dmat64 = NULL;
341 pba.pba_pc = &ccp->cc_pc;
342 pba.pba_bus = 0;
343 pba.pba_bridgetag = NULL;
344 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
345 if ((ccp->cc_flags & CCF_PYXISBUG) == 0)
346 pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
347 PCI_FLAGS_MWI_OKAY;
348 config_found(self, &pba, pcibusprint, CFARGS_NONE);
349 }
350
351 static int
cia_bus_get_window(int type,int window,struct alpha_bus_space_translation * abst)352 cia_bus_get_window(int type, int window,
353 struct alpha_bus_space_translation *abst)
354 {
355 struct cia_config *ccp = &cia_configuration;
356 bus_space_tag_t st;
357
358 switch (type) {
359 case ALPHA_BUS_TYPE_PCI_IO:
360 st = &ccp->cc_iot;
361 break;
362
363 case ALPHA_BUS_TYPE_PCI_MEM:
364 st = &ccp->cc_memt;
365 break;
366
367 default:
368 panic("cia_bus_get_window");
369 }
370
371 return (alpha_bus_space_get_window(st, window, abst));
372 }
373
374 void
cia_pyxis_intr_enable(int irq,int onoff)375 cia_pyxis_intr_enable(int irq, int onoff)
376 {
377 uint64_t imask;
378 int s;
379
380 #if 0
381 printf("cia_pyxis_intr_enable: %s %d\n",
382 onoff ? "enabling" : "disabling", irq);
383 #endif
384
385 s = splhigh();
386 alpha_mb();
387 imask = REGVAL64(PYXIS_INT_MASK);
388 if (onoff)
389 imask |= (1UL << irq);
390 else
391 imask &= ~(1UL << irq);
392 REGVAL64(PYXIS_INT_MASK) = imask;
393 alpha_mb();
394 splx(s);
395 }
396