1.\" $NetBSD: apic.4,v 1.3 2017/02/18 22:39:02 wiz Exp $ 2.\" 3.\" Copyright (c) 2011 Jukka Ruohonen <jruohonen@iki.fi> 4.\" All rights reserved. 5.\" 6.\" Redistribution and use in source and binary forms, with or without 7.\" modification, are permitted provided that the following conditions 8.\" are met: 9.\" 1. Redistributions of source code must retain the above copyright 10.\" notice, this list of conditions and the following disclaimer. 11.\" 2. Neither the name of the author nor the names of any 12.\" contributors may be used to endorse or promote products derived 13.\" from this software without specific prior written permission. 14.\" 15.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 16.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 19.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25.\" POSSIBILITY OF SUCH DAMAGE. 26.\" 27.Dd February 17, 2017 28.Dt APIC 4 x86 29.Os 30.Sh NAME 31.Nm apic , 32.Nm ioapic , 33.Nm lapic 34.Nd Intel APIC Architecture 35.Sh SYNOPSIS 36.Cd "ioapic* at mainbus*" 37.Sh DESCRIPTION 38The 39.Nm 40subsystem provides basis for a system of advanced programmable 41interrupt controllers 42.Pq Tn APICs 43originally designed by Intel but now widely used on all x86 systems. 44.Pp 45There are two elements in the architecture, the local 46.Tn APIC 47.Pq Tn LAPIC 48and the 49.Tn I/O APIC . 50Historically these were connected by a dedicated 3-wire 51.Dq APIC bus , 52but the system bus is used for communication today. 53The configuration is increasingly dependent on 54.Tn ACPI . 55.Pp 56Typically each 57.Tn CPU 58in the system contains one 59.Tn LAPIC 60that performs two primary functions: 61.Bl -enum -offset indent 62.It 63It receives interrupts both from internal sources and from the external 64.Tn I/O APIC . 65The interrupt sources include 66.Tn I/O 67devices, the programmable 68.Tn APIC 69timer, performance monitoring counters, 70thermal sensor interrupts, and others. 71.It 72In multiprocessor 73.Pq Tn MP 74systems a 75.Tn LAPIC 76receives and sends interprocessor interrupts 77.Pq Tn IPIs 78from and to other processors in the system. 79.Tn IPIs 80are used to provide software interrupts, 81interrupt forwarding, or preemptive scheduling. 82Against this, the architecture can be generally seen as an attempt 83to solve the interrupt routing efficiency issues in 84.Tn MP 85systems. 86.El 87.Pp 88There is typically one 89.Tn I/O APIC 90for each peripheral bus in the system. 91Each 92.Tn I/O APIC 93has a series of interrupt inputs to external interrupt sources. 94The architecture usually contains a redirection table which can be used 95to route the interrupts that an 96.Tn I/O APIC 97receives to one or more local 98.Tn APICs . 99When a 100.Tn LAPIC 101is able to accept an interrupt, it will signal the 102.Tn CPU . 103Without an 104.Tn I/O APIC , 105the local 106.Tn APICs 107are therefore mostly useless; one of the primary functions 108of the architecture is no longer achievable, interrupts can 109not be distributed to different 110.Tn CPUs . 111.Pp 112The 8259 113.Tn PIC 114has coexisted with the architecture since its introduction. 115It is still possible to disable the 116.Tn APIC 117system and revert back to a 8259-compatible 118.Tn PIC . 119But the widespread use of 120.Tn MP 121systems has made this mainly a fallback option. 122.Sh SEE ALSO 123.Xr acpi 4 , 124.Xr mainbus 4 , 125.Xr x86/ichlpcib 4 126.Rs 127.%A Intel Corporation 128.%T Intel 64 and IA-32 Architectures Software Developer's Manual 129.%V Volume 3A: System Programming Guide, Part 1 130.%P Chapter 10 131.%D January, 2011 132.%U http://www.intel.com/Assets/PDF/manual/253668.pdf 133.Re 134.Rs 135.%A Intel Corporation 136.%T Intel 82093AA I/O Advanced Programmable 137.%T Interrupt Controller (I/O APIC) Datasheet 138.%D May, 1996 139.%U http://www.intel.com/design/chipsets/datashts/29056601.pdf 140.Re 141.Rs 142.%A Intel Corporation 143.%T 8259A, Programmable Interrupt Controller 144.%D December, 1988 145.%U http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf 146.Re 147.Rs 148.%A John Baldwin 149.%T PCI Interrupts for x86 Machines under FreeBSD 150.%D May 18-19, 2007 151.%O Proceedings of BSDCan 2007 152.%U http://people.freebsd.org/~jhb/papers/bsdcan/2007/article.pdf 153.Re 154.Rs 155.%A Microsoft Corporation 156.%T PCI IRQ Routing on a Multiprocessor ACPI System 157.%D December 4, 2001 158.%U http://www.microsoft.com/whdc/archive/acpi-mp.mspx 159.Re 160.Sh AUTHORS 161.An -nosplit 162Authors of the 163.Nx 164implementation of the Intel APIC Architecture include 165.An Andrew Doran , 166.An Bill Sommerfeld , 167.An Frank van der Linden , 168and 169.An Stefan Grefen , 170among others. 171The older 8259 172.Tn PIC 173implementation is based on the work of 174.An William Jolitz . 175