1.\" $NetBSD: gio.4,v 1.21 2017/02/17 22:24:47 christos Exp $ 2.\" 3.\" Copyright (c) 2002 The NetBSD Foundation, Inc. 4.\" All rights reserved. 5.\" 6.\" This document is derived from work contributed to The NetBSD Foundation 7.\" by Antti Kantee. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS BE 22.\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28.\" POSSIBILITY OF SUCH DAMAGE. 29.\" 30.Dd February 17, 2017 31.Dt GIO 4 sgimips 32.Os 33.Sh NAME 34.Nm gio 35.Nd SGI's Graphics I/O (GIO) bus (an early PCI-like bus) 36.Sh SYNOPSIS 37.Cd "gio0 at imc0" 38.Cd "gio0 at pic0" 39.Sh DESCRIPTION 40The 41.Nm 42bus is a bus for connecting high-speed peripherals to the main memory and 43CPU. 44The devices themselves are typically (but not necessarily) connected to the 45.Xr sgimips/hpc 4 46peripheral controller, and memory and CPU are accessed through the 47.Xr sgimips/imc 4 48(Indy Memory Controller) or 49.Xr sgimips/pic 4 50(Processor Interface Controller). 51The 52.Nm 53bus is found on the Personal Iris 4D/3x, Indigo, Indy, Challenge S, 54Challenge M, and Indigo2 machines and exists in three incarnations: 55GIO32, GIO32-bis, and GIO64. 56.Sh SEE ALSO 57.Xr sgimips/giopci 4 , 58.Xr sgimips/grtwo 4 , 59.Xr sgimips/hpc 4 , 60.Xr sgimips/imc 4 , 61.Xr sgimips/light 4 , 62.Xr sgimips/newport 4 , 63.Xr sgimips/pic 4 64.Sh HISTORY 65The 66.Nm 67driver first appeared in 68.Nx 1.5 . 69.Sh CAVEATS 70Challenge S systems may use only one 71.Nm 72DMA-capable expansion card, despite having two slots. 73Cards based on the 74.Xr sgimips/hpc 4 75controller, such as the GIO32 scsi and E++ Ethernet adapters, must be 76placed in slot 1 (closest to the side of the case). 77All other cards must be placed in slot 0 (adjacent to the memory banks). 78.Pp 79Indigo2 and Challenge M systems contain either three or four GIO64 connectors, 80depending on the model. 81However, in both cases only two electrically 82distinct slots are present. 83Therefore, distinct expansion cards may not 84share physical connectors associated with the same slot. 85Refer to the PCB 86stencils to determine the association between physical connectors and slots. 87.Sh BUGS 88Systems employing the 89.Xr sgimips/imc 4 90may experience spurious SysAD bus parity errors when using expansion cards, 91which do not drive all data lines during a CPU PIO read. 92The only workaround is to disable SysAD parity checking when using such 93cards. 94