1.\" $NetBSD: cpu.4,v 1.2 2017/02/17 22:24:46 christos Exp $ 2.\" 3.\" $OpenBSD: cpu.4tbl,v 1.19 2004/04/08 16:17:09 mickey Exp $ 4.\" 5.\" Copyright (c) 2002 Michael Shalayeff 6.\" All rights reserved. 7.\" 8.\" Redistribution and use in source and binary forms, with or without 9.\" modification, are permitted provided that the following conditions 10.\" are met: 11.\" 1. Redistributions of source code must retain the above copyright 12.\" notice, this list of conditions and the following disclaimer. 13.\" 2. Redistributions in binary form must reproduce the above copyright 14.\" notice, this list of conditions and the following disclaimer in the 15.\" documentation and/or other materials provided with the distribution. 16.\" 17.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20.\" IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23.\" SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26.\" IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27.\" THE POSSIBILITY OF SUCH DAMAGE. 28.\" 29.Dd February 17, 2017 30.Dt CPU 4 hppa 31.Os 32.Sh NAME 33.Nm cpu 34.Nd HP PA-RISC CPU 35.Sh SYNOPSIS 36.Cd "cpu* at mainbus0 irq 31" 37.Sh DESCRIPTION 38The following table lists the 39.Tn PA-RISC 40CPU types and their characteristics, such as TLB, maximum 41cache sizes and 42.Tn HP 9000/700 43machines they were used in (see also 44.Xr hppa/intro 4 45for the reverse list). 46.Pp 47.in +\n(dIu 48.TS 49tab (:) ; 50l l l l l l l 51l l l l l l l 52_ _ _ _ _ _ _ 53l l l l l l l . 54CPU:PA:Clock:Caches:TLB:BTLB:Models 55 : :(max):(max) : : : 56 : : MHz : KB : : : 577000:1.1a:66 : 256 L1I:96I:4 I:705,710,720 58 : : : 256 L1D:96D:4 D:730,750 597100:1.1b:100:1024 L1I:120:16:715/33/50/75 60 : : :2048 L1D: : :725/50/75 61 : : : : : :{735,755}/100 62 : : : : : :742i, 745i, 747i 637150:1.1b:125:1024 L1I:120:16:{735,755}/125 64 : : :2048 L1D: : : 657100LC:1.1c:100: 1 L1I:64:8:712/60/80/100 66 : : :1024 L2I: : :715/64/80/100 67 : : :1024 L2D: : :715/100XC 68 : : : : : :725/64/100 69 : : : : : :743i, 748i 70 : : : : : :SAIC 717200:1.1d:140: 2 L1 :120:16:C100,C110 72 : : :1024 L2I: : :J200,J210 73 : : :1024 L2D: : : 747300LC:1.1e:180: 64 L1I:96:8:A180,A180C 75 : : : 64 L1D: : :B132,B160,B180 76 : : :8192 L2: : :C132L,C160L 77 : : : : : :744, 745, 748 78 : : : : : :RDI PrecisioBook 79.TE 80.in -\n(dIu 81.Sh FLOATING-POINT COPROCESSOR 82The following table summarizes available floating-point coprocessor 83models for the 32-bit 84.Tn PA-RISC 85processors. 86.Pp 87.in +\n(dIu 88.TS 89tab (:) ; 90l l 91_ _ 92l l . 93FPU:Model 94Indigo: 95Sterling I MIU (TYCO): 96Sterling I MIU (ROC w/Weitek): 97FPC (w/Weitek): 98FPC (w/Bit): 99Timex-II: 100Rolex:725/50, 745i 101HARP-I: 102Tornado:J2x0,C1x0 103PA-50 (Hitachi): 104PCXL:712/60/80/100 105.TE 106.in -\n(dIu 107.Sh SUPERSCALAR EXECUTION 108The following table summarizes the superscalar execution capabilities 109of 32-bit 110.Tn PA-RISC 111processors. 112.Pp 113.in +\n(dIu 114.TS 115nokeep tab (:) ; 116l l l 117_ _ _ 118l l l . 119CPU:Units:Bundles 1207100:1 integer ALU:load-store/fp 121 :1 FP :int/fp 122 : :branch/* 1237100LC:2 integer ALU:load-store/int 124 :1 FP :load-store/fp 125 : :int/fp 126 : :branch/* 1277200:2 integer ALU:load-store/int 128 :1 FP :load-store/fp 129 : :int/int 130 : :int/fp 131 : :branch/* 1327300LC:2 integer ALU:load-store/int 133 :1 FP :load-store/fp 134 : :int/fp 135 : :branch/* 136.TE 137.in -\n(dIu 138.Pp 139In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar, 140with the exception that on CPUs with two integer ALUs only one of these 141units is capable of doing shift, load/store, and test operations. 142Additionally, there are several kinds of restrictions placed upon the 143superscalar execution: 144.Pp 145For the purpose of showing which instructions are allowed to proceed 146together through the pipeline, they are divided into classes: 147.Pp 148.in +\n(dIu 149.TS 150tab (:) ; 151l l 152_ _ 153l l . 154Class:Description 155flop:floating point operation 156ldst:loads and stores 157flex:integer ALU 158mm:shifts, extracts and deposits 159nul:might nullify successor 160bv:BV, BE 161br:other branches 162fsys:FTEST and FP status/exception 163sys:system control instructions 164.TE 165.in -\n(dIu 166.Pp 167For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following 168table lists the instructions which are allowed to be executed 169concurrently: 170.Pp 171.in +\n(dIu 172.TS 173tab (:) ; 174l l 175_ _ 176l l . 177First:Second instruction 178flop: + ldst/flex/mm/nul/bv/br 179ldst: + flop/flex/mm/nul/br 180flex: + flop/ldst/flex/mm/nul/br/fsys 181mm: + flop/ldst/flex/fsys 182nul: + flop 183sys: never bundled 184.TE 185.in -\n(dIu 186.Pp 187ldst + ldst is also possible under certain circumstances, which is then 188called "double word load/store". 189.Pp 190The following restrictions are placed upon the superscalar execution: 191.Pp 192.Bl -bullet -compact 193.It 194An instruction that modifies a register will not be bundled with another 195instruction that takes this register as operand. 196Exception: a flop can be bundled with an FP store of the flop's result register. 197.It 198An FP load to one word of a doubleword register will not be bundled with 199a flop that uses the other doubleword of this register. 200.It 201A flop will not be bundled with an FP load if both instructions have the 202same target register. 203.It 204An instruction that could set the carry/borrow bits will not be bundled 205with an instruction that uses 206carry/borrow bits. 207.It 208An instruction which is in the delay slot of a branch is never bundled 209with other instructions. 210.It 211An instruction which is at an odd word address and executed as a target 212of a taken branch is never bundled. 213.It 214An instruction which might nullify its successor is never bundled with 215this successor. 216Only if the successor is a flop instruction is this bundle allowed. 217.El 218.Sh PERFORMANCE MONITOR COPROCESSOR 219The performance monitor coprocessor is an optional, 220implementation-dependent coprocessor which provides a minimal common 221software interface to implementation-dependent performance monitor hardware. 222.Sh DEBUG SPECIAL UNIT 223The debug special function unit is an optional, 224architected SFU which provides hardware assistance for software debugging 225using breakpoints. 226The debug SFU is currently defined only for Level 0 processors. 227.Sh SEE ALSO 228.Xr hppa/asp 4 , 229.Xr hppa/intro 4 , 230.Xr hppa/lasi 4 , 231.Xr hppa/mem 4 , 232.Xr hppa/wax 4 233.Pp 234.Lk http://www.openpa.net/ "PA-RISC Information Resource" 235.Rs 236.%T PA-RISC 1.1 Architecture and Instruction Set Reference Manual 237.%A Hewlett-Packard 238.%D May 15, 1996 239.Re 240.Rs 241.%T PA7100LC ERS 242.%A Hewlett-Packard 243.%D March 30 1999 244.%N Public version 1.0 245.Re 246.Rs 247.%T Design of the PA7200 CPU 248.%A Hewlett-Packard Journal 249.%D February 1996 250.Re 251.Rs 252.%T PA7300LC ERS 253.%A Hewlett-Packard 254.%D March 18 1996 255.%N Version 1.0 256.Re 257.Sh HISTORY 258The 259.Nm 260driver was written by 261.An Michael Shalayeff Aq Mt mickey@openbsd.org 262for the HPPA port for 263.Ox 2.5 . 264It was ported to 265.Nx 1.6 266by Matthew Fredette. 267