1.\" $NetBSD: gpioiic.4,v 1.6 2014/03/18 18:20:39 riastradh Exp $ 2.\" $OpenBSD: gpioiic.4,v 1.6 2008/11/24 15:30:21 jmc Exp $ 3.\" 4.\" Copyright (c) 2006 Alexander Yurchenko <grange@openbsd.org> 5.\" 6.\" Permission to use, copy, modify, and distribute this software for any 7.\" purpose with or without fee is hereby granted, provided that the above 8.\" copyright notice and this permission notice appear in all copies. 9.\" 10.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17.\" 18.Dd October 2, 2011 19.Dt GPIOIIC 4 20.Os 21.Sh NAME 22.Nm gpioiic 23.Nd GPIO I2C controller 24.Sh SYNOPSIS 25.Cd "gpioiic* at gpio? offset 0 mask 0x3 flag 0x0" 26.Cd "gpioiic* at gpio?" 27.Cd "iic* at gpioiic?" 28.Sh DESCRIPTION 29The 30.Nm 31driver allows bit-banging an I2C bus as a master using two GPIO pins. 32By default the first pin is used as a serial data (SDA) signal and the 33second as a serial clock (SCL). 34If the flag locator is set to 0x01, the order of the SDA and SCL signals 35is reversed. 36Both GPIO pins must be able to drive an output and the SDA pin must be 37also able to read an input. 38.Pp 39The pins can be specified in the kernel configuration with the 40.Ar offset 41and the 42.Ar mask 43locators. 44The 45.Ar offset 46and 47.Ar mask 48can also be specified when 49.Nm 50is attached at runtime using the 51.Dv GPIOATTACH 52.Xr ioctl 2 53on the 54.Xr gpio 4 55device. 56Each bit in the 57.Ar mask 58locator defines one pin; the pin number is calculated as an addition of 59the bit position and the 60.Ar offset 61locator. 62For example, 63.Ar offset 17 64and 65.Ar mask 0x5 66defines pin numbers 17 and 19. 67.Sh SEE ALSO 68.Xr gpio 4 , 69.Xr iic 4 , 70.Xr intro 4 71.Sh HISTORY 72The 73.Nm 74driver first appeared in 75.Ox 3.9 76and 77.Nx 5.0 . 78.Sh AUTHORS 79.An -nosplit 80The 81.Nm 82driver was written by 83.An Alexander Yurchenko Aq Mt grange@openbsd.org 84and was ported to 85.Nx 86by 87.An Marc Balmer Aq Mt marc@msys.ch . 88.Sh CAVEATS 89A 90.Nm 91device can not be detached from the 92.Xr gpio 4 93bus at runtime due to the fact that 94.Xr iic 4 95busses can not detach once attached. 96