1 /* Simulator instruction semantics for m32rbf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2024 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifdef DEFINE_LABELS 26 27 /* The labels have the case they have because the enum of insn types 28 is all uppercase and in the non-stdc case the insn symbol is built 29 into the enum name. */ 30 31 static struct { 32 int index; 33 void *label; 34 } labels[] = { 35 { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, 36 { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, 37 { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, 38 { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, 39 { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, 40 { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, 41 { M32RBF_INSN_ADD, && case_sem_INSN_ADD }, 42 { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 }, 43 { M32RBF_INSN_AND, && case_sem_INSN_AND }, 44 { M32RBF_INSN_AND3, && case_sem_INSN_AND3 }, 45 { M32RBF_INSN_OR, && case_sem_INSN_OR }, 46 { M32RBF_INSN_OR3, && case_sem_INSN_OR3 }, 47 { M32RBF_INSN_XOR, && case_sem_INSN_XOR }, 48 { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 }, 49 { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI }, 50 { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV }, 51 { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 }, 52 { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX }, 53 { M32RBF_INSN_BC8, && case_sem_INSN_BC8 }, 54 { M32RBF_INSN_BC24, && case_sem_INSN_BC24 }, 55 { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ }, 56 { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ }, 57 { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ }, 58 { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ }, 59 { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ }, 60 { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ }, 61 { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ }, 62 { M32RBF_INSN_BL8, && case_sem_INSN_BL8 }, 63 { M32RBF_INSN_BL24, && case_sem_INSN_BL24 }, 64 { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 }, 65 { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 }, 66 { M32RBF_INSN_BNE, && case_sem_INSN_BNE }, 67 { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 }, 68 { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 }, 69 { M32RBF_INSN_CMP, && case_sem_INSN_CMP }, 70 { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI }, 71 { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU }, 72 { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI }, 73 { M32RBF_INSN_DIV, && case_sem_INSN_DIV }, 74 { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU }, 75 { M32RBF_INSN_REM, && case_sem_INSN_REM }, 76 { M32RBF_INSN_REMU, && case_sem_INSN_REMU }, 77 { M32RBF_INSN_JL, && case_sem_INSN_JL }, 78 { M32RBF_INSN_JMP, && case_sem_INSN_JMP }, 79 { M32RBF_INSN_LD, && case_sem_INSN_LD }, 80 { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D }, 81 { M32RBF_INSN_LDB, && case_sem_INSN_LDB }, 82 { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D }, 83 { M32RBF_INSN_LDH, && case_sem_INSN_LDH }, 84 { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D }, 85 { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB }, 86 { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D }, 87 { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH }, 88 { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D }, 89 { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS }, 90 { M32RBF_INSN_LD24, && case_sem_INSN_LD24 }, 91 { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 }, 92 { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 }, 93 { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK }, 94 { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI }, 95 { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO }, 96 { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI }, 97 { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO }, 98 { M32RBF_INSN_MUL, && case_sem_INSN_MUL }, 99 { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI }, 100 { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO }, 101 { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI }, 102 { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO }, 103 { M32RBF_INSN_MV, && case_sem_INSN_MV }, 104 { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI }, 105 { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO }, 106 { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI }, 107 { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC }, 108 { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI }, 109 { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO }, 110 { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC }, 111 { M32RBF_INSN_NEG, && case_sem_INSN_NEG }, 112 { M32RBF_INSN_NOP, && case_sem_INSN_NOP }, 113 { M32RBF_INSN_NOT, && case_sem_INSN_NOT }, 114 { M32RBF_INSN_RAC, && case_sem_INSN_RAC }, 115 { M32RBF_INSN_RACH, && case_sem_INSN_RACH }, 116 { M32RBF_INSN_RTE, && case_sem_INSN_RTE }, 117 { M32RBF_INSN_SETH, && case_sem_INSN_SETH }, 118 { M32RBF_INSN_SLL, && case_sem_INSN_SLL }, 119 { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 }, 120 { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI }, 121 { M32RBF_INSN_SRA, && case_sem_INSN_SRA }, 122 { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 }, 123 { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI }, 124 { M32RBF_INSN_SRL, && case_sem_INSN_SRL }, 125 { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 }, 126 { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI }, 127 { M32RBF_INSN_ST, && case_sem_INSN_ST }, 128 { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D }, 129 { M32RBF_INSN_STB, && case_sem_INSN_STB }, 130 { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D }, 131 { M32RBF_INSN_STH, && case_sem_INSN_STH }, 132 { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D }, 133 { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS }, 134 { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS }, 135 { M32RBF_INSN_SUB, && case_sem_INSN_SUB }, 136 { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV }, 137 { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX }, 138 { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP }, 139 { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK }, 140 { M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW }, 141 { M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW }, 142 { M32RBF_INSN_BSET, && case_sem_INSN_BSET }, 143 { M32RBF_INSN_BCLR, && case_sem_INSN_BCLR }, 144 { M32RBF_INSN_BTST, && case_sem_INSN_BTST }, 145 { 0, 0 } 146 }; 147 int i; 148 149 for (i = 0; labels[i].label != 0; ++i) 150 { 151 #if FAST_P 152 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; 153 #else 154 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; 155 #endif 156 } 157 158 #undef DEFINE_LABELS 159 #endif /* DEFINE_LABELS */ 160 161 #ifdef DEFINE_SWITCH 162 163 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn 164 off frills like tracing and profiling. */ 165 /* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something 166 that can cause it to be optimized out. Another way would be to emit 167 special handlers into the instruction "stream". */ 168 169 #if FAST_P 170 #undef CGEN_TRACE_RESULT 171 #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) 172 #endif 173 174 #undef GET_ATTR 175 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) 176 177 { 178 179 #if WITH_SCACHE_PBB 180 181 /* Branch to next handler without going around main loop. */ 182 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case 183 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) 184 185 #else /* ! WITH_SCACHE_PBB */ 186 187 #define NEXT(vpc) BREAK (sem) 188 #ifdef __GNUC__ 189 #if FAST_P 190 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) 191 #else 192 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) 193 #endif 194 #else 195 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) 196 #endif 197 198 #endif /* ! WITH_SCACHE_PBB */ 199 200 { 201 202 CASE (sem, INSN_X_INVALID) : /* --invalid-- */ 203 { 204 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 205 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 206 #define FLD(f) abuf->fields.sfmt_empty.f 207 int UNUSED written = 0; 208 IADDR UNUSED pc = abuf->addr; 209 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 210 211 { 212 /* Update the recorded pc in the cpu state struct. 213 Only necessary for WITH_SCACHE case, but to avoid the 214 conditional compilation .... */ 215 SET_H_PC (pc); 216 /* Virtual insns have zero size. Overwrite vpc with address of next insn 217 using the default-insn-bitsize spec. When executing insns in parallel 218 we may want to queue the fault and continue execution. */ 219 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 220 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); 221 } 222 223 #undef FLD 224 } 225 NEXT (vpc); 226 227 CASE (sem, INSN_X_AFTER) : /* --after-- */ 228 { 229 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 230 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 231 #define FLD(f) abuf->fields.sfmt_empty.f 232 int UNUSED written = 0; 233 IADDR UNUSED pc = abuf->addr; 234 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 235 236 { 237 #if WITH_SCACHE_PBB_M32RBF 238 m32rbf_pbb_after (current_cpu, sem_arg); 239 #endif 240 } 241 242 #undef FLD 243 } 244 NEXT (vpc); 245 246 CASE (sem, INSN_X_BEFORE) : /* --before-- */ 247 { 248 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 249 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 250 #define FLD(f) abuf->fields.sfmt_empty.f 251 int UNUSED written = 0; 252 IADDR UNUSED pc = abuf->addr; 253 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 254 255 { 256 #if WITH_SCACHE_PBB_M32RBF 257 m32rbf_pbb_before (current_cpu, sem_arg); 258 #endif 259 } 260 261 #undef FLD 262 } 263 NEXT (vpc); 264 265 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ 266 { 267 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 268 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 269 #define FLD(f) abuf->fields.sfmt_empty.f 270 int UNUSED written = 0; 271 IADDR UNUSED pc = abuf->addr; 272 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 273 274 { 275 #if WITH_SCACHE_PBB_M32RBF 276 #ifdef DEFINE_SWITCH 277 vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, 278 pbb_br_type, pbb_br_npc); 279 BREAK (sem); 280 #else 281 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ 282 vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, 283 CPU_PBB_BR_TYPE (current_cpu), 284 CPU_PBB_BR_NPC (current_cpu)); 285 #endif 286 #endif 287 } 288 289 #undef FLD 290 } 291 NEXT (vpc); 292 293 CASE (sem, INSN_X_CHAIN) : /* --chain-- */ 294 { 295 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 296 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 297 #define FLD(f) abuf->fields.sfmt_empty.f 298 int UNUSED written = 0; 299 IADDR UNUSED pc = abuf->addr; 300 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 301 302 { 303 #if WITH_SCACHE_PBB_M32RBF 304 vpc = m32rbf_pbb_chain (current_cpu, sem_arg); 305 #ifdef DEFINE_SWITCH 306 BREAK (sem); 307 #endif 308 #endif 309 } 310 311 #undef FLD 312 } 313 NEXT (vpc); 314 315 CASE (sem, INSN_X_BEGIN) : /* --begin-- */ 316 { 317 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 318 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 319 #define FLD(f) abuf->fields.sfmt_empty.f 320 int UNUSED written = 0; 321 IADDR UNUSED pc = abuf->addr; 322 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 323 324 { 325 #if WITH_SCACHE_PBB_M32RBF 326 #if defined DEFINE_SWITCH || defined FAST_P 327 /* In the switch case FAST_P is a constant, allowing several optimizations 328 in any called inline functions. */ 329 vpc = m32rbf_pbb_begin (current_cpu, FAST_P); 330 #else 331 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ 332 vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); 333 #else 334 vpc = m32rbf_pbb_begin (current_cpu, 0); 335 #endif 336 #endif 337 #endif 338 } 339 340 #undef FLD 341 } 342 NEXT (vpc); 343 344 CASE (sem, INSN_ADD) : /* add $dr,$sr */ 345 { 346 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 347 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 348 #define FLD(f) abuf->fields.sfmt_add.f 349 int UNUSED written = 0; 350 IADDR UNUSED pc = abuf->addr; 351 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 352 353 { 354 SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr)); 355 * FLD (i_dr) = opval; 356 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 357 } 358 359 #undef FLD 360 } 361 NEXT (vpc); 362 363 CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */ 364 { 365 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 366 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 367 #define FLD(f) abuf->fields.sfmt_add3.f 368 int UNUSED written = 0; 369 IADDR UNUSED pc = abuf->addr; 370 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 371 372 { 373 SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16)); 374 * FLD (i_dr) = opval; 375 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 376 } 377 378 #undef FLD 379 } 380 NEXT (vpc); 381 382 CASE (sem, INSN_AND) : /* and $dr,$sr */ 383 { 384 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 385 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 386 #define FLD(f) abuf->fields.sfmt_add.f 387 int UNUSED written = 0; 388 IADDR UNUSED pc = abuf->addr; 389 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 390 391 { 392 SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr)); 393 * FLD (i_dr) = opval; 394 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 395 } 396 397 #undef FLD 398 } 399 NEXT (vpc); 400 401 CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */ 402 { 403 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 404 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 405 #define FLD(f) abuf->fields.sfmt_and3.f 406 int UNUSED written = 0; 407 IADDR UNUSED pc = abuf->addr; 408 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 409 410 { 411 SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16)); 412 * FLD (i_dr) = opval; 413 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 414 } 415 416 #undef FLD 417 } 418 NEXT (vpc); 419 420 CASE (sem, INSN_OR) : /* or $dr,$sr */ 421 { 422 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 423 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 424 #define FLD(f) abuf->fields.sfmt_add.f 425 int UNUSED written = 0; 426 IADDR UNUSED pc = abuf->addr; 427 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 428 429 { 430 SI opval = ORSI (* FLD (i_dr), * FLD (i_sr)); 431 * FLD (i_dr) = opval; 432 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 433 } 434 435 #undef FLD 436 } 437 NEXT (vpc); 438 439 CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */ 440 { 441 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 442 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 443 #define FLD(f) abuf->fields.sfmt_and3.f 444 int UNUSED written = 0; 445 IADDR UNUSED pc = abuf->addr; 446 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 447 448 { 449 SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16)); 450 * FLD (i_dr) = opval; 451 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 452 } 453 454 #undef FLD 455 } 456 NEXT (vpc); 457 458 CASE (sem, INSN_XOR) : /* xor $dr,$sr */ 459 { 460 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 461 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 462 #define FLD(f) abuf->fields.sfmt_add.f 463 int UNUSED written = 0; 464 IADDR UNUSED pc = abuf->addr; 465 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 466 467 { 468 SI opval = XORSI (* FLD (i_dr), * FLD (i_sr)); 469 * FLD (i_dr) = opval; 470 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 471 } 472 473 #undef FLD 474 } 475 NEXT (vpc); 476 477 CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */ 478 { 479 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 480 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 481 #define FLD(f) abuf->fields.sfmt_and3.f 482 int UNUSED written = 0; 483 IADDR UNUSED pc = abuf->addr; 484 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 485 486 { 487 SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16)); 488 * FLD (i_dr) = opval; 489 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 490 } 491 492 #undef FLD 493 } 494 NEXT (vpc); 495 496 CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */ 497 { 498 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 499 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 500 #define FLD(f) abuf->fields.sfmt_addi.f 501 int UNUSED written = 0; 502 IADDR UNUSED pc = abuf->addr; 503 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 504 505 { 506 SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8)); 507 * FLD (i_dr) = opval; 508 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 509 } 510 511 #undef FLD 512 } 513 NEXT (vpc); 514 515 CASE (sem, INSN_ADDV) : /* addv $dr,$sr */ 516 { 517 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 518 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 519 #define FLD(f) abuf->fields.sfmt_add.f 520 int UNUSED written = 0; 521 IADDR UNUSED pc = abuf->addr; 522 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 523 524 { 525 SI temp0;BI temp1; 526 temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); 527 temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); 528 { 529 SI opval = temp0; 530 * FLD (i_dr) = opval; 531 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 532 } 533 { 534 BI opval = temp1; 535 CPU (h_cond) = opval; 536 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 537 } 538 } 539 540 #undef FLD 541 } 542 NEXT (vpc); 543 544 CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */ 545 { 546 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 547 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 548 #define FLD(f) abuf->fields.sfmt_add3.f 549 int UNUSED written = 0; 550 IADDR UNUSED pc = abuf->addr; 551 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 552 553 { 554 SI temp0;BI temp1; 555 temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16)); 556 temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0); 557 { 558 SI opval = temp0; 559 * FLD (i_dr) = opval; 560 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 561 } 562 { 563 BI opval = temp1; 564 CPU (h_cond) = opval; 565 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 566 } 567 } 568 569 #undef FLD 570 } 571 NEXT (vpc); 572 573 CASE (sem, INSN_ADDX) : /* addx $dr,$sr */ 574 { 575 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 576 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 577 #define FLD(f) abuf->fields.sfmt_add.f 578 int UNUSED written = 0; 579 IADDR UNUSED pc = abuf->addr; 580 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 581 582 { 583 SI temp0;BI temp1; 584 temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); 585 temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); 586 { 587 SI opval = temp0; 588 * FLD (i_dr) = opval; 589 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 590 } 591 { 592 BI opval = temp1; 593 CPU (h_cond) = opval; 594 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 595 } 596 } 597 598 #undef FLD 599 } 600 NEXT (vpc); 601 602 CASE (sem, INSN_BC8) : /* bc.s $disp8 */ 603 { 604 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 605 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 606 #define FLD(f) abuf->fields.sfmt_bl8.f 607 int UNUSED written = 0; 608 IADDR UNUSED pc = abuf->addr; 609 SEM_BRANCH_INIT 610 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 611 612 if (CPU (h_cond)) { 613 { 614 USI opval = FLD (i_disp8); 615 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 616 written |= (1 << 2); 617 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 618 } 619 } 620 621 abuf->written = written; 622 SEM_BRANCH_FINI (vpc); 623 #undef FLD 624 } 625 NEXT (vpc); 626 627 CASE (sem, INSN_BC24) : /* bc.l $disp24 */ 628 { 629 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 630 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 631 #define FLD(f) abuf->fields.sfmt_bl24.f 632 int UNUSED written = 0; 633 IADDR UNUSED pc = abuf->addr; 634 SEM_BRANCH_INIT 635 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 636 637 if (CPU (h_cond)) { 638 { 639 USI opval = FLD (i_disp24); 640 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 641 written |= (1 << 2); 642 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 643 } 644 } 645 646 abuf->written = written; 647 SEM_BRANCH_FINI (vpc); 648 #undef FLD 649 } 650 NEXT (vpc); 651 652 CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */ 653 { 654 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 655 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 656 #define FLD(f) abuf->fields.sfmt_beq.f 657 int UNUSED written = 0; 658 IADDR UNUSED pc = abuf->addr; 659 SEM_BRANCH_INIT 660 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 661 662 if (EQSI (* FLD (i_src1), * FLD (i_src2))) { 663 { 664 USI opval = FLD (i_disp16); 665 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 666 written |= (1 << 3); 667 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 668 } 669 } 670 671 abuf->written = written; 672 SEM_BRANCH_FINI (vpc); 673 #undef FLD 674 } 675 NEXT (vpc); 676 677 CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */ 678 { 679 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 680 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 681 #define FLD(f) abuf->fields.sfmt_beq.f 682 int UNUSED written = 0; 683 IADDR UNUSED pc = abuf->addr; 684 SEM_BRANCH_INIT 685 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 686 687 if (EQSI (* FLD (i_src2), 0)) { 688 { 689 USI opval = FLD (i_disp16); 690 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 691 written |= (1 << 2); 692 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 693 } 694 } 695 696 abuf->written = written; 697 SEM_BRANCH_FINI (vpc); 698 #undef FLD 699 } 700 NEXT (vpc); 701 702 CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */ 703 { 704 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 705 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 706 #define FLD(f) abuf->fields.sfmt_beq.f 707 int UNUSED written = 0; 708 IADDR UNUSED pc = abuf->addr; 709 SEM_BRANCH_INIT 710 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 711 712 if (GESI (* FLD (i_src2), 0)) { 713 { 714 USI opval = FLD (i_disp16); 715 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 716 written |= (1 << 2); 717 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 718 } 719 } 720 721 abuf->written = written; 722 SEM_BRANCH_FINI (vpc); 723 #undef FLD 724 } 725 NEXT (vpc); 726 727 CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */ 728 { 729 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 730 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 731 #define FLD(f) abuf->fields.sfmt_beq.f 732 int UNUSED written = 0; 733 IADDR UNUSED pc = abuf->addr; 734 SEM_BRANCH_INIT 735 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 736 737 if (GTSI (* FLD (i_src2), 0)) { 738 { 739 USI opval = FLD (i_disp16); 740 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 741 written |= (1 << 2); 742 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 743 } 744 } 745 746 abuf->written = written; 747 SEM_BRANCH_FINI (vpc); 748 #undef FLD 749 } 750 NEXT (vpc); 751 752 CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */ 753 { 754 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 755 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 756 #define FLD(f) abuf->fields.sfmt_beq.f 757 int UNUSED written = 0; 758 IADDR UNUSED pc = abuf->addr; 759 SEM_BRANCH_INIT 760 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 761 762 if (LESI (* FLD (i_src2), 0)) { 763 { 764 USI opval = FLD (i_disp16); 765 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 766 written |= (1 << 2); 767 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 768 } 769 } 770 771 abuf->written = written; 772 SEM_BRANCH_FINI (vpc); 773 #undef FLD 774 } 775 NEXT (vpc); 776 777 CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */ 778 { 779 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 780 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 781 #define FLD(f) abuf->fields.sfmt_beq.f 782 int UNUSED written = 0; 783 IADDR UNUSED pc = abuf->addr; 784 SEM_BRANCH_INIT 785 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 786 787 if (LTSI (* FLD (i_src2), 0)) { 788 { 789 USI opval = FLD (i_disp16); 790 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 791 written |= (1 << 2); 792 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 793 } 794 } 795 796 abuf->written = written; 797 SEM_BRANCH_FINI (vpc); 798 #undef FLD 799 } 800 NEXT (vpc); 801 802 CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */ 803 { 804 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 805 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 806 #define FLD(f) abuf->fields.sfmt_beq.f 807 int UNUSED written = 0; 808 IADDR UNUSED pc = abuf->addr; 809 SEM_BRANCH_INIT 810 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 811 812 if (NESI (* FLD (i_src2), 0)) { 813 { 814 USI opval = FLD (i_disp16); 815 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 816 written |= (1 << 2); 817 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 818 } 819 } 820 821 abuf->written = written; 822 SEM_BRANCH_FINI (vpc); 823 #undef FLD 824 } 825 NEXT (vpc); 826 827 CASE (sem, INSN_BL8) : /* bl.s $disp8 */ 828 { 829 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 830 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 831 #define FLD(f) abuf->fields.sfmt_bl8.f 832 int UNUSED written = 0; 833 IADDR UNUSED pc = abuf->addr; 834 SEM_BRANCH_INIT 835 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 836 837 { 838 { 839 SI opval = ADDSI (ANDSI (pc, -4), 4); 840 CPU (h_gr[((UINT) 14)]) = opval; 841 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 842 } 843 { 844 USI opval = FLD (i_disp8); 845 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 846 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 847 } 848 } 849 850 SEM_BRANCH_FINI (vpc); 851 #undef FLD 852 } 853 NEXT (vpc); 854 855 CASE (sem, INSN_BL24) : /* bl.l $disp24 */ 856 { 857 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 858 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 859 #define FLD(f) abuf->fields.sfmt_bl24.f 860 int UNUSED written = 0; 861 IADDR UNUSED pc = abuf->addr; 862 SEM_BRANCH_INIT 863 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 864 865 { 866 { 867 SI opval = ADDSI (pc, 4); 868 CPU (h_gr[((UINT) 14)]) = opval; 869 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 870 } 871 { 872 USI opval = FLD (i_disp24); 873 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 874 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 875 } 876 } 877 878 SEM_BRANCH_FINI (vpc); 879 #undef FLD 880 } 881 NEXT (vpc); 882 883 CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */ 884 { 885 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 886 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 887 #define FLD(f) abuf->fields.sfmt_bl8.f 888 int UNUSED written = 0; 889 IADDR UNUSED pc = abuf->addr; 890 SEM_BRANCH_INIT 891 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 892 893 if (NOTBI (CPU (h_cond))) { 894 { 895 USI opval = FLD (i_disp8); 896 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 897 written |= (1 << 2); 898 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 899 } 900 } 901 902 abuf->written = written; 903 SEM_BRANCH_FINI (vpc); 904 #undef FLD 905 } 906 NEXT (vpc); 907 908 CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */ 909 { 910 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 911 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 912 #define FLD(f) abuf->fields.sfmt_bl24.f 913 int UNUSED written = 0; 914 IADDR UNUSED pc = abuf->addr; 915 SEM_BRANCH_INIT 916 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 917 918 if (NOTBI (CPU (h_cond))) { 919 { 920 USI opval = FLD (i_disp24); 921 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 922 written |= (1 << 2); 923 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 924 } 925 } 926 927 abuf->written = written; 928 SEM_BRANCH_FINI (vpc); 929 #undef FLD 930 } 931 NEXT (vpc); 932 933 CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */ 934 { 935 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 936 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 937 #define FLD(f) abuf->fields.sfmt_beq.f 938 int UNUSED written = 0; 939 IADDR UNUSED pc = abuf->addr; 940 SEM_BRANCH_INIT 941 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 942 943 if (NESI (* FLD (i_src1), * FLD (i_src2))) { 944 { 945 USI opval = FLD (i_disp16); 946 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 947 written |= (1 << 3); 948 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 949 } 950 } 951 952 abuf->written = written; 953 SEM_BRANCH_FINI (vpc); 954 #undef FLD 955 } 956 NEXT (vpc); 957 958 CASE (sem, INSN_BRA8) : /* bra.s $disp8 */ 959 { 960 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 961 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 962 #define FLD(f) abuf->fields.sfmt_bl8.f 963 int UNUSED written = 0; 964 IADDR UNUSED pc = abuf->addr; 965 SEM_BRANCH_INIT 966 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 967 968 { 969 USI opval = FLD (i_disp8); 970 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 971 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 972 } 973 974 SEM_BRANCH_FINI (vpc); 975 #undef FLD 976 } 977 NEXT (vpc); 978 979 CASE (sem, INSN_BRA24) : /* bra.l $disp24 */ 980 { 981 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 982 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 983 #define FLD(f) abuf->fields.sfmt_bl24.f 984 int UNUSED written = 0; 985 IADDR UNUSED pc = abuf->addr; 986 SEM_BRANCH_INIT 987 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 988 989 { 990 USI opval = FLD (i_disp24); 991 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 992 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 993 } 994 995 SEM_BRANCH_FINI (vpc); 996 #undef FLD 997 } 998 NEXT (vpc); 999 1000 CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */ 1001 { 1002 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1003 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1004 #define FLD(f) abuf->fields.sfmt_st_plus.f 1005 int UNUSED written = 0; 1006 IADDR UNUSED pc = abuf->addr; 1007 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1008 1009 { 1010 BI opval = LTSI (* FLD (i_src1), * FLD (i_src2)); 1011 CPU (h_cond) = opval; 1012 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 1013 } 1014 1015 #undef FLD 1016 } 1017 NEXT (vpc); 1018 1019 CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */ 1020 { 1021 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1022 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1023 #define FLD(f) abuf->fields.sfmt_st_d.f 1024 int UNUSED written = 0; 1025 IADDR UNUSED pc = abuf->addr; 1026 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1027 1028 { 1029 BI opval = LTSI (* FLD (i_src2), FLD (f_simm16)); 1030 CPU (h_cond) = opval; 1031 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 1032 } 1033 1034 #undef FLD 1035 } 1036 NEXT (vpc); 1037 1038 CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */ 1039 { 1040 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1041 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1042 #define FLD(f) abuf->fields.sfmt_st_plus.f 1043 int UNUSED written = 0; 1044 IADDR UNUSED pc = abuf->addr; 1045 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1046 1047 { 1048 BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2)); 1049 CPU (h_cond) = opval; 1050 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 1051 } 1052 1053 #undef FLD 1054 } 1055 NEXT (vpc); 1056 1057 CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */ 1058 { 1059 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1060 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1061 #define FLD(f) abuf->fields.sfmt_st_d.f 1062 int UNUSED written = 0; 1063 IADDR UNUSED pc = abuf->addr; 1064 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1065 1066 { 1067 BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16)); 1068 CPU (h_cond) = opval; 1069 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 1070 } 1071 1072 #undef FLD 1073 } 1074 NEXT (vpc); 1075 1076 CASE (sem, INSN_DIV) : /* div $dr,$sr */ 1077 { 1078 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1079 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1080 #define FLD(f) abuf->fields.sfmt_add.f 1081 int UNUSED written = 0; 1082 IADDR UNUSED pc = abuf->addr; 1083 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1084 1085 if (NESI (* FLD (i_sr), 0)) { 1086 { 1087 SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr)); 1088 * FLD (i_dr) = opval; 1089 written |= (1 << 2); 1090 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1091 } 1092 } 1093 1094 abuf->written = written; 1095 #undef FLD 1096 } 1097 NEXT (vpc); 1098 1099 CASE (sem, INSN_DIVU) : /* divu $dr,$sr */ 1100 { 1101 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1102 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1103 #define FLD(f) abuf->fields.sfmt_add.f 1104 int UNUSED written = 0; 1105 IADDR UNUSED pc = abuf->addr; 1106 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1107 1108 if (NESI (* FLD (i_sr), 0)) { 1109 { 1110 SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr)); 1111 * FLD (i_dr) = opval; 1112 written |= (1 << 2); 1113 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1114 } 1115 } 1116 1117 abuf->written = written; 1118 #undef FLD 1119 } 1120 NEXT (vpc); 1121 1122 CASE (sem, INSN_REM) : /* rem $dr,$sr */ 1123 { 1124 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1125 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1126 #define FLD(f) abuf->fields.sfmt_add.f 1127 int UNUSED written = 0; 1128 IADDR UNUSED pc = abuf->addr; 1129 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1130 1131 if (NESI (* FLD (i_sr), 0)) { 1132 { 1133 SI opval = MODSI (* FLD (i_dr), * FLD (i_sr)); 1134 * FLD (i_dr) = opval; 1135 written |= (1 << 2); 1136 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1137 } 1138 } 1139 1140 abuf->written = written; 1141 #undef FLD 1142 } 1143 NEXT (vpc); 1144 1145 CASE (sem, INSN_REMU) : /* remu $dr,$sr */ 1146 { 1147 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1148 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1149 #define FLD(f) abuf->fields.sfmt_add.f 1150 int UNUSED written = 0; 1151 IADDR UNUSED pc = abuf->addr; 1152 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1153 1154 if (NESI (* FLD (i_sr), 0)) { 1155 { 1156 SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr)); 1157 * FLD (i_dr) = opval; 1158 written |= (1 << 2); 1159 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1160 } 1161 } 1162 1163 abuf->written = written; 1164 #undef FLD 1165 } 1166 NEXT (vpc); 1167 1168 CASE (sem, INSN_JL) : /* jl $sr */ 1169 { 1170 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1171 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1172 #define FLD(f) abuf->fields.sfmt_jl.f 1173 int UNUSED written = 0; 1174 IADDR UNUSED pc = abuf->addr; 1175 SEM_BRANCH_INIT 1176 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1177 1178 { 1179 SI temp0;USI temp1; 1180 temp0 = ADDSI (ANDSI (pc, -4), 4); 1181 temp1 = ANDSI (* FLD (i_sr), -4); 1182 { 1183 SI opval = temp0; 1184 CPU (h_gr[((UINT) 14)]) = opval; 1185 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1186 } 1187 { 1188 USI opval = temp1; 1189 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1190 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1191 } 1192 } 1193 1194 SEM_BRANCH_FINI (vpc); 1195 #undef FLD 1196 } 1197 NEXT (vpc); 1198 1199 CASE (sem, INSN_JMP) : /* jmp $sr */ 1200 { 1201 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1202 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1203 #define FLD(f) abuf->fields.sfmt_jl.f 1204 int UNUSED written = 0; 1205 IADDR UNUSED pc = abuf->addr; 1206 SEM_BRANCH_INIT 1207 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1208 1209 { 1210 USI opval = ANDSI (* FLD (i_sr), -4); 1211 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1212 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1213 } 1214 1215 SEM_BRANCH_FINI (vpc); 1216 #undef FLD 1217 } 1218 NEXT (vpc); 1219 1220 CASE (sem, INSN_LD) : /* ld $dr,@$sr */ 1221 { 1222 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1223 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1224 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1225 int UNUSED written = 0; 1226 IADDR UNUSED pc = abuf->addr; 1227 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1228 1229 { 1230 SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); 1231 * FLD (i_dr) = opval; 1232 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1233 } 1234 1235 #undef FLD 1236 } 1237 NEXT (vpc); 1238 1239 CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */ 1240 { 1241 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1242 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1243 #define FLD(f) abuf->fields.sfmt_add3.f 1244 int UNUSED written = 0; 1245 IADDR UNUSED pc = abuf->addr; 1246 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1247 1248 { 1249 SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))); 1250 * FLD (i_dr) = opval; 1251 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1252 } 1253 1254 #undef FLD 1255 } 1256 NEXT (vpc); 1257 1258 CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */ 1259 { 1260 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1261 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1262 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1263 int UNUSED written = 0; 1264 IADDR UNUSED pc = abuf->addr; 1265 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1266 1267 { 1268 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); 1269 * FLD (i_dr) = opval; 1270 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1271 } 1272 1273 #undef FLD 1274 } 1275 NEXT (vpc); 1276 1277 CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */ 1278 { 1279 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1280 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1281 #define FLD(f) abuf->fields.sfmt_add3.f 1282 int UNUSED written = 0; 1283 IADDR UNUSED pc = abuf->addr; 1284 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1285 1286 { 1287 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); 1288 * FLD (i_dr) = opval; 1289 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1290 } 1291 1292 #undef FLD 1293 } 1294 NEXT (vpc); 1295 1296 CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */ 1297 { 1298 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1299 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1300 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1301 int UNUSED written = 0; 1302 IADDR UNUSED pc = abuf->addr; 1303 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1304 1305 { 1306 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); 1307 * FLD (i_dr) = opval; 1308 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1309 } 1310 1311 #undef FLD 1312 } 1313 NEXT (vpc); 1314 1315 CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */ 1316 { 1317 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1318 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1319 #define FLD(f) abuf->fields.sfmt_add3.f 1320 int UNUSED written = 0; 1321 IADDR UNUSED pc = abuf->addr; 1322 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1323 1324 { 1325 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); 1326 * FLD (i_dr) = opval; 1327 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1328 } 1329 1330 #undef FLD 1331 } 1332 NEXT (vpc); 1333 1334 CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */ 1335 { 1336 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1337 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1338 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1339 int UNUSED written = 0; 1340 IADDR UNUSED pc = abuf->addr; 1341 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1342 1343 { 1344 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr))); 1345 * FLD (i_dr) = opval; 1346 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1347 } 1348 1349 #undef FLD 1350 } 1351 NEXT (vpc); 1352 1353 CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */ 1354 { 1355 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1356 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1357 #define FLD(f) abuf->fields.sfmt_add3.f 1358 int UNUSED written = 0; 1359 IADDR UNUSED pc = abuf->addr; 1360 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1361 1362 { 1363 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); 1364 * FLD (i_dr) = opval; 1365 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1366 } 1367 1368 #undef FLD 1369 } 1370 NEXT (vpc); 1371 1372 CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */ 1373 { 1374 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1375 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1376 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1377 int UNUSED written = 0; 1378 IADDR UNUSED pc = abuf->addr; 1379 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1380 1381 { 1382 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr))); 1383 * FLD (i_dr) = opval; 1384 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1385 } 1386 1387 #undef FLD 1388 } 1389 NEXT (vpc); 1390 1391 CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */ 1392 { 1393 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1394 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1395 #define FLD(f) abuf->fields.sfmt_add3.f 1396 int UNUSED written = 0; 1397 IADDR UNUSED pc = abuf->addr; 1398 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1399 1400 { 1401 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)))); 1402 * FLD (i_dr) = opval; 1403 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1404 } 1405 1406 #undef FLD 1407 } 1408 NEXT (vpc); 1409 1410 CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */ 1411 { 1412 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1413 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1414 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1415 int UNUSED written = 0; 1416 IADDR UNUSED pc = abuf->addr; 1417 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1418 1419 { 1420 SI temp0;SI temp1; 1421 temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); 1422 temp1 = ADDSI (* FLD (i_sr), 4); 1423 { 1424 SI opval = temp0; 1425 * FLD (i_dr) = opval; 1426 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1427 } 1428 { 1429 SI opval = temp1; 1430 * FLD (i_sr) = opval; 1431 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1432 } 1433 } 1434 1435 #undef FLD 1436 } 1437 NEXT (vpc); 1438 1439 CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */ 1440 { 1441 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1442 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1443 #define FLD(f) abuf->fields.sfmt_ld24.f 1444 int UNUSED written = 0; 1445 IADDR UNUSED pc = abuf->addr; 1446 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1447 1448 { 1449 SI opval = FLD (i_uimm24); 1450 * FLD (i_dr) = opval; 1451 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1452 } 1453 1454 #undef FLD 1455 } 1456 NEXT (vpc); 1457 1458 CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */ 1459 { 1460 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1461 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1462 #define FLD(f) abuf->fields.sfmt_addi.f 1463 int UNUSED written = 0; 1464 IADDR UNUSED pc = abuf->addr; 1465 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1466 1467 { 1468 SI opval = FLD (f_simm8); 1469 * FLD (i_dr) = opval; 1470 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1471 } 1472 1473 #undef FLD 1474 } 1475 NEXT (vpc); 1476 1477 CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */ 1478 { 1479 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1480 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1481 #define FLD(f) abuf->fields.sfmt_add3.f 1482 int UNUSED written = 0; 1483 IADDR UNUSED pc = abuf->addr; 1484 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1485 1486 { 1487 SI opval = FLD (f_simm16); 1488 * FLD (i_dr) = opval; 1489 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1490 } 1491 1492 #undef FLD 1493 } 1494 NEXT (vpc); 1495 1496 CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */ 1497 { 1498 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1499 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1500 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1501 int UNUSED written = 0; 1502 IADDR UNUSED pc = abuf->addr; 1503 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1504 1505 { 1506 { 1507 BI opval = 1; 1508 CPU (h_lock) = opval; 1509 CGEN_TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); 1510 } 1511 { 1512 SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); 1513 * FLD (i_dr) = opval; 1514 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1515 } 1516 } 1517 1518 #undef FLD 1519 } 1520 NEXT (vpc); 1521 1522 CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */ 1523 { 1524 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1525 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1526 #define FLD(f) abuf->fields.sfmt_st_plus.f 1527 int UNUSED written = 0; 1528 IADDR UNUSED pc = abuf->addr; 1529 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1530 1531 { 1532 DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); 1533 SET_H_ACCUM (opval); 1534 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1535 } 1536 1537 #undef FLD 1538 } 1539 NEXT (vpc); 1540 1541 CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */ 1542 { 1543 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1544 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1545 #define FLD(f) abuf->fields.sfmt_st_plus.f 1546 int UNUSED written = 0; 1547 IADDR UNUSED pc = abuf->addr; 1548 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1549 1550 { 1551 DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); 1552 SET_H_ACCUM (opval); 1553 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1554 } 1555 1556 #undef FLD 1557 } 1558 NEXT (vpc); 1559 1560 CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */ 1561 { 1562 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1563 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1564 #define FLD(f) abuf->fields.sfmt_st_plus.f 1565 int UNUSED written = 0; 1566 IADDR UNUSED pc = abuf->addr; 1567 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1568 1569 { 1570 DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); 1571 SET_H_ACCUM (opval); 1572 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1573 } 1574 1575 #undef FLD 1576 } 1577 NEXT (vpc); 1578 1579 CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */ 1580 { 1581 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1582 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1583 #define FLD(f) abuf->fields.sfmt_st_plus.f 1584 int UNUSED written = 0; 1585 IADDR UNUSED pc = abuf->addr; 1586 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1587 1588 { 1589 DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); 1590 SET_H_ACCUM (opval); 1591 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1592 } 1593 1594 #undef FLD 1595 } 1596 NEXT (vpc); 1597 1598 CASE (sem, INSN_MUL) : /* mul $dr,$sr */ 1599 { 1600 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1601 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1602 #define FLD(f) abuf->fields.sfmt_add.f 1603 int UNUSED written = 0; 1604 IADDR UNUSED pc = abuf->addr; 1605 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1606 1607 { 1608 SI opval = MULSI (* FLD (i_dr), * FLD (i_sr)); 1609 * FLD (i_dr) = opval; 1610 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1611 } 1612 1613 #undef FLD 1614 } 1615 NEXT (vpc); 1616 1617 CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */ 1618 { 1619 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1620 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1621 #define FLD(f) abuf->fields.sfmt_st_plus.f 1622 int UNUSED written = 0; 1623 IADDR UNUSED pc = abuf->addr; 1624 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1625 1626 { 1627 DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); 1628 SET_H_ACCUM (opval); 1629 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1630 } 1631 1632 #undef FLD 1633 } 1634 NEXT (vpc); 1635 1636 CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */ 1637 { 1638 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1639 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1640 #define FLD(f) abuf->fields.sfmt_st_plus.f 1641 int UNUSED written = 0; 1642 IADDR UNUSED pc = abuf->addr; 1643 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1644 1645 { 1646 DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); 1647 SET_H_ACCUM (opval); 1648 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1649 } 1650 1651 #undef FLD 1652 } 1653 NEXT (vpc); 1654 1655 CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */ 1656 { 1657 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1658 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1659 #define FLD(f) abuf->fields.sfmt_st_plus.f 1660 int UNUSED written = 0; 1661 IADDR UNUSED pc = abuf->addr; 1662 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1663 1664 { 1665 DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8); 1666 SET_H_ACCUM (opval); 1667 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1668 } 1669 1670 #undef FLD 1671 } 1672 NEXT (vpc); 1673 1674 CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */ 1675 { 1676 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1677 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1678 #define FLD(f) abuf->fields.sfmt_st_plus.f 1679 int UNUSED written = 0; 1680 IADDR UNUSED pc = abuf->addr; 1681 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1682 1683 { 1684 DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8); 1685 SET_H_ACCUM (opval); 1686 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1687 } 1688 1689 #undef FLD 1690 } 1691 NEXT (vpc); 1692 1693 CASE (sem, INSN_MV) : /* mv $dr,$sr */ 1694 { 1695 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1696 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1697 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1698 int UNUSED written = 0; 1699 IADDR UNUSED pc = abuf->addr; 1700 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1701 1702 { 1703 SI opval = * FLD (i_sr); 1704 * FLD (i_dr) = opval; 1705 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1706 } 1707 1708 #undef FLD 1709 } 1710 NEXT (vpc); 1711 1712 CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */ 1713 { 1714 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1715 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1716 #define FLD(f) abuf->fields.sfmt_seth.f 1717 int UNUSED written = 0; 1718 IADDR UNUSED pc = abuf->addr; 1719 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1720 1721 { 1722 SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32)); 1723 * FLD (i_dr) = opval; 1724 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1725 } 1726 1727 #undef FLD 1728 } 1729 NEXT (vpc); 1730 1731 CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */ 1732 { 1733 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1734 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1735 #define FLD(f) abuf->fields.sfmt_seth.f 1736 int UNUSED written = 0; 1737 IADDR UNUSED pc = abuf->addr; 1738 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1739 1740 { 1741 SI opval = TRUNCDISI (GET_H_ACCUM ()); 1742 * FLD (i_dr) = opval; 1743 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1744 } 1745 1746 #undef FLD 1747 } 1748 NEXT (vpc); 1749 1750 CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */ 1751 { 1752 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1753 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1754 #define FLD(f) abuf->fields.sfmt_seth.f 1755 int UNUSED written = 0; 1756 IADDR UNUSED pc = abuf->addr; 1757 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1758 1759 { 1760 SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16)); 1761 * FLD (i_dr) = opval; 1762 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1763 } 1764 1765 #undef FLD 1766 } 1767 NEXT (vpc); 1768 1769 CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */ 1770 { 1771 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1772 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1773 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1774 int UNUSED written = 0; 1775 IADDR UNUSED pc = abuf->addr; 1776 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1777 1778 { 1779 SI opval = GET_H_CR (FLD (f_r2)); 1780 * FLD (i_dr) = opval; 1781 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1782 } 1783 1784 #undef FLD 1785 } 1786 NEXT (vpc); 1787 1788 CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */ 1789 { 1790 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1791 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1792 #define FLD(f) abuf->fields.sfmt_st_plus.f 1793 int UNUSED written = 0; 1794 IADDR UNUSED pc = abuf->addr; 1795 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1796 1797 { 1798 DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); 1799 SET_H_ACCUM (opval); 1800 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1801 } 1802 1803 #undef FLD 1804 } 1805 NEXT (vpc); 1806 1807 CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */ 1808 { 1809 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1810 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1811 #define FLD(f) abuf->fields.sfmt_st_plus.f 1812 int UNUSED written = 0; 1813 IADDR UNUSED pc = abuf->addr; 1814 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1815 1816 { 1817 DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); 1818 SET_H_ACCUM (opval); 1819 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1820 } 1821 1822 #undef FLD 1823 } 1824 NEXT (vpc); 1825 1826 CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */ 1827 { 1828 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1829 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1830 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1831 int UNUSED written = 0; 1832 IADDR UNUSED pc = abuf->addr; 1833 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1834 1835 { 1836 USI opval = * FLD (i_sr); 1837 SET_H_CR (FLD (f_r1), opval); 1838 CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); 1839 } 1840 1841 #undef FLD 1842 } 1843 NEXT (vpc); 1844 1845 CASE (sem, INSN_NEG) : /* neg $dr,$sr */ 1846 { 1847 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1848 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1849 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1850 int UNUSED written = 0; 1851 IADDR UNUSED pc = abuf->addr; 1852 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1853 1854 { 1855 SI opval = NEGSI (* FLD (i_sr)); 1856 * FLD (i_dr) = opval; 1857 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1858 } 1859 1860 #undef FLD 1861 } 1862 NEXT (vpc); 1863 1864 CASE (sem, INSN_NOP) : /* nop */ 1865 { 1866 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1867 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1868 #define FLD(f) abuf->fields.sfmt_empty.f 1869 int UNUSED written = 0; 1870 IADDR UNUSED pc = abuf->addr; 1871 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1872 1873 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); 1874 1875 #undef FLD 1876 } 1877 NEXT (vpc); 1878 1879 CASE (sem, INSN_NOT) : /* not $dr,$sr */ 1880 { 1881 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1882 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1883 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1884 int UNUSED written = 0; 1885 IADDR UNUSED pc = abuf->addr; 1886 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1887 1888 { 1889 SI opval = INVSI (* FLD (i_sr)); 1890 * FLD (i_dr) = opval; 1891 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1892 } 1893 1894 #undef FLD 1895 } 1896 NEXT (vpc); 1897 1898 CASE (sem, INSN_RAC) : /* rac */ 1899 { 1900 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1901 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1902 #define FLD(f) abuf->fields.sfmt_empty.f 1903 int UNUSED written = 0; 1904 IADDR UNUSED pc = abuf->addr; 1905 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1906 1907 { 1908 DI tmp_tmp1; 1909 tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1); 1910 tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); 1911 { 1912 DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); 1913 SET_H_ACCUM (opval); 1914 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1915 } 1916 } 1917 1918 #undef FLD 1919 } 1920 NEXT (vpc); 1921 1922 CASE (sem, INSN_RACH) : /* rach */ 1923 { 1924 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1925 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1926 #define FLD(f) abuf->fields.sfmt_empty.f 1927 int UNUSED written = 0; 1928 IADDR UNUSED pc = abuf->addr; 1929 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1930 1931 { 1932 DI tmp_tmp1; 1933 tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff)); 1934 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { 1935 tmp_tmp1 = MAKEDI (16383, 0x80000000); 1936 } else { 1937 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) { 1938 tmp_tmp1 = MAKEDI (16760832, 0); 1939 } else { 1940 tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000)); 1941 } 1942 } 1943 tmp_tmp1 = SLLDI (tmp_tmp1, 1); 1944 { 1945 DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7); 1946 SET_H_ACCUM (opval); 1947 CGEN_TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); 1948 } 1949 } 1950 1951 #undef FLD 1952 } 1953 NEXT (vpc); 1954 1955 CASE (sem, INSN_RTE) : /* rte */ 1956 { 1957 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1958 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1959 #define FLD(f) abuf->fields.sfmt_empty.f 1960 int UNUSED written = 0; 1961 IADDR UNUSED pc = abuf->addr; 1962 SEM_BRANCH_INIT 1963 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1964 1965 { 1966 { 1967 USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); 1968 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 1969 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 1970 } 1971 { 1972 USI opval = GET_H_CR (((UINT) 14)); 1973 SET_H_CR (((UINT) 6), opval); 1974 CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); 1975 } 1976 { 1977 UQI opval = CPU (h_bpsw); 1978 SET_H_PSW (opval); 1979 CGEN_TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); 1980 } 1981 { 1982 UQI opval = CPU (h_bbpsw); 1983 CPU (h_bpsw) = opval; 1984 CGEN_TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); 1985 } 1986 } 1987 1988 SEM_BRANCH_FINI (vpc); 1989 #undef FLD 1990 } 1991 NEXT (vpc); 1992 1993 CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */ 1994 { 1995 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1996 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1997 #define FLD(f) abuf->fields.sfmt_seth.f 1998 int UNUSED written = 0; 1999 IADDR UNUSED pc = abuf->addr; 2000 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2001 2002 { 2003 SI opval = SLLSI (FLD (f_hi16), 16); 2004 * FLD (i_dr) = opval; 2005 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2006 } 2007 2008 #undef FLD 2009 } 2010 NEXT (vpc); 2011 2012 CASE (sem, INSN_SLL) : /* sll $dr,$sr */ 2013 { 2014 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2015 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2016 #define FLD(f) abuf->fields.sfmt_add.f 2017 int UNUSED written = 0; 2018 IADDR UNUSED pc = abuf->addr; 2019 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2020 2021 { 2022 SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); 2023 * FLD (i_dr) = opval; 2024 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2025 } 2026 2027 #undef FLD 2028 } 2029 NEXT (vpc); 2030 2031 CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */ 2032 { 2033 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2034 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2035 #define FLD(f) abuf->fields.sfmt_add3.f 2036 int UNUSED written = 0; 2037 IADDR UNUSED pc = abuf->addr; 2038 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2039 2040 { 2041 SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); 2042 * FLD (i_dr) = opval; 2043 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2044 } 2045 2046 #undef FLD 2047 } 2048 NEXT (vpc); 2049 2050 CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */ 2051 { 2052 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2053 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2054 #define FLD(f) abuf->fields.sfmt_slli.f 2055 int UNUSED written = 0; 2056 IADDR UNUSED pc = abuf->addr; 2057 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2058 2059 { 2060 SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5)); 2061 * FLD (i_dr) = opval; 2062 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2063 } 2064 2065 #undef FLD 2066 } 2067 NEXT (vpc); 2068 2069 CASE (sem, INSN_SRA) : /* sra $dr,$sr */ 2070 { 2071 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2072 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2073 #define FLD(f) abuf->fields.sfmt_add.f 2074 int UNUSED written = 0; 2075 IADDR UNUSED pc = abuf->addr; 2076 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2077 2078 { 2079 SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); 2080 * FLD (i_dr) = opval; 2081 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2082 } 2083 2084 #undef FLD 2085 } 2086 NEXT (vpc); 2087 2088 CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */ 2089 { 2090 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2091 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2092 #define FLD(f) abuf->fields.sfmt_add3.f 2093 int UNUSED written = 0; 2094 IADDR UNUSED pc = abuf->addr; 2095 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2096 2097 { 2098 SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); 2099 * FLD (i_dr) = opval; 2100 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2101 } 2102 2103 #undef FLD 2104 } 2105 NEXT (vpc); 2106 2107 CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */ 2108 { 2109 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2110 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2111 #define FLD(f) abuf->fields.sfmt_slli.f 2112 int UNUSED written = 0; 2113 IADDR UNUSED pc = abuf->addr; 2114 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2115 2116 { 2117 SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5)); 2118 * FLD (i_dr) = opval; 2119 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2120 } 2121 2122 #undef FLD 2123 } 2124 NEXT (vpc); 2125 2126 CASE (sem, INSN_SRL) : /* srl $dr,$sr */ 2127 { 2128 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2129 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2130 #define FLD(f) abuf->fields.sfmt_add.f 2131 int UNUSED written = 0; 2132 IADDR UNUSED pc = abuf->addr; 2133 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2134 2135 { 2136 SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31)); 2137 * FLD (i_dr) = opval; 2138 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2139 } 2140 2141 #undef FLD 2142 } 2143 NEXT (vpc); 2144 2145 CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */ 2146 { 2147 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2148 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2149 #define FLD(f) abuf->fields.sfmt_add3.f 2150 int UNUSED written = 0; 2151 IADDR UNUSED pc = abuf->addr; 2152 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2153 2154 { 2155 SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31)); 2156 * FLD (i_dr) = opval; 2157 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2158 } 2159 2160 #undef FLD 2161 } 2162 NEXT (vpc); 2163 2164 CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */ 2165 { 2166 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2167 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2168 #define FLD(f) abuf->fields.sfmt_slli.f 2169 int UNUSED written = 0; 2170 IADDR UNUSED pc = abuf->addr; 2171 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2172 2173 { 2174 SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5)); 2175 * FLD (i_dr) = opval; 2176 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2177 } 2178 2179 #undef FLD 2180 } 2181 NEXT (vpc); 2182 2183 CASE (sem, INSN_ST) : /* st $src1,@$src2 */ 2184 { 2185 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2186 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2187 #define FLD(f) abuf->fields.sfmt_st_plus.f 2188 int UNUSED written = 0; 2189 IADDR UNUSED pc = abuf->addr; 2190 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2191 2192 { 2193 SI opval = * FLD (i_src1); 2194 SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); 2195 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2196 } 2197 2198 #undef FLD 2199 } 2200 NEXT (vpc); 2201 2202 CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */ 2203 { 2204 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2205 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2206 #define FLD(f) abuf->fields.sfmt_st_d.f 2207 int UNUSED written = 0; 2208 IADDR UNUSED pc = abuf->addr; 2209 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2210 2211 { 2212 SI opval = * FLD (i_src1); 2213 SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); 2214 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2215 } 2216 2217 #undef FLD 2218 } 2219 NEXT (vpc); 2220 2221 CASE (sem, INSN_STB) : /* stb $src1,@$src2 */ 2222 { 2223 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2224 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2225 #define FLD(f) abuf->fields.sfmt_st_plus.f 2226 int UNUSED written = 0; 2227 IADDR UNUSED pc = abuf->addr; 2228 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2229 2230 { 2231 QI opval = * FLD (i_src1); 2232 SETMEMQI (current_cpu, pc, * FLD (i_src2), opval); 2233 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2234 } 2235 2236 #undef FLD 2237 } 2238 NEXT (vpc); 2239 2240 CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */ 2241 { 2242 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2243 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2244 #define FLD(f) abuf->fields.sfmt_st_d.f 2245 int UNUSED written = 0; 2246 IADDR UNUSED pc = abuf->addr; 2247 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2248 2249 { 2250 QI opval = * FLD (i_src1); 2251 SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); 2252 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2253 } 2254 2255 #undef FLD 2256 } 2257 NEXT (vpc); 2258 2259 CASE (sem, INSN_STH) : /* sth $src1,@$src2 */ 2260 { 2261 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2262 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2263 #define FLD(f) abuf->fields.sfmt_st_plus.f 2264 int UNUSED written = 0; 2265 IADDR UNUSED pc = abuf->addr; 2266 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2267 2268 { 2269 HI opval = * FLD (i_src1); 2270 SETMEMHI (current_cpu, pc, * FLD (i_src2), opval); 2271 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2272 } 2273 2274 #undef FLD 2275 } 2276 NEXT (vpc); 2277 2278 CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */ 2279 { 2280 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2281 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2282 #define FLD(f) abuf->fields.sfmt_st_d.f 2283 int UNUSED written = 0; 2284 IADDR UNUSED pc = abuf->addr; 2285 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2286 2287 { 2288 HI opval = * FLD (i_src1); 2289 SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); 2290 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2291 } 2292 2293 #undef FLD 2294 } 2295 NEXT (vpc); 2296 2297 CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */ 2298 { 2299 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2300 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2301 #define FLD(f) abuf->fields.sfmt_st_plus.f 2302 int UNUSED written = 0; 2303 IADDR UNUSED pc = abuf->addr; 2304 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2305 2306 { 2307 SI tmp_new_src2; 2308 tmp_new_src2 = ADDSI (* FLD (i_src2), 4); 2309 { 2310 SI opval = * FLD (i_src1); 2311 SETMEMSI (current_cpu, pc, tmp_new_src2, opval); 2312 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2313 } 2314 { 2315 SI opval = tmp_new_src2; 2316 * FLD (i_src2) = opval; 2317 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2318 } 2319 } 2320 2321 #undef FLD 2322 } 2323 NEXT (vpc); 2324 2325 CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */ 2326 { 2327 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2328 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2329 #define FLD(f) abuf->fields.sfmt_st_plus.f 2330 int UNUSED written = 0; 2331 IADDR UNUSED pc = abuf->addr; 2332 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2333 2334 { 2335 SI tmp_new_src2; 2336 tmp_new_src2 = SUBSI (* FLD (i_src2), 4); 2337 { 2338 SI opval = * FLD (i_src1); 2339 SETMEMSI (current_cpu, pc, tmp_new_src2, opval); 2340 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2341 } 2342 { 2343 SI opval = tmp_new_src2; 2344 * FLD (i_src2) = opval; 2345 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2346 } 2347 } 2348 2349 #undef FLD 2350 } 2351 NEXT (vpc); 2352 2353 CASE (sem, INSN_SUB) : /* sub $dr,$sr */ 2354 { 2355 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2356 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2357 #define FLD(f) abuf->fields.sfmt_add.f 2358 int UNUSED written = 0; 2359 IADDR UNUSED pc = abuf->addr; 2360 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2361 2362 { 2363 SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr)); 2364 * FLD (i_dr) = opval; 2365 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2366 } 2367 2368 #undef FLD 2369 } 2370 NEXT (vpc); 2371 2372 CASE (sem, INSN_SUBV) : /* subv $dr,$sr */ 2373 { 2374 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2375 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2376 #define FLD(f) abuf->fields.sfmt_add.f 2377 int UNUSED written = 0; 2378 IADDR UNUSED pc = abuf->addr; 2379 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2380 2381 { 2382 SI temp0;BI temp1; 2383 temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); 2384 temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); 2385 { 2386 SI opval = temp0; 2387 * FLD (i_dr) = opval; 2388 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2389 } 2390 { 2391 BI opval = temp1; 2392 CPU (h_cond) = opval; 2393 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 2394 } 2395 } 2396 2397 #undef FLD 2398 } 2399 NEXT (vpc); 2400 2401 CASE (sem, INSN_SUBX) : /* subx $dr,$sr */ 2402 { 2403 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2404 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2405 #define FLD(f) abuf->fields.sfmt_add.f 2406 int UNUSED written = 0; 2407 IADDR UNUSED pc = abuf->addr; 2408 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2409 2410 { 2411 SI temp0;BI temp1; 2412 temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); 2413 temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); 2414 { 2415 SI opval = temp0; 2416 * FLD (i_dr) = opval; 2417 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2418 } 2419 { 2420 BI opval = temp1; 2421 CPU (h_cond) = opval; 2422 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 2423 } 2424 } 2425 2426 #undef FLD 2427 } 2428 NEXT (vpc); 2429 2430 CASE (sem, INSN_TRAP) : /* trap $uimm4 */ 2431 { 2432 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2433 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2434 #define FLD(f) abuf->fields.sfmt_trap.f 2435 int UNUSED written = 0; 2436 IADDR UNUSED pc = abuf->addr; 2437 SEM_BRANCH_INIT 2438 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2439 2440 { 2441 { 2442 USI opval = GET_H_CR (((UINT) 6)); 2443 SET_H_CR (((UINT) 14), opval); 2444 CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); 2445 } 2446 { 2447 USI opval = ADDSI (pc, 4); 2448 SET_H_CR (((UINT) 6), opval); 2449 CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); 2450 } 2451 { 2452 UQI opval = CPU (h_bpsw); 2453 CPU (h_bbpsw) = opval; 2454 CGEN_TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); 2455 } 2456 { 2457 UQI opval = GET_H_PSW (); 2458 CPU (h_bpsw) = opval; 2459 CGEN_TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); 2460 } 2461 { 2462 UQI opval = ANDQI (GET_H_PSW (), 128); 2463 SET_H_PSW (opval); 2464 CGEN_TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); 2465 } 2466 { 2467 SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); 2468 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 2469 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 2470 } 2471 } 2472 2473 SEM_BRANCH_FINI (vpc); 2474 #undef FLD 2475 } 2476 NEXT (vpc); 2477 2478 CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */ 2479 { 2480 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2481 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2482 #define FLD(f) abuf->fields.sfmt_st_plus.f 2483 int UNUSED written = 0; 2484 IADDR UNUSED pc = abuf->addr; 2485 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2486 2487 { 2488 if (CPU (h_lock)) { 2489 { 2490 SI opval = * FLD (i_src1); 2491 SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); 2492 written |= (1 << 4); 2493 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2494 } 2495 } 2496 { 2497 BI opval = 0; 2498 CPU (h_lock) = opval; 2499 CGEN_TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); 2500 } 2501 } 2502 2503 abuf->written = written; 2504 #undef FLD 2505 } 2506 NEXT (vpc); 2507 2508 CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */ 2509 { 2510 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2511 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2512 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2513 int UNUSED written = 0; 2514 IADDR UNUSED pc = abuf->addr; 2515 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2516 2517 { 2518 USI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (ZEXTQISI (INVQI (FLD (f_uimm8))), 65280)); 2519 SET_H_CR (((UINT) 0), opval); 2520 CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); 2521 } 2522 2523 #undef FLD 2524 } 2525 NEXT (vpc); 2526 2527 CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */ 2528 { 2529 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2530 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2531 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2532 int UNUSED written = 0; 2533 IADDR UNUSED pc = abuf->addr; 2534 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2535 2536 { 2537 USI opval = FLD (f_uimm8); 2538 SET_H_CR (((UINT) 0), opval); 2539 CGEN_TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval); 2540 } 2541 2542 #undef FLD 2543 } 2544 NEXT (vpc); 2545 2546 CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */ 2547 { 2548 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2549 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2550 #define FLD(f) abuf->fields.sfmt_bset.f 2551 int UNUSED written = 0; 2552 IADDR UNUSED pc = abuf->addr; 2553 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2554 2555 { 2556 QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLQI (1, SUBSI (7, FLD (f_uimm3)))); 2557 SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval); 2558 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2559 } 2560 2561 #undef FLD 2562 } 2563 NEXT (vpc); 2564 2565 CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */ 2566 { 2567 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2568 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2569 #define FLD(f) abuf->fields.sfmt_bset.f 2570 int UNUSED written = 0; 2571 IADDR UNUSED pc = abuf->addr; 2572 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2573 2574 { 2575 QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLQI (1, SUBSI (7, FLD (f_uimm3))))); 2576 SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval); 2577 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 2578 } 2579 2580 #undef FLD 2581 } 2582 NEXT (vpc); 2583 2584 CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */ 2585 { 2586 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2587 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2588 #define FLD(f) abuf->fields.sfmt_bset.f 2589 int UNUSED written = 0; 2590 IADDR UNUSED pc = abuf->addr; 2591 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2592 2593 { 2594 BI opval = ANDQI (SRLQI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1); 2595 CPU (h_cond) = opval; 2596 CGEN_TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval); 2597 } 2598 2599 #undef FLD 2600 } 2601 NEXT (vpc); 2602 2603 2604 } 2605 ENDSWITCH (sem) /* End of semantic switch. */ 2606 2607 /* At this point `vpc' contains the next insn to execute. */ 2608 } 2609 2610 #undef DEFINE_SWITCH 2611 #endif /* DEFINE_SWITCH */ 2612