1 /* Simulator instruction decoder for m32rxf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2024 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #define WANT_CPU m32rxf 26 #define WANT_CPU_M32RXF 27 28 #include "sim-main.h" 29 #include "sim-assert.h" 30 #include "cgen-mem.h" 31 #include "cgen-ops.h" 32 33 /* Insn can't be executed in parallel. 34 Or is that "do NOt Pass to Air defense Radar"? :-) */ 35 #define NOPAR (-1) 36 37 /* The instruction descriptor array. 38 This is computed at runtime. Space for it is not malloc'd to save a 39 teensy bit of cpu in the decoder. Moving it to malloc space is trivial 40 but won't be done until necessary (we don't currently support the runtime 41 addition of instructions nor an SMP machine with different cpus). */ 42 static IDESC m32rxf_insn_data[M32RXF_INSN__MAX]; 43 44 /* Commas between elements are contained in the macros. 45 Some of these are conditionally compiled out. */ 46 47 static const struct insn_sem m32rxf_insn_sem[] = 48 { 49 { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 50 { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 51 { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 52 { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 53 { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 54 { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR }, 55 { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD }, 56 { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR }, 57 { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND }, 58 { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, 59 { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR }, 60 { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR }, 61 { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR }, 62 { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR }, 63 { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI }, 64 { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV }, 65 { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR }, 66 { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX }, 67 { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 }, 68 { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, 69 { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, 70 { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 71 { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 72 { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 73 { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 74 { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 75 { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR }, 76 { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 }, 77 { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR }, 78 { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 }, 79 { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, 80 { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 }, 81 { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR }, 82 { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR }, 83 { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 }, 84 { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR }, 85 { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 }, 86 { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR }, 87 { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP }, 88 { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, 89 { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU }, 90 { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR }, 91 { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ }, 92 { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ }, 93 { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 94 { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 95 { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 96 { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 97 { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR }, 98 { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC }, 99 { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC }, 100 { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL }, 101 { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP }, 102 { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD }, 103 { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR }, 104 { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB }, 105 { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR }, 106 { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH }, 107 { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR }, 108 { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB }, 109 { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR }, 110 { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH }, 111 { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR }, 112 { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS }, 113 { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR }, 114 { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 }, 115 { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR }, 116 { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK }, 117 { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A }, 118 { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A }, 119 { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A }, 120 { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A }, 121 { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL }, 122 { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A }, 123 { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A }, 124 { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A }, 125 { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A }, 126 { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV }, 127 { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A }, 128 { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A }, 129 { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A }, 130 { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC }, 131 { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A }, 132 { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A }, 133 { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC }, 134 { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG }, 135 { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP }, 136 { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT }, 137 { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI }, 138 { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI }, 139 { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE }, 140 { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR }, 141 { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL }, 142 { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, 143 { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI }, 144 { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA }, 145 { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, 146 { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI }, 147 { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL }, 148 { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR }, 149 { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI }, 150 { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST }, 151 { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR }, 152 { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB }, 153 { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR }, 154 { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH }, 155 { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR }, 156 { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS }, 157 { M32R_INSN_STH_PLUS, M32RXF_INSN_STH_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS }, 158 { M32R_INSN_STB_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS }, 159 { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS }, 160 { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB }, 161 { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV }, 162 { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX }, 163 { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP }, 164 { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK }, 165 { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR }, 166 { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR }, 167 { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR }, 168 { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ }, 169 { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD }, 170 { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 }, 171 { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO }, 172 { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 }, 173 { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 }, 174 { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC }, 175 { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC }, 176 { M32R_INSN_CLRPSW, M32RXF_INSN_CLRPSW, M32RXF_SFMT_CLRPSW, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW }, 177 { M32R_INSN_SETPSW, M32RXF_INSN_SETPSW, M32RXF_SFMT_SETPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW }, 178 { M32R_INSN_BSET, M32RXF_INSN_BSET, M32RXF_SFMT_BSET, NOPAR, NOPAR }, 179 { M32R_INSN_BCLR, M32RXF_INSN_BCLR, M32RXF_SFMT_BSET, NOPAR, NOPAR }, 180 { M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST }, 181 }; 182 183 static const struct insn_sem m32rxf_insn_sem_invalid = 184 { 185 VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR 186 }; 187 188 /* Initialize an IDESC from the compile-time computable parts. */ 189 190 static INLINE void 191 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 192 { 193 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; 194 195 id->num = t->index; 196 id->sfmt = t->sfmt; 197 if ((int) t->type <= 0) 198 id->idata = & cgen_virtual_insn_table[- (int) t->type]; 199 else 200 id->idata = & insn_table[t->type]; 201 id->attrs = CGEN_INSN_ATTRS (id->idata); 202 /* Oh my god, a magic number. */ 203 id->length = CGEN_INSN_BITSIZE (id->idata) / 8; 204 205 #if WITH_PROFILE_MODEL_P 206 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; 207 { 208 SIM_DESC sd = CPU_STATE (cpu); 209 SIM_ASSERT (t->index == id->timing->num); 210 } 211 #endif 212 213 /* Semantic pointers are initialized elsewhere. */ 214 } 215 216 /* Initialize the instruction descriptor table. */ 217 218 void 219 m32rxf_init_idesc_table (SIM_CPU *cpu) 220 { 221 IDESC *id,*tabend; 222 const struct insn_sem *t,*tend; 223 int tabsize = M32RXF_INSN__MAX; 224 IDESC *table = m32rxf_insn_data; 225 226 memset (table, 0, tabsize * sizeof (IDESC)); 227 228 /* First set all entries to the `invalid insn'. */ 229 t = & m32rxf_insn_sem_invalid; 230 for (id = table, tabend = table + tabsize; id < tabend; ++id) 231 init_idesc (cpu, id, t); 232 233 /* Now fill in the values for the chosen cpu. */ 234 for (t = m32rxf_insn_sem, tend = t + ARRAY_SIZE (m32rxf_insn_sem); 235 t != tend; ++t) 236 { 237 init_idesc (cpu, & table[t->index], t); 238 if (t->par_index != NOPAR) 239 { 240 init_idesc (cpu, &table[t->par_index], t); 241 table[t->index].par_idesc = &table[t->par_index]; 242 } 243 if (t->par_index != NOPAR) 244 { 245 init_idesc (cpu, &table[t->write_index], t); 246 table[t->par_index].par_idesc = &table[t->write_index]; 247 } 248 } 249 250 /* Link the IDESC table into the cpu. */ 251 CPU_IDESC (cpu) = table; 252 } 253 254 /* Given an instruction, return a pointer to its IDESC entry. */ 255 256 const IDESC * 257 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, 258 CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, 259 ARGBUF *abuf) 260 { 261 /* Result of decoder. */ 262 M32RXF_INSN_TYPE itype; 263 264 { 265 CGEN_INSN_WORD insn = base_insn; 266 267 { 268 unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); 269 switch (val0) 270 { 271 case 0: itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv; 272 case 1: itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx; 273 case 2: itype = M32RXF_INSN_SUB; goto extract_sfmt_add; 274 case 3: itype = M32RXF_INSN_NEG; goto extract_sfmt_mv; 275 case 4: itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp; 276 case 5: itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp; 277 case 6: itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp; 278 case 7: 279 { 280 unsigned int val1 = (((insn >> 8) & (3 << 0))); 281 switch (val1) 282 { 283 case 0: 284 if ((entire_insn & 0xfff0) == 0x70) 285 { itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; } 286 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 287 case 3: 288 if ((entire_insn & 0xfff0) == 0x370) 289 { itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; } 290 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 291 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 292 } 293 } 294 case 8: itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv; 295 case 9: itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx; 296 case 10: itype = M32RXF_INSN_ADD; goto extract_sfmt_add; 297 case 11: itype = M32RXF_INSN_NOT; goto extract_sfmt_mv; 298 case 12: itype = M32RXF_INSN_AND; goto extract_sfmt_add; 299 case 13: itype = M32RXF_INSN_XOR; goto extract_sfmt_add; 300 case 14: itype = M32RXF_INSN_OR; goto extract_sfmt_add; 301 case 15: 302 if ((entire_insn & 0xf8f0) == 0xf0) 303 { itype = M32RXF_INSN_BTST; goto extract_sfmt_btst; } 304 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 305 case 16: itype = M32RXF_INSN_SRL; goto extract_sfmt_add; 306 case 18: itype = M32RXF_INSN_SRA; goto extract_sfmt_add; 307 case 20: itype = M32RXF_INSN_SLL; goto extract_sfmt_add; 308 case 22: itype = M32RXF_INSN_MUL; goto extract_sfmt_add; 309 case 24: itype = M32RXF_INSN_MV; goto extract_sfmt_mv; 310 case 25: itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc; 311 case 26: itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc; 312 case 28: 313 { 314 unsigned int val1 = (((insn >> 8) & (3 << 0))); 315 switch (val1) 316 { 317 case 0: 318 if ((entire_insn & 0xfff0) == 0x1cc0) 319 { itype = M32RXF_INSN_JC; goto extract_sfmt_jc; } 320 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 321 case 1: 322 if ((entire_insn & 0xfff0) == 0x1dc0) 323 { itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; } 324 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 325 case 2: 326 if ((entire_insn & 0xfff0) == 0x1ec0) 327 { itype = M32RXF_INSN_JL; goto extract_sfmt_jl; } 328 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 329 case 3: 330 if ((entire_insn & 0xfff0) == 0x1fc0) 331 { itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; } 332 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 333 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 334 } 335 } 336 case 29: 337 if ((entire_insn & 0xffff) == 0x10d6) 338 { itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; } 339 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 340 case 31: 341 if ((entire_insn & 0xfff0) == 0x10f0) 342 { itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; } 343 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 344 case 32: itype = M32RXF_INSN_STB; goto extract_sfmt_stb; 345 case 33: itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus; 346 case 34: itype = M32RXF_INSN_STH; goto extract_sfmt_sth; 347 case 35: itype = M32RXF_INSN_STH_PLUS; goto extract_sfmt_sth_plus; 348 case 36: itype = M32RXF_INSN_ST; goto extract_sfmt_st; 349 case 37: itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock; 350 case 38: itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus; 351 case 39: itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus; 352 case 40: itype = M32RXF_INSN_LDB; goto extract_sfmt_ldb; 353 case 41: itype = M32RXF_INSN_LDUB; goto extract_sfmt_ldb; 354 case 42: itype = M32RXF_INSN_LDH; goto extract_sfmt_ldh; 355 case 43: itype = M32RXF_INSN_LDUH; goto extract_sfmt_ldh; 356 case 44: itype = M32RXF_INSN_LD; goto extract_sfmt_ld; 357 case 45: itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock; 358 case 46: itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; 359 case 48: 360 case 56: itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a; 361 case 49: 362 case 57: itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a; 363 case 50: 364 case 58: itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a; 365 case 51: 366 case 59: itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a; 367 case 52: 368 case 60: itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a; 369 case 53: 370 case 61: itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a; 371 case 54: 372 case 62: itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a; 373 case 55: 374 case 63: itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a; 375 case 64: 376 case 65: 377 case 66: 378 case 67: 379 case 68: 380 case 69: 381 case 70: 382 case 71: 383 case 72: 384 case 73: 385 case 74: 386 case 75: 387 case 76: 388 case 77: 389 case 78: 390 case 79: itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi; 391 case 80: 392 case 81: itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli; 393 case 82: 394 case 83: itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli; 395 case 84: 396 case 85: itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli; 397 case 87: 398 { 399 unsigned int val1 = (((insn >> 0) & (1 << 0))); 400 switch (val1) 401 { 402 case 0: 403 if ((entire_insn & 0xf0f3) == 0x5070) 404 { itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; } 405 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 406 case 1: 407 if ((entire_insn & 0xf0f3) == 0x5071) 408 { itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; } 409 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 410 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 411 } 412 } 413 case 88: 414 if ((entire_insn & 0xf3f2) == 0x5080) 415 { itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; } 416 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 417 case 89: 418 if ((entire_insn & 0xf3f2) == 0x5090) 419 { itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; } 420 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 421 case 90: itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1; 422 case 91: itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1; 423 case 92: itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1; 424 case 93: itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo; 425 case 94: 426 if ((entire_insn & 0xffff) == 0x50e4) 427 { itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; } 428 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 429 case 95: 430 { 431 unsigned int val1 = (((insn >> 0) & (3 << 0))); 432 switch (val1) 433 { 434 case 0: itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; 435 case 1: itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; 436 case 2: itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a; 437 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 438 } 439 } 440 case 96: 441 case 97: 442 case 98: 443 case 99: 444 case 100: 445 case 101: 446 case 102: 447 case 103: 448 case 104: 449 case 105: 450 case 106: 451 case 107: 452 case 108: 453 case 109: 454 case 110: 455 case 111: itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8; 456 case 112: 457 { 458 unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); 459 switch (val1) 460 { 461 case 0: 462 if ((entire_insn & 0xffff) == 0x7000) 463 { itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; } 464 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 465 case 2: 466 case 3: itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; 467 case 4: 468 case 5: itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; 469 case 9: 470 if ((entire_insn & 0xffff) == 0x7401) 471 { itype = M32RXF_INSN_SC; goto extract_sfmt_sc; } 472 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 473 case 11: 474 if ((entire_insn & 0xffff) == 0x7501) 475 { itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; } 476 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 477 case 16: 478 case 17: itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; 479 case 18: 480 case 19: itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; 481 case 24: 482 case 25: itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; 483 case 26: 484 case 27: itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; 485 case 28: 486 case 29: itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; 487 case 30: 488 case 31: itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; 489 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 490 } 491 } 492 case 113: 493 case 114: 494 case 115: 495 case 116: 496 case 117: 497 case 118: 498 case 119: 499 case 120: 500 case 121: 501 case 122: 502 case 123: 503 case 124: 504 case 125: 505 case 126: 506 case 127: 507 { 508 unsigned int val1 = (((insn >> 8) & (15 << 0))); 509 switch (val1) 510 { 511 case 1: itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; 512 case 2: itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; 513 case 8: itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8; 514 case 9: itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8; 515 case 12: itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8; 516 case 13: itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8; 517 case 14: itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8; 518 case 15: itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8; 519 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 520 } 521 } 522 case 132: 523 if ((entire_insn & 0xfff00000) == 0x80400000) 524 { itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; } 525 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 526 case 133: 527 if ((entire_insn & 0xfff00000) == 0x80500000) 528 { itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; } 529 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 530 case 134: 531 { 532 unsigned int val1 = (((entire_insn >> 8) & (3 << 0))); 533 switch (val1) 534 { 535 case 0: 536 if ((entire_insn & 0xf0f0ffff) == 0x80600000) 537 { itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; } 538 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 539 case 2: 540 if ((entire_insn & 0xf0f0ffff) == 0x80600200) 541 { itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; } 542 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 543 case 3: 544 if ((entire_insn & 0xf0f0ffff) == 0x80600300) 545 { itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; } 546 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 547 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 548 } 549 } 550 case 136: itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3; 551 case 138: itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3; 552 case 140: itype = M32RXF_INSN_AND3; goto extract_sfmt_and3; 553 case 141: itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3; 554 case 142: itype = M32RXF_INSN_OR3; goto extract_sfmt_or3; 555 case 144: 556 { 557 unsigned int val1 = (((entire_insn >> 4) & (1 << 0))); 558 switch (val1) 559 { 560 case 0: 561 if ((entire_insn & 0xf0f0ffff) == 0x90000000) 562 { itype = M32RXF_INSN_DIV; goto extract_sfmt_div; } 563 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 564 case 1: 565 if ((entire_insn & 0xf0f0ffff) == 0x90000010) 566 { itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; } 567 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 568 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 569 } 570 } 571 case 145: 572 if ((entire_insn & 0xf0f0ffff) == 0x90100000) 573 { itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; } 574 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 575 case 146: 576 if ((entire_insn & 0xf0f0ffff) == 0x90200000) 577 { itype = M32RXF_INSN_REM; goto extract_sfmt_div; } 578 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 579 case 147: 580 if ((entire_insn & 0xf0f0ffff) == 0x90300000) 581 { itype = M32RXF_INSN_REMU; goto extract_sfmt_div; } 582 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 583 case 152: itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3; 584 case 154: itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3; 585 case 156: itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3; 586 case 159: 587 if ((entire_insn & 0xf0ff0000) == 0x90f00000) 588 { itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; } 589 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 590 case 160: itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d; 591 case 162: itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d; 592 case 164: itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d; 593 case 166: 594 if ((entire_insn & 0xf8f00000) == 0xa0600000) 595 { itype = M32RXF_INSN_BSET; goto extract_sfmt_bset; } 596 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 597 case 167: 598 if ((entire_insn & 0xf8f00000) == 0xa0700000) 599 { itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset; } 600 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 601 case 168: itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d; 602 case 169: itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d; 603 case 170: itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d; 604 case 171: itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ldh_d; 605 case 172: itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d; 606 case 176: itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq; 607 case 177: itype = M32RXF_INSN_BNE; goto extract_sfmt_beq; 608 case 184: 609 if ((entire_insn & 0xfff00000) == 0xb0800000) 610 { itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; } 611 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 612 case 185: 613 if ((entire_insn & 0xfff00000) == 0xb0900000) 614 { itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; } 615 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 616 case 186: 617 if ((entire_insn & 0xfff00000) == 0xb0a00000) 618 { itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; } 619 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 620 case 187: 621 if ((entire_insn & 0xfff00000) == 0xb0b00000) 622 { itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; } 623 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 624 case 188: 625 if ((entire_insn & 0xfff00000) == 0xb0c00000) 626 { itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; } 627 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 628 case 189: 629 if ((entire_insn & 0xfff00000) == 0xb0d00000) 630 { itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; } 631 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 632 case 220: 633 if ((entire_insn & 0xf0ff0000) == 0xd0c00000) 634 { itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; } 635 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 636 case 224: 637 case 225: 638 case 226: 639 case 227: 640 case 228: 641 case 229: 642 case 230: 643 case 231: 644 case 232: 645 case 233: 646 case 234: 647 case 235: 648 case 236: 649 case 237: 650 case 238: 651 case 239: itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24; 652 case 240: 653 case 241: 654 case 242: 655 case 243: 656 case 244: 657 case 245: 658 case 246: 659 case 247: 660 case 248: 661 case 249: 662 case 250: 663 case 251: 664 case 252: 665 case 253: 666 case 254: 667 case 255: 668 { 669 unsigned int val1 = (((insn >> 8) & (7 << 0))); 670 switch (val1) 671 { 672 case 0: 673 if ((entire_insn & 0xff000000) == 0xf8000000) 674 { itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; } 675 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 676 case 1: 677 if ((entire_insn & 0xff000000) == 0xf9000000) 678 { itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; } 679 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 680 case 4: 681 if ((entire_insn & 0xff000000) == 0xfc000000) 682 { itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; } 683 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 684 case 5: 685 if ((entire_insn & 0xff000000) == 0xfd000000) 686 { itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; } 687 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 688 case 6: 689 if ((entire_insn & 0xff000000) == 0xfe000000) 690 { itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; } 691 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 692 case 7: 693 if ((entire_insn & 0xff000000) == 0xff000000) 694 { itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; } 695 itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 696 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 697 } 698 } 699 default: itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; 700 } 701 } 702 } 703 704 /* The instruction has been decoded, now extract the fields. */ 705 706 extract_sfmt_empty: 707 { 708 const IDESC *idesc = &m32rxf_insn_data[itype]; 709 #define FLD(f) abuf->fields.sfmt_empty.f 710 711 712 /* Record the fields for the semantic handler. */ 713 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); 714 715 #undef FLD 716 return idesc; 717 } 718 719 extract_sfmt_add: 720 { 721 const IDESC *idesc = &m32rxf_insn_data[itype]; 722 CGEN_INSN_WORD insn = entire_insn; 723 #define FLD(f) abuf->fields.sfmt_add.f 724 UINT f_r1; 725 UINT f_r2; 726 727 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 728 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 729 730 /* Record the fields for the semantic handler. */ 731 FLD (f_r1) = f_r1; 732 FLD (f_r2) = f_r2; 733 FLD (i_dr) = & CPU (h_gr)[f_r1]; 734 FLD (i_sr) = & CPU (h_gr)[f_r2]; 735 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 736 737 #if WITH_PROFILE_MODEL_P 738 /* Record the fields for profiling. */ 739 if (PROFILE_MODEL_P (current_cpu)) 740 { 741 FLD (in_dr) = f_r1; 742 FLD (in_sr) = f_r2; 743 FLD (out_dr) = f_r1; 744 } 745 #endif 746 #undef FLD 747 return idesc; 748 } 749 750 extract_sfmt_add3: 751 { 752 const IDESC *idesc = &m32rxf_insn_data[itype]; 753 CGEN_INSN_WORD insn = entire_insn; 754 #define FLD(f) abuf->fields.sfmt_add3.f 755 UINT f_r1; 756 UINT f_r2; 757 INT f_simm16; 758 759 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 760 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 761 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 762 763 /* Record the fields for the semantic handler. */ 764 FLD (f_simm16) = f_simm16; 765 FLD (f_r2) = f_r2; 766 FLD (f_r1) = f_r1; 767 FLD (i_sr) = & CPU (h_gr)[f_r2]; 768 FLD (i_dr) = & CPU (h_gr)[f_r1]; 769 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 770 771 #if WITH_PROFILE_MODEL_P 772 /* Record the fields for profiling. */ 773 if (PROFILE_MODEL_P (current_cpu)) 774 { 775 FLD (in_sr) = f_r2; 776 FLD (out_dr) = f_r1; 777 } 778 #endif 779 #undef FLD 780 return idesc; 781 } 782 783 extract_sfmt_and3: 784 { 785 const IDESC *idesc = &m32rxf_insn_data[itype]; 786 CGEN_INSN_WORD insn = entire_insn; 787 #define FLD(f) abuf->fields.sfmt_and3.f 788 UINT f_r1; 789 UINT f_r2; 790 UINT f_uimm16; 791 792 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 793 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 794 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 795 796 /* Record the fields for the semantic handler. */ 797 FLD (f_r2) = f_r2; 798 FLD (f_uimm16) = f_uimm16; 799 FLD (f_r1) = f_r1; 800 FLD (i_sr) = & CPU (h_gr)[f_r2]; 801 FLD (i_dr) = & CPU (h_gr)[f_r1]; 802 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 803 804 #if WITH_PROFILE_MODEL_P 805 /* Record the fields for profiling. */ 806 if (PROFILE_MODEL_P (current_cpu)) 807 { 808 FLD (in_sr) = f_r2; 809 FLD (out_dr) = f_r1; 810 } 811 #endif 812 #undef FLD 813 return idesc; 814 } 815 816 extract_sfmt_or3: 817 { 818 const IDESC *idesc = &m32rxf_insn_data[itype]; 819 CGEN_INSN_WORD insn = entire_insn; 820 #define FLD(f) abuf->fields.sfmt_and3.f 821 UINT f_r1; 822 UINT f_r2; 823 UINT f_uimm16; 824 825 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 826 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 827 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 828 829 /* Record the fields for the semantic handler. */ 830 FLD (f_r2) = f_r2; 831 FLD (f_uimm16) = f_uimm16; 832 FLD (f_r1) = f_r1; 833 FLD (i_sr) = & CPU (h_gr)[f_r2]; 834 FLD (i_dr) = & CPU (h_gr)[f_r1]; 835 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 836 837 #if WITH_PROFILE_MODEL_P 838 /* Record the fields for profiling. */ 839 if (PROFILE_MODEL_P (current_cpu)) 840 { 841 FLD (in_sr) = f_r2; 842 FLD (out_dr) = f_r1; 843 } 844 #endif 845 #undef FLD 846 return idesc; 847 } 848 849 extract_sfmt_addi: 850 { 851 const IDESC *idesc = &m32rxf_insn_data[itype]; 852 CGEN_INSN_WORD insn = entire_insn; 853 #define FLD(f) abuf->fields.sfmt_addi.f 854 UINT f_r1; 855 INT f_simm8; 856 857 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 858 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); 859 860 /* Record the fields for the semantic handler. */ 861 FLD (f_r1) = f_r1; 862 FLD (f_simm8) = f_simm8; 863 FLD (i_dr) = & CPU (h_gr)[f_r1]; 864 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); 865 866 #if WITH_PROFILE_MODEL_P 867 /* Record the fields for profiling. */ 868 if (PROFILE_MODEL_P (current_cpu)) 869 { 870 FLD (in_dr) = f_r1; 871 FLD (out_dr) = f_r1; 872 } 873 #endif 874 #undef FLD 875 return idesc; 876 } 877 878 extract_sfmt_addv: 879 { 880 const IDESC *idesc = &m32rxf_insn_data[itype]; 881 CGEN_INSN_WORD insn = entire_insn; 882 #define FLD(f) abuf->fields.sfmt_add.f 883 UINT f_r1; 884 UINT f_r2; 885 886 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 887 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 888 889 /* Record the fields for the semantic handler. */ 890 FLD (f_r1) = f_r1; 891 FLD (f_r2) = f_r2; 892 FLD (i_dr) = & CPU (h_gr)[f_r1]; 893 FLD (i_sr) = & CPU (h_gr)[f_r2]; 894 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 895 896 #if WITH_PROFILE_MODEL_P 897 /* Record the fields for profiling. */ 898 if (PROFILE_MODEL_P (current_cpu)) 899 { 900 FLD (in_dr) = f_r1; 901 FLD (in_sr) = f_r2; 902 FLD (out_dr) = f_r1; 903 } 904 #endif 905 #undef FLD 906 return idesc; 907 } 908 909 extract_sfmt_addv3: 910 { 911 const IDESC *idesc = &m32rxf_insn_data[itype]; 912 CGEN_INSN_WORD insn = entire_insn; 913 #define FLD(f) abuf->fields.sfmt_add3.f 914 UINT f_r1; 915 UINT f_r2; 916 INT f_simm16; 917 918 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 919 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 920 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 921 922 /* Record the fields for the semantic handler. */ 923 FLD (f_simm16) = f_simm16; 924 FLD (f_r2) = f_r2; 925 FLD (f_r1) = f_r1; 926 FLD (i_sr) = & CPU (h_gr)[f_r2]; 927 FLD (i_dr) = & CPU (h_gr)[f_r1]; 928 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 929 930 #if WITH_PROFILE_MODEL_P 931 /* Record the fields for profiling. */ 932 if (PROFILE_MODEL_P (current_cpu)) 933 { 934 FLD (in_sr) = f_r2; 935 FLD (out_dr) = f_r1; 936 } 937 #endif 938 #undef FLD 939 return idesc; 940 } 941 942 extract_sfmt_addx: 943 { 944 const IDESC *idesc = &m32rxf_insn_data[itype]; 945 CGEN_INSN_WORD insn = entire_insn; 946 #define FLD(f) abuf->fields.sfmt_add.f 947 UINT f_r1; 948 UINT f_r2; 949 950 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 951 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 952 953 /* Record the fields for the semantic handler. */ 954 FLD (f_r1) = f_r1; 955 FLD (f_r2) = f_r2; 956 FLD (i_dr) = & CPU (h_gr)[f_r1]; 957 FLD (i_sr) = & CPU (h_gr)[f_r2]; 958 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 959 960 #if WITH_PROFILE_MODEL_P 961 /* Record the fields for profiling. */ 962 if (PROFILE_MODEL_P (current_cpu)) 963 { 964 FLD (in_dr) = f_r1; 965 FLD (in_sr) = f_r2; 966 FLD (out_dr) = f_r1; 967 } 968 #endif 969 #undef FLD 970 return idesc; 971 } 972 973 extract_sfmt_bc8: 974 { 975 const IDESC *idesc = &m32rxf_insn_data[itype]; 976 CGEN_INSN_WORD insn = entire_insn; 977 #define FLD(f) abuf->fields.sfmt_bl8.f 978 SI f_disp8; 979 980 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); 981 982 /* Record the fields for the semantic handler. */ 983 FLD (i_disp8) = f_disp8; 984 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 985 986 #if WITH_PROFILE_MODEL_P 987 /* Record the fields for profiling. */ 988 if (PROFILE_MODEL_P (current_cpu)) 989 { 990 } 991 #endif 992 #undef FLD 993 return idesc; 994 } 995 996 extract_sfmt_bc24: 997 { 998 const IDESC *idesc = &m32rxf_insn_data[itype]; 999 CGEN_INSN_WORD insn = entire_insn; 1000 #define FLD(f) abuf->fields.sfmt_bl24.f 1001 SI f_disp24; 1002 1003 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); 1004 1005 /* Record the fields for the semantic handler. */ 1006 FLD (i_disp24) = f_disp24; 1007 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1008 1009 #if WITH_PROFILE_MODEL_P 1010 /* Record the fields for profiling. */ 1011 if (PROFILE_MODEL_P (current_cpu)) 1012 { 1013 } 1014 #endif 1015 #undef FLD 1016 return idesc; 1017 } 1018 1019 extract_sfmt_beq: 1020 { 1021 const IDESC *idesc = &m32rxf_insn_data[itype]; 1022 CGEN_INSN_WORD insn = entire_insn; 1023 #define FLD(f) abuf->fields.sfmt_beq.f 1024 UINT f_r1; 1025 UINT f_r2; 1026 SI f_disp16; 1027 1028 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1029 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1030 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); 1031 1032 /* Record the fields for the semantic handler. */ 1033 FLD (f_r1) = f_r1; 1034 FLD (f_r2) = f_r2; 1035 FLD (i_disp16) = f_disp16; 1036 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1037 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1038 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1039 1040 #if WITH_PROFILE_MODEL_P 1041 /* Record the fields for profiling. */ 1042 if (PROFILE_MODEL_P (current_cpu)) 1043 { 1044 FLD (in_src1) = f_r1; 1045 FLD (in_src2) = f_r2; 1046 } 1047 #endif 1048 #undef FLD 1049 return idesc; 1050 } 1051 1052 extract_sfmt_beqz: 1053 { 1054 const IDESC *idesc = &m32rxf_insn_data[itype]; 1055 CGEN_INSN_WORD insn = entire_insn; 1056 #define FLD(f) abuf->fields.sfmt_beq.f 1057 UINT f_r2; 1058 SI f_disp16; 1059 1060 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1061 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); 1062 1063 /* Record the fields for the semantic handler. */ 1064 FLD (f_r2) = f_r2; 1065 FLD (i_disp16) = f_disp16; 1066 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1067 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); 1068 1069 #if WITH_PROFILE_MODEL_P 1070 /* Record the fields for profiling. */ 1071 if (PROFILE_MODEL_P (current_cpu)) 1072 { 1073 FLD (in_src2) = f_r2; 1074 } 1075 #endif 1076 #undef FLD 1077 return idesc; 1078 } 1079 1080 extract_sfmt_bl8: 1081 { 1082 const IDESC *idesc = &m32rxf_insn_data[itype]; 1083 CGEN_INSN_WORD insn = entire_insn; 1084 #define FLD(f) abuf->fields.sfmt_bl8.f 1085 SI f_disp8; 1086 1087 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); 1088 1089 /* Record the fields for the semantic handler. */ 1090 FLD (i_disp8) = f_disp8; 1091 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1092 1093 #if WITH_PROFILE_MODEL_P 1094 /* Record the fields for profiling. */ 1095 if (PROFILE_MODEL_P (current_cpu)) 1096 { 1097 FLD (out_h_gr_SI_14) = 14; 1098 } 1099 #endif 1100 #undef FLD 1101 return idesc; 1102 } 1103 1104 extract_sfmt_bl24: 1105 { 1106 const IDESC *idesc = &m32rxf_insn_data[itype]; 1107 CGEN_INSN_WORD insn = entire_insn; 1108 #define FLD(f) abuf->fields.sfmt_bl24.f 1109 SI f_disp24; 1110 1111 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); 1112 1113 /* Record the fields for the semantic handler. */ 1114 FLD (i_disp24) = f_disp24; 1115 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1116 1117 #if WITH_PROFILE_MODEL_P 1118 /* Record the fields for profiling. */ 1119 if (PROFILE_MODEL_P (current_cpu)) 1120 { 1121 FLD (out_h_gr_SI_14) = 14; 1122 } 1123 #endif 1124 #undef FLD 1125 return idesc; 1126 } 1127 1128 extract_sfmt_bcl8: 1129 { 1130 const IDESC *idesc = &m32rxf_insn_data[itype]; 1131 CGEN_INSN_WORD insn = entire_insn; 1132 #define FLD(f) abuf->fields.sfmt_bl8.f 1133 SI f_disp8; 1134 1135 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); 1136 1137 /* Record the fields for the semantic handler. */ 1138 FLD (i_disp8) = f_disp8; 1139 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1140 1141 #if WITH_PROFILE_MODEL_P 1142 /* Record the fields for profiling. */ 1143 if (PROFILE_MODEL_P (current_cpu)) 1144 { 1145 FLD (out_h_gr_SI_14) = 14; 1146 } 1147 #endif 1148 #undef FLD 1149 return idesc; 1150 } 1151 1152 extract_sfmt_bcl24: 1153 { 1154 const IDESC *idesc = &m32rxf_insn_data[itype]; 1155 CGEN_INSN_WORD insn = entire_insn; 1156 #define FLD(f) abuf->fields.sfmt_bl24.f 1157 SI f_disp24; 1158 1159 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); 1160 1161 /* Record the fields for the semantic handler. */ 1162 FLD (i_disp24) = f_disp24; 1163 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1164 1165 #if WITH_PROFILE_MODEL_P 1166 /* Record the fields for profiling. */ 1167 if (PROFILE_MODEL_P (current_cpu)) 1168 { 1169 FLD (out_h_gr_SI_14) = 14; 1170 } 1171 #endif 1172 #undef FLD 1173 return idesc; 1174 } 1175 1176 extract_sfmt_bra8: 1177 { 1178 const IDESC *idesc = &m32rxf_insn_data[itype]; 1179 CGEN_INSN_WORD insn = entire_insn; 1180 #define FLD(f) abuf->fields.sfmt_bl8.f 1181 SI f_disp8; 1182 1183 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); 1184 1185 /* Record the fields for the semantic handler. */ 1186 FLD (i_disp8) = f_disp8; 1187 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); 1188 1189 #if WITH_PROFILE_MODEL_P 1190 /* Record the fields for profiling. */ 1191 if (PROFILE_MODEL_P (current_cpu)) 1192 { 1193 } 1194 #endif 1195 #undef FLD 1196 return idesc; 1197 } 1198 1199 extract_sfmt_bra24: 1200 { 1201 const IDESC *idesc = &m32rxf_insn_data[itype]; 1202 CGEN_INSN_WORD insn = entire_insn; 1203 #define FLD(f) abuf->fields.sfmt_bl24.f 1204 SI f_disp24; 1205 1206 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); 1207 1208 /* Record the fields for the semantic handler. */ 1209 FLD (i_disp24) = f_disp24; 1210 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); 1211 1212 #if WITH_PROFILE_MODEL_P 1213 /* Record the fields for profiling. */ 1214 if (PROFILE_MODEL_P (current_cpu)) 1215 { 1216 } 1217 #endif 1218 #undef FLD 1219 return idesc; 1220 } 1221 1222 extract_sfmt_cmp: 1223 { 1224 const IDESC *idesc = &m32rxf_insn_data[itype]; 1225 CGEN_INSN_WORD insn = entire_insn; 1226 #define FLD(f) abuf->fields.sfmt_st_plus.f 1227 UINT f_r1; 1228 UINT f_r2; 1229 1230 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1231 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1232 1233 /* Record the fields for the semantic handler. */ 1234 FLD (f_r1) = f_r1; 1235 FLD (f_r2) = f_r2; 1236 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1237 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1238 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1239 1240 #if WITH_PROFILE_MODEL_P 1241 /* Record the fields for profiling. */ 1242 if (PROFILE_MODEL_P (current_cpu)) 1243 { 1244 FLD (in_src1) = f_r1; 1245 FLD (in_src2) = f_r2; 1246 } 1247 #endif 1248 #undef FLD 1249 return idesc; 1250 } 1251 1252 extract_sfmt_cmpi: 1253 { 1254 const IDESC *idesc = &m32rxf_insn_data[itype]; 1255 CGEN_INSN_WORD insn = entire_insn; 1256 #define FLD(f) abuf->fields.sfmt_st_d.f 1257 UINT f_r2; 1258 INT f_simm16; 1259 1260 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1261 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1262 1263 /* Record the fields for the semantic handler. */ 1264 FLD (f_simm16) = f_simm16; 1265 FLD (f_r2) = f_r2; 1266 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1267 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1268 1269 #if WITH_PROFILE_MODEL_P 1270 /* Record the fields for profiling. */ 1271 if (PROFILE_MODEL_P (current_cpu)) 1272 { 1273 FLD (in_src2) = f_r2; 1274 } 1275 #endif 1276 #undef FLD 1277 return idesc; 1278 } 1279 1280 extract_sfmt_cmpz: 1281 { 1282 const IDESC *idesc = &m32rxf_insn_data[itype]; 1283 CGEN_INSN_WORD insn = entire_insn; 1284 #define FLD(f) abuf->fields.sfmt_st_plus.f 1285 UINT f_r2; 1286 1287 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1288 1289 /* Record the fields for the semantic handler. */ 1290 FLD (f_r2) = f_r2; 1291 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1292 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0)); 1293 1294 #if WITH_PROFILE_MODEL_P 1295 /* Record the fields for profiling. */ 1296 if (PROFILE_MODEL_P (current_cpu)) 1297 { 1298 FLD (in_src2) = f_r2; 1299 } 1300 #endif 1301 #undef FLD 1302 return idesc; 1303 } 1304 1305 extract_sfmt_div: 1306 { 1307 const IDESC *idesc = &m32rxf_insn_data[itype]; 1308 CGEN_INSN_WORD insn = entire_insn; 1309 #define FLD(f) abuf->fields.sfmt_add.f 1310 UINT f_r1; 1311 UINT f_r2; 1312 1313 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1314 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1315 1316 /* Record the fields for the semantic handler. */ 1317 FLD (f_r1) = f_r1; 1318 FLD (f_r2) = f_r2; 1319 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1320 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1321 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1322 1323 #if WITH_PROFILE_MODEL_P 1324 /* Record the fields for profiling. */ 1325 if (PROFILE_MODEL_P (current_cpu)) 1326 { 1327 FLD (in_dr) = f_r1; 1328 FLD (in_sr) = f_r2; 1329 FLD (out_dr) = f_r1; 1330 } 1331 #endif 1332 #undef FLD 1333 return idesc; 1334 } 1335 1336 extract_sfmt_jc: 1337 { 1338 const IDESC *idesc = &m32rxf_insn_data[itype]; 1339 CGEN_INSN_WORD insn = entire_insn; 1340 #define FLD(f) abuf->fields.sfmt_jl.f 1341 UINT f_r2; 1342 1343 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1344 1345 /* Record the fields for the semantic handler. */ 1346 FLD (f_r2) = f_r2; 1347 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1348 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1349 1350 #if WITH_PROFILE_MODEL_P 1351 /* Record the fields for profiling. */ 1352 if (PROFILE_MODEL_P (current_cpu)) 1353 { 1354 FLD (in_sr) = f_r2; 1355 } 1356 #endif 1357 #undef FLD 1358 return idesc; 1359 } 1360 1361 extract_sfmt_jl: 1362 { 1363 const IDESC *idesc = &m32rxf_insn_data[itype]; 1364 CGEN_INSN_WORD insn = entire_insn; 1365 #define FLD(f) abuf->fields.sfmt_jl.f 1366 UINT f_r2; 1367 1368 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1369 1370 /* Record the fields for the semantic handler. */ 1371 FLD (f_r2) = f_r2; 1372 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1373 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1374 1375 #if WITH_PROFILE_MODEL_P 1376 /* Record the fields for profiling. */ 1377 if (PROFILE_MODEL_P (current_cpu)) 1378 { 1379 FLD (in_sr) = f_r2; 1380 FLD (out_h_gr_SI_14) = 14; 1381 } 1382 #endif 1383 #undef FLD 1384 return idesc; 1385 } 1386 1387 extract_sfmt_jmp: 1388 { 1389 const IDESC *idesc = &m32rxf_insn_data[itype]; 1390 CGEN_INSN_WORD insn = entire_insn; 1391 #define FLD(f) abuf->fields.sfmt_jl.f 1392 UINT f_r2; 1393 1394 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1395 1396 /* Record the fields for the semantic handler. */ 1397 FLD (f_r2) = f_r2; 1398 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1399 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0)); 1400 1401 #if WITH_PROFILE_MODEL_P 1402 /* Record the fields for profiling. */ 1403 if (PROFILE_MODEL_P (current_cpu)) 1404 { 1405 FLD (in_sr) = f_r2; 1406 } 1407 #endif 1408 #undef FLD 1409 return idesc; 1410 } 1411 1412 extract_sfmt_ld: 1413 { 1414 const IDESC *idesc = &m32rxf_insn_data[itype]; 1415 CGEN_INSN_WORD insn = entire_insn; 1416 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1417 UINT f_r1; 1418 UINT f_r2; 1419 1420 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1421 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1422 1423 /* Record the fields for the semantic handler. */ 1424 FLD (f_r2) = f_r2; 1425 FLD (f_r1) = f_r1; 1426 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1427 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1428 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1429 1430 #if WITH_PROFILE_MODEL_P 1431 /* Record the fields for profiling. */ 1432 if (PROFILE_MODEL_P (current_cpu)) 1433 { 1434 FLD (in_sr) = f_r2; 1435 FLD (out_dr) = f_r1; 1436 } 1437 #endif 1438 #undef FLD 1439 return idesc; 1440 } 1441 1442 extract_sfmt_ld_d: 1443 { 1444 const IDESC *idesc = &m32rxf_insn_data[itype]; 1445 CGEN_INSN_WORD insn = entire_insn; 1446 #define FLD(f) abuf->fields.sfmt_add3.f 1447 UINT f_r1; 1448 UINT f_r2; 1449 INT f_simm16; 1450 1451 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1452 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1453 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1454 1455 /* Record the fields for the semantic handler. */ 1456 FLD (f_simm16) = f_simm16; 1457 FLD (f_r2) = f_r2; 1458 FLD (f_r1) = f_r1; 1459 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1460 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1461 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1462 1463 #if WITH_PROFILE_MODEL_P 1464 /* Record the fields for profiling. */ 1465 if (PROFILE_MODEL_P (current_cpu)) 1466 { 1467 FLD (in_sr) = f_r2; 1468 FLD (out_dr) = f_r1; 1469 } 1470 #endif 1471 #undef FLD 1472 return idesc; 1473 } 1474 1475 extract_sfmt_ldb: 1476 { 1477 const IDESC *idesc = &m32rxf_insn_data[itype]; 1478 CGEN_INSN_WORD insn = entire_insn; 1479 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1480 UINT f_r1; 1481 UINT f_r2; 1482 1483 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1484 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1485 1486 /* Record the fields for the semantic handler. */ 1487 FLD (f_r2) = f_r2; 1488 FLD (f_r1) = f_r1; 1489 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1490 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1491 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1492 1493 #if WITH_PROFILE_MODEL_P 1494 /* Record the fields for profiling. */ 1495 if (PROFILE_MODEL_P (current_cpu)) 1496 { 1497 FLD (in_sr) = f_r2; 1498 FLD (out_dr) = f_r1; 1499 } 1500 #endif 1501 #undef FLD 1502 return idesc; 1503 } 1504 1505 extract_sfmt_ldb_d: 1506 { 1507 const IDESC *idesc = &m32rxf_insn_data[itype]; 1508 CGEN_INSN_WORD insn = entire_insn; 1509 #define FLD(f) abuf->fields.sfmt_add3.f 1510 UINT f_r1; 1511 UINT f_r2; 1512 INT f_simm16; 1513 1514 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1515 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1516 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1517 1518 /* Record the fields for the semantic handler. */ 1519 FLD (f_simm16) = f_simm16; 1520 FLD (f_r2) = f_r2; 1521 FLD (f_r1) = f_r1; 1522 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1523 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1524 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1525 1526 #if WITH_PROFILE_MODEL_P 1527 /* Record the fields for profiling. */ 1528 if (PROFILE_MODEL_P (current_cpu)) 1529 { 1530 FLD (in_sr) = f_r2; 1531 FLD (out_dr) = f_r1; 1532 } 1533 #endif 1534 #undef FLD 1535 return idesc; 1536 } 1537 1538 extract_sfmt_ldh: 1539 { 1540 const IDESC *idesc = &m32rxf_insn_data[itype]; 1541 CGEN_INSN_WORD insn = entire_insn; 1542 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1543 UINT f_r1; 1544 UINT f_r2; 1545 1546 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1547 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1548 1549 /* Record the fields for the semantic handler. */ 1550 FLD (f_r2) = f_r2; 1551 FLD (f_r1) = f_r1; 1552 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1553 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1554 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1555 1556 #if WITH_PROFILE_MODEL_P 1557 /* Record the fields for profiling. */ 1558 if (PROFILE_MODEL_P (current_cpu)) 1559 { 1560 FLD (in_sr) = f_r2; 1561 FLD (out_dr) = f_r1; 1562 } 1563 #endif 1564 #undef FLD 1565 return idesc; 1566 } 1567 1568 extract_sfmt_ldh_d: 1569 { 1570 const IDESC *idesc = &m32rxf_insn_data[itype]; 1571 CGEN_INSN_WORD insn = entire_insn; 1572 #define FLD(f) abuf->fields.sfmt_add3.f 1573 UINT f_r1; 1574 UINT f_r2; 1575 INT f_simm16; 1576 1577 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1578 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 1579 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1580 1581 /* Record the fields for the semantic handler. */ 1582 FLD (f_simm16) = f_simm16; 1583 FLD (f_r2) = f_r2; 1584 FLD (f_r1) = f_r1; 1585 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1586 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1587 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1588 1589 #if WITH_PROFILE_MODEL_P 1590 /* Record the fields for profiling. */ 1591 if (PROFILE_MODEL_P (current_cpu)) 1592 { 1593 FLD (in_sr) = f_r2; 1594 FLD (out_dr) = f_r1; 1595 } 1596 #endif 1597 #undef FLD 1598 return idesc; 1599 } 1600 1601 extract_sfmt_ld_plus: 1602 { 1603 const IDESC *idesc = &m32rxf_insn_data[itype]; 1604 CGEN_INSN_WORD insn = entire_insn; 1605 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1606 UINT f_r1; 1607 UINT f_r2; 1608 1609 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1610 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1611 1612 /* Record the fields for the semantic handler. */ 1613 FLD (f_r2) = f_r2; 1614 FLD (f_r1) = f_r1; 1615 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1616 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1617 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1618 1619 #if WITH_PROFILE_MODEL_P 1620 /* Record the fields for profiling. */ 1621 if (PROFILE_MODEL_P (current_cpu)) 1622 { 1623 FLD (in_sr) = f_r2; 1624 FLD (out_dr) = f_r1; 1625 FLD (out_sr) = f_r2; 1626 } 1627 #endif 1628 #undef FLD 1629 return idesc; 1630 } 1631 1632 extract_sfmt_ld24: 1633 { 1634 const IDESC *idesc = &m32rxf_insn_data[itype]; 1635 CGEN_INSN_WORD insn = entire_insn; 1636 #define FLD(f) abuf->fields.sfmt_ld24.f 1637 UINT f_r1; 1638 UINT f_uimm24; 1639 1640 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1641 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); 1642 1643 /* Record the fields for the semantic handler. */ 1644 FLD (f_r1) = f_r1; 1645 FLD (i_uimm24) = f_uimm24; 1646 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1647 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); 1648 1649 #if WITH_PROFILE_MODEL_P 1650 /* Record the fields for profiling. */ 1651 if (PROFILE_MODEL_P (current_cpu)) 1652 { 1653 FLD (out_dr) = f_r1; 1654 } 1655 #endif 1656 #undef FLD 1657 return idesc; 1658 } 1659 1660 extract_sfmt_ldi8: 1661 { 1662 const IDESC *idesc = &m32rxf_insn_data[itype]; 1663 CGEN_INSN_WORD insn = entire_insn; 1664 #define FLD(f) abuf->fields.sfmt_addi.f 1665 UINT f_r1; 1666 INT f_simm8; 1667 1668 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1669 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); 1670 1671 /* Record the fields for the semantic handler. */ 1672 FLD (f_simm8) = f_simm8; 1673 FLD (f_r1) = f_r1; 1674 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1675 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1676 1677 #if WITH_PROFILE_MODEL_P 1678 /* Record the fields for profiling. */ 1679 if (PROFILE_MODEL_P (current_cpu)) 1680 { 1681 FLD (out_dr) = f_r1; 1682 } 1683 #endif 1684 #undef FLD 1685 return idesc; 1686 } 1687 1688 extract_sfmt_ldi16: 1689 { 1690 const IDESC *idesc = &m32rxf_insn_data[itype]; 1691 CGEN_INSN_WORD insn = entire_insn; 1692 #define FLD(f) abuf->fields.sfmt_add3.f 1693 UINT f_r1; 1694 INT f_simm16; 1695 1696 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 1697 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 1698 1699 /* Record the fields for the semantic handler. */ 1700 FLD (f_simm16) = f_simm16; 1701 FLD (f_r1) = f_r1; 1702 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1703 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1704 1705 #if WITH_PROFILE_MODEL_P 1706 /* Record the fields for profiling. */ 1707 if (PROFILE_MODEL_P (current_cpu)) 1708 { 1709 FLD (out_dr) = f_r1; 1710 } 1711 #endif 1712 #undef FLD 1713 return idesc; 1714 } 1715 1716 extract_sfmt_lock: 1717 { 1718 const IDESC *idesc = &m32rxf_insn_data[itype]; 1719 CGEN_INSN_WORD insn = entire_insn; 1720 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1721 UINT f_r1; 1722 UINT f_r2; 1723 1724 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1725 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1726 1727 /* Record the fields for the semantic handler. */ 1728 FLD (f_r2) = f_r2; 1729 FLD (f_r1) = f_r1; 1730 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1731 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1732 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1733 1734 #if WITH_PROFILE_MODEL_P 1735 /* Record the fields for profiling. */ 1736 if (PROFILE_MODEL_P (current_cpu)) 1737 { 1738 FLD (in_sr) = f_r2; 1739 FLD (out_dr) = f_r1; 1740 } 1741 #endif 1742 #undef FLD 1743 return idesc; 1744 } 1745 1746 extract_sfmt_machi_a: 1747 { 1748 const IDESC *idesc = &m32rxf_insn_data[itype]; 1749 CGEN_INSN_WORD insn = entire_insn; 1750 #define FLD(f) abuf->fields.sfmt_machi_a.f 1751 UINT f_r1; 1752 UINT f_acc; 1753 UINT f_r2; 1754 1755 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1756 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); 1757 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1758 1759 /* Record the fields for the semantic handler. */ 1760 FLD (f_acc) = f_acc; 1761 FLD (f_r1) = f_r1; 1762 FLD (f_r2) = f_r2; 1763 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1764 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1765 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1766 1767 #if WITH_PROFILE_MODEL_P 1768 /* Record the fields for profiling. */ 1769 if (PROFILE_MODEL_P (current_cpu)) 1770 { 1771 FLD (in_src1) = f_r1; 1772 FLD (in_src2) = f_r2; 1773 } 1774 #endif 1775 #undef FLD 1776 return idesc; 1777 } 1778 1779 extract_sfmt_mulhi_a: 1780 { 1781 const IDESC *idesc = &m32rxf_insn_data[itype]; 1782 CGEN_INSN_WORD insn = entire_insn; 1783 #define FLD(f) abuf->fields.sfmt_machi_a.f 1784 UINT f_r1; 1785 UINT f_acc; 1786 UINT f_r2; 1787 1788 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1789 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); 1790 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1791 1792 /* Record the fields for the semantic handler. */ 1793 FLD (f_r1) = f_r1; 1794 FLD (f_r2) = f_r2; 1795 FLD (f_acc) = f_acc; 1796 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1797 FLD (i_src2) = & CPU (h_gr)[f_r2]; 1798 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 1799 1800 #if WITH_PROFILE_MODEL_P 1801 /* Record the fields for profiling. */ 1802 if (PROFILE_MODEL_P (current_cpu)) 1803 { 1804 FLD (in_src1) = f_r1; 1805 FLD (in_src2) = f_r2; 1806 } 1807 #endif 1808 #undef FLD 1809 return idesc; 1810 } 1811 1812 extract_sfmt_mv: 1813 { 1814 const IDESC *idesc = &m32rxf_insn_data[itype]; 1815 CGEN_INSN_WORD insn = entire_insn; 1816 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1817 UINT f_r1; 1818 UINT f_r2; 1819 1820 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1821 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1822 1823 /* Record the fields for the semantic handler. */ 1824 FLD (f_r2) = f_r2; 1825 FLD (f_r1) = f_r1; 1826 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1827 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1828 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 1829 1830 #if WITH_PROFILE_MODEL_P 1831 /* Record the fields for profiling. */ 1832 if (PROFILE_MODEL_P (current_cpu)) 1833 { 1834 FLD (in_sr) = f_r2; 1835 FLD (out_dr) = f_r1; 1836 } 1837 #endif 1838 #undef FLD 1839 return idesc; 1840 } 1841 1842 extract_sfmt_mvfachi_a: 1843 { 1844 const IDESC *idesc = &m32rxf_insn_data[itype]; 1845 CGEN_INSN_WORD insn = entire_insn; 1846 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1847 UINT f_r1; 1848 UINT f_accs; 1849 1850 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1851 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1852 1853 /* Record the fields for the semantic handler. */ 1854 FLD (f_accs) = f_accs; 1855 FLD (f_r1) = f_r1; 1856 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1857 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1858 1859 #if WITH_PROFILE_MODEL_P 1860 /* Record the fields for profiling. */ 1861 if (PROFILE_MODEL_P (current_cpu)) 1862 { 1863 FLD (out_dr) = f_r1; 1864 } 1865 #endif 1866 #undef FLD 1867 return idesc; 1868 } 1869 1870 extract_sfmt_mvfc: 1871 { 1872 const IDESC *idesc = &m32rxf_insn_data[itype]; 1873 CGEN_INSN_WORD insn = entire_insn; 1874 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1875 UINT f_r1; 1876 UINT f_r2; 1877 1878 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1879 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1880 1881 /* Record the fields for the semantic handler. */ 1882 FLD (f_r2) = f_r2; 1883 FLD (f_r1) = f_r1; 1884 FLD (i_dr) = & CPU (h_gr)[f_r1]; 1885 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 1886 1887 #if WITH_PROFILE_MODEL_P 1888 /* Record the fields for profiling. */ 1889 if (PROFILE_MODEL_P (current_cpu)) 1890 { 1891 FLD (out_dr) = f_r1; 1892 } 1893 #endif 1894 #undef FLD 1895 return idesc; 1896 } 1897 1898 extract_sfmt_mvtachi_a: 1899 { 1900 const IDESC *idesc = &m32rxf_insn_data[itype]; 1901 CGEN_INSN_WORD insn = entire_insn; 1902 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1903 UINT f_r1; 1904 UINT f_accs; 1905 1906 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1907 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1908 1909 /* Record the fields for the semantic handler. */ 1910 FLD (f_accs) = f_accs; 1911 FLD (f_r1) = f_r1; 1912 FLD (i_src1) = & CPU (h_gr)[f_r1]; 1913 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0)); 1914 1915 #if WITH_PROFILE_MODEL_P 1916 /* Record the fields for profiling. */ 1917 if (PROFILE_MODEL_P (current_cpu)) 1918 { 1919 FLD (in_src1) = f_r1; 1920 } 1921 #endif 1922 #undef FLD 1923 return idesc; 1924 } 1925 1926 extract_sfmt_mvtc: 1927 { 1928 const IDESC *idesc = &m32rxf_insn_data[itype]; 1929 CGEN_INSN_WORD insn = entire_insn; 1930 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1931 UINT f_r1; 1932 UINT f_r2; 1933 1934 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 1935 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 1936 1937 /* Record the fields for the semantic handler. */ 1938 FLD (f_r2) = f_r2; 1939 FLD (f_r1) = f_r1; 1940 FLD (i_sr) = & CPU (h_gr)[f_r2]; 1941 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); 1942 1943 #if WITH_PROFILE_MODEL_P 1944 /* Record the fields for profiling. */ 1945 if (PROFILE_MODEL_P (current_cpu)) 1946 { 1947 FLD (in_sr) = f_r2; 1948 } 1949 #endif 1950 #undef FLD 1951 return idesc; 1952 } 1953 1954 extract_sfmt_nop: 1955 { 1956 const IDESC *idesc = &m32rxf_insn_data[itype]; 1957 #define FLD(f) abuf->fields.sfmt_empty.f 1958 1959 1960 /* Record the fields for the semantic handler. */ 1961 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); 1962 1963 #undef FLD 1964 return idesc; 1965 } 1966 1967 extract_sfmt_rac_dsi: 1968 { 1969 const IDESC *idesc = &m32rxf_insn_data[itype]; 1970 CGEN_INSN_WORD insn = entire_insn; 1971 #define FLD(f) abuf->fields.sfmt_rac_dsi.f 1972 UINT f_accd; 1973 UINT f_accs; 1974 SI f_imm1; 1975 1976 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); 1977 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); 1978 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); 1979 1980 /* Record the fields for the semantic handler. */ 1981 FLD (f_accs) = f_accs; 1982 FLD (f_imm1) = f_imm1; 1983 FLD (f_accd) = f_accd; 1984 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0)); 1985 1986 #undef FLD 1987 return idesc; 1988 } 1989 1990 extract_sfmt_rte: 1991 { 1992 const IDESC *idesc = &m32rxf_insn_data[itype]; 1993 #define FLD(f) abuf->fields.sfmt_empty.f 1994 1995 1996 /* Record the fields for the semantic handler. */ 1997 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); 1998 1999 #if WITH_PROFILE_MODEL_P 2000 /* Record the fields for profiling. */ 2001 if (PROFILE_MODEL_P (current_cpu)) 2002 { 2003 } 2004 #endif 2005 #undef FLD 2006 return idesc; 2007 } 2008 2009 extract_sfmt_seth: 2010 { 2011 const IDESC *idesc = &m32rxf_insn_data[itype]; 2012 CGEN_INSN_WORD insn = entire_insn; 2013 #define FLD(f) abuf->fields.sfmt_seth.f 2014 UINT f_r1; 2015 UINT f_hi16; 2016 2017 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2018 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); 2019 2020 /* Record the fields for the semantic handler. */ 2021 FLD (f_hi16) = f_hi16; 2022 FLD (f_r1) = f_r1; 2023 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2024 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0)); 2025 2026 #if WITH_PROFILE_MODEL_P 2027 /* Record the fields for profiling. */ 2028 if (PROFILE_MODEL_P (current_cpu)) 2029 { 2030 FLD (out_dr) = f_r1; 2031 } 2032 #endif 2033 #undef FLD 2034 return idesc; 2035 } 2036 2037 extract_sfmt_sll3: 2038 { 2039 const IDESC *idesc = &m32rxf_insn_data[itype]; 2040 CGEN_INSN_WORD insn = entire_insn; 2041 #define FLD(f) abuf->fields.sfmt_add3.f 2042 UINT f_r1; 2043 UINT f_r2; 2044 INT f_simm16; 2045 2046 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2047 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2048 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2049 2050 /* Record the fields for the semantic handler. */ 2051 FLD (f_simm16) = f_simm16; 2052 FLD (f_r2) = f_r2; 2053 FLD (f_r1) = f_r1; 2054 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2055 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2056 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2057 2058 #if WITH_PROFILE_MODEL_P 2059 /* Record the fields for profiling. */ 2060 if (PROFILE_MODEL_P (current_cpu)) 2061 { 2062 FLD (in_sr) = f_r2; 2063 FLD (out_dr) = f_r1; 2064 } 2065 #endif 2066 #undef FLD 2067 return idesc; 2068 } 2069 2070 extract_sfmt_slli: 2071 { 2072 const IDESC *idesc = &m32rxf_insn_data[itype]; 2073 CGEN_INSN_WORD insn = entire_insn; 2074 #define FLD(f) abuf->fields.sfmt_slli.f 2075 UINT f_r1; 2076 UINT f_uimm5; 2077 2078 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2079 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); 2080 2081 /* Record the fields for the semantic handler. */ 2082 FLD (f_r1) = f_r1; 2083 FLD (f_uimm5) = f_uimm5; 2084 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2085 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); 2086 2087 #if WITH_PROFILE_MODEL_P 2088 /* Record the fields for profiling. */ 2089 if (PROFILE_MODEL_P (current_cpu)) 2090 { 2091 FLD (in_dr) = f_r1; 2092 FLD (out_dr) = f_r1; 2093 } 2094 #endif 2095 #undef FLD 2096 return idesc; 2097 } 2098 2099 extract_sfmt_st: 2100 { 2101 const IDESC *idesc = &m32rxf_insn_data[itype]; 2102 CGEN_INSN_WORD insn = entire_insn; 2103 #define FLD(f) abuf->fields.sfmt_st_plus.f 2104 UINT f_r1; 2105 UINT f_r2; 2106 2107 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2108 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2109 2110 /* Record the fields for the semantic handler. */ 2111 FLD (f_r1) = f_r1; 2112 FLD (f_r2) = f_r2; 2113 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2114 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2115 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2116 2117 #if WITH_PROFILE_MODEL_P 2118 /* Record the fields for profiling. */ 2119 if (PROFILE_MODEL_P (current_cpu)) 2120 { 2121 FLD (in_src1) = f_r1; 2122 FLD (in_src2) = f_r2; 2123 } 2124 #endif 2125 #undef FLD 2126 return idesc; 2127 } 2128 2129 extract_sfmt_st_d: 2130 { 2131 const IDESC *idesc = &m32rxf_insn_data[itype]; 2132 CGEN_INSN_WORD insn = entire_insn; 2133 #define FLD(f) abuf->fields.sfmt_st_d.f 2134 UINT f_r1; 2135 UINT f_r2; 2136 INT f_simm16; 2137 2138 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2139 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2140 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2141 2142 /* Record the fields for the semantic handler. */ 2143 FLD (f_simm16) = f_simm16; 2144 FLD (f_r1) = f_r1; 2145 FLD (f_r2) = f_r2; 2146 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2147 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2148 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2149 2150 #if WITH_PROFILE_MODEL_P 2151 /* Record the fields for profiling. */ 2152 if (PROFILE_MODEL_P (current_cpu)) 2153 { 2154 FLD (in_src1) = f_r1; 2155 FLD (in_src2) = f_r2; 2156 } 2157 #endif 2158 #undef FLD 2159 return idesc; 2160 } 2161 2162 extract_sfmt_stb: 2163 { 2164 const IDESC *idesc = &m32rxf_insn_data[itype]; 2165 CGEN_INSN_WORD insn = entire_insn; 2166 #define FLD(f) abuf->fields.sfmt_st_plus.f 2167 UINT f_r1; 2168 UINT f_r2; 2169 2170 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2171 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2172 2173 /* Record the fields for the semantic handler. */ 2174 FLD (f_r1) = f_r1; 2175 FLD (f_r2) = f_r2; 2176 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2177 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2178 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2179 2180 #if WITH_PROFILE_MODEL_P 2181 /* Record the fields for profiling. */ 2182 if (PROFILE_MODEL_P (current_cpu)) 2183 { 2184 FLD (in_src1) = f_r1; 2185 FLD (in_src2) = f_r2; 2186 } 2187 #endif 2188 #undef FLD 2189 return idesc; 2190 } 2191 2192 extract_sfmt_stb_d: 2193 { 2194 const IDESC *idesc = &m32rxf_insn_data[itype]; 2195 CGEN_INSN_WORD insn = entire_insn; 2196 #define FLD(f) abuf->fields.sfmt_st_d.f 2197 UINT f_r1; 2198 UINT f_r2; 2199 INT f_simm16; 2200 2201 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2202 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2203 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2204 2205 /* Record the fields for the semantic handler. */ 2206 FLD (f_simm16) = f_simm16; 2207 FLD (f_r1) = f_r1; 2208 FLD (f_r2) = f_r2; 2209 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2210 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2211 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2212 2213 #if WITH_PROFILE_MODEL_P 2214 /* Record the fields for profiling. */ 2215 if (PROFILE_MODEL_P (current_cpu)) 2216 { 2217 FLD (in_src1) = f_r1; 2218 FLD (in_src2) = f_r2; 2219 } 2220 #endif 2221 #undef FLD 2222 return idesc; 2223 } 2224 2225 extract_sfmt_sth: 2226 { 2227 const IDESC *idesc = &m32rxf_insn_data[itype]; 2228 CGEN_INSN_WORD insn = entire_insn; 2229 #define FLD(f) abuf->fields.sfmt_st_plus.f 2230 UINT f_r1; 2231 UINT f_r2; 2232 2233 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2234 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2235 2236 /* Record the fields for the semantic handler. */ 2237 FLD (f_r1) = f_r1; 2238 FLD (f_r2) = f_r2; 2239 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2240 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2241 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2242 2243 #if WITH_PROFILE_MODEL_P 2244 /* Record the fields for profiling. */ 2245 if (PROFILE_MODEL_P (current_cpu)) 2246 { 2247 FLD (in_src1) = f_r1; 2248 FLD (in_src2) = f_r2; 2249 } 2250 #endif 2251 #undef FLD 2252 return idesc; 2253 } 2254 2255 extract_sfmt_sth_d: 2256 { 2257 const IDESC *idesc = &m32rxf_insn_data[itype]; 2258 CGEN_INSN_WORD insn = entire_insn; 2259 #define FLD(f) abuf->fields.sfmt_st_d.f 2260 UINT f_r1; 2261 UINT f_r2; 2262 INT f_simm16; 2263 2264 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2265 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2266 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2267 2268 /* Record the fields for the semantic handler. */ 2269 FLD (f_simm16) = f_simm16; 2270 FLD (f_r1) = f_r1; 2271 FLD (f_r2) = f_r2; 2272 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2273 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2274 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2275 2276 #if WITH_PROFILE_MODEL_P 2277 /* Record the fields for profiling. */ 2278 if (PROFILE_MODEL_P (current_cpu)) 2279 { 2280 FLD (in_src1) = f_r1; 2281 FLD (in_src2) = f_r2; 2282 } 2283 #endif 2284 #undef FLD 2285 return idesc; 2286 } 2287 2288 extract_sfmt_st_plus: 2289 { 2290 const IDESC *idesc = &m32rxf_insn_data[itype]; 2291 CGEN_INSN_WORD insn = entire_insn; 2292 #define FLD(f) abuf->fields.sfmt_st_plus.f 2293 UINT f_r1; 2294 UINT f_r2; 2295 2296 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2297 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2298 2299 /* Record the fields for the semantic handler. */ 2300 FLD (f_r1) = f_r1; 2301 FLD (f_r2) = f_r2; 2302 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2303 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2304 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2305 2306 #if WITH_PROFILE_MODEL_P 2307 /* Record the fields for profiling. */ 2308 if (PROFILE_MODEL_P (current_cpu)) 2309 { 2310 FLD (in_src1) = f_r1; 2311 FLD (in_src2) = f_r2; 2312 FLD (out_src2) = f_r2; 2313 } 2314 #endif 2315 #undef FLD 2316 return idesc; 2317 } 2318 2319 extract_sfmt_sth_plus: 2320 { 2321 const IDESC *idesc = &m32rxf_insn_data[itype]; 2322 CGEN_INSN_WORD insn = entire_insn; 2323 #define FLD(f) abuf->fields.sfmt_st_plus.f 2324 UINT f_r1; 2325 UINT f_r2; 2326 2327 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2328 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2329 2330 /* Record the fields for the semantic handler. */ 2331 FLD (f_r1) = f_r1; 2332 FLD (f_r2) = f_r2; 2333 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2334 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2335 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2336 2337 #if WITH_PROFILE_MODEL_P 2338 /* Record the fields for profiling. */ 2339 if (PROFILE_MODEL_P (current_cpu)) 2340 { 2341 FLD (in_src1) = f_r1; 2342 FLD (in_src2) = f_r2; 2343 FLD (out_src2) = f_r2; 2344 } 2345 #endif 2346 #undef FLD 2347 return idesc; 2348 } 2349 2350 extract_sfmt_stb_plus: 2351 { 2352 const IDESC *idesc = &m32rxf_insn_data[itype]; 2353 CGEN_INSN_WORD insn = entire_insn; 2354 #define FLD(f) abuf->fields.sfmt_st_plus.f 2355 UINT f_r1; 2356 UINT f_r2; 2357 2358 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2359 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2360 2361 /* Record the fields for the semantic handler. */ 2362 FLD (f_r1) = f_r1; 2363 FLD (f_r2) = f_r2; 2364 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2365 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2366 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2367 2368 #if WITH_PROFILE_MODEL_P 2369 /* Record the fields for profiling. */ 2370 if (PROFILE_MODEL_P (current_cpu)) 2371 { 2372 FLD (in_src1) = f_r1; 2373 FLD (in_src2) = f_r2; 2374 FLD (out_src2) = f_r2; 2375 } 2376 #endif 2377 #undef FLD 2378 return idesc; 2379 } 2380 2381 extract_sfmt_trap: 2382 { 2383 const IDESC *idesc = &m32rxf_insn_data[itype]; 2384 CGEN_INSN_WORD insn = entire_insn; 2385 #define FLD(f) abuf->fields.sfmt_trap.f 2386 UINT f_uimm4; 2387 2388 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2389 2390 /* Record the fields for the semantic handler. */ 2391 FLD (f_uimm4) = f_uimm4; 2392 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); 2393 2394 #if WITH_PROFILE_MODEL_P 2395 /* Record the fields for profiling. */ 2396 if (PROFILE_MODEL_P (current_cpu)) 2397 { 2398 } 2399 #endif 2400 #undef FLD 2401 return idesc; 2402 } 2403 2404 extract_sfmt_unlock: 2405 { 2406 const IDESC *idesc = &m32rxf_insn_data[itype]; 2407 CGEN_INSN_WORD insn = entire_insn; 2408 #define FLD(f) abuf->fields.sfmt_st_plus.f 2409 UINT f_r1; 2410 UINT f_r2; 2411 2412 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2413 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2414 2415 /* Record the fields for the semantic handler. */ 2416 FLD (f_r1) = f_r1; 2417 FLD (f_r2) = f_r2; 2418 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2419 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2420 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2421 2422 #if WITH_PROFILE_MODEL_P 2423 /* Record the fields for profiling. */ 2424 if (PROFILE_MODEL_P (current_cpu)) 2425 { 2426 FLD (in_src1) = f_r1; 2427 FLD (in_src2) = f_r2; 2428 } 2429 #endif 2430 #undef FLD 2431 return idesc; 2432 } 2433 2434 extract_sfmt_satb: 2435 { 2436 const IDESC *idesc = &m32rxf_insn_data[itype]; 2437 CGEN_INSN_WORD insn = entire_insn; 2438 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2439 UINT f_r1; 2440 UINT f_r2; 2441 2442 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2443 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2444 2445 /* Record the fields for the semantic handler. */ 2446 FLD (f_r2) = f_r2; 2447 FLD (f_r1) = f_r1; 2448 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2449 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2450 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2451 2452 #if WITH_PROFILE_MODEL_P 2453 /* Record the fields for profiling. */ 2454 if (PROFILE_MODEL_P (current_cpu)) 2455 { 2456 FLD (in_sr) = f_r2; 2457 FLD (out_dr) = f_r1; 2458 } 2459 #endif 2460 #undef FLD 2461 return idesc; 2462 } 2463 2464 extract_sfmt_sat: 2465 { 2466 const IDESC *idesc = &m32rxf_insn_data[itype]; 2467 CGEN_INSN_WORD insn = entire_insn; 2468 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2469 UINT f_r1; 2470 UINT f_r2; 2471 2472 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); 2473 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2474 2475 /* Record the fields for the semantic handler. */ 2476 FLD (f_r2) = f_r2; 2477 FLD (f_r1) = f_r1; 2478 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2479 FLD (i_dr) = & CPU (h_gr)[f_r1]; 2480 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); 2481 2482 #if WITH_PROFILE_MODEL_P 2483 /* Record the fields for profiling. */ 2484 if (PROFILE_MODEL_P (current_cpu)) 2485 { 2486 FLD (in_sr) = f_r2; 2487 FLD (out_dr) = f_r1; 2488 } 2489 #endif 2490 #undef FLD 2491 return idesc; 2492 } 2493 2494 extract_sfmt_sadd: 2495 { 2496 const IDESC *idesc = &m32rxf_insn_data[itype]; 2497 #define FLD(f) abuf->fields.sfmt_empty.f 2498 2499 2500 /* Record the fields for the semantic handler. */ 2501 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0)); 2502 2503 #undef FLD 2504 return idesc; 2505 } 2506 2507 extract_sfmt_macwu1: 2508 { 2509 const IDESC *idesc = &m32rxf_insn_data[itype]; 2510 CGEN_INSN_WORD insn = entire_insn; 2511 #define FLD(f) abuf->fields.sfmt_st_plus.f 2512 UINT f_r1; 2513 UINT f_r2; 2514 2515 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2516 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2517 2518 /* Record the fields for the semantic handler. */ 2519 FLD (f_r1) = f_r1; 2520 FLD (f_r2) = f_r2; 2521 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2522 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2523 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2524 2525 #if WITH_PROFILE_MODEL_P 2526 /* Record the fields for profiling. */ 2527 if (PROFILE_MODEL_P (current_cpu)) 2528 { 2529 FLD (in_src1) = f_r1; 2530 FLD (in_src2) = f_r2; 2531 } 2532 #endif 2533 #undef FLD 2534 return idesc; 2535 } 2536 2537 extract_sfmt_msblo: 2538 { 2539 const IDESC *idesc = &m32rxf_insn_data[itype]; 2540 CGEN_INSN_WORD insn = entire_insn; 2541 #define FLD(f) abuf->fields.sfmt_st_plus.f 2542 UINT f_r1; 2543 UINT f_r2; 2544 2545 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2546 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2547 2548 /* Record the fields for the semantic handler. */ 2549 FLD (f_r1) = f_r1; 2550 FLD (f_r2) = f_r2; 2551 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2552 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2553 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2554 2555 #if WITH_PROFILE_MODEL_P 2556 /* Record the fields for profiling. */ 2557 if (PROFILE_MODEL_P (current_cpu)) 2558 { 2559 FLD (in_src1) = f_r1; 2560 FLD (in_src2) = f_r2; 2561 } 2562 #endif 2563 #undef FLD 2564 return idesc; 2565 } 2566 2567 extract_sfmt_mulwu1: 2568 { 2569 const IDESC *idesc = &m32rxf_insn_data[itype]; 2570 CGEN_INSN_WORD insn = entire_insn; 2571 #define FLD(f) abuf->fields.sfmt_st_plus.f 2572 UINT f_r1; 2573 UINT f_r2; 2574 2575 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); 2576 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2577 2578 /* Record the fields for the semantic handler. */ 2579 FLD (f_r1) = f_r1; 2580 FLD (f_r2) = f_r2; 2581 FLD (i_src1) = & CPU (h_gr)[f_r1]; 2582 FLD (i_src2) = & CPU (h_gr)[f_r2]; 2583 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); 2584 2585 #if WITH_PROFILE_MODEL_P 2586 /* Record the fields for profiling. */ 2587 if (PROFILE_MODEL_P (current_cpu)) 2588 { 2589 FLD (in_src1) = f_r1; 2590 FLD (in_src2) = f_r2; 2591 } 2592 #endif 2593 #undef FLD 2594 return idesc; 2595 } 2596 2597 extract_sfmt_sc: 2598 { 2599 const IDESC *idesc = &m32rxf_insn_data[itype]; 2600 #define FLD(f) abuf->fields.sfmt_empty.f 2601 2602 2603 /* Record the fields for the semantic handler. */ 2604 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0)); 2605 2606 #undef FLD 2607 return idesc; 2608 } 2609 2610 extract_sfmt_clrpsw: 2611 { 2612 const IDESC *idesc = &m32rxf_insn_data[itype]; 2613 CGEN_INSN_WORD insn = entire_insn; 2614 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2615 UINT f_uimm8; 2616 2617 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2618 2619 /* Record the fields for the semantic handler. */ 2620 FLD (f_uimm8) = f_uimm8; 2621 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2622 2623 #undef FLD 2624 return idesc; 2625 } 2626 2627 extract_sfmt_setpsw: 2628 { 2629 const IDESC *idesc = &m32rxf_insn_data[itype]; 2630 CGEN_INSN_WORD insn = entire_insn; 2631 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2632 UINT f_uimm8; 2633 2634 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); 2635 2636 /* Record the fields for the semantic handler. */ 2637 FLD (f_uimm8) = f_uimm8; 2638 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0)); 2639 2640 #undef FLD 2641 return idesc; 2642 } 2643 2644 extract_sfmt_bset: 2645 { 2646 const IDESC *idesc = &m32rxf_insn_data[itype]; 2647 CGEN_INSN_WORD insn = entire_insn; 2648 #define FLD(f) abuf->fields.sfmt_bset.f 2649 UINT f_uimm3; 2650 UINT f_r2; 2651 INT f_simm16; 2652 2653 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); 2654 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); 2655 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); 2656 2657 /* Record the fields for the semantic handler. */ 2658 FLD (f_simm16) = f_simm16; 2659 FLD (f_r2) = f_r2; 2660 FLD (f_uimm3) = f_uimm3; 2661 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2662 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2663 2664 #if WITH_PROFILE_MODEL_P 2665 /* Record the fields for profiling. */ 2666 if (PROFILE_MODEL_P (current_cpu)) 2667 { 2668 FLD (in_sr) = f_r2; 2669 } 2670 #endif 2671 #undef FLD 2672 return idesc; 2673 } 2674 2675 extract_sfmt_btst: 2676 { 2677 const IDESC *idesc = &m32rxf_insn_data[itype]; 2678 CGEN_INSN_WORD insn = entire_insn; 2679 #define FLD(f) abuf->fields.sfmt_bset.f 2680 UINT f_uimm3; 2681 UINT f_r2; 2682 2683 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); 2684 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); 2685 2686 /* Record the fields for the semantic handler. */ 2687 FLD (f_r2) = f_r2; 2688 FLD (f_uimm3) = f_uimm3; 2689 FLD (i_sr) = & CPU (h_gr)[f_r2]; 2690 CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0)); 2691 2692 #if WITH_PROFILE_MODEL_P 2693 /* Record the fields for profiling. */ 2694 if (PROFILE_MODEL_P (current_cpu)) 2695 { 2696 FLD (in_sr) = f_r2; 2697 } 2698 #endif 2699 #undef FLD 2700 return idesc; 2701 } 2702 2703 } 2704