1 /* Simulator for Atmel's AVR core. 2 Copyright (C) 2009-2024 Free Software Foundation, Inc. 3 Written by Tristan Gingold, AdaCore. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* This must come before any other includes. */ 21 #include "defs.h" 22 23 #include <string.h> 24 25 #include "bfd.h" 26 #include "libiberty.h" 27 #include "sim/sim.h" 28 29 #include "sim-main.h" 30 #include "sim-base.h" 31 #include "sim-options.h" 32 #include "sim-signal.h" 33 #include "avr-sim.h" 34 35 /* As AVR is a 8/16 bits processor, define handy types. */ 36 typedef unsigned short int word; 37 typedef signed short int sword; 38 typedef unsigned char byte; 39 typedef signed char sbyte; 40 41 /* Max size of I space (which is always flash on avr). */ 42 #define MAX_AVR_FLASH (128 * 1024) 43 #define PC_MASK (MAX_AVR_FLASH - 1) 44 45 /* Mac size of D space. */ 46 #define MAX_AVR_SRAM (64 * 1024) 47 #define SRAM_MASK (MAX_AVR_SRAM - 1) 48 49 /* D space offset in ELF file. */ 50 #define SRAM_VADDR 0x800000 51 52 /* Simulator specific ports. */ 53 #define STDIO_PORT 0x52 54 #define EXIT_PORT 0x4F 55 #define ABORT_PORT 0x49 56 57 /* GDB defined register numbers. */ 58 #define AVR_SREG_REGNUM 32 59 #define AVR_SP_REGNUM 33 60 #define AVR_PC_REGNUM 34 61 62 /* Memory mapped registers. */ 63 #define SREG 0x5F 64 #define REG_SP 0x5D 65 #define EIND 0x5C 66 #define RAMPZ 0x5B 67 68 #define REGX 0x1a 69 #define REGY 0x1c 70 #define REGZ 0x1e 71 #define REGZ_LO 0x1e 72 #define REGZ_HI 0x1f 73 74 /* Sreg (status) bits. */ 75 #define SREG_I 0x80 76 #define SREG_T 0x40 77 #define SREG_H 0x20 78 #define SREG_S 0x10 79 #define SREG_V 0x08 80 #define SREG_N 0x04 81 #define SREG_Z 0x02 82 #define SREG_C 0x01 83 84 /* In order to speed up emulation we use a simple approach: 85 a code is associated with each instruction. The pre-decoding occurs 86 usually once when the instruction is first seen. 87 This works well because I&D spaces are separated. 88 89 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent). 90 */ 91 enum avr_opcode 92 { 93 /* Opcode not yet decoded. */ 94 OP_unknown, 95 OP_bad, 96 97 OP_nop, 98 99 OP_rjmp, 100 OP_rcall, 101 OP_ret, 102 OP_reti, 103 104 OP_break, 105 106 OP_brbs, 107 OP_brbc, 108 109 OP_bset, 110 OP_bclr, 111 112 OP_bld, 113 OP_bst, 114 115 OP_sbrc, 116 OP_sbrs, 117 118 OP_eor, 119 OP_and, 120 OP_andi, 121 OP_or, 122 OP_ori, 123 OP_com, 124 OP_swap, 125 OP_neg, 126 127 OP_out, 128 OP_in, 129 OP_cbi, 130 OP_sbi, 131 132 OP_sbic, 133 OP_sbis, 134 135 OP_ldi, 136 OP_cpse, 137 OP_cp, 138 OP_cpi, 139 OP_cpc, 140 OP_sub, 141 OP_sbc, 142 OP_sbiw, 143 OP_adiw, 144 OP_add, 145 OP_adc, 146 OP_subi, 147 OP_sbci, 148 OP_inc, 149 OP_dec, 150 OP_lsr, 151 OP_ror, 152 OP_asr, 153 154 OP_mul, 155 OP_muls, 156 OP_mulsu, 157 OP_fmul, 158 OP_fmuls, 159 OP_fmulsu, 160 161 OP_mov, 162 OP_movw, 163 164 OP_push, 165 OP_pop, 166 167 OP_st_X, 168 OP_st_dec_X, 169 OP_st_X_inc, 170 OP_st_Y_inc, 171 OP_st_dec_Y, 172 OP_st_Z_inc, 173 OP_st_dec_Z, 174 OP_std_Y, 175 OP_std_Z, 176 OP_ldd_Y, 177 OP_ldd_Z, 178 OP_ld_Z_inc, 179 OP_ld_dec_Z, 180 OP_ld_Y_inc, 181 OP_ld_dec_Y, 182 OP_ld_X, 183 OP_ld_X_inc, 184 OP_ld_dec_X, 185 186 OP_lpm, 187 OP_lpm_Z, 188 OP_lpm_inc_Z, 189 OP_elpm, 190 OP_elpm_Z, 191 OP_elpm_inc_Z, 192 193 OP_ijmp, 194 OP_icall, 195 196 OP_eijmp, 197 OP_eicall, 198 199 /* 2 words opcodes. */ 200 #define OP_2words OP_jmp 201 OP_jmp, 202 OP_call, 203 OP_sts, 204 OP_lds 205 }; 206 207 struct avr_insn_cell 208 { 209 /* The insn (16 bits). */ 210 word op; 211 212 /* Pre-decoding code. */ 213 enum avr_opcode code : 8; 214 /* One byte of additional information. */ 215 byte r; 216 }; 217 218 /* I&D memories. */ 219 /* TODO: Should be moved to SIM_CPU. */ 220 static struct avr_insn_cell flash[MAX_AVR_FLASH]; 221 static byte sram[MAX_AVR_SRAM]; 222 223 /* Sign extend a value. */ 224 static int sign_ext (word val, int nb_bits) 225 { 226 if (val & (1 << (nb_bits - 1))) 227 return val | -(1 << nb_bits); 228 return val; 229 } 230 231 /* Insn field extractors. */ 232 233 /* Extract xxxx_xxxRx_xxxx_RRRR. */ 234 static inline byte get_r (word op) 235 { 236 return (op & 0xf) | ((op >> 5) & 0x10); 237 } 238 239 /* Extract xxxx_xxxxx_xxxx_RRRR. */ 240 static inline byte get_r16 (word op) 241 { 242 return 16 + (op & 0xf); 243 } 244 245 /* Extract xxxx_xxxxx_xxxx_xRRR. */ 246 static inline byte get_r16_23 (word op) 247 { 248 return 16 + (op & 0x7); 249 } 250 251 /* Extract xxxx_xxxD_DDDD_xxxx. */ 252 static inline byte get_d (word op) 253 { 254 return (op >> 4) & 0x1f; 255 } 256 257 /* Extract xxxx_xxxx_DDDD_xxxx. */ 258 static inline byte get_d16 (word op) 259 { 260 return 16 + ((op >> 4) & 0x0f); 261 } 262 263 /* Extract xxxx_xxxx_xDDD_xxxx. */ 264 static inline byte get_d16_23 (word op) 265 { 266 return 16 + ((op >> 4) & 0x07); 267 } 268 269 /* Extract xxxx_xAAx_xxxx_AAAA. */ 270 static inline byte get_A (word op) 271 { 272 return (op & 0x0f) | ((op & 0x600) >> 5); 273 } 274 275 /* Extract xxxx_xxxx_AAAA_Axxx. */ 276 static inline byte get_biA (word op) 277 { 278 return (op >> 3) & 0x1f; 279 } 280 281 /* Extract xxxx_KKKK_xxxx_KKKK. */ 282 static inline byte get_K (word op) 283 { 284 return (op & 0xf) | ((op & 0xf00) >> 4); 285 } 286 287 /* Extract xxxx_xxKK_KKKK_Kxxx. */ 288 static inline int get_k (word op) 289 { 290 return sign_ext ((op & 0x3f8) >> 3, 7); 291 } 292 293 /* Extract xxxx_xxxx_xxDD_xxxx. */ 294 static inline byte get_d24 (word op) 295 { 296 return 24 + ((op >> 3) & 6); 297 } 298 299 /* Extract xxxx_xxxx_KKxx_KKKK. */ 300 static inline byte get_k6 (word op) 301 { 302 return (op & 0xf) | ((op >> 2) & 0x30); 303 } 304 305 /* Extract xxQx_QQxx_xxxx_xQQQ. */ 306 static inline byte get_q (word op) 307 { 308 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20); 309 } 310 311 /* Extract xxxx_xxxx_xxxx_xBBB. */ 312 static inline byte get_b (word op) 313 { 314 return (op & 7); 315 } 316 317 /* AVR is little endian. */ 318 static inline word 319 read_word (unsigned int addr) 320 { 321 return sram[addr] | (sram[addr + 1] << 8); 322 } 323 324 static inline void 325 write_word (unsigned int addr, word w) 326 { 327 sram[addr] = w; 328 sram[addr + 1] = w >> 8; 329 } 330 331 static inline word 332 read_word_post_inc (unsigned int addr) 333 { 334 word v = read_word (addr); 335 write_word (addr, v + 1); 336 return v; 337 } 338 339 static inline word 340 read_word_pre_dec (unsigned int addr) 341 { 342 word v = read_word (addr) - 1; 343 write_word (addr, v); 344 return v; 345 } 346 347 static void 348 update_flags_logic (byte res) 349 { 350 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 351 if (res == 0) 352 sram[SREG] |= SREG_Z; 353 if (res & 0x80) 354 sram[SREG] |= SREG_N | SREG_S; 355 } 356 357 static void 358 update_flags_add (byte r, byte a, byte b) 359 { 360 byte carry; 361 362 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 363 if (r & 0x80) 364 sram[SREG] |= SREG_N; 365 carry = (a & b) | (a & ~r) | (b & ~r); 366 if (carry & 0x08) 367 sram[SREG] |= SREG_H; 368 if (carry & 0x80) 369 sram[SREG] |= SREG_C; 370 if (((a & b & ~r) | (~a & ~b & r)) & 0x80) 371 sram[SREG] |= SREG_V; 372 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) 373 sram[SREG] |= SREG_S; 374 if (r == 0) 375 sram[SREG] |= SREG_Z; 376 } 377 378 static void update_flags_sub (byte r, byte a, byte b) 379 { 380 byte carry; 381 382 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 383 if (r & 0x80) 384 sram[SREG] |= SREG_N; 385 carry = (~a & b) | (b & r) | (r & ~a); 386 if (carry & 0x08) 387 sram[SREG] |= SREG_H; 388 if (carry & 0x80) 389 sram[SREG] |= SREG_C; 390 if (((a & ~b & ~r) | (~a & b & r)) & 0x80) 391 sram[SREG] |= SREG_V; 392 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) 393 sram[SREG] |= SREG_S; 394 /* Note: Z is not set. */ 395 } 396 397 static enum avr_opcode 398 decode (unsigned int pc) 399 { 400 word op1 = flash[pc].op; 401 402 switch ((op1 >> 12) & 0x0f) 403 { 404 case 0x0: 405 switch ((op1 >> 10) & 0x3) 406 { 407 case 0x0: 408 switch ((op1 >> 8) & 0x3) 409 { 410 case 0x0: 411 if (op1 == 0) 412 return OP_nop; 413 break; 414 case 0x1: 415 return OP_movw; 416 case 0x2: 417 return OP_muls; 418 case 0x3: 419 if (op1 & 0x80) 420 { 421 if (op1 & 0x08) 422 return OP_fmulsu; 423 else 424 return OP_fmuls; 425 } 426 else 427 { 428 if (op1 & 0x08) 429 return OP_fmul; 430 else 431 return OP_mulsu; 432 } 433 } 434 break; 435 case 0x1: 436 return OP_cpc; 437 case 0x2: 438 flash[pc].r = SREG_C; 439 return OP_sbc; 440 case 0x3: 441 flash[pc].r = 0; 442 return OP_add; 443 } 444 break; 445 case 0x1: 446 switch ((op1 >> 10) & 0x3) 447 { 448 case 0x0: 449 return OP_cpse; 450 case 0x1: 451 return OP_cp; 452 case 0x2: 453 flash[pc].r = 0; 454 return OP_sub; 455 case 0x3: 456 flash[pc].r = SREG_C; 457 return OP_adc; 458 } 459 break; 460 case 0x2: 461 switch ((op1 >> 10) & 0x3) 462 { 463 case 0x0: 464 return OP_and; 465 case 0x1: 466 return OP_eor; 467 case 0x2: 468 return OP_or; 469 case 0x3: 470 return OP_mov; 471 } 472 break; 473 case 0x3: 474 return OP_cpi; 475 case 0x4: 476 return OP_sbci; 477 case 0x5: 478 return OP_subi; 479 case 0x6: 480 return OP_ori; 481 case 0x7: 482 return OP_andi; 483 case 0x8: 484 case 0xa: 485 if (op1 & 0x0200) 486 { 487 if (op1 & 0x0008) 488 { 489 flash[pc].r = get_q (op1); 490 return OP_std_Y; 491 } 492 else 493 { 494 flash[pc].r = get_q (op1); 495 return OP_std_Z; 496 } 497 } 498 else 499 { 500 if (op1 & 0x0008) 501 { 502 flash[pc].r = get_q (op1); 503 return OP_ldd_Y; 504 } 505 else 506 { 507 flash[pc].r = get_q (op1); 508 return OP_ldd_Z; 509 } 510 } 511 break; 512 case 0x9: /* 9xxx */ 513 switch ((op1 >> 8) & 0xf) 514 { 515 case 0x0: 516 case 0x1: 517 switch ((op1 >> 0) & 0xf) 518 { 519 case 0x0: 520 return OP_lds; 521 case 0x1: 522 return OP_ld_Z_inc; 523 case 0x2: 524 return OP_ld_dec_Z; 525 case 0x4: 526 return OP_lpm_Z; 527 case 0x5: 528 return OP_lpm_inc_Z; 529 case 0x6: 530 return OP_elpm_Z; 531 case 0x7: 532 return OP_elpm_inc_Z; 533 case 0x9: 534 return OP_ld_Y_inc; 535 case 0xa: 536 return OP_ld_dec_Y; 537 case 0xc: 538 return OP_ld_X; 539 case 0xd: 540 return OP_ld_X_inc; 541 case 0xe: 542 return OP_ld_dec_X; 543 case 0xf: 544 return OP_pop; 545 } 546 break; 547 case 0x2: 548 case 0x3: 549 switch ((op1 >> 0) & 0xf) 550 { 551 case 0x0: 552 return OP_sts; 553 case 0x1: 554 return OP_st_Z_inc; 555 case 0x2: 556 return OP_st_dec_Z; 557 case 0x9: 558 return OP_st_Y_inc; 559 case 0xa: 560 return OP_st_dec_Y; 561 case 0xc: 562 return OP_st_X; 563 case 0xd: 564 return OP_st_X_inc; 565 case 0xe: 566 return OP_st_dec_X; 567 case 0xf: 568 return OP_push; 569 } 570 break; 571 case 0x4: 572 case 0x5: 573 switch (op1 & 0xf) 574 { 575 case 0x0: 576 return OP_com; 577 case 0x1: 578 return OP_neg; 579 case 0x2: 580 return OP_swap; 581 case 0x3: 582 return OP_inc; 583 case 0x5: 584 flash[pc].r = 0x80; 585 return OP_asr; 586 case 0x6: 587 flash[pc].r = 0; 588 return OP_lsr; 589 case 0x7: 590 return OP_ror; 591 case 0x8: /* 9[45]x8 */ 592 switch ((op1 >> 4) & 0x1f) 593 { 594 case 0x00: 595 case 0x01: 596 case 0x02: 597 case 0x03: 598 case 0x04: 599 case 0x05: 600 case 0x06: 601 case 0x07: 602 return OP_bset; 603 case 0x08: 604 case 0x09: 605 case 0x0a: 606 case 0x0b: 607 case 0x0c: 608 case 0x0d: 609 case 0x0e: 610 case 0x0f: 611 return OP_bclr; 612 case 0x10: 613 return OP_ret; 614 case 0x11: 615 return OP_reti; 616 case 0x19: 617 return OP_break; 618 case 0x1c: 619 return OP_lpm; 620 case 0x1d: 621 return OP_elpm; 622 default: 623 break; 624 } 625 break; 626 case 0x9: /* 9[45]x9 */ 627 switch ((op1 >> 4) & 0x1f) 628 { 629 case 0x00: 630 return OP_ijmp; 631 case 0x01: 632 return OP_eijmp; 633 case 0x10: 634 return OP_icall; 635 case 0x11: 636 return OP_eicall; 637 default: 638 break; 639 } 640 break; 641 case 0xa: 642 return OP_dec; 643 case 0xc: 644 case 0xd: 645 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); 646 return OP_jmp; 647 case 0xe: 648 case 0xf: 649 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); 650 return OP_call; 651 } 652 break; 653 case 0x6: 654 return OP_adiw; 655 case 0x7: 656 return OP_sbiw; 657 case 0x8: 658 return OP_cbi; 659 case 0x9: 660 return OP_sbic; 661 case 0xa: 662 return OP_sbi; 663 case 0xb: 664 return OP_sbis; 665 case 0xc: 666 case 0xd: 667 case 0xe: 668 case 0xf: 669 return OP_mul; 670 } 671 break; 672 case 0xb: 673 flash[pc].r = get_A (op1); 674 if (((op1 >> 11) & 1) == 0) 675 return OP_in; 676 else 677 return OP_out; 678 case 0xc: 679 return OP_rjmp; 680 case 0xd: 681 return OP_rcall; 682 case 0xe: 683 return OP_ldi; 684 case 0xf: 685 switch ((op1 >> 9) & 7) 686 { 687 case 0: 688 case 1: 689 flash[pc].r = 1 << (op1 & 7); 690 return OP_brbs; 691 case 2: 692 case 3: 693 flash[pc].r = 1 << (op1 & 7); 694 return OP_brbc; 695 case 4: 696 if ((op1 & 8) == 0) 697 { 698 flash[pc].r = 1 << (op1 & 7); 699 return OP_bld; 700 } 701 break; 702 case 5: 703 if ((op1 & 8) == 0) 704 { 705 flash[pc].r = 1 << (op1 & 7); 706 return OP_bst; 707 } 708 break; 709 case 6: 710 if ((op1 & 8) == 0) 711 { 712 flash[pc].r = 1 << (op1 & 7); 713 return OP_sbrc; 714 } 715 break; 716 case 7: 717 if ((op1 & 8) == 0) 718 { 719 flash[pc].r = 1 << (op1 & 7); 720 return OP_sbrs; 721 } 722 break; 723 } 724 } 725 726 return OP_bad; 727 } 728 729 static void 730 do_call (SIM_CPU *cpu, unsigned int npc) 731 { 732 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu)); 733 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu); 734 unsigned int sp = read_word (REG_SP); 735 736 /* Big endian! */ 737 sram[sp--] = avr_cpu->pc; 738 sram[sp--] = avr_cpu->pc >> 8; 739 if (state->avr_pc22) 740 { 741 sram[sp--] = avr_cpu->pc >> 16; 742 avr_cpu->cycles++; 743 } 744 write_word (REG_SP, sp); 745 avr_cpu->pc = npc & PC_MASK; 746 avr_cpu->cycles += 3; 747 } 748 749 static int 750 get_insn_length (unsigned int p) 751 { 752 if (flash[p].code == OP_unknown) 753 flash[p].code = decode(p); 754 if (flash[p].code >= OP_2words) 755 return 2; 756 else 757 return 1; 758 } 759 760 static unsigned int 761 get_z (void) 762 { 763 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO]; 764 } 765 766 static unsigned char 767 get_lpm (unsigned int addr) 768 { 769 word w; 770 771 w = flash[(addr >> 1) & PC_MASK].op; 772 if (addr & 1) 773 w >>= 8; 774 return w; 775 } 776 777 static void 778 gen_mul (SIM_CPU *cpu, unsigned int res) 779 { 780 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu); 781 782 write_word (0, res); 783 sram[SREG] &= ~(SREG_Z | SREG_C); 784 if (res == 0) 785 sram[SREG] |= SREG_Z; 786 if (res & 0x8000) 787 sram[SREG] |= SREG_C; 788 avr_cpu->cycles++; 789 } 790 791 static void 792 step_once (SIM_CPU *cpu) 793 { 794 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu); 795 unsigned int ipc; 796 797 int code; 798 word op; 799 byte res; 800 byte r, d, vd; 801 802 again: 803 code = flash[avr_cpu->pc].code; 804 op = flash[avr_cpu->pc].op; 805 806 #if 0 807 if (tracing && code != OP_unknown) 808 { 809 if (verbose > 0) { 810 int flags; 811 int i; 812 813 sim_cb_eprintf (callback, "R00-07:"); 814 for (i = 0; i < 8; i++) 815 sim_cb_eprintf (callback, " %02x", sram[i]); 816 sim_cb_eprintf (callback, " -"); 817 for (i = 8; i < 16; i++) 818 sim_cb_eprintf (callback, " %02x", sram[i]); 819 sim_cb_eprintf (callback, " SP: %02x %02x", 820 sram[REG_SP + 1], sram[REG_SP]); 821 sim_cb_eprintf (callback, "\n"); 822 sim_cb_eprintf (callback, "R16-31:"); 823 for (i = 16; i < 24; i++) 824 sim_cb_eprintf (callback, " %02x", sram[i]); 825 sim_cb_eprintf (callback, " -"); 826 for (i = 24; i < 32; i++) 827 sim_cb_eprintf (callback, " %02x", sram[i]); 828 sim_cb_eprintf (callback, " "); 829 flags = sram[SREG]; 830 for (i = 0; i < 8; i++) 831 sim_cb_eprintf (callback, "%c", 832 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-'); 833 sim_cb_eprintf (callback, "\n"); 834 } 835 836 if (!tracing) 837 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * avr_cpu->pc, flash[avr_cpu->pc].op); 838 else 839 { 840 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n", 841 2 * avr_cpu->pc, flash[avr_cpu->pc].op, code, flash[avr_cpu->pc].r); 842 disassemble_insn (CPU_STATE (cpu), avr_cpu->pc); 843 sim_cb_eprintf (callback, "\n"); 844 } 845 } 846 #endif 847 848 ipc = avr_cpu->pc; 849 avr_cpu->pc = (avr_cpu->pc + 1) & PC_MASK; 850 avr_cpu->cycles++; 851 852 switch (code) 853 { 854 case OP_unknown: 855 flash[ipc].code = decode(ipc); 856 avr_cpu->pc = ipc; 857 avr_cpu->cycles--; 858 goto again; 859 860 case OP_nop: 861 break; 862 863 case OP_jmp: 864 /* 2 words instruction, but we don't care about the pc. */ 865 avr_cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK; 866 avr_cpu->cycles += 2; 867 break; 868 869 case OP_eijmp: 870 avr_cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK; 871 avr_cpu->cycles += 2; 872 break; 873 874 case OP_ijmp: 875 avr_cpu->pc = read_word (REGZ) & PC_MASK; 876 avr_cpu->cycles += 1; 877 break; 878 879 case OP_call: 880 /* 2 words instruction. */ 881 avr_cpu->pc++; 882 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op); 883 break; 884 885 case OP_eicall: 886 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ)); 887 break; 888 889 case OP_icall: 890 do_call (cpu, read_word (REGZ)); 891 break; 892 893 case OP_rcall: 894 do_call (cpu, avr_cpu->pc + sign_ext (op & 0xfff, 12)); 895 break; 896 897 case OP_reti: 898 sram[SREG] |= SREG_I; 899 ATTRIBUTE_FALLTHROUGH; 900 case OP_ret: 901 { 902 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu)); 903 unsigned int sp = read_word (REG_SP); 904 if (state->avr_pc22) 905 { 906 avr_cpu->pc = sram[++sp] << 16; 907 avr_cpu->cycles++; 908 } 909 else 910 avr_cpu->pc = 0; 911 avr_cpu->pc |= sram[++sp] << 8; 912 avr_cpu->pc |= sram[++sp]; 913 write_word (REG_SP, sp); 914 } 915 avr_cpu->cycles += 3; 916 break; 917 918 case OP_break: 919 /* Stop on this address. */ 920 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, ipc, sim_stopped, SIM_SIGTRAP); 921 break; 922 923 case OP_bld: 924 d = get_d (op); 925 r = flash[ipc].r; 926 if (sram[SREG] & SREG_T) 927 sram[d] |= r; 928 else 929 sram[d] &= ~r; 930 break; 931 932 case OP_bst: 933 if (sram[get_d (op)] & flash[ipc].r) 934 sram[SREG] |= SREG_T; 935 else 936 sram[SREG] &= ~SREG_T; 937 break; 938 939 case OP_sbrc: 940 case OP_sbrs: 941 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0)) 942 { 943 int l = get_insn_length (avr_cpu->pc); 944 avr_cpu->pc += l; 945 avr_cpu->cycles += l; 946 } 947 break; 948 949 case OP_push: 950 { 951 unsigned int sp = read_word (REG_SP); 952 sram[sp--] = sram[get_d (op)]; 953 write_word (REG_SP, sp); 954 } 955 avr_cpu->cycles++; 956 break; 957 958 case OP_pop: 959 { 960 unsigned int sp = read_word (REG_SP); 961 sram[get_d (op)] = sram[++sp]; 962 write_word (REG_SP, sp); 963 } 964 avr_cpu->cycles++; 965 break; 966 967 case OP_bclr: 968 sram[SREG] &= ~(1 << ((op >> 4) & 0x7)); 969 break; 970 971 case OP_bset: 972 sram[SREG] |= 1 << ((op >> 4) & 0x7); 973 break; 974 975 case OP_rjmp: 976 avr_cpu->pc = (avr_cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK; 977 avr_cpu->cycles++; 978 break; 979 980 case OP_eor: 981 d = get_d (op); 982 res = sram[d] ^ sram[get_r (op)]; 983 sram[d] = res; 984 update_flags_logic (res); 985 break; 986 987 case OP_and: 988 d = get_d (op); 989 res = sram[d] & sram[get_r (op)]; 990 sram[d] = res; 991 update_flags_logic (res); 992 break; 993 994 case OP_andi: 995 d = get_d16 (op); 996 res = sram[d] & get_K (op); 997 sram[d] = res; 998 update_flags_logic (res); 999 break; 1000 1001 case OP_or: 1002 d = get_d (op); 1003 res = sram[d] | sram[get_r (op)]; 1004 sram[d] = res; 1005 update_flags_logic (res); 1006 break; 1007 1008 case OP_ori: 1009 d = get_d16 (op); 1010 res = sram[d] | get_K (op); 1011 sram[d] = res; 1012 update_flags_logic (res); 1013 break; 1014 1015 case OP_com: 1016 d = get_d (op); 1017 res = ~sram[d]; 1018 sram[d] = res; 1019 update_flags_logic (res); 1020 sram[SREG] |= SREG_C; 1021 break; 1022 1023 case OP_swap: 1024 d = get_d (op); 1025 vd = sram[d]; 1026 sram[d] = (vd >> 4) | (vd << 4); 1027 break; 1028 1029 case OP_neg: 1030 d = get_d (op); 1031 vd = sram[d]; 1032 res = -vd; 1033 sram[d] = res; 1034 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1035 if (res == 0) 1036 sram[SREG] |= SREG_Z; 1037 else 1038 sram[SREG] |= SREG_C; 1039 if (res == 0x80) 1040 sram[SREG] |= SREG_V | SREG_N; 1041 else if (res & 0x80) 1042 sram[SREG] |= SREG_N | SREG_S; 1043 if ((res | vd) & 0x08) 1044 sram[SREG] |= SREG_H; 1045 break; 1046 1047 case OP_inc: 1048 d = get_d (op); 1049 res = sram[d] + 1; 1050 sram[d] = res; 1051 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 1052 if (res == 0x80) 1053 sram[SREG] |= SREG_V | SREG_N; 1054 else if (res & 0x80) 1055 sram[SREG] |= SREG_N | SREG_S; 1056 else if (res == 0) 1057 sram[SREG] |= SREG_Z; 1058 break; 1059 1060 case OP_dec: 1061 d = get_d (op); 1062 res = sram[d] - 1; 1063 sram[d] = res; 1064 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); 1065 if (res == 0x7f) 1066 sram[SREG] |= SREG_V | SREG_S; 1067 else if (res & 0x80) 1068 sram[SREG] |= SREG_N | SREG_S; 1069 else if (res == 0) 1070 sram[SREG] |= SREG_Z; 1071 break; 1072 1073 case OP_lsr: 1074 case OP_asr: 1075 d = get_d (op); 1076 vd = sram[d]; 1077 res = (vd >> 1) | (vd & flash[ipc].r); 1078 sram[d] = res; 1079 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1080 if (vd & 1) 1081 sram[SREG] |= SREG_C | SREG_S; 1082 if (res & 0x80) 1083 sram[SREG] |= SREG_N; 1084 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) 1085 sram[SREG] |= SREG_V; 1086 if (res == 0) 1087 sram[SREG] |= SREG_Z; 1088 break; 1089 1090 case OP_ror: 1091 d = get_d (op); 1092 vd = sram[d]; 1093 res = vd >> 1 | (sram[SREG] << 7); 1094 sram[d] = res; 1095 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1096 if (vd & 1) 1097 sram[SREG] |= SREG_C | SREG_S; 1098 if (res & 0x80) 1099 sram[SREG] |= SREG_N; 1100 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) 1101 sram[SREG] |= SREG_V; 1102 if (res == 0) 1103 sram[SREG] |= SREG_Z; 1104 break; 1105 1106 case OP_mul: 1107 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]); 1108 break; 1109 1110 case OP_muls: 1111 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)] 1112 * (sword)(sbyte)sram[get_d16 (op)]); 1113 break; 1114 1115 case OP_mulsu: 1116 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)] 1117 * (sword)(sbyte)sram[get_d16_23 (op)]); 1118 break; 1119 1120 case OP_fmul: 1121 gen_mul (cpu, ((word)sram[get_r16_23 (op)] 1122 * (word)sram[get_d16_23 (op)]) << 1); 1123 break; 1124 1125 case OP_fmuls: 1126 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)] 1127 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); 1128 break; 1129 1130 case OP_fmulsu: 1131 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)] 1132 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); 1133 break; 1134 1135 case OP_adc: 1136 case OP_add: 1137 r = sram[get_r (op)]; 1138 d = get_d (op); 1139 vd = sram[d]; 1140 res = r + vd + (sram[SREG] & flash[ipc].r); 1141 sram[d] = res; 1142 update_flags_add (res, vd, r); 1143 break; 1144 1145 case OP_sub: 1146 d = get_d (op); 1147 vd = sram[d]; 1148 r = sram[get_r (op)]; 1149 res = vd - r; 1150 sram[d] = res; 1151 update_flags_sub (res, vd, r); 1152 if (res == 0) 1153 sram[SREG] |= SREG_Z; 1154 break; 1155 1156 case OP_sbc: 1157 { 1158 byte old = sram[SREG]; 1159 d = get_d (op); 1160 vd = sram[d]; 1161 r = sram[get_r (op)]; 1162 res = vd - r - (old & SREG_C); 1163 sram[d] = res; 1164 update_flags_sub (res, vd, r); 1165 if (res == 0 && (old & SREG_Z)) 1166 sram[SREG] |= SREG_Z; 1167 } 1168 break; 1169 1170 case OP_subi: 1171 d = get_d16 (op); 1172 vd = sram[d]; 1173 r = get_K (op); 1174 res = vd - r; 1175 sram[d] = res; 1176 update_flags_sub (res, vd, r); 1177 if (res == 0) 1178 sram[SREG] |= SREG_Z; 1179 break; 1180 1181 case OP_sbci: 1182 { 1183 byte old = sram[SREG]; 1184 1185 d = get_d16 (op); 1186 vd = sram[d]; 1187 r = get_K (op); 1188 res = vd - r - (old & SREG_C); 1189 sram[d] = res; 1190 update_flags_sub (res, vd, r); 1191 if (res == 0 && (old & SREG_Z)) 1192 sram[SREG] |= SREG_Z; 1193 } 1194 break; 1195 1196 case OP_mov: 1197 sram[get_d (op)] = sram[get_r (op)]; 1198 break; 1199 1200 case OP_movw: 1201 d = (op & 0xf0) >> 3; 1202 r = (op & 0x0f) << 1; 1203 sram[d] = sram[r]; 1204 sram[d + 1] = sram[r + 1]; 1205 break; 1206 1207 case OP_out: 1208 d = get_A (op) + 0x20; 1209 res = sram[get_d (op)]; 1210 sram[d] = res; 1211 if (d == STDIO_PORT) 1212 putchar (res); 1213 else if (d == EXIT_PORT) 1214 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_exited, 0); 1215 else if (d == ABORT_PORT) 1216 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_exited, 1); 1217 break; 1218 1219 case OP_in: 1220 d = get_A (op) + 0x20; 1221 sram[get_d (op)] = sram[d]; 1222 break; 1223 1224 case OP_cbi: 1225 d = get_biA (op) + 0x20; 1226 sram[d] &= ~(1 << get_b(op)); 1227 break; 1228 1229 case OP_sbi: 1230 d = get_biA (op) + 0x20; 1231 sram[d] |= 1 << get_b(op); 1232 break; 1233 1234 case OP_sbic: 1235 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op))) 1236 { 1237 int l = get_insn_length (avr_cpu->pc); 1238 avr_cpu->pc += l; 1239 avr_cpu->cycles += l; 1240 } 1241 break; 1242 1243 case OP_sbis: 1244 if (sram[get_biA (op) + 0x20] & 1 << get_b(op)) 1245 { 1246 int l = get_insn_length (avr_cpu->pc); 1247 avr_cpu->pc += l; 1248 avr_cpu->cycles += l; 1249 } 1250 break; 1251 1252 case OP_ldi: 1253 res = get_K (op); 1254 d = get_d16 (op); 1255 sram[d] = res; 1256 break; 1257 1258 case OP_lds: 1259 sram[get_d (op)] = sram[flash[avr_cpu->pc].op]; 1260 avr_cpu->pc++; 1261 avr_cpu->cycles++; 1262 break; 1263 1264 case OP_sts: 1265 sram[flash[avr_cpu->pc].op] = sram[get_d (op)]; 1266 avr_cpu->pc++; 1267 avr_cpu->cycles++; 1268 break; 1269 1270 case OP_cpse: 1271 if (sram[get_r (op)] == sram[get_d (op)]) 1272 { 1273 int l = get_insn_length (avr_cpu->pc); 1274 avr_cpu->pc += l; 1275 avr_cpu->cycles += l; 1276 } 1277 break; 1278 1279 case OP_cp: 1280 r = sram[get_r (op)]; 1281 d = sram[get_d (op)]; 1282 res = d - r; 1283 update_flags_sub (res, d, r); 1284 if (res == 0) 1285 sram[SREG] |= SREG_Z; 1286 break; 1287 1288 case OP_cpi: 1289 r = get_K (op); 1290 d = sram[get_d16 (op)]; 1291 res = d - r; 1292 update_flags_sub (res, d, r); 1293 if (res == 0) 1294 sram[SREG] |= SREG_Z; 1295 break; 1296 1297 case OP_cpc: 1298 { 1299 byte old = sram[SREG]; 1300 d = sram[get_d (op)]; 1301 r = sram[get_r (op)]; 1302 res = d - r - (old & SREG_C); 1303 update_flags_sub (res, d, r); 1304 if (res == 0 && (old & SREG_Z)) 1305 sram[SREG] |= SREG_Z; 1306 } 1307 break; 1308 1309 case OP_brbc: 1310 if (!(sram[SREG] & flash[ipc].r)) 1311 { 1312 avr_cpu->pc = (avr_cpu->pc + get_k (op)) & PC_MASK; 1313 avr_cpu->cycles++; 1314 } 1315 break; 1316 1317 case OP_brbs: 1318 if (sram[SREG] & flash[ipc].r) 1319 { 1320 avr_cpu->pc = (avr_cpu->pc + get_k (op)) & PC_MASK; 1321 avr_cpu->cycles++; 1322 } 1323 break; 1324 1325 case OP_lpm: 1326 sram[0] = get_lpm (read_word (REGZ)); 1327 avr_cpu->cycles += 2; 1328 break; 1329 1330 case OP_lpm_Z: 1331 sram[get_d (op)] = get_lpm (read_word (REGZ)); 1332 avr_cpu->cycles += 2; 1333 break; 1334 1335 case OP_lpm_inc_Z: 1336 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ)); 1337 avr_cpu->cycles += 2; 1338 break; 1339 1340 case OP_elpm: 1341 sram[0] = get_lpm (get_z ()); 1342 avr_cpu->cycles += 2; 1343 break; 1344 1345 case OP_elpm_Z: 1346 sram[get_d (op)] = get_lpm (get_z ()); 1347 avr_cpu->cycles += 2; 1348 break; 1349 1350 case OP_elpm_inc_Z: 1351 { 1352 unsigned int z = get_z (); 1353 1354 sram[get_d (op)] = get_lpm (z); 1355 z++; 1356 sram[REGZ_LO] = z; 1357 sram[REGZ_HI] = z >> 8; 1358 sram[RAMPZ] = z >> 16; 1359 } 1360 avr_cpu->cycles += 2; 1361 break; 1362 1363 case OP_ld_Z_inc: 1364 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK]; 1365 avr_cpu->cycles++; 1366 break; 1367 1368 case OP_ld_dec_Z: 1369 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK]; 1370 avr_cpu->cycles++; 1371 break; 1372 1373 case OP_ld_X_inc: 1374 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK]; 1375 avr_cpu->cycles++; 1376 break; 1377 1378 case OP_ld_dec_X: 1379 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK]; 1380 avr_cpu->cycles++; 1381 break; 1382 1383 case OP_ld_Y_inc: 1384 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK]; 1385 avr_cpu->cycles++; 1386 break; 1387 1388 case OP_ld_dec_Y: 1389 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK]; 1390 avr_cpu->cycles++; 1391 break; 1392 1393 case OP_st_X: 1394 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)]; 1395 avr_cpu->cycles++; 1396 break; 1397 1398 case OP_st_X_inc: 1399 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)]; 1400 avr_cpu->cycles++; 1401 break; 1402 1403 case OP_st_dec_X: 1404 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)]; 1405 avr_cpu->cycles++; 1406 break; 1407 1408 case OP_st_Z_inc: 1409 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)]; 1410 avr_cpu->cycles++; 1411 break; 1412 1413 case OP_st_dec_Z: 1414 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)]; 1415 avr_cpu->cycles++; 1416 break; 1417 1418 case OP_st_Y_inc: 1419 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)]; 1420 avr_cpu->cycles++; 1421 break; 1422 1423 case OP_st_dec_Y: 1424 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)]; 1425 avr_cpu->cycles++; 1426 break; 1427 1428 case OP_std_Y: 1429 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)]; 1430 avr_cpu->cycles++; 1431 break; 1432 1433 case OP_std_Z: 1434 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)]; 1435 avr_cpu->cycles++; 1436 break; 1437 1438 case OP_ldd_Z: 1439 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r]; 1440 avr_cpu->cycles++; 1441 break; 1442 1443 case OP_ldd_Y: 1444 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r]; 1445 avr_cpu->cycles++; 1446 break; 1447 1448 case OP_ld_X: 1449 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK]; 1450 avr_cpu->cycles++; 1451 break; 1452 1453 case OP_sbiw: 1454 { 1455 word wk = get_k6 (op); 1456 word wres; 1457 word wr; 1458 1459 d = get_d24 (op); 1460 wr = read_word (d); 1461 wres = wr - wk; 1462 1463 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1464 if (wres == 0) 1465 sram[SREG] |= SREG_Z; 1466 if (wres & 0x8000) 1467 sram[SREG] |= SREG_N; 1468 if (wres & ~wr & 0x8000) 1469 sram[SREG] |= SREG_C; 1470 if (~wres & wr & 0x8000) 1471 sram[SREG] |= SREG_V; 1472 if (((~wres & wr) ^ wres) & 0x8000) 1473 sram[SREG] |= SREG_S; 1474 write_word (d, wres); 1475 } 1476 avr_cpu->cycles++; 1477 break; 1478 1479 case OP_adiw: 1480 { 1481 word wk = get_k6 (op); 1482 word wres; 1483 word wr; 1484 1485 d = get_d24 (op); 1486 wr = read_word (d); 1487 wres = wr + wk; 1488 1489 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); 1490 if (wres == 0) 1491 sram[SREG] |= SREG_Z; 1492 if (wres & 0x8000) 1493 sram[SREG] |= SREG_N; 1494 if (~wres & wr & 0x8000) 1495 sram[SREG] |= SREG_C; 1496 if (wres & ~wr & 0x8000) 1497 sram[SREG] |= SREG_V; 1498 if (((wres & ~wr) ^ wres) & 0x8000) 1499 sram[SREG] |= SREG_S; 1500 write_word (d, wres); 1501 } 1502 avr_cpu->cycles++; 1503 break; 1504 1505 case OP_bad: 1506 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_signalled, SIM_SIGILL); 1507 1508 default: 1509 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_signalled, SIM_SIGILL); 1510 } 1511 } 1512 1513 void 1514 sim_engine_run (SIM_DESC sd, 1515 int next_cpu_nr, /* ignore */ 1516 int nr_cpus, /* ignore */ 1517 int siggnal) /* ignore */ 1518 { 1519 SIM_CPU *cpu; 1520 1521 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1522 1523 cpu = STATE_CPU (sd, 0); 1524 1525 while (1) 1526 { 1527 step_once (cpu); 1528 if (sim_events_tick (sd)) 1529 sim_events_process (sd); 1530 } 1531 } 1532 1533 uint64_t 1534 sim_write (SIM_DESC sd, uint64_t addr, const void *buffer, uint64_t size) 1535 { 1536 int osize = size; 1537 1538 if (addr >= 0 && addr < SRAM_VADDR) 1539 { 1540 const unsigned char *data = buffer; 1541 while (size > 0 && addr < (MAX_AVR_FLASH << 1)) 1542 { 1543 word val = flash[addr >> 1].op; 1544 1545 if (addr & 1) 1546 val = (val & 0xff) | (data[0] << 8); 1547 else 1548 val = (val & 0xff00) | data[0]; 1549 1550 flash[addr >> 1].op = val; 1551 flash[addr >> 1].code = OP_unknown; 1552 addr++; 1553 data++; 1554 size--; 1555 } 1556 return osize - size; 1557 } 1558 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) 1559 { 1560 addr -= SRAM_VADDR; 1561 if (addr + size > MAX_AVR_SRAM) 1562 size = MAX_AVR_SRAM - addr; 1563 memcpy (sram + addr, buffer, size); 1564 return size; 1565 } 1566 else 1567 return 0; 1568 } 1569 1570 uint64_t 1571 sim_read (SIM_DESC sd, uint64_t addr, void *buffer, uint64_t size) 1572 { 1573 int osize = size; 1574 1575 if (addr >= 0 && addr < SRAM_VADDR) 1576 { 1577 unsigned char *data = buffer; 1578 while (size > 0 && addr < (MAX_AVR_FLASH << 1)) 1579 { 1580 word val = flash[addr >> 1].op; 1581 1582 if (addr & 1) 1583 val >>= 8; 1584 1585 *data++ = val; 1586 addr++; 1587 size--; 1588 } 1589 return osize - size; 1590 } 1591 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) 1592 { 1593 addr -= SRAM_VADDR; 1594 if (addr + size > MAX_AVR_SRAM) 1595 size = MAX_AVR_SRAM - addr; 1596 memcpy (buffer, sram + addr, size); 1597 return size; 1598 } 1599 else 1600 { 1601 /* Avoid errors. */ 1602 memset (buffer, 0, size); 1603 return size; 1604 } 1605 } 1606 1607 static int 1608 avr_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length) 1609 { 1610 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu); 1611 const unsigned char *memory = buf; 1612 1613 if (rn < 32 && length == 1) 1614 { 1615 sram[rn] = *memory; 1616 return 1; 1617 } 1618 if (rn == AVR_SREG_REGNUM && length == 1) 1619 { 1620 sram[SREG] = *memory; 1621 return 1; 1622 } 1623 if (rn == AVR_SP_REGNUM && length == 2) 1624 { 1625 sram[REG_SP] = memory[0]; 1626 sram[REG_SP + 1] = memory[1]; 1627 return 2; 1628 } 1629 if (rn == AVR_PC_REGNUM && length == 4) 1630 { 1631 avr_cpu->pc = (memory[0] >> 1) | (memory[1] << 7) 1632 | (memory[2] << 15) | (memory[3] << 23); 1633 avr_cpu->pc &= PC_MASK; 1634 return 4; 1635 } 1636 return 0; 1637 } 1638 1639 static int 1640 avr_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length) 1641 { 1642 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu); 1643 unsigned char *memory = buf; 1644 1645 if (rn < 32 && length == 1) 1646 { 1647 *memory = sram[rn]; 1648 return 1; 1649 } 1650 if (rn == AVR_SREG_REGNUM && length == 1) 1651 { 1652 *memory = sram[SREG]; 1653 return 1; 1654 } 1655 if (rn == AVR_SP_REGNUM && length == 2) 1656 { 1657 memory[0] = sram[REG_SP]; 1658 memory[1] = sram[REG_SP + 1]; 1659 return 2; 1660 } 1661 if (rn == AVR_PC_REGNUM && length == 4) 1662 { 1663 memory[0] = avr_cpu->pc << 1; 1664 memory[1] = avr_cpu->pc >> 7; 1665 memory[2] = avr_cpu->pc >> 15; 1666 memory[3] = avr_cpu->pc >> 23; 1667 return 4; 1668 } 1669 return 0; 1670 } 1671 1672 static sim_cia 1673 avr_pc_get (sim_cpu *cpu) 1674 { 1675 return AVR_SIM_CPU (cpu)->pc; 1676 } 1677 1678 static void 1679 avr_pc_set (sim_cpu *cpu, sim_cia pc) 1680 { 1681 AVR_SIM_CPU (cpu)->pc = pc; 1682 } 1683 1684 static void 1685 free_state (SIM_DESC sd) 1686 { 1687 if (STATE_MODULES (sd) != NULL) 1688 sim_module_uninstall (sd); 1689 sim_cpu_free_all (sd); 1690 sim_state_free (sd); 1691 } 1692 1693 SIM_DESC 1694 sim_open (SIM_OPEN_KIND kind, host_callback *cb, 1695 struct bfd *abfd, char * const *argv) 1696 { 1697 int i; 1698 SIM_DESC sd = sim_state_alloc_extra (kind, cb, sizeof (struct avr_sim_state)); 1699 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 1700 1701 /* Set default options before parsing user options. */ 1702 current_alignment = STRICT_ALIGNMENT; 1703 current_target_byte_order = BFD_ENDIAN_LITTLE; 1704 1705 /* The cpu data is kept in a separately allocated chunk of memory. */ 1706 if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct avr_sim_cpu)) 1707 != SIM_RC_OK) 1708 { 1709 free_state (sd); 1710 return 0; 1711 } 1712 1713 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 1714 { 1715 free_state (sd); 1716 return 0; 1717 } 1718 1719 /* The parser will print an error message for us, so we silently return. */ 1720 if (sim_parse_args (sd, argv) != SIM_RC_OK) 1721 { 1722 free_state (sd); 1723 return 0; 1724 } 1725 1726 /* Check for/establish the a reference program image. */ 1727 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK) 1728 { 1729 free_state (sd); 1730 return 0; 1731 } 1732 1733 /* Configure/verify the target byte order and other runtime 1734 configuration options. */ 1735 if (sim_config (sd) != SIM_RC_OK) 1736 { 1737 sim_module_uninstall (sd); 1738 return 0; 1739 } 1740 1741 if (sim_post_argv_init (sd) != SIM_RC_OK) 1742 { 1743 /* Uninstall the modules to avoid memory leaks, 1744 file descriptor leaks, etc. */ 1745 sim_module_uninstall (sd); 1746 return 0; 1747 } 1748 1749 /* CPU specific initialization. */ 1750 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 1751 { 1752 SIM_CPU *cpu = STATE_CPU (sd, i); 1753 1754 CPU_REG_FETCH (cpu) = avr_reg_fetch; 1755 CPU_REG_STORE (cpu) = avr_reg_store; 1756 CPU_PC_FETCH (cpu) = avr_pc_get; 1757 CPU_PC_STORE (cpu) = avr_pc_set; 1758 } 1759 1760 /* Clear all the memory. */ 1761 memset (sram, 0, sizeof (sram)); 1762 memset (flash, 0, sizeof (flash)); 1763 1764 return sd; 1765 } 1766 1767 SIM_RC 1768 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, 1769 char * const *argv, char * const *env) 1770 { 1771 struct avr_sim_state *state = AVR_SIM_STATE (sd); 1772 SIM_CPU *cpu = STATE_CPU (sd, 0); 1773 bfd_vma addr; 1774 1775 /* Set the PC. */ 1776 if (abfd != NULL) 1777 addr = bfd_get_start_address (abfd); 1778 else 1779 addr = 0; 1780 sim_pc_set (cpu, addr); 1781 1782 if (abfd != NULL) 1783 state->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6); 1784 1785 return SIM_RC_OK; 1786 } 1787