1 /* riscv-opc.h. RISC-V instruction opcode and CSR macros. 2 Copyright (C) 2011-2024 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 3, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; see the file COPYING3. If not, 19 see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef RISCV_ENCODING_H 22 #define RISCV_ENCODING_H 23 /* Instruction opcode macros. */ 24 #define MATCH_SLLI_RV32 0x1013 25 #define MASK_SLLI_RV32 0xfe00707f 26 #define MATCH_SRLI_RV32 0x5013 27 #define MASK_SRLI_RV32 0xfe00707f 28 #define MATCH_SRAI_RV32 0x40005013 29 #define MASK_SRAI_RV32 0xfe00707f 30 #define MATCH_FRFLAGS 0x102073 31 #define MASK_FRFLAGS 0xfffff07f 32 #define MATCH_FSFLAGS 0x101073 33 #define MASK_FSFLAGS 0xfff0707f 34 #define MATCH_FSFLAGSI 0x105073 35 #define MASK_FSFLAGSI 0xfff0707f 36 #define MATCH_FRRM 0x202073 37 #define MASK_FRRM 0xfffff07f 38 #define MATCH_FSRM 0x201073 39 #define MASK_FSRM 0xfff0707f 40 #define MATCH_FSRMI 0x205073 41 #define MASK_FSRMI 0xfff0707f 42 #define MATCH_FSCSR 0x301073 43 #define MASK_FSCSR 0xfff0707f 44 #define MATCH_FRCSR 0x302073 45 #define MASK_FRCSR 0xfffff07f 46 #define MATCH_RDCYCLE 0xc0002073 47 #define MASK_RDCYCLE 0xfffff07f 48 #define MATCH_RDTIME 0xc0102073 49 #define MASK_RDTIME 0xfffff07f 50 #define MATCH_RDINSTRET 0xc0202073 51 #define MASK_RDINSTRET 0xfffff07f 52 #define MATCH_RDCYCLEH 0xc8002073 53 #define MASK_RDCYCLEH 0xfffff07f 54 #define MATCH_RDTIMEH 0xc8102073 55 #define MASK_RDTIMEH 0xfffff07f 56 #define MATCH_RDINSTRETH 0xc8202073 57 #define MASK_RDINSTRETH 0xfffff07f 58 #define MATCH_SCALL 0x73 59 #define MASK_SCALL 0xffffffff 60 #define MATCH_SBREAK 0x100073 61 #define MASK_SBREAK 0xffffffff 62 #define MATCH_BEQ 0x63 63 #define MASK_BEQ 0x707f 64 #define MATCH_BNE 0x1063 65 #define MASK_BNE 0x707f 66 #define MATCH_BLT 0x4063 67 #define MASK_BLT 0x707f 68 #define MATCH_BGE 0x5063 69 #define MASK_BGE 0x707f 70 #define MATCH_BLTU 0x6063 71 #define MASK_BLTU 0x707f 72 #define MATCH_BGEU 0x7063 73 #define MASK_BGEU 0x707f 74 #define MATCH_JALR 0x67 75 #define MASK_JALR 0x707f 76 #define MATCH_JAL 0x6f 77 #define MASK_JAL 0x7f 78 #define MATCH_LUI 0x37 79 #define MASK_LUI 0x7f 80 #define MATCH_AUIPC 0x17 81 #define MASK_AUIPC 0x7f 82 #define MATCH_ADDI 0x13 83 #define MASK_ADDI 0x707f 84 #define MATCH_SLLI 0x1013 85 #define MASK_SLLI 0xfc00707f 86 #define MATCH_SLTI 0x2013 87 #define MASK_SLTI 0x707f 88 #define MATCH_SLTIU 0x3013 89 #define MASK_SLTIU 0x707f 90 #define MATCH_XORI 0x4013 91 #define MASK_XORI 0x707f 92 #define MATCH_SRLI 0x5013 93 #define MASK_SRLI 0xfc00707f 94 #define MATCH_SRAI 0x40005013 95 #define MASK_SRAI 0xfc00707f 96 #define MATCH_ORI 0x6013 97 #define MASK_ORI 0x707f 98 #define MATCH_ANDI 0x7013 99 #define MASK_ANDI 0x707f 100 #define MATCH_ADD 0x33 101 #define MASK_ADD 0xfe00707f 102 #define MATCH_SUB 0x40000033 103 #define MASK_SUB 0xfe00707f 104 #define MATCH_SLL 0x1033 105 #define MASK_SLL 0xfe00707f 106 #define MATCH_SLT 0x2033 107 #define MASK_SLT 0xfe00707f 108 #define MATCH_SLTU 0x3033 109 #define MASK_SLTU 0xfe00707f 110 #define MATCH_XOR 0x4033 111 #define MASK_XOR 0xfe00707f 112 #define MATCH_SRL 0x5033 113 #define MASK_SRL 0xfe00707f 114 #define MATCH_SRA 0x40005033 115 #define MASK_SRA 0xfe00707f 116 #define MATCH_OR 0x6033 117 #define MASK_OR 0xfe00707f 118 #define MATCH_AND 0x7033 119 #define MASK_AND 0xfe00707f 120 #define MATCH_ADDIW 0x1b 121 #define MASK_ADDIW 0x707f 122 #define MATCH_SLLIW 0x101b 123 #define MASK_SLLIW 0xfe00707f 124 #define MATCH_SRLIW 0x501b 125 #define MASK_SRLIW 0xfe00707f 126 #define MATCH_SRAIW 0x4000501b 127 #define MASK_SRAIW 0xfe00707f 128 #define MATCH_ADDW 0x3b 129 #define MASK_ADDW 0xfe00707f 130 #define MATCH_SUBW 0x4000003b 131 #define MASK_SUBW 0xfe00707f 132 #define MATCH_SLLW 0x103b 133 #define MASK_SLLW 0xfe00707f 134 #define MATCH_SRLW 0x503b 135 #define MASK_SRLW 0xfe00707f 136 #define MATCH_SRAW 0x4000503b 137 #define MASK_SRAW 0xfe00707f 138 #define MATCH_LB 0x3 139 #define MASK_LB 0x707f 140 #define MATCH_LH 0x1003 141 #define MASK_LH 0x707f 142 #define MATCH_LW 0x2003 143 #define MASK_LW 0x707f 144 #define MATCH_LD 0x3003 145 #define MASK_LD 0x707f 146 #define MATCH_LBU 0x4003 147 #define MASK_LBU 0x707f 148 #define MATCH_LHU 0x5003 149 #define MASK_LHU 0x707f 150 #define MATCH_LWU 0x6003 151 #define MASK_LWU 0x707f 152 #define MATCH_SB 0x23 153 #define MASK_SB 0x707f 154 #define MATCH_SH 0x1023 155 #define MASK_SH 0x707f 156 #define MATCH_SW 0x2023 157 #define MASK_SW 0x707f 158 #define MATCH_SD 0x3023 159 #define MASK_SD 0x707f 160 #define MATCH_PAUSE 0x0100000f 161 #define MASK_PAUSE 0xffffffff 162 #define MATCH_FENCE 0xf 163 #define MASK_FENCE 0x707f 164 #define MATCH_FENCE_I 0x100f 165 #define MASK_FENCE_I 0x707f 166 #define MATCH_FENCE_TSO 0x8330000f 167 #define MASK_FENCE_TSO 0xfff0707f 168 #define MATCH_MUL 0x2000033 169 #define MASK_MUL 0xfe00707f 170 #define MATCH_MULH 0x2001033 171 #define MASK_MULH 0xfe00707f 172 #define MATCH_MULHSU 0x2002033 173 #define MASK_MULHSU 0xfe00707f 174 #define MATCH_MULHU 0x2003033 175 #define MASK_MULHU 0xfe00707f 176 #define MATCH_DIV 0x2004033 177 #define MASK_DIV 0xfe00707f 178 #define MATCH_DIVU 0x2005033 179 #define MASK_DIVU 0xfe00707f 180 #define MATCH_REM 0x2006033 181 #define MASK_REM 0xfe00707f 182 #define MATCH_REMU 0x2007033 183 #define MASK_REMU 0xfe00707f 184 #define MATCH_MULW 0x200003b 185 #define MASK_MULW 0xfe00707f 186 #define MATCH_DIVW 0x200403b 187 #define MASK_DIVW 0xfe00707f 188 #define MATCH_DIVUW 0x200503b 189 #define MASK_DIVUW 0xfe00707f 190 #define MATCH_REMW 0x200603b 191 #define MASK_REMW 0xfe00707f 192 #define MATCH_REMUW 0x200703b 193 #define MASK_REMUW 0xfe00707f 194 #define MATCH_AMOADD_W 0x202f 195 #define MASK_AMOADD_W 0xf800707f 196 #define MATCH_AMOXOR_W 0x2000202f 197 #define MASK_AMOXOR_W 0xf800707f 198 #define MATCH_AMOOR_W 0x4000202f 199 #define MASK_AMOOR_W 0xf800707f 200 #define MATCH_AMOAND_W 0x6000202f 201 #define MASK_AMOAND_W 0xf800707f 202 #define MATCH_AMOMIN_W 0x8000202f 203 #define MASK_AMOMIN_W 0xf800707f 204 #define MATCH_AMOMAX_W 0xa000202f 205 #define MASK_AMOMAX_W 0xf800707f 206 #define MATCH_AMOMINU_W 0xc000202f 207 #define MASK_AMOMINU_W 0xf800707f 208 #define MATCH_AMOMAXU_W 0xe000202f 209 #define MASK_AMOMAXU_W 0xf800707f 210 #define MATCH_AMOSWAP_W 0x800202f 211 #define MASK_AMOSWAP_W 0xf800707f 212 #define MATCH_LR_W 0x1000202f 213 #define MASK_LR_W 0xf9f0707f 214 #define MATCH_SC_W 0x1800202f 215 #define MASK_SC_W 0xf800707f 216 #define MATCH_AMOADD_D 0x302f 217 #define MASK_AMOADD_D 0xf800707f 218 #define MATCH_AMOXOR_D 0x2000302f 219 #define MASK_AMOXOR_D 0xf800707f 220 #define MATCH_AMOOR_D 0x4000302f 221 #define MASK_AMOOR_D 0xf800707f 222 #define MATCH_AMOAND_D 0x6000302f 223 #define MASK_AMOAND_D 0xf800707f 224 #define MATCH_AMOMIN_D 0x8000302f 225 #define MASK_AMOMIN_D 0xf800707f 226 #define MATCH_AMOMAX_D 0xa000302f 227 #define MASK_AMOMAX_D 0xf800707f 228 #define MATCH_AMOMINU_D 0xc000302f 229 #define MASK_AMOMINU_D 0xf800707f 230 #define MATCH_AMOMAXU_D 0xe000302f 231 #define MASK_AMOMAXU_D 0xf800707f 232 #define MATCH_AMOSWAP_D 0x800302f 233 #define MASK_AMOSWAP_D 0xf800707f 234 #define MATCH_LR_D 0x1000302f 235 #define MASK_LR_D 0xf9f0707f 236 #define MATCH_SC_D 0x1800302f 237 #define MASK_SC_D 0xf800707f 238 #define MATCH_AMOADD_B 0x02f 239 #define MASK_AMOADD_B 0xf800707f 240 #define MATCH_AMOXOR_B 0x2000002f 241 #define MASK_AMOXOR_B 0xf800707f 242 #define MATCH_AMOOR_B 0x4000002f 243 #define MASK_AMOOR_B 0xf800707f 244 #define MATCH_AMOAND_B 0x6000002f 245 #define MASK_AMOAND_B 0xf800707f 246 #define MATCH_AMOMIN_B 0x8000002f 247 #define MASK_AMOMIN_B 0xf800707f 248 #define MATCH_AMOMAX_B 0xa000002f 249 #define MASK_AMOMAX_B 0xf800707f 250 #define MATCH_AMOMINU_B 0xc000002f 251 #define MASK_AMOMINU_B 0xf800707f 252 #define MATCH_AMOMAXU_B 0xe000002f 253 #define MASK_AMOMAXU_B 0xf800707f 254 #define MATCH_AMOSWAP_B 0x800002f 255 #define MASK_AMOSWAP_B 0xf800707f 256 #define MATCH_AMOADD_H 0x102f 257 #define MASK_AMOADD_H 0xf800707f 258 #define MATCH_AMOXOR_H 0x2000102f 259 #define MASK_AMOXOR_H 0xf800707f 260 #define MATCH_AMOOR_H 0x4000102f 261 #define MASK_AMOOR_H 0xf800707f 262 #define MATCH_AMOAND_H 0x6000102f 263 #define MASK_AMOAND_H 0xf800707f 264 #define MATCH_AMOMIN_H 0x8000102f 265 #define MASK_AMOMIN_H 0xf800707f 266 #define MATCH_AMOMAX_H 0xa000102f 267 #define MASK_AMOMAX_H 0xf800707f 268 #define MATCH_AMOMINU_H 0xc000102f 269 #define MASK_AMOMINU_H 0xf800707f 270 #define MATCH_AMOMAXU_H 0xe000102f 271 #define MASK_AMOMAXU_H 0xf800707f 272 #define MATCH_AMOSWAP_H 0x800102f 273 #define MASK_AMOSWAP_H 0xf800707f 274 #define MATCH_ECALL 0x73 275 #define MASK_ECALL 0xffffffff 276 #define MATCH_EBREAK 0x100073 277 #define MASK_EBREAK 0xffffffff 278 #define MATCH_URET 0x200073 279 #define MASK_URET 0xffffffff 280 #define MATCH_SRET 0x10200073 281 #define MASK_SRET 0xffffffff 282 #define MATCH_HRET 0x20200073 283 #define MASK_HRET 0xffffffff 284 #define MATCH_MRET 0x30200073 285 #define MASK_MRET 0xffffffff 286 #define MATCH_DRET 0x7b200073 287 #define MASK_DRET 0xffffffff 288 #define MATCH_SFENCE_VM 0x10400073 289 #define MASK_SFENCE_VM 0xfff07fff 290 #define MATCH_SFENCE_VMA 0x12000073 291 #define MASK_SFENCE_VMA 0xfe007fff 292 #define MATCH_WFI 0x10500073 293 #define MASK_WFI 0xffffffff 294 #define MATCH_CSRRW 0x1073 295 #define MASK_CSRRW 0x707f 296 #define MATCH_CSRRS 0x2073 297 #define MASK_CSRRS 0x707f 298 #define MATCH_CSRRC 0x3073 299 #define MASK_CSRRC 0x707f 300 #define MATCH_CSRRWI 0x5073 301 #define MASK_CSRRWI 0x707f 302 #define MATCH_CSRRSI 0x6073 303 #define MASK_CSRRSI 0x707f 304 #define MATCH_CSRRCI 0x7073 305 #define MASK_CSRRCI 0x707f 306 #define MATCH_FADD_S 0x53 307 #define MASK_FADD_S 0xfe00007f 308 #define MATCH_FSUB_S 0x8000053 309 #define MASK_FSUB_S 0xfe00007f 310 #define MATCH_FMUL_S 0x10000053 311 #define MASK_FMUL_S 0xfe00007f 312 #define MATCH_FDIV_S 0x18000053 313 #define MASK_FDIV_S 0xfe00007f 314 #define MATCH_FSGNJ_S 0x20000053 315 #define MASK_FSGNJ_S 0xfe00707f 316 #define MATCH_FSGNJN_S 0x20001053 317 #define MASK_FSGNJN_S 0xfe00707f 318 #define MATCH_FSGNJX_S 0x20002053 319 #define MASK_FSGNJX_S 0xfe00707f 320 #define MATCH_FMIN_S 0x28000053 321 #define MASK_FMIN_S 0xfe00707f 322 #define MATCH_FMAX_S 0x28001053 323 #define MASK_FMAX_S 0xfe00707f 324 #define MATCH_FSQRT_S 0x58000053 325 #define MASK_FSQRT_S 0xfff0007f 326 #define MATCH_FADD_D 0x2000053 327 #define MASK_FADD_D 0xfe00007f 328 #define MATCH_FSUB_D 0xa000053 329 #define MASK_FSUB_D 0xfe00007f 330 #define MATCH_FMUL_D 0x12000053 331 #define MASK_FMUL_D 0xfe00007f 332 #define MATCH_FDIV_D 0x1a000053 333 #define MASK_FDIV_D 0xfe00007f 334 #define MATCH_FSGNJ_D 0x22000053 335 #define MASK_FSGNJ_D 0xfe00707f 336 #define MATCH_FSGNJN_D 0x22001053 337 #define MASK_FSGNJN_D 0xfe00707f 338 #define MATCH_FSGNJX_D 0x22002053 339 #define MASK_FSGNJX_D 0xfe00707f 340 #define MATCH_FMIN_D 0x2a000053 341 #define MASK_FMIN_D 0xfe00707f 342 #define MATCH_FMAX_D 0x2a001053 343 #define MASK_FMAX_D 0xfe00707f 344 #define MATCH_FCVT_S_D 0x40100053 345 #define MASK_FCVT_S_D 0xfff0007f 346 #define MATCH_FCVT_D_S 0x42000053 347 #define MASK_FCVT_D_S 0xfff0007f 348 #define MATCH_FSQRT_D 0x5a000053 349 #define MASK_FSQRT_D 0xfff0007f 350 #define MATCH_FADD_Q 0x6000053 351 #define MASK_FADD_Q 0xfe00007f 352 #define MATCH_FSUB_Q 0xe000053 353 #define MASK_FSUB_Q 0xfe00007f 354 #define MATCH_FMUL_Q 0x16000053 355 #define MASK_FMUL_Q 0xfe00007f 356 #define MATCH_FDIV_Q 0x1e000053 357 #define MASK_FDIV_Q 0xfe00007f 358 #define MATCH_FSGNJ_Q 0x26000053 359 #define MASK_FSGNJ_Q 0xfe00707f 360 #define MATCH_FSGNJN_Q 0x26001053 361 #define MASK_FSGNJN_Q 0xfe00707f 362 #define MATCH_FSGNJX_Q 0x26002053 363 #define MASK_FSGNJX_Q 0xfe00707f 364 #define MATCH_FMIN_Q 0x2e000053 365 #define MASK_FMIN_Q 0xfe00707f 366 #define MATCH_FMAX_Q 0x2e001053 367 #define MASK_FMAX_Q 0xfe00707f 368 #define MATCH_FCVT_S_Q 0x40300053 369 #define MASK_FCVT_S_Q 0xfff0007f 370 #define MATCH_FCVT_Q_S 0x46000053 371 #define MASK_FCVT_Q_S 0xfff0007f 372 #define MATCH_FCVT_D_Q 0x42300053 373 #define MASK_FCVT_D_Q 0xfff0007f 374 #define MATCH_FCVT_Q_D 0x46100053 375 #define MASK_FCVT_Q_D 0xfff0007f 376 #define MATCH_FSQRT_Q 0x5e000053 377 #define MASK_FSQRT_Q 0xfff0007f 378 #define MATCH_FLE_S 0xa0000053 379 #define MASK_FLE_S 0xfe00707f 380 #define MATCH_FLT_S 0xa0001053 381 #define MASK_FLT_S 0xfe00707f 382 #define MATCH_FEQ_S 0xa0002053 383 #define MASK_FEQ_S 0xfe00707f 384 #define MATCH_FLE_D 0xa2000053 385 #define MASK_FLE_D 0xfe00707f 386 #define MATCH_FLT_D 0xa2001053 387 #define MASK_FLT_D 0xfe00707f 388 #define MATCH_FEQ_D 0xa2002053 389 #define MASK_FEQ_D 0xfe00707f 390 #define MATCH_FLE_Q 0xa6000053 391 #define MASK_FLE_Q 0xfe00707f 392 #define MATCH_FLT_Q 0xa6001053 393 #define MASK_FLT_Q 0xfe00707f 394 #define MATCH_FEQ_Q 0xa6002053 395 #define MASK_FEQ_Q 0xfe00707f 396 #define MATCH_FCVT_W_S 0xc0000053 397 #define MASK_FCVT_W_S 0xfff0007f 398 #define MATCH_FCVT_WU_S 0xc0100053 399 #define MASK_FCVT_WU_S 0xfff0007f 400 #define MATCH_FCVT_L_S 0xc0200053 401 #define MASK_FCVT_L_S 0xfff0007f 402 #define MATCH_FCVT_LU_S 0xc0300053 403 #define MASK_FCVT_LU_S 0xfff0007f 404 #define MATCH_FMV_X_S 0xe0000053 405 #define MASK_FMV_X_S 0xfff0707f 406 #define MATCH_FCLASS_S 0xe0001053 407 #define MASK_FCLASS_S 0xfff0707f 408 #define MATCH_FCVT_W_D 0xc2000053 409 #define MASK_FCVT_W_D 0xfff0007f 410 #define MATCH_FCVT_WU_D 0xc2100053 411 #define MASK_FCVT_WU_D 0xfff0007f 412 #define MATCH_FCVT_L_D 0xc2200053 413 #define MASK_FCVT_L_D 0xfff0007f 414 #define MATCH_FCVT_LU_D 0xc2300053 415 #define MASK_FCVT_LU_D 0xfff0007f 416 #define MATCH_FMV_X_D 0xe2000053 417 #define MASK_FMV_X_D 0xfff0707f 418 #define MATCH_FCLASS_D 0xe2001053 419 #define MASK_FCLASS_D 0xfff0707f 420 #define MATCH_FCVT_W_Q 0xc6000053 421 #define MASK_FCVT_W_Q 0xfff0007f 422 #define MATCH_FCVT_WU_Q 0xc6100053 423 #define MASK_FCVT_WU_Q 0xfff0007f 424 #define MATCH_FCVT_L_Q 0xc6200053 425 #define MASK_FCVT_L_Q 0xfff0007f 426 #define MATCH_FCVT_LU_Q 0xc6300053 427 #define MASK_FCVT_LU_Q 0xfff0007f 428 #define MATCH_FCLASS_Q 0xe6001053 429 #define MASK_FCLASS_Q 0xfff0707f 430 #define MATCH_FCVT_S_W 0xd0000053 431 #define MASK_FCVT_S_W 0xfff0007f 432 #define MATCH_FCVT_S_WU 0xd0100053 433 #define MASK_FCVT_S_WU 0xfff0007f 434 #define MATCH_FCVT_S_L 0xd0200053 435 #define MASK_FCVT_S_L 0xfff0007f 436 #define MATCH_FCVT_S_LU 0xd0300053 437 #define MASK_FCVT_S_LU 0xfff0007f 438 #define MATCH_FMV_S_X 0xf0000053 439 #define MASK_FMV_S_X 0xfff0707f 440 #define MATCH_FCVT_D_W 0xd2000053 441 #define MASK_FCVT_D_W 0xfff0007f 442 #define MATCH_FCVT_D_WU 0xd2100053 443 #define MASK_FCVT_D_WU 0xfff0007f 444 #define MATCH_FCVT_D_L 0xd2200053 445 #define MASK_FCVT_D_L 0xfff0007f 446 #define MATCH_FCVT_D_LU 0xd2300053 447 #define MASK_FCVT_D_LU 0xfff0007f 448 #define MATCH_FMV_D_X 0xf2000053 449 #define MASK_FMV_D_X 0xfff0707f 450 #define MATCH_FCVT_Q_W 0xd6000053 451 #define MASK_FCVT_Q_W 0xfff0007f 452 #define MATCH_FCVT_Q_WU 0xd6100053 453 #define MASK_FCVT_Q_WU 0xfff0007f 454 #define MATCH_FCVT_Q_L 0xd6200053 455 #define MASK_FCVT_Q_L 0xfff0007f 456 #define MATCH_FCVT_Q_LU 0xd6300053 457 #define MASK_FCVT_Q_LU 0xfff0007f 458 #define MATCH_FLI_H 0xf4100053 459 #define MASK_FLI_H 0xfff0707f 460 #define MATCH_FMINM_H 0x2c002053 461 #define MASK_FMINM_H 0xfe00707f 462 #define MATCH_FMAXM_H 0x2c003053 463 #define MASK_FMAXM_H 0xfe00707f 464 #define MATCH_FROUND_H 0x44400053 465 #define MASK_FROUND_H 0xfff0007f 466 #define MATCH_FROUNDNX_H 0x44500053 467 #define MASK_FROUNDNX_H 0xfff0007f 468 #define MATCH_FLTQ_H 0xa4005053 469 #define MASK_FLTQ_H 0xfe00707f 470 #define MATCH_FLEQ_H 0xa4004053 471 #define MASK_FLEQ_H 0xfe00707f 472 #define MATCH_FLI_S 0xf0100053 473 #define MASK_FLI_S 0xfff0707f 474 #define MATCH_FMINM_S 0x28002053 475 #define MASK_FMINM_S 0xfe00707f 476 #define MATCH_FMAXM_S 0x28003053 477 #define MASK_FMAXM_S 0xfe00707f 478 #define MATCH_FROUND_S 0x40400053 479 #define MASK_FROUND_S 0xfff0007f 480 #define MATCH_FROUNDNX_S 0x40500053 481 #define MASK_FROUNDNX_S 0xfff0007f 482 #define MATCH_FLTQ_S 0xa0005053 483 #define MASK_FLTQ_S 0xfe00707f 484 #define MATCH_FLEQ_S 0xa0004053 485 #define MASK_FLEQ_S 0xfe00707f 486 #define MATCH_FLI_D 0xf2100053 487 #define MASK_FLI_D 0xfff0707f 488 #define MATCH_FMINM_D 0x2a002053 489 #define MASK_FMINM_D 0xfe00707f 490 #define MATCH_FMAXM_D 0x2a003053 491 #define MASK_FMAXM_D 0xfe00707f 492 #define MATCH_FROUND_D 0x42400053 493 #define MASK_FROUND_D 0xfff0007f 494 #define MATCH_FROUNDNX_D 0x42500053 495 #define MASK_FROUNDNX_D 0xfff0007f 496 #define MATCH_FLTQ_D 0xa2005053 497 #define MASK_FLTQ_D 0xfe00707f 498 #define MATCH_FLEQ_D 0xa2004053 499 #define MASK_FLEQ_D 0xfe00707f 500 #define MATCH_FLI_Q 0xf6100053 501 #define MASK_FLI_Q 0xfff0707f 502 #define MATCH_FMINM_Q 0x2e002053 503 #define MASK_FMINM_Q 0xfe00707f 504 #define MATCH_FMAXM_Q 0x2e003053 505 #define MASK_FMAXM_Q 0xfe00707f 506 #define MATCH_FROUND_Q 0x46400053 507 #define MASK_FROUND_Q 0xfff0007f 508 #define MATCH_FROUNDNX_Q 0x46500053 509 #define MASK_FROUNDNX_Q 0xfff0007f 510 #define MATCH_FLTQ_Q 0xa6005053 511 #define MASK_FLTQ_Q 0xfe00707f 512 #define MATCH_FLEQ_Q 0xa6004053 513 #define MASK_FLEQ_Q 0xfe00707f 514 #define MATCH_FCVTMOD_W_D 0xc2801053 515 #define MASK_FCVTMOD_W_D 0xfff0707f 516 #define MATCH_FMVH_X_D 0xe2100053 517 #define MASK_FMVH_X_D 0xfff0707f 518 #define MATCH_FMVH_X_Q 0xe6100053 519 #define MASK_FMVH_X_Q 0xfff0707f 520 #define MATCH_FMVP_D_X 0xb2000053 521 #define MASK_FMVP_D_X 0xfe00707f 522 #define MATCH_FMVP_Q_X 0xb6000053 523 #define MASK_FMVP_Q_X 0xfe00707f 524 #define MATCH_CLZ 0x60001013 525 #define MASK_CLZ 0xfff0707f 526 #define MATCH_CTZ 0x60101013 527 #define MASK_CTZ 0xfff0707f 528 #define MATCH_CPOP 0x60201013 529 #define MASK_CPOP 0xfff0707f 530 #define MATCH_MIN 0xa004033 531 #define MASK_MIN 0xfe00707f 532 #define MATCH_MINU 0xa005033 533 #define MASK_MINU 0xfe00707f 534 #define MATCH_MAX 0xa006033 535 #define MASK_MAX 0xfe00707f 536 #define MATCH_MAXU 0xa007033 537 #define MASK_MAXU 0xfe00707f 538 #define MATCH_SEXT_B 0x60401013 539 #define MASK_SEXT_B 0xfff0707f 540 #define MATCH_SEXT_H 0x60501013 541 #define MASK_SEXT_H 0xfff0707f 542 #define MATCH_PACK 0x8004033 543 #define MASK_PACK 0xfe00707f 544 #define MATCH_PACKH 0x8007033 545 #define MASK_PACKH 0xfe00707f 546 #define MATCH_PACKW 0x800403b 547 #define MASK_PACKW 0xfe00707f 548 #define MATCH_ANDN 0x40007033 549 #define MASK_ANDN 0xfe00707f 550 #define MATCH_ORN 0x40006033 551 #define MASK_ORN 0xfe00707f 552 #define MATCH_XNOR 0x40004033 553 #define MASK_XNOR 0xfe00707f 554 #define MATCH_ROL 0x60001033 555 #define MASK_ROL 0xfe00707f 556 #define MATCH_ROR 0x60005033 557 #define MASK_ROR 0xfe00707f 558 #define MATCH_RORI 0x60005013 559 #define MASK_RORI 0xfc00707f 560 #define MATCH_GREVI 0x68005013 561 #define MASK_GREVI 0xfc00707f 562 #define MATCH_GORCI 0x28005013 563 #define MASK_GORCI 0xfc00707f 564 #define MATCH_SHFLI 0x8001013 565 #define MASK_SHFLI 0xfe00707f 566 #define MATCH_UNSHFLI 0x8005013 567 #define MASK_UNSHFLI 0xfe00707f 568 #define MATCH_CLZW 0x6000101b 569 #define MASK_CLZW 0xfff0707f 570 #define MATCH_CTZW 0x6010101b 571 #define MASK_CTZW 0xfff0707f 572 #define MATCH_CPOPW 0x6020101b 573 #define MASK_CPOPW 0xfff0707f 574 #define MATCH_ROLW 0x6000103b 575 #define MASK_ROLW 0xfe00707f 576 #define MATCH_RORW 0x6000503b 577 #define MASK_RORW 0xfe00707f 578 #define MATCH_RORIW 0x6000501b 579 #define MASK_RORIW 0xfe00707f 580 #define MATCH_SH1ADD 0x20002033 581 #define MASK_SH1ADD 0xfe00707f 582 #define MATCH_SH2ADD 0x20004033 583 #define MASK_SH2ADD 0xfe00707f 584 #define MATCH_SH3ADD 0x20006033 585 #define MASK_SH3ADD 0xfe00707f 586 #define MATCH_SH1ADD_UW 0x2000203b 587 #define MASK_SH1ADD_UW 0xfe00707f 588 #define MATCH_SH2ADD_UW 0x2000403b 589 #define MASK_SH2ADD_UW 0xfe00707f 590 #define MATCH_SH3ADD_UW 0x2000603b 591 #define MASK_SH3ADD_UW 0xfe00707f 592 #define MATCH_ADD_UW 0x800003b 593 #define MASK_ADD_UW 0xfe00707f 594 #define MATCH_SLLI_UW 0x800101b 595 #define MASK_SLLI_UW 0xfc00707f 596 #define MATCH_CLMUL 0xa001033 597 #define MASK_CLMUL 0xfe00707f 598 #define MATCH_CLMULH 0xa003033 599 #define MASK_CLMULH 0xfe00707f 600 #define MATCH_CLMULR 0xa002033 601 #define MASK_CLMULR 0xfe00707f 602 #define MATCH_XPERM4 0x28002033 603 #define MASK_XPERM4 0xfe00707f 604 #define MATCH_XPERM8 0x28004033 605 #define MASK_XPERM8 0xfe00707f 606 #define MATCH_BCLRI 0x48001013 607 #define MASK_BCLRI 0xfc00707f 608 #define MATCH_BSETI 0x28001013 609 #define MASK_BSETI 0xfc00707f 610 #define MATCH_BINVI 0x68001013 611 #define MASK_BINVI 0xfc00707f 612 #define MATCH_BEXTI 0x48005013 613 #define MASK_BEXTI 0xfc00707f 614 #define MATCH_BCLR 0x48001033 615 #define MASK_BCLR 0xfe00707f 616 #define MATCH_BSET 0x28001033 617 #define MASK_BSET 0xfe00707f 618 #define MATCH_BINV 0x68001033 619 #define MASK_BINV 0xfe00707f 620 #define MATCH_BEXT 0x48005033 621 #define MASK_BEXT 0xfe00707f 622 #define MATCH_FLW 0x2007 623 #define MASK_FLW 0x707f 624 #define MATCH_FLD 0x3007 625 #define MASK_FLD 0x707f 626 #define MATCH_FLQ 0x4007 627 #define MASK_FLQ 0x707f 628 #define MATCH_FSW 0x2027 629 #define MASK_FSW 0x707f 630 #define MATCH_FSD 0x3027 631 #define MASK_FSD 0x707f 632 #define MATCH_FSQ 0x4027 633 #define MASK_FSQ 0x707f 634 #define MATCH_FMADD_S 0x43 635 #define MASK_FMADD_S 0x600007f 636 #define MATCH_FMSUB_S 0x47 637 #define MASK_FMSUB_S 0x600007f 638 #define MATCH_FNMSUB_S 0x4b 639 #define MASK_FNMSUB_S 0x600007f 640 #define MATCH_FNMADD_S 0x4f 641 #define MASK_FNMADD_S 0x600007f 642 #define MATCH_FMADD_D 0x2000043 643 #define MASK_FMADD_D 0x600007f 644 #define MATCH_FMSUB_D 0x2000047 645 #define MASK_FMSUB_D 0x600007f 646 #define MATCH_FNMSUB_D 0x200004b 647 #define MASK_FNMSUB_D 0x600007f 648 #define MATCH_FNMADD_D 0x200004f 649 #define MASK_FNMADD_D 0x600007f 650 #define MATCH_FMADD_Q 0x6000043 651 #define MASK_FMADD_Q 0x600007f 652 #define MATCH_FMSUB_Q 0x6000047 653 #define MASK_FMSUB_Q 0x600007f 654 #define MATCH_FNMSUB_Q 0x600004b 655 #define MASK_FNMSUB_Q 0x600007f 656 #define MATCH_FNMADD_Q 0x600004f 657 #define MASK_FNMADD_Q 0x600007f 658 #define MATCH_C_ADDI4SPN 0x0 659 #define MASK_C_ADDI4SPN 0xe003 660 #define MATCH_C_FLD 0x2000 661 #define MASK_C_FLD 0xe003 662 #define MATCH_C_LW 0x4000 663 #define MASK_C_LW 0xe003 664 #define MATCH_C_FLW 0x6000 665 #define MASK_C_FLW 0xe003 666 #define MATCH_C_FSD 0xa000 667 #define MASK_C_FSD 0xe003 668 #define MATCH_C_SW 0xc000 669 #define MASK_C_SW 0xe003 670 #define MATCH_C_FSW 0xe000 671 #define MASK_C_FSW 0xe003 672 #define MATCH_C_ADDI 0x1 673 #define MASK_C_ADDI 0xe003 674 #define MATCH_C_JAL 0x2001 675 #define MASK_C_JAL 0xe003 676 #define MATCH_C_LI 0x4001 677 #define MASK_C_LI 0xe003 678 #define MATCH_C_LUI 0x6001 679 #define MASK_C_LUI 0xe003 680 #define MATCH_C_SRLI 0x8001 681 #define MASK_C_SRLI 0xec03 682 #define MATCH_C_SRLI64 0x8001 683 #define MASK_C_SRLI64 0xfc7f 684 #define MATCH_C_SRAI 0x8401 685 #define MASK_C_SRAI 0xec03 686 #define MATCH_C_SRAI64 0x8401 687 #define MASK_C_SRAI64 0xfc7f 688 #define MATCH_C_ANDI 0x8801 689 #define MASK_C_ANDI 0xec03 690 #define MATCH_C_SUB 0x8c01 691 #define MASK_C_SUB 0xfc63 692 #define MATCH_C_XOR 0x8c21 693 #define MASK_C_XOR 0xfc63 694 #define MATCH_C_OR 0x8c41 695 #define MASK_C_OR 0xfc63 696 #define MATCH_C_AND 0x8c61 697 #define MASK_C_AND 0xfc63 698 #define MATCH_C_SUBW 0x9c01 699 #define MASK_C_SUBW 0xfc63 700 #define MATCH_C_ADDW 0x9c21 701 #define MASK_C_ADDW 0xfc63 702 #define MATCH_C_J 0xa001 703 #define MASK_C_J 0xe003 704 #define MATCH_C_BEQZ 0xc001 705 #define MASK_C_BEQZ 0xe003 706 #define MATCH_C_BNEZ 0xe001 707 #define MASK_C_BNEZ 0xe003 708 #define MATCH_C_SLLI 0x2 709 #define MASK_C_SLLI 0xe003 710 #define MATCH_C_SLLI64 0x2 711 #define MASK_C_SLLI64 0xf07f 712 #define MATCH_C_FLDSP 0x2002 713 #define MASK_C_FLDSP 0xe003 714 #define MATCH_C_LWSP 0x4002 715 #define MASK_C_LWSP 0xe003 716 #define MATCH_C_FLWSP 0x6002 717 #define MASK_C_FLWSP 0xe003 718 #define MATCH_C_MV 0x8002 719 #define MASK_C_MV 0xf003 720 #define MATCH_C_ADD 0x9002 721 #define MASK_C_ADD 0xf003 722 #define MATCH_C_FSDSP 0xa002 723 #define MASK_C_FSDSP 0xe003 724 #define MATCH_C_SWSP 0xc002 725 #define MASK_C_SWSP 0xe003 726 #define MATCH_C_FSWSP 0xe002 727 #define MASK_C_FSWSP 0xe003 728 #define MATCH_C_NOP 0x1 729 #define MASK_C_NOP 0xffff 730 #define MATCH_C_ADDI16SP 0x6101 731 #define MASK_C_ADDI16SP 0xef83 732 #define MATCH_C_JR 0x8002 733 #define MASK_C_JR 0xf07f 734 #define MATCH_C_JALR 0x9002 735 #define MASK_C_JALR 0xf07f 736 #define MATCH_C_EBREAK 0x9002 737 #define MASK_C_EBREAK 0xffff 738 #define MATCH_C_LD 0x6000 739 #define MASK_C_LD 0xe003 740 #define MATCH_C_SD 0xe000 741 #define MASK_C_SD 0xe003 742 #define MATCH_C_ADDIW 0x2001 743 #define MASK_C_ADDIW 0xe003 744 #define MATCH_C_LDSP 0x6002 745 #define MASK_C_LDSP 0xe003 746 #define MATCH_C_SDSP 0xe002 747 #define MASK_C_SDSP 0xe003 748 #define MATCH_SM3P0 0x10801013 749 #define MASK_SM3P0 0xfff0707f 750 #define MATCH_SM3P1 0x10901013 751 #define MASK_SM3P1 0xfff0707f 752 #define MATCH_SHA256SUM0 0x10001013 753 #define MASK_SHA256SUM0 0xfff0707f 754 #define MATCH_SHA256SUM1 0x10101013 755 #define MASK_SHA256SUM1 0xfff0707f 756 #define MATCH_SHA256SIG0 0x10201013 757 #define MASK_SHA256SIG0 0xfff0707f 758 #define MATCH_SHA256SIG1 0x10301013 759 #define MASK_SHA256SIG1 0xfff0707f 760 #define MATCH_SHA512SUM0R 0x50000033 761 #define MASK_SHA512SUM0R 0xfe00707f 762 #define MATCH_SHA512SUM1R 0x52000033 763 #define MASK_SHA512SUM1R 0xfe00707f 764 #define MATCH_SHA512SIG0L 0x54000033 765 #define MASK_SHA512SIG0L 0xfe00707f 766 #define MATCH_SHA512SIG0H 0x5c000033 767 #define MASK_SHA512SIG0H 0xfe00707f 768 #define MATCH_SHA512SIG1L 0x56000033 769 #define MASK_SHA512SIG1L 0xfe00707f 770 #define MATCH_SHA512SIG1H 0x5e000033 771 #define MASK_SHA512SIG1H 0xfe00707f 772 #define MATCH_SM4ED 0x30000033 773 #define MASK_SM4ED 0x3e00707f 774 #define MATCH_SM4KS 0x34000033 775 #define MASK_SM4KS 0x3e00707f 776 #define MATCH_AES32ESMI 0x26000033 777 #define MASK_AES32ESMI 0x3e00707f 778 #define MATCH_AES32ESI 0x22000033 779 #define MASK_AES32ESI 0x3e00707f 780 #define MATCH_AES32DSMI 0x2e000033 781 #define MASK_AES32DSMI 0x3e00707f 782 #define MATCH_AES32DSI 0x2a000033 783 #define MASK_AES32DSI 0x3e00707f 784 #define MATCH_SHA512SUM0 0x10401013 785 #define MASK_SHA512SUM0 0xfff0707f 786 #define MATCH_SHA512SUM1 0x10501013 787 #define MASK_SHA512SUM1 0xfff0707f 788 #define MATCH_SHA512SIG0 0x10601013 789 #define MASK_SHA512SIG0 0xfff0707f 790 #define MATCH_SHA512SIG1 0x10701013 791 #define MASK_SHA512SIG1 0xfff0707f 792 #define MATCH_AES64KS1I 0x31001013 793 #define MASK_AES64KS1I 0xff00707f 794 #define MATCH_AES64IM 0x30001013 795 #define MASK_AES64IM 0xfff0707f 796 #define MATCH_AES64KS2 0x7e000033 797 #define MASK_AES64KS2 0xfe00707f 798 #define MATCH_AES64ESM 0x36000033 799 #define MASK_AES64ESM 0xfe00707f 800 #define MATCH_AES64ES 0x32000033 801 #define MASK_AES64ES 0xfe00707f 802 #define MATCH_AES64DSM 0x3e000033 803 #define MASK_AES64DSM 0xfe00707f 804 #define MATCH_AES64DS 0x3a000033 805 #define MASK_AES64DS 0xfe00707f 806 #define MATCH_FADD_H 0x4000053 807 #define MASK_FADD_H 0xfe00007f 808 #define MATCH_FSUB_H 0xc000053 809 #define MASK_FSUB_H 0xfe00007f 810 #define MATCH_FMUL_H 0x14000053 811 #define MASK_FMUL_H 0xfe00007f 812 #define MATCH_FDIV_H 0x1c000053 813 #define MASK_FDIV_H 0xfe00007f 814 #define MATCH_FSGNJ_H 0x24000053 815 #define MASK_FSGNJ_H 0xfe00707f 816 #define MATCH_FSGNJN_H 0x24001053 817 #define MASK_FSGNJN_H 0xfe00707f 818 #define MATCH_FSGNJX_H 0x24002053 819 #define MASK_FSGNJX_H 0xfe00707f 820 #define MATCH_FMIN_H 0x2c000053 821 #define MASK_FMIN_H 0xfe00707f 822 #define MATCH_FMAX_H 0x2c001053 823 #define MASK_FMAX_H 0xfe00707f 824 #define MATCH_FCVT_H_S 0x44000053 825 #define MASK_FCVT_H_S 0xfff0007f 826 #define MATCH_FCVT_S_H 0x40200053 827 #define MASK_FCVT_S_H 0xfff0007f 828 #define MATCH_FSQRT_H 0x5c000053 829 #define MASK_FSQRT_H 0xfff0007f 830 #define MATCH_FLE_H 0xa4000053 831 #define MASK_FLE_H 0xfe00707f 832 #define MATCH_FLT_H 0xa4001053 833 #define MASK_FLT_H 0xfe00707f 834 #define MATCH_FEQ_H 0xa4002053 835 #define MASK_FEQ_H 0xfe00707f 836 #define MATCH_FCVT_W_H 0xc4000053 837 #define MASK_FCVT_W_H 0xfff0007f 838 #define MATCH_FCVT_WU_H 0xc4100053 839 #define MASK_FCVT_WU_H 0xfff0007f 840 #define MATCH_FMV_X_H 0xe4000053 841 #define MASK_FMV_X_H 0xfff0707f 842 #define MATCH_FCLASS_H 0xe4001053 843 #define MASK_FCLASS_H 0xfff0707f 844 #define MATCH_FCVT_H_W 0xd4000053 845 #define MASK_FCVT_H_W 0xfff0007f 846 #define MATCH_FCVT_H_WU 0xd4100053 847 #define MASK_FCVT_H_WU 0xfff0007f 848 #define MATCH_FMV_H_X 0xf4000053 849 #define MASK_FMV_H_X 0xfff0707f 850 #define MATCH_FLH 0x1007 851 #define MASK_FLH 0x707f 852 #define MATCH_FSH 0x1027 853 #define MASK_FSH 0x707f 854 #define MATCH_FMADD_H 0x4000043 855 #define MASK_FMADD_H 0x600007f 856 #define MATCH_FMSUB_H 0x4000047 857 #define MASK_FMSUB_H 0x600007f 858 #define MATCH_FNMSUB_H 0x400004b 859 #define MASK_FNMSUB_H 0x600007f 860 #define MATCH_FNMADD_H 0x400004f 861 #define MASK_FNMADD_H 0x600007f 862 #define MATCH_FCVT_H_D 0x44100053 863 #define MASK_FCVT_H_D 0xfff0007f 864 #define MATCH_FCVT_D_H 0x42200053 865 #define MASK_FCVT_D_H 0xfff0007f 866 #define MATCH_FCVT_H_Q 0x44300053 867 #define MASK_FCVT_H_Q 0xfff0007f 868 #define MATCH_FCVT_Q_H 0x46200053 869 #define MASK_FCVT_Q_H 0xfff0007f 870 #define MATCH_FCVT_L_H 0xc4200053 871 #define MASK_FCVT_L_H 0xfff0007f 872 #define MATCH_FCVT_LU_H 0xc4300053 873 #define MASK_FCVT_LU_H 0xfff0007f 874 #define MATCH_FCVT_H_L 0xd4200053 875 #define MASK_FCVT_H_L 0xfff0007f 876 #define MATCH_FCVT_H_LU 0xd4300053 877 #define MASK_FCVT_H_LU 0xfff0007f 878 #define MATCH_VSETVL 0x80007057 879 #define MASK_VSETVL 0xfe00707f 880 #define MATCH_VSETIVLI 0xc0007057 881 #define MASK_VSETIVLI 0xc000707f 882 #define MATCH_VSETVLI 0x00007057 883 #define MASK_VSETVLI 0x8000707f 884 #define MATCH_VLMV 0x02b00007 885 #define MASK_VLMV 0xfff0707f 886 #define MATCH_VSMV 0x02b00027 887 #define MASK_VSMV 0xfff0707f 888 #define MATCH_VLE8V 0x00000007 889 #define MASK_VLE8V 0xfdf0707f 890 #define MATCH_VLE16V 0x00005007 891 #define MASK_VLE16V 0xfdf0707f 892 #define MATCH_VLE32V 0x00006007 893 #define MASK_VLE32V 0xfdf0707f 894 #define MATCH_VLE64V 0x00007007 895 #define MASK_VLE64V 0xfdf0707f 896 #define MATCH_VSE8V 0x00000027 897 #define MASK_VSE8V 0xfdf0707f 898 #define MATCH_VSE16V 0x00005027 899 #define MASK_VSE16V 0xfdf0707f 900 #define MATCH_VSE32V 0x00006027 901 #define MASK_VSE32V 0xfdf0707f 902 #define MATCH_VSE64V 0x00007027 903 #define MASK_VSE64V 0xfdf0707f 904 #define MATCH_VLSE8V 0x08000007 905 #define MASK_VLSE8V 0xfc00707f 906 #define MATCH_VLSE16V 0x08005007 907 #define MASK_VLSE16V 0xfc00707f 908 #define MATCH_VLSE32V 0x08006007 909 #define MASK_VLSE32V 0xfc00707f 910 #define MATCH_VLSE64V 0x08007007 911 #define MASK_VLSE64V 0xfc00707f 912 #define MATCH_VSSE8V 0x08000027 913 #define MASK_VSSE8V 0xfc00707f 914 #define MATCH_VSSE16V 0x08005027 915 #define MASK_VSSE16V 0xfc00707f 916 #define MATCH_VSSE32V 0x08006027 917 #define MASK_VSSE32V 0xfc00707f 918 #define MATCH_VSSE64V 0x08007027 919 #define MASK_VSSE64V 0xfc00707f 920 #define MATCH_VLOXEI8V 0x0c000007 921 #define MASK_VLOXEI8V 0xfc00707f 922 #define MATCH_VLOXEI16V 0x0c005007 923 #define MASK_VLOXEI16V 0xfc00707f 924 #define MATCH_VLOXEI32V 0x0c006007 925 #define MASK_VLOXEI32V 0xfc00707f 926 #define MATCH_VLOXEI64V 0x0c007007 927 #define MASK_VLOXEI64V 0xfc00707f 928 #define MATCH_VSOXEI8V 0x0c000027 929 #define MASK_VSOXEI8V 0xfc00707f 930 #define MATCH_VSOXEI16V 0x0c005027 931 #define MASK_VSOXEI16V 0xfc00707f 932 #define MATCH_VSOXEI32V 0x0c006027 933 #define MASK_VSOXEI32V 0xfc00707f 934 #define MATCH_VSOXEI64V 0x0c007027 935 #define MASK_VSOXEI64V 0xfc00707f 936 #define MATCH_VLUXEI8V 0x04000007 937 #define MASK_VLUXEI8V 0xfc00707f 938 #define MATCH_VLUXEI16V 0x04005007 939 #define MASK_VLUXEI16V 0xfc00707f 940 #define MATCH_VLUXEI32V 0x04006007 941 #define MASK_VLUXEI32V 0xfc00707f 942 #define MATCH_VLUXEI64V 0x04007007 943 #define MASK_VLUXEI64V 0xfc00707f 944 #define MATCH_VSUXEI8V 0x04000027 945 #define MASK_VSUXEI8V 0xfc00707f 946 #define MATCH_VSUXEI16V 0x04005027 947 #define MASK_VSUXEI16V 0xfc00707f 948 #define MATCH_VSUXEI32V 0x04006027 949 #define MASK_VSUXEI32V 0xfc00707f 950 #define MATCH_VSUXEI64V 0x04007027 951 #define MASK_VSUXEI64V 0xfc00707f 952 #define MATCH_VLE8FFV 0x01000007 953 #define MASK_VLE8FFV 0xfdf0707f 954 #define MATCH_VLE16FFV 0x01005007 955 #define MASK_VLE16FFV 0xfdf0707f 956 #define MATCH_VLE32FFV 0x01006007 957 #define MASK_VLE32FFV 0xfdf0707f 958 #define MATCH_VLE64FFV 0x01007007 959 #define MASK_VLE64FFV 0xfdf0707f 960 #define MATCH_VLSEG2E8V 0x20000007 961 #define MASK_VLSEG2E8V 0xfdf0707f 962 #define MATCH_VSSEG2E8V 0x20000027 963 #define MASK_VSSEG2E8V 0xfdf0707f 964 #define MATCH_VLSEG3E8V 0x40000007 965 #define MASK_VLSEG3E8V 0xfdf0707f 966 #define MATCH_VSSEG3E8V 0x40000027 967 #define MASK_VSSEG3E8V 0xfdf0707f 968 #define MATCH_VLSEG4E8V 0x60000007 969 #define MASK_VLSEG4E8V 0xfdf0707f 970 #define MATCH_VSSEG4E8V 0x60000027 971 #define MASK_VSSEG4E8V 0xfdf0707f 972 #define MATCH_VLSEG5E8V 0x80000007 973 #define MASK_VLSEG5E8V 0xfdf0707f 974 #define MATCH_VSSEG5E8V 0x80000027 975 #define MASK_VSSEG5E8V 0xfdf0707f 976 #define MATCH_VLSEG6E8V 0xa0000007 977 #define MASK_VLSEG6E8V 0xfdf0707f 978 #define MATCH_VSSEG6E8V 0xa0000027 979 #define MASK_VSSEG6E8V 0xfdf0707f 980 #define MATCH_VLSEG7E8V 0xc0000007 981 #define MASK_VLSEG7E8V 0xfdf0707f 982 #define MATCH_VSSEG7E8V 0xc0000027 983 #define MASK_VSSEG7E8V 0xfdf0707f 984 #define MATCH_VLSEG8E8V 0xe0000007 985 #define MASK_VLSEG8E8V 0xfdf0707f 986 #define MATCH_VSSEG8E8V 0xe0000027 987 #define MASK_VSSEG8E8V 0xfdf0707f 988 #define MATCH_VLSEG2E16V 0x20005007 989 #define MASK_VLSEG2E16V 0xfdf0707f 990 #define MATCH_VSSEG2E16V 0x20005027 991 #define MASK_VSSEG2E16V 0xfdf0707f 992 #define MATCH_VLSEG3E16V 0x40005007 993 #define MASK_VLSEG3E16V 0xfdf0707f 994 #define MATCH_VSSEG3E16V 0x40005027 995 #define MASK_VSSEG3E16V 0xfdf0707f 996 #define MATCH_VLSEG4E16V 0x60005007 997 #define MASK_VLSEG4E16V 0xfdf0707f 998 #define MATCH_VSSEG4E16V 0x60005027 999 #define MASK_VSSEG4E16V 0xfdf0707f 1000 #define MATCH_VLSEG5E16V 0x80005007 1001 #define MASK_VLSEG5E16V 0xfdf0707f 1002 #define MATCH_VSSEG5E16V 0x80005027 1003 #define MASK_VSSEG5E16V 0xfdf0707f 1004 #define MATCH_VLSEG6E16V 0xa0005007 1005 #define MASK_VLSEG6E16V 0xfdf0707f 1006 #define MATCH_VSSEG6E16V 0xa0005027 1007 #define MASK_VSSEG6E16V 0xfdf0707f 1008 #define MATCH_VLSEG7E16V 0xc0005007 1009 #define MASK_VLSEG7E16V 0xfdf0707f 1010 #define MATCH_VSSEG7E16V 0xc0005027 1011 #define MASK_VSSEG7E16V 0xfdf0707f 1012 #define MATCH_VLSEG8E16V 0xe0005007 1013 #define MASK_VLSEG8E16V 0xfdf0707f 1014 #define MATCH_VSSEG8E16V 0xe0005027 1015 #define MASK_VSSEG8E16V 0xfdf0707f 1016 #define MATCH_VLSEG2E32V 0x20006007 1017 #define MASK_VLSEG2E32V 0xfdf0707f 1018 #define MATCH_VSSEG2E32V 0x20006027 1019 #define MASK_VSSEG2E32V 0xfdf0707f 1020 #define MATCH_VLSEG3E32V 0x40006007 1021 #define MASK_VLSEG3E32V 0xfdf0707f 1022 #define MATCH_VSSEG3E32V 0x40006027 1023 #define MASK_VSSEG3E32V 0xfdf0707f 1024 #define MATCH_VLSEG4E32V 0x60006007 1025 #define MASK_VLSEG4E32V 0xfdf0707f 1026 #define MATCH_VSSEG4E32V 0x60006027 1027 #define MASK_VSSEG4E32V 0xfdf0707f 1028 #define MATCH_VLSEG5E32V 0x80006007 1029 #define MASK_VLSEG5E32V 0xfdf0707f 1030 #define MATCH_VSSEG5E32V 0x80006027 1031 #define MASK_VSSEG5E32V 0xfdf0707f 1032 #define MATCH_VLSEG6E32V 0xa0006007 1033 #define MASK_VLSEG6E32V 0xfdf0707f 1034 #define MATCH_VSSEG6E32V 0xa0006027 1035 #define MASK_VSSEG6E32V 0xfdf0707f 1036 #define MATCH_VLSEG7E32V 0xc0006007 1037 #define MASK_VLSEG7E32V 0xfdf0707f 1038 #define MATCH_VSSEG7E32V 0xc0006027 1039 #define MASK_VSSEG7E32V 0xfdf0707f 1040 #define MATCH_VLSEG8E32V 0xe0006007 1041 #define MASK_VLSEG8E32V 0xfdf0707f 1042 #define MATCH_VSSEG8E32V 0xe0006027 1043 #define MASK_VSSEG8E32V 0xfdf0707f 1044 #define MATCH_VLSEG2E64V 0x20007007 1045 #define MASK_VLSEG2E64V 0xfdf0707f 1046 #define MATCH_VSSEG2E64V 0x20007027 1047 #define MASK_VSSEG2E64V 0xfdf0707f 1048 #define MATCH_VLSEG3E64V 0x40007007 1049 #define MASK_VLSEG3E64V 0xfdf0707f 1050 #define MATCH_VSSEG3E64V 0x40007027 1051 #define MASK_VSSEG3E64V 0xfdf0707f 1052 #define MATCH_VLSEG4E64V 0x60007007 1053 #define MASK_VLSEG4E64V 0xfdf0707f 1054 #define MATCH_VSSEG4E64V 0x60007027 1055 #define MASK_VSSEG4E64V 0xfdf0707f 1056 #define MATCH_VLSEG5E64V 0x80007007 1057 #define MASK_VLSEG5E64V 0xfdf0707f 1058 #define MATCH_VSSEG5E64V 0x80007027 1059 #define MASK_VSSEG5E64V 0xfdf0707f 1060 #define MATCH_VLSEG6E64V 0xa0007007 1061 #define MASK_VLSEG6E64V 0xfdf0707f 1062 #define MATCH_VSSEG6E64V 0xa0007027 1063 #define MASK_VSSEG6E64V 0xfdf0707f 1064 #define MATCH_VLSEG7E64V 0xc0007007 1065 #define MASK_VLSEG7E64V 0xfdf0707f 1066 #define MATCH_VSSEG7E64V 0xc0007027 1067 #define MASK_VSSEG7E64V 0xfdf0707f 1068 #define MATCH_VLSEG8E64V 0xe0007007 1069 #define MASK_VLSEG8E64V 0xfdf0707f 1070 #define MATCH_VSSEG8E64V 0xe0007027 1071 #define MASK_VSSEG8E64V 0xfdf0707f 1072 #define MATCH_VLSSEG2E8V 0x28000007 1073 #define MASK_VLSSEG2E8V 0xfc00707f 1074 #define MATCH_VSSSEG2E8V 0x28000027 1075 #define MASK_VSSSEG2E8V 0xfc00707f 1076 #define MATCH_VLSSEG3E8V 0x48000007 1077 #define MASK_VLSSEG3E8V 0xfc00707f 1078 #define MATCH_VSSSEG3E8V 0x48000027 1079 #define MASK_VSSSEG3E8V 0xfc00707f 1080 #define MATCH_VLSSEG4E8V 0x68000007 1081 #define MASK_VLSSEG4E8V 0xfc00707f 1082 #define MATCH_VSSSEG4E8V 0x68000027 1083 #define MASK_VSSSEG4E8V 0xfc00707f 1084 #define MATCH_VLSSEG5E8V 0x88000007 1085 #define MASK_VLSSEG5E8V 0xfc00707f 1086 #define MATCH_VSSSEG5E8V 0x88000027 1087 #define MASK_VSSSEG5E8V 0xfc00707f 1088 #define MATCH_VLSSEG6E8V 0xa8000007 1089 #define MASK_VLSSEG6E8V 0xfc00707f 1090 #define MATCH_VSSSEG6E8V 0xa8000027 1091 #define MASK_VSSSEG6E8V 0xfc00707f 1092 #define MATCH_VLSSEG7E8V 0xc8000007 1093 #define MASK_VLSSEG7E8V 0xfc00707f 1094 #define MATCH_VSSSEG7E8V 0xc8000027 1095 #define MASK_VSSSEG7E8V 0xfc00707f 1096 #define MATCH_VLSSEG8E8V 0xe8000007 1097 #define MASK_VLSSEG8E8V 0xfc00707f 1098 #define MATCH_VSSSEG8E8V 0xe8000027 1099 #define MASK_VSSSEG8E8V 0xfc00707f 1100 #define MATCH_VLSSEG2E16V 0x28005007 1101 #define MASK_VLSSEG2E16V 0xfc00707f 1102 #define MATCH_VSSSEG2E16V 0x28005027 1103 #define MASK_VSSSEG2E16V 0xfc00707f 1104 #define MATCH_VLSSEG3E16V 0x48005007 1105 #define MASK_VLSSEG3E16V 0xfc00707f 1106 #define MATCH_VSSSEG3E16V 0x48005027 1107 #define MASK_VSSSEG3E16V 0xfc00707f 1108 #define MATCH_VLSSEG4E16V 0x68005007 1109 #define MASK_VLSSEG4E16V 0xfc00707f 1110 #define MATCH_VSSSEG4E16V 0x68005027 1111 #define MASK_VSSSEG4E16V 0xfc00707f 1112 #define MATCH_VLSSEG5E16V 0x88005007 1113 #define MASK_VLSSEG5E16V 0xfc00707f 1114 #define MATCH_VSSSEG5E16V 0x88005027 1115 #define MASK_VSSSEG5E16V 0xfc00707f 1116 #define MATCH_VLSSEG6E16V 0xa8005007 1117 #define MASK_VLSSEG6E16V 0xfc00707f 1118 #define MATCH_VSSSEG6E16V 0xa8005027 1119 #define MASK_VSSSEG6E16V 0xfc00707f 1120 #define MATCH_VLSSEG7E16V 0xc8005007 1121 #define MASK_VLSSEG7E16V 0xfc00707f 1122 #define MATCH_VSSSEG7E16V 0xc8005027 1123 #define MASK_VSSSEG7E16V 0xfc00707f 1124 #define MATCH_VLSSEG8E16V 0xe8005007 1125 #define MASK_VLSSEG8E16V 0xfc00707f 1126 #define MATCH_VSSSEG8E16V 0xe8005027 1127 #define MASK_VSSSEG8E16V 0xfc00707f 1128 #define MATCH_VLSSEG2E32V 0x28006007 1129 #define MASK_VLSSEG2E32V 0xfc00707f 1130 #define MATCH_VSSSEG2E32V 0x28006027 1131 #define MASK_VSSSEG2E32V 0xfc00707f 1132 #define MATCH_VLSSEG3E32V 0x48006007 1133 #define MASK_VLSSEG3E32V 0xfc00707f 1134 #define MATCH_VSSSEG3E32V 0x48006027 1135 #define MASK_VSSSEG3E32V 0xfc00707f 1136 #define MATCH_VLSSEG4E32V 0x68006007 1137 #define MASK_VLSSEG4E32V 0xfc00707f 1138 #define MATCH_VSSSEG4E32V 0x68006027 1139 #define MASK_VSSSEG4E32V 0xfc00707f 1140 #define MATCH_VLSSEG5E32V 0x88006007 1141 #define MASK_VLSSEG5E32V 0xfc00707f 1142 #define MATCH_VSSSEG5E32V 0x88006027 1143 #define MASK_VSSSEG5E32V 0xfc00707f 1144 #define MATCH_VLSSEG6E32V 0xa8006007 1145 #define MASK_VLSSEG6E32V 0xfc00707f 1146 #define MATCH_VSSSEG6E32V 0xa8006027 1147 #define MASK_VSSSEG6E32V 0xfc00707f 1148 #define MATCH_VLSSEG7E32V 0xc8006007 1149 #define MASK_VLSSEG7E32V 0xfc00707f 1150 #define MATCH_VSSSEG7E32V 0xc8006027 1151 #define MASK_VSSSEG7E32V 0xfc00707f 1152 #define MATCH_VLSSEG8E32V 0xe8006007 1153 #define MASK_VLSSEG8E32V 0xfc00707f 1154 #define MATCH_VSSSEG8E32V 0xe8006027 1155 #define MASK_VSSSEG8E32V 0xfc00707f 1156 #define MATCH_VLSSEG2E64V 0x28007007 1157 #define MASK_VLSSEG2E64V 0xfc00707f 1158 #define MATCH_VSSSEG2E64V 0x28007027 1159 #define MASK_VSSSEG2E64V 0xfc00707f 1160 #define MATCH_VLSSEG3E64V 0x48007007 1161 #define MASK_VLSSEG3E64V 0xfc00707f 1162 #define MATCH_VSSSEG3E64V 0x48007027 1163 #define MASK_VSSSEG3E64V 0xfc00707f 1164 #define MATCH_VLSSEG4E64V 0x68007007 1165 #define MASK_VLSSEG4E64V 0xfc00707f 1166 #define MATCH_VSSSEG4E64V 0x68007027 1167 #define MASK_VSSSEG4E64V 0xfc00707f 1168 #define MATCH_VLSSEG5E64V 0x88007007 1169 #define MASK_VLSSEG5E64V 0xfc00707f 1170 #define MATCH_VSSSEG5E64V 0x88007027 1171 #define MASK_VSSSEG5E64V 0xfc00707f 1172 #define MATCH_VLSSEG6E64V 0xa8007007 1173 #define MASK_VLSSEG6E64V 0xfc00707f 1174 #define MATCH_VSSSEG6E64V 0xa8007027 1175 #define MASK_VSSSEG6E64V 0xfc00707f 1176 #define MATCH_VLSSEG7E64V 0xc8007007 1177 #define MASK_VLSSEG7E64V 0xfc00707f 1178 #define MATCH_VSSSEG7E64V 0xc8007027 1179 #define MASK_VSSSEG7E64V 0xfc00707f 1180 #define MATCH_VLSSEG8E64V 0xe8007007 1181 #define MASK_VLSSEG8E64V 0xfc00707f 1182 #define MATCH_VSSSEG8E64V 0xe8007027 1183 #define MASK_VSSSEG8E64V 0xfc00707f 1184 #define MATCH_VLOXSEG2EI8V 0x2c000007 1185 #define MASK_VLOXSEG2EI8V 0xfc00707f 1186 #define MATCH_VSOXSEG2EI8V 0x2c000027 1187 #define MASK_VSOXSEG2EI8V 0xfc00707f 1188 #define MATCH_VLOXSEG3EI8V 0x4c000007 1189 #define MASK_VLOXSEG3EI8V 0xfc00707f 1190 #define MATCH_VSOXSEG3EI8V 0x4c000027 1191 #define MASK_VSOXSEG3EI8V 0xfc00707f 1192 #define MATCH_VLOXSEG4EI8V 0x6c000007 1193 #define MASK_VLOXSEG4EI8V 0xfc00707f 1194 #define MATCH_VSOXSEG4EI8V 0x6c000027 1195 #define MASK_VSOXSEG4EI8V 0xfc00707f 1196 #define MATCH_VLOXSEG5EI8V 0x8c000007 1197 #define MASK_VLOXSEG5EI8V 0xfc00707f 1198 #define MATCH_VSOXSEG5EI8V 0x8c000027 1199 #define MASK_VSOXSEG5EI8V 0xfc00707f 1200 #define MATCH_VLOXSEG6EI8V 0xac000007 1201 #define MASK_VLOXSEG6EI8V 0xfc00707f 1202 #define MATCH_VSOXSEG6EI8V 0xac000027 1203 #define MASK_VSOXSEG6EI8V 0xfc00707f 1204 #define MATCH_VLOXSEG7EI8V 0xcc000007 1205 #define MASK_VLOXSEG7EI8V 0xfc00707f 1206 #define MATCH_VSOXSEG7EI8V 0xcc000027 1207 #define MASK_VSOXSEG7EI8V 0xfc00707f 1208 #define MATCH_VLOXSEG8EI8V 0xec000007 1209 #define MASK_VLOXSEG8EI8V 0xfc00707f 1210 #define MATCH_VSOXSEG8EI8V 0xec000027 1211 #define MASK_VSOXSEG8EI8V 0xfc00707f 1212 #define MATCH_VLUXSEG2EI8V 0x24000007 1213 #define MASK_VLUXSEG2EI8V 0xfc00707f 1214 #define MATCH_VSUXSEG2EI8V 0x24000027 1215 #define MASK_VSUXSEG2EI8V 0xfc00707f 1216 #define MATCH_VLUXSEG3EI8V 0x44000007 1217 #define MASK_VLUXSEG3EI8V 0xfc00707f 1218 #define MATCH_VSUXSEG3EI8V 0x44000027 1219 #define MASK_VSUXSEG3EI8V 0xfc00707f 1220 #define MATCH_VLUXSEG4EI8V 0x64000007 1221 #define MASK_VLUXSEG4EI8V 0xfc00707f 1222 #define MATCH_VSUXSEG4EI8V 0x64000027 1223 #define MASK_VSUXSEG4EI8V 0xfc00707f 1224 #define MATCH_VLUXSEG5EI8V 0x84000007 1225 #define MASK_VLUXSEG5EI8V 0xfc00707f 1226 #define MATCH_VSUXSEG5EI8V 0x84000027 1227 #define MASK_VSUXSEG5EI8V 0xfc00707f 1228 #define MATCH_VLUXSEG6EI8V 0xa4000007 1229 #define MASK_VLUXSEG6EI8V 0xfc00707f 1230 #define MATCH_VSUXSEG6EI8V 0xa4000027 1231 #define MASK_VSUXSEG6EI8V 0xfc00707f 1232 #define MATCH_VLUXSEG7EI8V 0xc4000007 1233 #define MASK_VLUXSEG7EI8V 0xfc00707f 1234 #define MATCH_VSUXSEG7EI8V 0xc4000027 1235 #define MASK_VSUXSEG7EI8V 0xfc00707f 1236 #define MATCH_VLUXSEG8EI8V 0xe4000007 1237 #define MASK_VLUXSEG8EI8V 0xfc00707f 1238 #define MATCH_VSUXSEG8EI8V 0xe4000027 1239 #define MASK_VSUXSEG8EI8V 0xfc00707f 1240 #define MATCH_VLOXSEG2EI16V 0x2c005007 1241 #define MASK_VLOXSEG2EI16V 0xfc00707f 1242 #define MATCH_VSOXSEG2EI16V 0x2c005027 1243 #define MASK_VSOXSEG2EI16V 0xfc00707f 1244 #define MATCH_VLOXSEG3EI16V 0x4c005007 1245 #define MASK_VLOXSEG3EI16V 0xfc00707f 1246 #define MATCH_VSOXSEG3EI16V 0x4c005027 1247 #define MASK_VSOXSEG3EI16V 0xfc00707f 1248 #define MATCH_VLOXSEG4EI16V 0x6c005007 1249 #define MASK_VLOXSEG4EI16V 0xfc00707f 1250 #define MATCH_VSOXSEG4EI16V 0x6c005027 1251 #define MASK_VSOXSEG4EI16V 0xfc00707f 1252 #define MATCH_VLOXSEG5EI16V 0x8c005007 1253 #define MASK_VLOXSEG5EI16V 0xfc00707f 1254 #define MATCH_VSOXSEG5EI16V 0x8c005027 1255 #define MASK_VSOXSEG5EI16V 0xfc00707f 1256 #define MATCH_VLOXSEG6EI16V 0xac005007 1257 #define MASK_VLOXSEG6EI16V 0xfc00707f 1258 #define MATCH_VSOXSEG6EI16V 0xac005027 1259 #define MASK_VSOXSEG6EI16V 0xfc00707f 1260 #define MATCH_VLOXSEG7EI16V 0xcc005007 1261 #define MASK_VLOXSEG7EI16V 0xfc00707f 1262 #define MATCH_VSOXSEG7EI16V 0xcc005027 1263 #define MASK_VSOXSEG7EI16V 0xfc00707f 1264 #define MATCH_VLOXSEG8EI16V 0xec005007 1265 #define MASK_VLOXSEG8EI16V 0xfc00707f 1266 #define MATCH_VSOXSEG8EI16V 0xec005027 1267 #define MASK_VSOXSEG8EI16V 0xfc00707f 1268 #define MATCH_VLUXSEG2EI16V 0x24005007 1269 #define MASK_VLUXSEG2EI16V 0xfc00707f 1270 #define MATCH_VSUXSEG2EI16V 0x24005027 1271 #define MASK_VSUXSEG2EI16V 0xfc00707f 1272 #define MATCH_VLUXSEG3EI16V 0x44005007 1273 #define MASK_VLUXSEG3EI16V 0xfc00707f 1274 #define MATCH_VSUXSEG3EI16V 0x44005027 1275 #define MASK_VSUXSEG3EI16V 0xfc00707f 1276 #define MATCH_VLUXSEG4EI16V 0x64005007 1277 #define MASK_VLUXSEG4EI16V 0xfc00707f 1278 #define MATCH_VSUXSEG4EI16V 0x64005027 1279 #define MASK_VSUXSEG4EI16V 0xfc00707f 1280 #define MATCH_VLUXSEG5EI16V 0x84005007 1281 #define MASK_VLUXSEG5EI16V 0xfc00707f 1282 #define MATCH_VSUXSEG5EI16V 0x84005027 1283 #define MASK_VSUXSEG5EI16V 0xfc00707f 1284 #define MATCH_VLUXSEG6EI16V 0xa4005007 1285 #define MASK_VLUXSEG6EI16V 0xfc00707f 1286 #define MATCH_VSUXSEG6EI16V 0xa4005027 1287 #define MASK_VSUXSEG6EI16V 0xfc00707f 1288 #define MATCH_VLUXSEG7EI16V 0xc4005007 1289 #define MASK_VLUXSEG7EI16V 0xfc00707f 1290 #define MATCH_VSUXSEG7EI16V 0xc4005027 1291 #define MASK_VSUXSEG7EI16V 0xfc00707f 1292 #define MATCH_VLUXSEG8EI16V 0xe4005007 1293 #define MASK_VLUXSEG8EI16V 0xfc00707f 1294 #define MATCH_VSUXSEG8EI16V 0xe4005027 1295 #define MASK_VSUXSEG8EI16V 0xfc00707f 1296 #define MATCH_VLOXSEG2EI32V 0x2c006007 1297 #define MASK_VLOXSEG2EI32V 0xfc00707f 1298 #define MATCH_VSOXSEG2EI32V 0x2c006027 1299 #define MASK_VSOXSEG2EI32V 0xfc00707f 1300 #define MATCH_VLOXSEG3EI32V 0x4c006007 1301 #define MASK_VLOXSEG3EI32V 0xfc00707f 1302 #define MATCH_VSOXSEG3EI32V 0x4c006027 1303 #define MASK_VSOXSEG3EI32V 0xfc00707f 1304 #define MATCH_VLOXSEG4EI32V 0x6c006007 1305 #define MASK_VLOXSEG4EI32V 0xfc00707f 1306 #define MATCH_VSOXSEG4EI32V 0x6c006027 1307 #define MASK_VSOXSEG4EI32V 0xfc00707f 1308 #define MATCH_VLOXSEG5EI32V 0x8c006007 1309 #define MASK_VLOXSEG5EI32V 0xfc00707f 1310 #define MATCH_VSOXSEG5EI32V 0x8c006027 1311 #define MASK_VSOXSEG5EI32V 0xfc00707f 1312 #define MATCH_VLOXSEG6EI32V 0xac006007 1313 #define MASK_VLOXSEG6EI32V 0xfc00707f 1314 #define MATCH_VSOXSEG6EI32V 0xac006027 1315 #define MASK_VSOXSEG6EI32V 0xfc00707f 1316 #define MATCH_VLOXSEG7EI32V 0xcc006007 1317 #define MASK_VLOXSEG7EI32V 0xfc00707f 1318 #define MATCH_VSOXSEG7EI32V 0xcc006027 1319 #define MASK_VSOXSEG7EI32V 0xfc00707f 1320 #define MATCH_VLOXSEG8EI32V 0xec006007 1321 #define MASK_VLOXSEG8EI32V 0xfc00707f 1322 #define MATCH_VSOXSEG8EI32V 0xec006027 1323 #define MASK_VSOXSEG8EI32V 0xfc00707f 1324 #define MATCH_VLUXSEG2EI32V 0x24006007 1325 #define MASK_VLUXSEG2EI32V 0xfc00707f 1326 #define MATCH_VSUXSEG2EI32V 0x24006027 1327 #define MASK_VSUXSEG2EI32V 0xfc00707f 1328 #define MATCH_VLUXSEG3EI32V 0x44006007 1329 #define MASK_VLUXSEG3EI32V 0xfc00707f 1330 #define MATCH_VSUXSEG3EI32V 0x44006027 1331 #define MASK_VSUXSEG3EI32V 0xfc00707f 1332 #define MATCH_VLUXSEG4EI32V 0x64006007 1333 #define MASK_VLUXSEG4EI32V 0xfc00707f 1334 #define MATCH_VSUXSEG4EI32V 0x64006027 1335 #define MASK_VSUXSEG4EI32V 0xfc00707f 1336 #define MATCH_VLUXSEG5EI32V 0x84006007 1337 #define MASK_VLUXSEG5EI32V 0xfc00707f 1338 #define MATCH_VSUXSEG5EI32V 0x84006027 1339 #define MASK_VSUXSEG5EI32V 0xfc00707f 1340 #define MATCH_VLUXSEG6EI32V 0xa4006007 1341 #define MASK_VLUXSEG6EI32V 0xfc00707f 1342 #define MATCH_VSUXSEG6EI32V 0xa4006027 1343 #define MASK_VSUXSEG6EI32V 0xfc00707f 1344 #define MATCH_VLUXSEG7EI32V 0xc4006007 1345 #define MASK_VLUXSEG7EI32V 0xfc00707f 1346 #define MATCH_VSUXSEG7EI32V 0xc4006027 1347 #define MASK_VSUXSEG7EI32V 0xfc00707f 1348 #define MATCH_VLUXSEG8EI32V 0xe4006007 1349 #define MASK_VLUXSEG8EI32V 0xfc00707f 1350 #define MATCH_VSUXSEG8EI32V 0xe4006027 1351 #define MASK_VSUXSEG8EI32V 0xfc00707f 1352 #define MATCH_VLOXSEG2EI64V 0x2c007007 1353 #define MASK_VLOXSEG2EI64V 0xfc00707f 1354 #define MATCH_VSOXSEG2EI64V 0x2c007027 1355 #define MASK_VSOXSEG2EI64V 0xfc00707f 1356 #define MATCH_VLOXSEG3EI64V 0x4c007007 1357 #define MASK_VLOXSEG3EI64V 0xfc00707f 1358 #define MATCH_VSOXSEG3EI64V 0x4c007027 1359 #define MASK_VSOXSEG3EI64V 0xfc00707f 1360 #define MATCH_VLOXSEG4EI64V 0x6c007007 1361 #define MASK_VLOXSEG4EI64V 0xfc00707f 1362 #define MATCH_VSOXSEG4EI64V 0x6c007027 1363 #define MASK_VSOXSEG4EI64V 0xfc00707f 1364 #define MATCH_VLOXSEG5EI64V 0x8c007007 1365 #define MASK_VLOXSEG5EI64V 0xfc00707f 1366 #define MATCH_VSOXSEG5EI64V 0x8c007027 1367 #define MASK_VSOXSEG5EI64V 0xfc00707f 1368 #define MATCH_VLOXSEG6EI64V 0xac007007 1369 #define MASK_VLOXSEG6EI64V 0xfc00707f 1370 #define MATCH_VSOXSEG6EI64V 0xac007027 1371 #define MASK_VSOXSEG6EI64V 0xfc00707f 1372 #define MATCH_VLOXSEG7EI64V 0xcc007007 1373 #define MASK_VLOXSEG7EI64V 0xfc00707f 1374 #define MATCH_VSOXSEG7EI64V 0xcc007027 1375 #define MASK_VSOXSEG7EI64V 0xfc00707f 1376 #define MATCH_VLOXSEG8EI64V 0xec007007 1377 #define MASK_VLOXSEG8EI64V 0xfc00707f 1378 #define MATCH_VSOXSEG8EI64V 0xec007027 1379 #define MASK_VSOXSEG8EI64V 0xfc00707f 1380 #define MATCH_VLUXSEG2EI64V 0x24007007 1381 #define MASK_VLUXSEG2EI64V 0xfc00707f 1382 #define MATCH_VSUXSEG2EI64V 0x24007027 1383 #define MASK_VSUXSEG2EI64V 0xfc00707f 1384 #define MATCH_VLUXSEG3EI64V 0x44007007 1385 #define MASK_VLUXSEG3EI64V 0xfc00707f 1386 #define MATCH_VSUXSEG3EI64V 0x44007027 1387 #define MASK_VSUXSEG3EI64V 0xfc00707f 1388 #define MATCH_VLUXSEG4EI64V 0x64007007 1389 #define MASK_VLUXSEG4EI64V 0xfc00707f 1390 #define MATCH_VSUXSEG4EI64V 0x64007027 1391 #define MASK_VSUXSEG4EI64V 0xfc00707f 1392 #define MATCH_VLUXSEG5EI64V 0x84007007 1393 #define MASK_VLUXSEG5EI64V 0xfc00707f 1394 #define MATCH_VSUXSEG5EI64V 0x84007027 1395 #define MASK_VSUXSEG5EI64V 0xfc00707f 1396 #define MATCH_VLUXSEG6EI64V 0xa4007007 1397 #define MASK_VLUXSEG6EI64V 0xfc00707f 1398 #define MATCH_VSUXSEG6EI64V 0xa4007027 1399 #define MASK_VSUXSEG6EI64V 0xfc00707f 1400 #define MATCH_VLUXSEG7EI64V 0xc4007007 1401 #define MASK_VLUXSEG7EI64V 0xfc00707f 1402 #define MATCH_VSUXSEG7EI64V 0xc4007027 1403 #define MASK_VSUXSEG7EI64V 0xfc00707f 1404 #define MATCH_VLUXSEG8EI64V 0xe4007007 1405 #define MASK_VLUXSEG8EI64V 0xfc00707f 1406 #define MATCH_VSUXSEG8EI64V 0xe4007027 1407 #define MASK_VSUXSEG8EI64V 0xfc00707f 1408 #define MATCH_VLSEG2E8FFV 0x21000007 1409 #define MASK_VLSEG2E8FFV 0xfdf0707f 1410 #define MATCH_VLSEG3E8FFV 0x41000007 1411 #define MASK_VLSEG3E8FFV 0xfdf0707f 1412 #define MATCH_VLSEG4E8FFV 0x61000007 1413 #define MASK_VLSEG4E8FFV 0xfdf0707f 1414 #define MATCH_VLSEG5E8FFV 0x81000007 1415 #define MASK_VLSEG5E8FFV 0xfdf0707f 1416 #define MATCH_VLSEG6E8FFV 0xa1000007 1417 #define MASK_VLSEG6E8FFV 0xfdf0707f 1418 #define MATCH_VLSEG7E8FFV 0xc1000007 1419 #define MASK_VLSEG7E8FFV 0xfdf0707f 1420 #define MATCH_VLSEG8E8FFV 0xe1000007 1421 #define MASK_VLSEG8E8FFV 0xfdf0707f 1422 #define MATCH_VLSEG2E16FFV 0x21005007 1423 #define MASK_VLSEG2E16FFV 0xfdf0707f 1424 #define MATCH_VLSEG3E16FFV 0x41005007 1425 #define MASK_VLSEG3E16FFV 0xfdf0707f 1426 #define MATCH_VLSEG4E16FFV 0x61005007 1427 #define MASK_VLSEG4E16FFV 0xfdf0707f 1428 #define MATCH_VLSEG5E16FFV 0x81005007 1429 #define MASK_VLSEG5E16FFV 0xfdf0707f 1430 #define MATCH_VLSEG6E16FFV 0xa1005007 1431 #define MASK_VLSEG6E16FFV 0xfdf0707f 1432 #define MATCH_VLSEG7E16FFV 0xc1005007 1433 #define MASK_VLSEG7E16FFV 0xfdf0707f 1434 #define MATCH_VLSEG8E16FFV 0xe1005007 1435 #define MASK_VLSEG8E16FFV 0xfdf0707f 1436 #define MATCH_VLSEG2E32FFV 0x21006007 1437 #define MASK_VLSEG2E32FFV 0xfdf0707f 1438 #define MATCH_VLSEG3E32FFV 0x41006007 1439 #define MASK_VLSEG3E32FFV 0xfdf0707f 1440 #define MATCH_VLSEG4E32FFV 0x61006007 1441 #define MASK_VLSEG4E32FFV 0xfdf0707f 1442 #define MATCH_VLSEG5E32FFV 0x81006007 1443 #define MASK_VLSEG5E32FFV 0xfdf0707f 1444 #define MATCH_VLSEG6E32FFV 0xa1006007 1445 #define MASK_VLSEG6E32FFV 0xfdf0707f 1446 #define MATCH_VLSEG7E32FFV 0xc1006007 1447 #define MASK_VLSEG7E32FFV 0xfdf0707f 1448 #define MATCH_VLSEG8E32FFV 0xe1006007 1449 #define MASK_VLSEG8E32FFV 0xfdf0707f 1450 #define MATCH_VLSEG2E64FFV 0x21007007 1451 #define MASK_VLSEG2E64FFV 0xfdf0707f 1452 #define MATCH_VLSEG3E64FFV 0x41007007 1453 #define MASK_VLSEG3E64FFV 0xfdf0707f 1454 #define MATCH_VLSEG4E64FFV 0x61007007 1455 #define MASK_VLSEG4E64FFV 0xfdf0707f 1456 #define MATCH_VLSEG5E64FFV 0x81007007 1457 #define MASK_VLSEG5E64FFV 0xfdf0707f 1458 #define MATCH_VLSEG6E64FFV 0xa1007007 1459 #define MASK_VLSEG6E64FFV 0xfdf0707f 1460 #define MATCH_VLSEG7E64FFV 0xc1007007 1461 #define MASK_VLSEG7E64FFV 0xfdf0707f 1462 #define MATCH_VLSEG8E64FFV 0xe1007007 1463 #define MASK_VLSEG8E64FFV 0xfdf0707f 1464 #define MATCH_VL1RE8V 0x02800007 1465 #define MASK_VL1RE8V 0xfff0707f 1466 #define MATCH_VL1RE16V 0x02805007 1467 #define MASK_VL1RE16V 0xfff0707f 1468 #define MATCH_VL1RE32V 0x02806007 1469 #define MASK_VL1RE32V 0xfff0707f 1470 #define MATCH_VL1RE64V 0x02807007 1471 #define MASK_VL1RE64V 0xfff0707f 1472 #define MATCH_VL2RE8V 0x22800007 1473 #define MASK_VL2RE8V 0xfff0707f 1474 #define MATCH_VL2RE16V 0x22805007 1475 #define MASK_VL2RE16V 0xfff0707f 1476 #define MATCH_VL2RE32V 0x22806007 1477 #define MASK_VL2RE32V 0xfff0707f 1478 #define MATCH_VL2RE64V 0x22807007 1479 #define MASK_VL2RE64V 0xfff0707f 1480 #define MATCH_VL4RE8V 0x62800007 1481 #define MASK_VL4RE8V 0xfff0707f 1482 #define MATCH_VL4RE16V 0x62805007 1483 #define MASK_VL4RE16V 0xfff0707f 1484 #define MATCH_VL4RE32V 0x62806007 1485 #define MASK_VL4RE32V 0xfff0707f 1486 #define MATCH_VL4RE64V 0x62807007 1487 #define MASK_VL4RE64V 0xfff0707f 1488 #define MATCH_VL8RE8V 0xe2800007 1489 #define MASK_VL8RE8V 0xfff0707f 1490 #define MATCH_VL8RE16V 0xe2805007 1491 #define MASK_VL8RE16V 0xfff0707f 1492 #define MATCH_VL8RE32V 0xe2806007 1493 #define MASK_VL8RE32V 0xfff0707f 1494 #define MATCH_VL8RE64V 0xe2807007 1495 #define MASK_VL8RE64V 0xfff0707f 1496 #define MATCH_VS1RV 0x02800027 1497 #define MASK_VS1RV 0xfff0707f 1498 #define MATCH_VS2RV 0x22800027 1499 #define MASK_VS2RV 0xfff0707f 1500 #define MATCH_VS4RV 0x62800027 1501 #define MASK_VS4RV 0xfff0707f 1502 #define MATCH_VS8RV 0xe2800027 1503 #define MASK_VS8RV 0xfff0707f 1504 #define MATCH_VADDVV 0x00000057 1505 #define MASK_VADDVV 0xfc00707f 1506 #define MATCH_VADDVX 0x00004057 1507 #define MASK_VADDVX 0xfc00707f 1508 #define MATCH_VADDVI 0x00003057 1509 #define MASK_VADDVI 0xfc00707f 1510 #define MATCH_VSUBVV 0x08000057 1511 #define MASK_VSUBVV 0xfc00707f 1512 #define MATCH_VSUBVX 0x08004057 1513 #define MASK_VSUBVX 0xfc00707f 1514 #define MATCH_VRSUBVX 0x0c004057 1515 #define MASK_VRSUBVX 0xfc00707f 1516 #define MATCH_VRSUBVI 0x0c003057 1517 #define MASK_VRSUBVI 0xfc00707f 1518 #define MATCH_VWCVTXXV 0xc4006057 1519 #define MASK_VWCVTXXV 0xfc0ff07f 1520 #define MATCH_VWCVTUXXV 0xc0006057 1521 #define MASK_VWCVTUXXV 0xfc0ff07f 1522 #define MATCH_VWADDVV 0xc4002057 1523 #define MASK_VWADDVV 0xfc00707f 1524 #define MATCH_VWADDVX 0xc4006057 1525 #define MASK_VWADDVX 0xfc00707f 1526 #define MATCH_VWSUBVV 0xcc002057 1527 #define MASK_VWSUBVV 0xfc00707f 1528 #define MATCH_VWSUBVX 0xcc006057 1529 #define MASK_VWSUBVX 0xfc00707f 1530 #define MATCH_VWADDWV 0xd4002057 1531 #define MASK_VWADDWV 0xfc00707f 1532 #define MATCH_VWADDWX 0xd4006057 1533 #define MASK_VWADDWX 0xfc00707f 1534 #define MATCH_VWSUBWV 0xdc002057 1535 #define MASK_VWSUBWV 0xfc00707f 1536 #define MATCH_VWSUBWX 0xdc006057 1537 #define MASK_VWSUBWX 0xfc00707f 1538 #define MATCH_VWADDUVV 0xc0002057 1539 #define MASK_VWADDUVV 0xfc00707f 1540 #define MATCH_VWADDUVX 0xc0006057 1541 #define MASK_VWADDUVX 0xfc00707f 1542 #define MATCH_VWSUBUVV 0xc8002057 1543 #define MASK_VWSUBUVV 0xfc00707f 1544 #define MATCH_VWSUBUVX 0xc8006057 1545 #define MASK_VWSUBUVX 0xfc00707f 1546 #define MATCH_VWADDUWV 0xd0002057 1547 #define MASK_VWADDUWV 0xfc00707f 1548 #define MATCH_VWADDUWX 0xd0006057 1549 #define MASK_VWADDUWX 0xfc00707f 1550 #define MATCH_VWSUBUWV 0xd8002057 1551 #define MASK_VWSUBUWV 0xfc00707f 1552 #define MATCH_VWSUBUWX 0xd8006057 1553 #define MASK_VWSUBUWX 0xfc00707f 1554 #define MATCH_VZEXT_VF8 0x48012057 1555 #define MASK_VZEXT_VF8 0xfc0ff07f 1556 #define MATCH_VSEXT_VF8 0x4801a057 1557 #define MASK_VSEXT_VF8 0xfc0ff07f 1558 #define MATCH_VZEXT_VF4 0x48022057 1559 #define MASK_VZEXT_VF4 0xfc0ff07f 1560 #define MATCH_VSEXT_VF4 0x4802a057 1561 #define MASK_VSEXT_VF4 0xfc0ff07f 1562 #define MATCH_VZEXT_VF2 0x48032057 1563 #define MASK_VZEXT_VF2 0xfc0ff07f 1564 #define MATCH_VSEXT_VF2 0x4803a057 1565 #define MASK_VSEXT_VF2 0xfc0ff07f 1566 #define MATCH_VADCVVM 0x40000057 1567 #define MASK_VADCVVM 0xfe00707f 1568 #define MATCH_VADCVXM 0x40004057 1569 #define MASK_VADCVXM 0xfe00707f 1570 #define MATCH_VADCVIM 0x40003057 1571 #define MASK_VADCVIM 0xfe00707f 1572 #define MATCH_VMADCVVM 0x44000057 1573 #define MASK_VMADCVVM 0xfe00707f 1574 #define MATCH_VMADCVXM 0x44004057 1575 #define MASK_VMADCVXM 0xfe00707f 1576 #define MATCH_VMADCVIM 0x44003057 1577 #define MASK_VMADCVIM 0xfe00707f 1578 #define MATCH_VMADCVV 0x46000057 1579 #define MASK_VMADCVV 0xfe00707f 1580 #define MATCH_VMADCVX 0x46004057 1581 #define MASK_VMADCVX 0xfe00707f 1582 #define MATCH_VMADCVI 0x46003057 1583 #define MASK_VMADCVI 0xfe00707f 1584 #define MATCH_VSBCVVM 0x48000057 1585 #define MASK_VSBCVVM 0xfe00707f 1586 #define MATCH_VSBCVXM 0x48004057 1587 #define MASK_VSBCVXM 0xfe00707f 1588 #define MATCH_VMSBCVVM 0x4c000057 1589 #define MASK_VMSBCVVM 0xfe00707f 1590 #define MATCH_VMSBCVXM 0x4c004057 1591 #define MASK_VMSBCVXM 0xfe00707f 1592 #define MATCH_VMSBCVV 0x4e000057 1593 #define MASK_VMSBCVV 0xfe00707f 1594 #define MATCH_VMSBCVX 0x4e004057 1595 #define MASK_VMSBCVX 0xfe00707f 1596 #define MATCH_VNOTV 0x2c0fb057 1597 #define MASK_VNOTV 0xfc0ff07f 1598 #define MATCH_VANDVV 0x24000057 1599 #define MASK_VANDVV 0xfc00707f 1600 #define MATCH_VANDVX 0x24004057 1601 #define MASK_VANDVX 0xfc00707f 1602 #define MATCH_VANDVI 0x24003057 1603 #define MASK_VANDVI 0xfc00707f 1604 #define MATCH_VORVV 0x28000057 1605 #define MASK_VORVV 0xfc00707f 1606 #define MATCH_VORVX 0x28004057 1607 #define MASK_VORVX 0xfc00707f 1608 #define MATCH_VORVI 0x28003057 1609 #define MASK_VORVI 0xfc00707f 1610 #define MATCH_VXORVV 0x2c000057 1611 #define MASK_VXORVV 0xfc00707f 1612 #define MATCH_VXORVX 0x2c004057 1613 #define MASK_VXORVX 0xfc00707f 1614 #define MATCH_VXORVI 0x2c003057 1615 #define MASK_VXORVI 0xfc00707f 1616 #define MATCH_VSLLVV 0x94000057 1617 #define MASK_VSLLVV 0xfc00707f 1618 #define MATCH_VSLLVX 0x94004057 1619 #define MASK_VSLLVX 0xfc00707f 1620 #define MATCH_VSLLVI 0x94003057 1621 #define MASK_VSLLVI 0xfc00707f 1622 #define MATCH_VSRLVV 0xa0000057 1623 #define MASK_VSRLVV 0xfc00707f 1624 #define MATCH_VSRLVX 0xa0004057 1625 #define MASK_VSRLVX 0xfc00707f 1626 #define MATCH_VSRLVI 0xa0003057 1627 #define MASK_VSRLVI 0xfc00707f 1628 #define MATCH_VSRAVV 0xa4000057 1629 #define MASK_VSRAVV 0xfc00707f 1630 #define MATCH_VSRAVX 0xa4004057 1631 #define MASK_VSRAVX 0xfc00707f 1632 #define MATCH_VSRAVI 0xa4003057 1633 #define MASK_VSRAVI 0xfc00707f 1634 #define MATCH_VNCVTXXW 0xb0004057 1635 #define MASK_VNCVTXXW 0xfc0ff07f 1636 #define MATCH_VNSRLWV 0xb0000057 1637 #define MASK_VNSRLWV 0xfc00707f 1638 #define MATCH_VNSRLWX 0xb0004057 1639 #define MASK_VNSRLWX 0xfc00707f 1640 #define MATCH_VNSRLWI 0xb0003057 1641 #define MASK_VNSRLWI 0xfc00707f 1642 #define MATCH_VNSRAWV 0xb4000057 1643 #define MASK_VNSRAWV 0xfc00707f 1644 #define MATCH_VNSRAWX 0xb4004057 1645 #define MASK_VNSRAWX 0xfc00707f 1646 #define MATCH_VNSRAWI 0xb4003057 1647 #define MASK_VNSRAWI 0xfc00707f 1648 #define MATCH_VMSEQVV 0x60000057 1649 #define MASK_VMSEQVV 0xfc00707f 1650 #define MATCH_VMSEQVX 0x60004057 1651 #define MASK_VMSEQVX 0xfc00707f 1652 #define MATCH_VMSEQVI 0x60003057 1653 #define MASK_VMSEQVI 0xfc00707f 1654 #define MATCH_VMSNEVV 0x64000057 1655 #define MASK_VMSNEVV 0xfc00707f 1656 #define MATCH_VMSNEVX 0x64004057 1657 #define MASK_VMSNEVX 0xfc00707f 1658 #define MATCH_VMSNEVI 0x64003057 1659 #define MASK_VMSNEVI 0xfc00707f 1660 #define MATCH_VMSLTVV 0x6c000057 1661 #define MASK_VMSLTVV 0xfc00707f 1662 #define MATCH_VMSLTVX 0x6c004057 1663 #define MASK_VMSLTVX 0xfc00707f 1664 #define MATCH_VMSLTUVV 0x68000057 1665 #define MASK_VMSLTUVV 0xfc00707f 1666 #define MATCH_VMSLTUVX 0x68004057 1667 #define MASK_VMSLTUVX 0xfc00707f 1668 #define MATCH_VMSLEVV 0x74000057 1669 #define MASK_VMSLEVV 0xfc00707f 1670 #define MATCH_VMSLEVX 0x74004057 1671 #define MASK_VMSLEVX 0xfc00707f 1672 #define MATCH_VMSLEVI 0x74003057 1673 #define MASK_VMSLEVI 0xfc00707f 1674 #define MATCH_VMSLEUVV 0x70000057 1675 #define MASK_VMSLEUVV 0xfc00707f 1676 #define MATCH_VMSLEUVX 0x70004057 1677 #define MASK_VMSLEUVX 0xfc00707f 1678 #define MATCH_VMSLEUVI 0x70003057 1679 #define MASK_VMSLEUVI 0xfc00707f 1680 #define MATCH_VMSGTVX 0x7c004057 1681 #define MASK_VMSGTVX 0xfc00707f 1682 #define MATCH_VMSGTVI 0x7c003057 1683 #define MASK_VMSGTVI 0xfc00707f 1684 #define MATCH_VMSGTUVX 0x78004057 1685 #define MASK_VMSGTUVX 0xfc00707f 1686 #define MATCH_VMSGTUVI 0x78003057 1687 #define MASK_VMSGTUVI 0xfc00707f 1688 #define MATCH_VMINVV 0x14000057 1689 #define MASK_VMINVV 0xfc00707f 1690 #define MATCH_VMINVX 0x14004057 1691 #define MASK_VMINVX 0xfc00707f 1692 #define MATCH_VMAXVV 0x1c000057 1693 #define MASK_VMAXVV 0xfc00707f 1694 #define MATCH_VMAXVX 0x1c004057 1695 #define MASK_VMAXVX 0xfc00707f 1696 #define MATCH_VMINUVV 0x10000057 1697 #define MASK_VMINUVV 0xfc00707f 1698 #define MATCH_VMINUVX 0x10004057 1699 #define MASK_VMINUVX 0xfc00707f 1700 #define MATCH_VMAXUVV 0x18000057 1701 #define MASK_VMAXUVV 0xfc00707f 1702 #define MATCH_VMAXUVX 0x18004057 1703 #define MASK_VMAXUVX 0xfc00707f 1704 #define MATCH_VMULVV 0x94002057 1705 #define MASK_VMULVV 0xfc00707f 1706 #define MATCH_VMULVX 0x94006057 1707 #define MASK_VMULVX 0xfc00707f 1708 #define MATCH_VMULHVV 0x9c002057 1709 #define MASK_VMULHVV 0xfc00707f 1710 #define MATCH_VMULHVX 0x9c006057 1711 #define MASK_VMULHVX 0xfc00707f 1712 #define MATCH_VMULHUVV 0x90002057 1713 #define MASK_VMULHUVV 0xfc00707f 1714 #define MATCH_VMULHUVX 0x90006057 1715 #define MASK_VMULHUVX 0xfc00707f 1716 #define MATCH_VMULHSUVV 0x98002057 1717 #define MASK_VMULHSUVV 0xfc00707f 1718 #define MATCH_VMULHSUVX 0x98006057 1719 #define MASK_VMULHSUVX 0xfc00707f 1720 #define MATCH_VWMULVV 0xec002057 1721 #define MASK_VWMULVV 0xfc00707f 1722 #define MATCH_VWMULVX 0xec006057 1723 #define MASK_VWMULVX 0xfc00707f 1724 #define MATCH_VWMULUVV 0xe0002057 1725 #define MASK_VWMULUVV 0xfc00707f 1726 #define MATCH_VWMULUVX 0xe0006057 1727 #define MASK_VWMULUVX 0xfc00707f 1728 #define MATCH_VWMULSUVV 0xe8002057 1729 #define MASK_VWMULSUVV 0xfc00707f 1730 #define MATCH_VWMULSUVX 0xe8006057 1731 #define MASK_VWMULSUVX 0xfc00707f 1732 #define MATCH_VMACCVV 0xb4002057 1733 #define MASK_VMACCVV 0xfc00707f 1734 #define MATCH_VMACCVX 0xb4006057 1735 #define MASK_VMACCVX 0xfc00707f 1736 #define MATCH_VNMSACVV 0xbc002057 1737 #define MASK_VNMSACVV 0xfc00707f 1738 #define MATCH_VNMSACVX 0xbc006057 1739 #define MASK_VNMSACVX 0xfc00707f 1740 #define MATCH_VMADDVV 0xa4002057 1741 #define MASK_VMADDVV 0xfc00707f 1742 #define MATCH_VMADDVX 0xa4006057 1743 #define MASK_VMADDVX 0xfc00707f 1744 #define MATCH_VNMSUBVV 0xac002057 1745 #define MASK_VNMSUBVV 0xfc00707f 1746 #define MATCH_VNMSUBVX 0xac006057 1747 #define MASK_VNMSUBVX 0xfc00707f 1748 #define MATCH_VWMACCUVV 0xf0002057 1749 #define MASK_VWMACCUVV 0xfc00707f 1750 #define MATCH_VWMACCUVX 0xf0006057 1751 #define MASK_VWMACCUVX 0xfc00707f 1752 #define MATCH_VWMACCVV 0xf4002057 1753 #define MASK_VWMACCVV 0xfc00707f 1754 #define MATCH_VWMACCVX 0xf4006057 1755 #define MASK_VWMACCVX 0xfc00707f 1756 #define MATCH_VWMACCSUVV 0xfc002057 1757 #define MASK_VWMACCSUVV 0xfc00707f 1758 #define MATCH_VWMACCSUVX 0xfc006057 1759 #define MASK_VWMACCSUVX 0xfc00707f 1760 #define MATCH_VWMACCUSVX 0xf8006057 1761 #define MASK_VWMACCUSVX 0xfc00707f 1762 #define MATCH_VQMACCUVV 0xf0000057 1763 #define MASK_VQMACCUVV 0xfc00707f 1764 #define MATCH_VQMACCUVX 0xf0004057 1765 #define MASK_VQMACCUVX 0xfc00707f 1766 #define MATCH_VQMACCVV 0xf4000057 1767 #define MASK_VQMACCVV 0xfc00707f 1768 #define MATCH_VQMACCVX 0xf4004057 1769 #define MASK_VQMACCVX 0xfc00707f 1770 #define MATCH_VQMACCSUVV 0xfc000057 1771 #define MASK_VQMACCSUVV 0xfc00707f 1772 #define MATCH_VQMACCSUVX 0xfc004057 1773 #define MASK_VQMACCSUVX 0xfc00707f 1774 #define MATCH_VQMACCUSVX 0xf8004057 1775 #define MASK_VQMACCUSVX 0xfc00707f 1776 #define MATCH_VDIVVV 0x84002057 1777 #define MASK_VDIVVV 0xfc00707f 1778 #define MATCH_VDIVVX 0x84006057 1779 #define MASK_VDIVVX 0xfc00707f 1780 #define MATCH_VDIVUVV 0x80002057 1781 #define MASK_VDIVUVV 0xfc00707f 1782 #define MATCH_VDIVUVX 0x80006057 1783 #define MASK_VDIVUVX 0xfc00707f 1784 #define MATCH_VREMVV 0x8c002057 1785 #define MASK_VREMVV 0xfc00707f 1786 #define MATCH_VREMVX 0x8c006057 1787 #define MASK_VREMVX 0xfc00707f 1788 #define MATCH_VREMUVV 0x88002057 1789 #define MASK_VREMUVV 0xfc00707f 1790 #define MATCH_VREMUVX 0x88006057 1791 #define MASK_VREMUVX 0xfc00707f 1792 #define MATCH_VMERGEVVM 0x5c000057 1793 #define MASK_VMERGEVVM 0xfe00707f 1794 #define MATCH_VMERGEVXM 0x5c004057 1795 #define MASK_VMERGEVXM 0xfe00707f 1796 #define MATCH_VMERGEVIM 0x5c003057 1797 #define MASK_VMERGEVIM 0xfe00707f 1798 #define MATCH_VMVVV 0x5e000057 1799 #define MASK_VMVVV 0xfff0707f 1800 #define MATCH_VMVVX 0x5e004057 1801 #define MASK_VMVVX 0xfff0707f 1802 #define MATCH_VMVVI 0x5e003057 1803 #define MASK_VMVVI 0xfff0707f 1804 #define MATCH_VSADDUVV 0x80000057 1805 #define MASK_VSADDUVV 0xfc00707f 1806 #define MATCH_VSADDUVX 0x80004057 1807 #define MASK_VSADDUVX 0xfc00707f 1808 #define MATCH_VSADDUVI 0x80003057 1809 #define MASK_VSADDUVI 0xfc00707f 1810 #define MATCH_VSADDVV 0x84000057 1811 #define MASK_VSADDVV 0xfc00707f 1812 #define MATCH_VSADDVX 0x84004057 1813 #define MASK_VSADDVX 0xfc00707f 1814 #define MATCH_VSADDVI 0x84003057 1815 #define MASK_VSADDVI 0xfc00707f 1816 #define MATCH_VSSUBUVV 0x88000057 1817 #define MASK_VSSUBUVV 0xfc00707f 1818 #define MATCH_VSSUBUVX 0x88004057 1819 #define MASK_VSSUBUVX 0xfc00707f 1820 #define MATCH_VSSUBVV 0x8c000057 1821 #define MASK_VSSUBVV 0xfc00707f 1822 #define MATCH_VSSUBVX 0x8c004057 1823 #define MASK_VSSUBVX 0xfc00707f 1824 #define MATCH_VAADDUVV 0x20002057 1825 #define MASK_VAADDUVV 0xfc00707f 1826 #define MATCH_VAADDUVX 0x20006057 1827 #define MASK_VAADDUVX 0xfc00707f 1828 #define MATCH_VAADDVV 0x24002057 1829 #define MASK_VAADDVV 0xfc00707f 1830 #define MATCH_VAADDVX 0x24006057 1831 #define MASK_VAADDVX 0xfc00707f 1832 #define MATCH_VASUBUVV 0x28002057 1833 #define MASK_VASUBUVV 0xfc00707f 1834 #define MATCH_VASUBUVX 0x28006057 1835 #define MASK_VASUBUVX 0xfc00707f 1836 #define MATCH_VASUBVV 0x2c002057 1837 #define MASK_VASUBVV 0xfc00707f 1838 #define MATCH_VASUBVX 0x2c006057 1839 #define MASK_VASUBVX 0xfc00707f 1840 #define MATCH_VSMULVV 0x9c000057 1841 #define MASK_VSMULVV 0xfc00707f 1842 #define MATCH_VSMULVX 0x9c004057 1843 #define MASK_VSMULVX 0xfc00707f 1844 #define MATCH_VSSRLVV 0xa8000057 1845 #define MASK_VSSRLVV 0xfc00707f 1846 #define MATCH_VSSRLVX 0xa8004057 1847 #define MASK_VSSRLVX 0xfc00707f 1848 #define MATCH_VSSRLVI 0xa8003057 1849 #define MASK_VSSRLVI 0xfc00707f 1850 #define MATCH_VSSRAVV 0xac000057 1851 #define MASK_VSSRAVV 0xfc00707f 1852 #define MATCH_VSSRAVX 0xac004057 1853 #define MASK_VSSRAVX 0xfc00707f 1854 #define MATCH_VSSRAVI 0xac003057 1855 #define MASK_VSSRAVI 0xfc00707f 1856 #define MATCH_VNCLIPUWV 0xb8000057 1857 #define MASK_VNCLIPUWV 0xfc00707f 1858 #define MATCH_VNCLIPUWX 0xb8004057 1859 #define MASK_VNCLIPUWX 0xfc00707f 1860 #define MATCH_VNCLIPUWI 0xb8003057 1861 #define MASK_VNCLIPUWI 0xfc00707f 1862 #define MATCH_VNCLIPWV 0xbc000057 1863 #define MASK_VNCLIPWV 0xfc00707f 1864 #define MATCH_VNCLIPWX 0xbc004057 1865 #define MASK_VNCLIPWX 0xfc00707f 1866 #define MATCH_VNCLIPWI 0xbc003057 1867 #define MASK_VNCLIPWI 0xfc00707f 1868 #define MATCH_VFADDVV 0x00001057 1869 #define MASK_VFADDVV 0xfc00707f 1870 #define MATCH_VFADDVF 0x00005057 1871 #define MASK_VFADDVF 0xfc00707f 1872 #define MATCH_VFSUBVV 0x08001057 1873 #define MASK_VFSUBVV 0xfc00707f 1874 #define MATCH_VFSUBVF 0x08005057 1875 #define MASK_VFSUBVF 0xfc00707f 1876 #define MATCH_VFRSUBVF 0x9c005057 1877 #define MASK_VFRSUBVF 0xfc00707f 1878 #define MATCH_VFWADDVV 0xc0001057 1879 #define MASK_VFWADDVV 0xfc00707f 1880 #define MATCH_VFWADDVF 0xc0005057 1881 #define MASK_VFWADDVF 0xfc00707f 1882 #define MATCH_VFWSUBVV 0xc8001057 1883 #define MASK_VFWSUBVV 0xfc00707f 1884 #define MATCH_VFWSUBVF 0xc8005057 1885 #define MASK_VFWSUBVF 0xfc00707f 1886 #define MATCH_VFWADDWV 0xd0001057 1887 #define MASK_VFWADDWV 0xfc00707f 1888 #define MATCH_VFWADDWF 0xd0005057 1889 #define MASK_VFWADDWF 0xfc00707f 1890 #define MATCH_VFWSUBWV 0xd8001057 1891 #define MASK_VFWSUBWV 0xfc00707f 1892 #define MATCH_VFWSUBWF 0xd8005057 1893 #define MASK_VFWSUBWF 0xfc00707f 1894 #define MATCH_VFMULVV 0x90001057 1895 #define MASK_VFMULVV 0xfc00707f 1896 #define MATCH_VFMULVF 0x90005057 1897 #define MASK_VFMULVF 0xfc00707f 1898 #define MATCH_VFDIVVV 0x80001057 1899 #define MASK_VFDIVVV 0xfc00707f 1900 #define MATCH_VFDIVVF 0x80005057 1901 #define MASK_VFDIVVF 0xfc00707f 1902 #define MATCH_VFRDIVVF 0x84005057 1903 #define MASK_VFRDIVVF 0xfc00707f 1904 #define MATCH_VFWMULVV 0xe0001057 1905 #define MASK_VFWMULVV 0xfc00707f 1906 #define MATCH_VFWMULVF 0xe0005057 1907 #define MASK_VFWMULVF 0xfc00707f 1908 #define MATCH_VFMADDVV 0xa0001057 1909 #define MASK_VFMADDVV 0xfc00707f 1910 #define MATCH_VFMADDVF 0xa0005057 1911 #define MASK_VFMADDVF 0xfc00707f 1912 #define MATCH_VFNMADDVV 0xa4001057 1913 #define MASK_VFNMADDVV 0xfc00707f 1914 #define MATCH_VFNMADDVF 0xa4005057 1915 #define MASK_VFNMADDVF 0xfc00707f 1916 #define MATCH_VFMSUBVV 0xa8001057 1917 #define MASK_VFMSUBVV 0xfc00707f 1918 #define MATCH_VFMSUBVF 0xa8005057 1919 #define MASK_VFMSUBVF 0xfc00707f 1920 #define MATCH_VFNMSUBVV 0xac001057 1921 #define MASK_VFNMSUBVV 0xfc00707f 1922 #define MATCH_VFNMSUBVF 0xac005057 1923 #define MASK_VFNMSUBVF 0xfc00707f 1924 #define MATCH_VFMACCVV 0xb0001057 1925 #define MASK_VFMACCVV 0xfc00707f 1926 #define MATCH_VFMACCVF 0xb0005057 1927 #define MASK_VFMACCVF 0xfc00707f 1928 #define MATCH_VFNMACCVV 0xb4001057 1929 #define MASK_VFNMACCVV 0xfc00707f 1930 #define MATCH_VFNMACCVF 0xb4005057 1931 #define MASK_VFNMACCVF 0xfc00707f 1932 #define MATCH_VFMSACVV 0xb8001057 1933 #define MASK_VFMSACVV 0xfc00707f 1934 #define MATCH_VFMSACVF 0xb8005057 1935 #define MASK_VFMSACVF 0xfc00707f 1936 #define MATCH_VFNMSACVV 0xbc001057 1937 #define MASK_VFNMSACVV 0xfc00707f 1938 #define MATCH_VFNMSACVF 0xbc005057 1939 #define MASK_VFNMSACVF 0xfc00707f 1940 #define MATCH_VFWMACCVV 0xf0001057 1941 #define MASK_VFWMACCVV 0xfc00707f 1942 #define MATCH_VFWMACCVF 0xf0005057 1943 #define MASK_VFWMACCVF 0xfc00707f 1944 #define MATCH_VFWNMACCVV 0xf4001057 1945 #define MASK_VFWNMACCVV 0xfc00707f 1946 #define MATCH_VFWNMACCVF 0xf4005057 1947 #define MASK_VFWNMACCVF 0xfc00707f 1948 #define MATCH_VFWMSACVV 0xf8001057 1949 #define MASK_VFWMSACVV 0xfc00707f 1950 #define MATCH_VFWMSACVF 0xf8005057 1951 #define MASK_VFWMSACVF 0xfc00707f 1952 #define MATCH_VFWNMSACVV 0xfc001057 1953 #define MASK_VFWNMSACVV 0xfc00707f 1954 #define MATCH_VFWNMSACVF 0xfc005057 1955 #define MASK_VFWNMSACVF 0xfc00707f 1956 #define MATCH_VFSQRTV 0x4c001057 1957 #define MASK_VFSQRTV 0xfc0ff07f 1958 #define MATCH_VFRSQRT7V 0x4c021057 1959 #define MASK_VFRSQRT7V 0xfc0ff07f 1960 #define MATCH_VFREC7V 0x4c029057 1961 #define MASK_VFREC7V 0xfc0ff07f 1962 #define MATCH_VFCLASSV 0x4c081057 1963 #define MASK_VFCLASSV 0xfc0ff07f 1964 #define MATCH_VFMINVV 0x10001057 1965 #define MASK_VFMINVV 0xfc00707f 1966 #define MATCH_VFMINVF 0x10005057 1967 #define MASK_VFMINVF 0xfc00707f 1968 #define MATCH_VFMAXVV 0x18001057 1969 #define MASK_VFMAXVV 0xfc00707f 1970 #define MATCH_VFMAXVF 0x18005057 1971 #define MASK_VFMAXVF 0xfc00707f 1972 #define MATCH_VFSGNJVV 0x20001057 1973 #define MASK_VFSGNJVV 0xfc00707f 1974 #define MATCH_VFSGNJVF 0x20005057 1975 #define MASK_VFSGNJVF 0xfc00707f 1976 #define MATCH_VFSGNJNVV 0x24001057 1977 #define MASK_VFSGNJNVV 0xfc00707f 1978 #define MATCH_VFSGNJNVF 0x24005057 1979 #define MASK_VFSGNJNVF 0xfc00707f 1980 #define MATCH_VFSGNJXVV 0x28001057 1981 #define MASK_VFSGNJXVV 0xfc00707f 1982 #define MATCH_VFSGNJXVF 0x28005057 1983 #define MASK_VFSGNJXVF 0xfc00707f 1984 #define MATCH_VMFEQVV 0x60001057 1985 #define MASK_VMFEQVV 0xfc00707f 1986 #define MATCH_VMFEQVF 0x60005057 1987 #define MASK_VMFEQVF 0xfc00707f 1988 #define MATCH_VMFNEVV 0x70001057 1989 #define MASK_VMFNEVV 0xfc00707f 1990 #define MATCH_VMFNEVF 0x70005057 1991 #define MASK_VMFNEVF 0xfc00707f 1992 #define MATCH_VMFLTVV 0x6c001057 1993 #define MASK_VMFLTVV 0xfc00707f 1994 #define MATCH_VMFLTVF 0x6c005057 1995 #define MASK_VMFLTVF 0xfc00707f 1996 #define MATCH_VMFLEVV 0x64001057 1997 #define MASK_VMFLEVV 0xfc00707f 1998 #define MATCH_VMFLEVF 0x64005057 1999 #define MASK_VMFLEVF 0xfc00707f 2000 #define MATCH_VMFGTVF 0x74005057 2001 #define MASK_VMFGTVF 0xfc00707f 2002 #define MATCH_VMFGEVF 0x7c005057 2003 #define MASK_VMFGEVF 0xfc00707f 2004 #define MATCH_VFMERGEVFM 0x5c005057 2005 #define MASK_VFMERGEVFM 0xfe00707f 2006 #define MATCH_VFMVVF 0x5e005057 2007 #define MASK_VFMVVF 0xfff0707f 2008 #define MATCH_VFCVTXUFV 0x48001057 2009 #define MASK_VFCVTXUFV 0xfc0ff07f 2010 #define MATCH_VFCVTXFV 0x48009057 2011 #define MASK_VFCVTXFV 0xfc0ff07f 2012 #define MATCH_VFCVTFXUV 0x48011057 2013 #define MASK_VFCVTFXUV 0xfc0ff07f 2014 #define MATCH_VFCVTFXV 0x48019057 2015 #define MASK_VFCVTFXV 0xfc0ff07f 2016 #define MATCH_VFCVTRTZXUFV 0x48031057 2017 #define MASK_VFCVTRTZXUFV 0xfc0ff07f 2018 #define MATCH_VFCVTRTZXFV 0x48039057 2019 #define MASK_VFCVTRTZXFV 0xfc0ff07f 2020 #define MATCH_VFWCVTXUFV 0x48041057 2021 #define MASK_VFWCVTXUFV 0xfc0ff07f 2022 #define MATCH_VFWCVTXFV 0x48049057 2023 #define MASK_VFWCVTXFV 0xfc0ff07f 2024 #define MATCH_VFWCVTFXUV 0x48051057 2025 #define MASK_VFWCVTFXUV 0xfc0ff07f 2026 #define MATCH_VFWCVTFXV 0x48059057 2027 #define MASK_VFWCVTFXV 0xfc0ff07f 2028 #define MATCH_VFWCVTFFV 0x48061057 2029 #define MASK_VFWCVTFFV 0xfc0ff07f 2030 #define MATCH_VFWCVTRTZXUFV 0x48071057 2031 #define MASK_VFWCVTRTZXUFV 0xfc0ff07f 2032 #define MATCH_VFWCVTRTZXFV 0x48079057 2033 #define MASK_VFWCVTRTZXFV 0xfc0ff07f 2034 #define MATCH_VFNCVTXUFW 0x48081057 2035 #define MASK_VFNCVTXUFW 0xfc0ff07f 2036 #define MATCH_VFNCVTXFW 0x48089057 2037 #define MASK_VFNCVTXFW 0xfc0ff07f 2038 #define MATCH_VFNCVTFXUW 0x48091057 2039 #define MASK_VFNCVTFXUW 0xfc0ff07f 2040 #define MATCH_VFNCVTFXW 0x48099057 2041 #define MASK_VFNCVTFXW 0xfc0ff07f 2042 #define MATCH_VFNCVTFFW 0x480a1057 2043 #define MASK_VFNCVTFFW 0xfc0ff07f 2044 #define MATCH_VFNCVTRODFFW 0x480a9057 2045 #define MASK_VFNCVTRODFFW 0xfc0ff07f 2046 #define MATCH_VFNCVTRTZXUFW 0x480b1057 2047 #define MASK_VFNCVTRTZXUFW 0xfc0ff07f 2048 #define MATCH_VFNCVTRTZXFW 0x480b9057 2049 #define MASK_VFNCVTRTZXFW 0xfc0ff07f 2050 #define MATCH_VREDSUMVS 0x00002057 2051 #define MASK_VREDSUMVS 0xfc00707f 2052 #define MATCH_VREDMAXVS 0x1c002057 2053 #define MASK_VREDMAXVS 0xfc00707f 2054 #define MATCH_VREDMAXUVS 0x18002057 2055 #define MASK_VREDMAXUVS 0xfc00707f 2056 #define MATCH_VREDMINVS 0x14002057 2057 #define MASK_VREDMINVS 0xfc00707f 2058 #define MATCH_VREDMINUVS 0x10002057 2059 #define MASK_VREDMINUVS 0xfc00707f 2060 #define MATCH_VREDANDVS 0x04002057 2061 #define MASK_VREDANDVS 0xfc00707f 2062 #define MATCH_VREDORVS 0x08002057 2063 #define MASK_VREDORVS 0xfc00707f 2064 #define MATCH_VREDXORVS 0x0c002057 2065 #define MASK_VREDXORVS 0xfc00707f 2066 #define MATCH_VWREDSUMUVS 0xc0000057 2067 #define MASK_VWREDSUMUVS 0xfc00707f 2068 #define MATCH_VWREDSUMVS 0xc4000057 2069 #define MASK_VWREDSUMVS 0xfc00707f 2070 #define MATCH_VFREDOSUMVS 0x0c001057 2071 #define MASK_VFREDOSUMVS 0xfc00707f 2072 #define MATCH_VFREDUSUMVS 0x04001057 2073 #define MASK_VFREDUSUMVS 0xfc00707f 2074 #define MATCH_VFREDMAXVS 0x1c001057 2075 #define MASK_VFREDMAXVS 0xfc00707f 2076 #define MATCH_VFREDMINVS 0x14001057 2077 #define MASK_VFREDMINVS 0xfc00707f 2078 #define MATCH_VFWREDOSUMVS 0xcc001057 2079 #define MASK_VFWREDOSUMVS 0xfc00707f 2080 #define MATCH_VFWREDUSUMVS 0xc4001057 2081 #define MASK_VFWREDUSUMVS 0xfc00707f 2082 #define MATCH_VMANDMM 0x66002057 2083 #define MASK_VMANDMM 0xfe00707f 2084 #define MATCH_VMNANDMM 0x76002057 2085 #define MASK_VMNANDMM 0xfe00707f 2086 #define MATCH_VMANDNMM 0x62002057 2087 #define MASK_VMANDNMM 0xfe00707f 2088 #define MATCH_VMXORMM 0x6e002057 2089 #define MASK_VMXORMM 0xfe00707f 2090 #define MATCH_VMORMM 0x6a002057 2091 #define MASK_VMORMM 0xfe00707f 2092 #define MATCH_VMNORMM 0x7a002057 2093 #define MASK_VMNORMM 0xfe00707f 2094 #define MATCH_VMORNMM 0x72002057 2095 #define MASK_VMORNMM 0xfe00707f 2096 #define MATCH_VMXNORMM 0x7e002057 2097 #define MASK_VMXNORMM 0xfe00707f 2098 #define MATCH_VCPOPM 0x40082057 2099 #define MASK_VCPOPM 0xfc0ff07f 2100 #define MATCH_VFIRSTM 0x4008a057 2101 #define MASK_VFIRSTM 0xfc0ff07f 2102 #define MATCH_VMSBFM 0x5000a057 2103 #define MASK_VMSBFM 0xfc0ff07f 2104 #define MATCH_VMSIFM 0x5001a057 2105 #define MASK_VMSIFM 0xfc0ff07f 2106 #define MATCH_VMSOFM 0x50012057 2107 #define MASK_VMSOFM 0xfc0ff07f 2108 #define MATCH_VIOTAM 0x50082057 2109 #define MASK_VIOTAM 0xfc0ff07f 2110 #define MATCH_VIDV 0x5008a057 2111 #define MASK_VIDV 0xfdfff07f 2112 #define MATCH_VMVXS 0x42002057 2113 #define MASK_VMVXS 0xfe0ff07f 2114 #define MATCH_VMVSX 0x42006057 2115 #define MASK_VMVSX 0xfff0707f 2116 #define MATCH_VFMVFS 0x42001057 2117 #define MASK_VFMVFS 0xfe0ff07f 2118 #define MATCH_VFMVSF 0x42005057 2119 #define MASK_VFMVSF 0xfff0707f 2120 #define MATCH_VSLIDEUPVX 0x38004057 2121 #define MASK_VSLIDEUPVX 0xfc00707f 2122 #define MATCH_VSLIDEUPVI 0x38003057 2123 #define MASK_VSLIDEUPVI 0xfc00707f 2124 #define MATCH_VSLIDEDOWNVX 0x3c004057 2125 #define MASK_VSLIDEDOWNVX 0xfc00707f 2126 #define MATCH_VSLIDEDOWNVI 0x3c003057 2127 #define MASK_VSLIDEDOWNVI 0xfc00707f 2128 #define MATCH_VSLIDE1UPVX 0x38006057 2129 #define MASK_VSLIDE1UPVX 0xfc00707f 2130 #define MATCH_VSLIDE1DOWNVX 0x3c006057 2131 #define MASK_VSLIDE1DOWNVX 0xfc00707f 2132 #define MATCH_VFSLIDE1UPVF 0x38005057 2133 #define MASK_VFSLIDE1UPVF 0xfc00707f 2134 #define MATCH_VFSLIDE1DOWNVF 0x3c005057 2135 #define MASK_VFSLIDE1DOWNVF 0xfc00707f 2136 #define MATCH_VRGATHERVV 0x30000057 2137 #define MASK_VRGATHERVV 0xfc00707f 2138 #define MATCH_VRGATHERVX 0x30004057 2139 #define MASK_VRGATHERVX 0xfc00707f 2140 #define MATCH_VRGATHERVI 0x30003057 2141 #define MASK_VRGATHERVI 0xfc00707f 2142 #define MATCH_VRGATHEREI16VV 0x38000057 2143 #define MASK_VRGATHEREI16VV 0xfc00707f 2144 #define MATCH_VCOMPRESSVM 0x5e002057 2145 #define MASK_VCOMPRESSVM 0xfe00707f 2146 #define MATCH_VMV1RV 0x9e003057 2147 #define MASK_VMV1RV 0xfe0ff07f 2148 #define MATCH_VMV2RV 0x9e00b057 2149 #define MASK_VMV2RV 0xfe0ff07f 2150 #define MATCH_VMV4RV 0x9e01b057 2151 #define MASK_VMV4RV 0xfe0ff07f 2152 #define MATCH_VMV8RV 0x9e03b057 2153 #define MASK_VMV8RV 0xfe0ff07f 2154 #define MATCH_VDOTVV 0xe4000057 2155 #define MASK_VDOTVV 0xfc00707f 2156 #define MATCH_VDOTUVV 0xe0000057 2157 #define MASK_VDOTUVV 0xfc00707f 2158 #define MATCH_VFDOTVV 0xe4001057 2159 #define MASK_VFDOTVV 0xfc00707f 2160 /* Zvbb/Zvkb instructions. */ 2161 #define MATCH_VANDN_VV 0x4000057 2162 #define MASK_VANDN_VV 0xfc00707f 2163 #define MATCH_VANDN_VX 0x4004057 2164 #define MASK_VANDN_VX 0xfc00707f 2165 #define MATCH_VBREV8_V 0x48042057 2166 #define MASK_VBREV8_V 0xfc0ff07f 2167 #define MATCH_VBREV_V 0x48052057 2168 #define MASK_VBREV_V 0xfc0ff07f 2169 #define MATCH_VCLZ_V 0x48062057 2170 #define MASK_VCLZ_V 0xfc0ff07f 2171 #define MATCH_VCPOP_V 0x48072057 2172 #define MASK_VCPOP_V 0xfc0ff07f 2173 #define MATCH_VCTZ_V 0x4806a057 2174 #define MASK_VCTZ_V 0xfc0ff07f 2175 #define MATCH_VREV8_V 0x4804a057 2176 #define MASK_VREV8_V 0xfc0ff07f 2177 #define MATCH_VROL_VV 0x54000057 2178 #define MASK_VROL_VV 0xfc00707f 2179 #define MATCH_VROL_VX 0x54004057 2180 #define MASK_VROL_VX 0xfc00707f 2181 #define MATCH_VROR_VI 0x50003057 2182 #define MASK_VROR_VI 0xf800707f 2183 #define MATCH_VROR_VV 0x50000057 2184 #define MASK_VROR_VV 0xfc00707f 2185 #define MATCH_VROR_VX 0x50004057 2186 #define MASK_VROR_VX 0xfc00707f 2187 #define MATCH_VWSLL_VI 0xd4003057 2188 #define MASK_VWSLL_VI 0xfc00707f 2189 #define MATCH_VWSLL_VV 0xd4000057 2190 #define MASK_VWSLL_VV 0xfc00707f 2191 #define MATCH_VWSLL_VX 0xd4004057 2192 #define MASK_VWSLL_VX 0xfc00707f 2193 /* Zvbc instructions. */ 2194 #define MATCH_VCLMUL_VV 0x30002057 2195 #define MASK_VCLMUL_VV 0xfc00707f 2196 #define MATCH_VCLMUL_VX 0x30006057 2197 #define MASK_VCLMUL_VX 0xfc00707f 2198 #define MATCH_VCLMULH_VV 0x34002057 2199 #define MASK_VCLMULH_VV 0xfc00707f 2200 #define MATCH_VCLMULH_VX 0x34006057 2201 #define MASK_VCLMULH_VX 0xfc00707f 2202 /* Zvkg instructions. */ 2203 #define MATCH_VGHSH_VV 0xb2002077 2204 #define MASK_VGHSH_VV 0xfe00707f 2205 #define MATCH_VGMUL_VV 0xa208a077 2206 #define MASK_VGMUL_VV 0xfe0ff07f 2207 /* Zvkned instructions. */ 2208 #define MATCH_VAESDF_VS 0xa600a077 2209 #define MASK_VAESDF_VS 0xfe0ff07f 2210 #define MATCH_VAESDF_VV 0xa200a077 2211 #define MASK_VAESDF_VV 0xfe0ff07f 2212 #define MATCH_VAESDM_VS 0xa6002077 2213 #define MASK_VAESDM_VS 0xfe0ff07f 2214 #define MATCH_VAESDM_VV 0xa2002077 2215 #define MASK_VAESDM_VV 0xfe0ff07f 2216 #define MATCH_VAESEF_VS 0xa601a077 2217 #define MASK_VAESEF_VS 0xfe0ff07f 2218 #define MATCH_VAESEF_VV 0xa201a077 2219 #define MASK_VAESEF_VV 0xfe0ff07f 2220 #define MATCH_VAESEM_VS 0xa6012077 2221 #define MASK_VAESEM_VS 0xfe0ff07f 2222 #define MATCH_VAESEM_VV 0xa2012077 2223 #define MASK_VAESEM_VV 0xfe0ff07f 2224 #define MATCH_VAESKF1_VI 0x8a002077 2225 #define MASK_VAESKF1_VI 0xfe00707f 2226 #define MATCH_VAESKF2_VI 0xaa002077 2227 #define MASK_VAESKF2_VI 0xfe00707f 2228 #define MATCH_VAESZ_VS 0xa603a077 2229 #define MASK_VAESZ_VS 0xfe0ff07f 2230 /* Zvknh[a,b] instructions. */ 2231 #define MATCH_VSHA2CH_VV 0xba002077 2232 #define MASK_VSHA2CH_VV 0xfe00707f 2233 #define MATCH_VSHA2CL_VV 0xbe002077 2234 #define MASK_VSHA2CL_VV 0xfe00707f 2235 #define MATCH_VSHA2MS_VV 0xb6002077 2236 #define MASK_VSHA2MS_VV 0xfe00707f 2237 /* Zvksed instructions. */ 2238 #define MATCH_VSM4K_VI 0x86002077 2239 #define MASK_VSM4K_VI 0xfe00707f 2240 #define MATCH_VSM4R_VS 0xa6082077 2241 #define MASK_VSM4R_VS 0xfe0ff07f 2242 #define MATCH_VSM4R_VV 0xa2082077 2243 #define MASK_VSM4R_VV 0xfe0ff07f 2244 /* Zvksh instructions. */ 2245 #define MATCH_VSM3C_VI 0xae002077 2246 #define MASK_VSM3C_VI 0xfe00707f 2247 #define MATCH_VSM3ME_VV 0x82002077 2248 #define MASK_VSM3ME_VV 0xfe00707f 2249 /* Zcb instructions. */ 2250 #define MATCH_C_LBU 0x8000 2251 #define MASK_C_LBU 0xfc03 2252 #define MATCH_C_LHU 0x8400 2253 #define MASK_C_LHU 0xfc43 2254 #define MATCH_C_LH 0x8440 2255 #define MASK_C_LH 0xfc43 2256 #define MATCH_C_SB 0x8800 2257 #define MASK_C_SB 0xfc03 2258 #define MATCH_C_SH 0x8c00 2259 #define MASK_C_SH 0xfc43 2260 #define MATCH_C_ZEXT_B 0x9c61 2261 #define MASK_C_ZEXT_B 0xfc7f 2262 #define MATCH_C_SEXT_B 0x9c65 2263 #define MASK_C_SEXT_B 0xfc7f 2264 #define MATCH_C_ZEXT_H 0x9c69 2265 #define MASK_C_ZEXT_H 0xfc7f 2266 #define MATCH_C_SEXT_H 0x9c6d 2267 #define MASK_C_SEXT_H 0xfc7f 2268 #define MATCH_C_ZEXT_W 0x9c71 2269 #define MASK_C_ZEXT_W 0xfc7f 2270 #define MATCH_C_NOT 0x9c75 2271 #define MASK_C_NOT 0xfc7f 2272 #define MATCH_C_MUL 0x9c41 2273 #define MASK_C_MUL 0xfc63 2274 /* Zcmp instructions. */ 2275 #define MATCH_CM_PUSH 0xb802 2276 #define MASK_CM_PUSH 0xff03 2277 #define MATCH_CM_POP 0xba02 2278 #define MASK_CM_POP 0xff03 2279 #define MATCH_CM_POPRET 0xbe02 2280 #define MASK_CM_POPRET 0xff03 2281 #define MATCH_CM_POPRETZ 0xbc02 2282 #define MASK_CM_POPRETZ 0xff03 2283 /* Svinval instruction. */ 2284 #define MATCH_SINVAL_VMA 0x16000073 2285 #define MASK_SINVAL_VMA 0xfe007fff 2286 #define MATCH_SFENCE_W_INVAL 0x18000073 2287 #define MASK_SFENCE_W_INVAL 0xffffffff 2288 #define MATCH_SFENCE_INVAL_IR 0x18100073 2289 #define MASK_SFENCE_INVAL_IR 0xffffffff 2290 #define MATCH_HINVAL_VVMA 0x26000073 2291 #define MASK_HINVAL_VVMA 0xfe007fff 2292 #define MATCH_HINVAL_GVMA 0x66000073 2293 #define MASK_HINVAL_GVMA 0xfe007fff 2294 /* Hypervisor instruction. */ 2295 #define MATCH_HFENCE_VVMA 0x22000073 2296 #define MASK_HFENCE_VVMA 0xfe007fff 2297 #define MATCH_HFENCE_GVMA 0x62000073 2298 #define MASK_HFENCE_GVMA 0xfe007fff 2299 #define MATCH_HLV_B 0x60004073 2300 #define MASK_HLV_B 0xfff0707f 2301 #define MATCH_HLV_H 0x64004073 2302 #define MASK_HLV_H 0xfff0707f 2303 #define MATCH_HLV_W 0x68004073 2304 #define MASK_HLV_W 0xfff0707f 2305 #define MATCH_HLV_D 0x6c004073 2306 #define MASK_HLV_D 0xfff0707f 2307 #define MATCH_HLV_BU 0x60104073 2308 #define MASK_HLV_BU 0xfff0707f 2309 #define MATCH_HLV_HU 0x64104073 2310 #define MASK_HLV_HU 0xfff0707f 2311 #define MATCH_HLV_WU 0x68104073 2312 #define MASK_HLV_WU 0xfff0707f 2313 #define MATCH_HLVX_HU 0x64304073 2314 #define MASK_HLVX_HU 0xfff0707f 2315 #define MATCH_HLVX_WU 0x68304073 2316 #define MASK_HLVX_WU 0xfff0707f 2317 #define MATCH_HSV_B 0x62004073 2318 #define MASK_HSV_B 0xfe007fff 2319 #define MATCH_HSV_H 0x66004073 2320 #define MASK_HSV_H 0xfe007fff 2321 #define MATCH_HSV_W 0x6a004073 2322 #define MASK_HSV_W 0xfe007fff 2323 #define MATCH_HSV_D 0x6e004073 2324 #define MASK_HSV_D 0xfe007fff 2325 /* Zicbop hint instructions. */ 2326 #define MATCH_PREFETCH_I 0x6013 2327 #define MASK_PREFETCH_I 0x1f07fff 2328 #define MATCH_PREFETCH_R 0x106013 2329 #define MASK_PREFETCH_R 0x1f07fff 2330 #define MATCH_PREFETCH_W 0x306013 2331 #define MASK_PREFETCH_W 0x1f07fff 2332 /* Zicbom/Zicboz instructions. */ 2333 #define MATCH_CBO_CLEAN 0x10200f 2334 #define MASK_CBO_CLEAN 0xfff07fff 2335 #define MATCH_CBO_FLUSH 0x20200f 2336 #define MASK_CBO_FLUSH 0xfff07fff 2337 #define MATCH_CBO_INVAL 0x200f 2338 #define MASK_CBO_INVAL 0xfff07fff 2339 #define MATCH_CBO_ZERO 0x40200f 2340 #define MASK_CBO_ZERO 0xfff07fff 2341 /* Zicond instructions. */ 2342 #define MATCH_CZERO_EQZ 0xe005033 2343 #define MASK_CZERO_EQZ 0xfe00707f 2344 #define MATCH_CZERO_NEZ 0xe007033 2345 #define MASK_CZERO_NEZ 0xfe00707f 2346 /* Zihintntl hint instructions. */ 2347 #define MATCH_NTL_P1 0x200033 2348 #define MASK_NTL_P1 0xffffffff 2349 #define MATCH_NTL_PALL 0x300033 2350 #define MASK_NTL_PALL 0xffffffff 2351 #define MATCH_NTL_S1 0x400033 2352 #define MASK_NTL_S1 0xffffffff 2353 #define MATCH_NTL_ALL 0x500033 2354 #define MASK_NTL_ALL 0xffffffff 2355 #define MATCH_C_NTL_P1 0x900a 2356 #define MASK_C_NTL_P1 0xffff 2357 #define MATCH_C_NTL_PALL 0x900e 2358 #define MASK_C_NTL_PALL 0xffff 2359 #define MATCH_C_NTL_S1 0x9012 2360 #define MASK_C_NTL_S1 0xffff 2361 #define MATCH_C_NTL_ALL 0x9016 2362 #define MASK_C_NTL_ALL 0xffff 2363 /* Zawrs instructions. */ 2364 #define MATCH_WRS_NTO 0x00d00073 2365 #define MASK_WRS_NTO 0xffffffff 2366 #define MATCH_WRS_STO 0x01d00073 2367 #define MASK_WRS_STO 0xffffffff 2368 /* Vendor-specific (CORE-V) Xcvmac instructions. */ 2369 #define MATCH_CV_MAC 0x9000302b 2370 #define MASK_CV_MAC 0xfe00707f 2371 #define MATCH_CV_MSU 0x9200302b 2372 #define MASK_CV_MSU 0xfe00707f 2373 #define MATCH_CV_MULSN 0x405b 2374 #define MASK_CV_MULSN 0xc000707f 2375 #define MATCH_CV_MULHHSN 0x4000405b 2376 #define MASK_CV_MULHHSN 0xc000707f 2377 #define MATCH_CV_MULSRN 0x8000405b 2378 #define MASK_CV_MULSRN 0xc000707f 2379 #define MATCH_CV_MULHHSRN 0xc000405b 2380 #define MASK_CV_MULHHSRN 0xc000707f 2381 #define MATCH_CV_MULUN 0x505b 2382 #define MASK_CV_MULUN 0xc000707f 2383 #define MATCH_CV_MULHHUN 0x4000505b 2384 #define MASK_CV_MULHHUN 0xc000707f 2385 #define MATCH_CV_MULURN 0x8000505b 2386 #define MASK_CV_MULURN 0xc000707f 2387 #define MATCH_CV_MULHHURN 0xc000505b 2388 #define MASK_CV_MULHHURN 0xc000707f 2389 #define MATCH_CV_MACSN 0x605b 2390 #define MASK_CV_MACSN 0xc000707f 2391 #define MATCH_CV_MACHHSN 0x4000605b 2392 #define MASK_CV_MACHHSN 0xc000707f 2393 #define MATCH_CV_MACSRN 0x8000605b 2394 #define MASK_CV_MACSRN 0xc000707f 2395 #define MATCH_CV_MACHHSRN 0xc000605b 2396 #define MASK_CV_MACHHSRN 0xc000707f 2397 #define MATCH_CV_MACUN 0x705b 2398 #define MASK_CV_MACUN 0xc000707f 2399 #define MATCH_CV_MACHHUN 0x4000705b 2400 #define MASK_CV_MACHHUN 0xc000707f 2401 #define MATCH_CV_MACURN 0x8000705b 2402 #define MASK_CV_MACURN 0xc000707f 2403 #define MATCH_CV_MACHHURN 0xc000705b 2404 #define MASK_CV_MACHHURN 0xc000707f 2405 /* Vendor-specific (CORE-V) Xcvalu instructions. */ 2406 #define MATCH_CV_ABS 0x5000302b 2407 #define MASK_CV_ABS 0xfff0707f 2408 #define MATCH_CV_SLE 0x5200302b 2409 #define MASK_CV_SLE 0xfe00707f 2410 #define MATCH_CV_SLET 0x5200302b 2411 #define MASK_CV_SLET 0xfe00707f 2412 #define MATCH_CV_SLEU 0x5400302b 2413 #define MASK_CV_SLEU 0xfe00707f 2414 #define MATCH_CV_SLETU 0x5400302b 2415 #define MASK_CV_SLETU 0xfe00707f 2416 #define MATCH_CV_MIN 0x5600302b 2417 #define MASK_CV_MIN 0xfe00707f 2418 #define MATCH_CV_MINU 0x5800302b 2419 #define MASK_CV_MINU 0xfe00707f 2420 #define MATCH_CV_MAX 0x5a00302b 2421 #define MASK_CV_MAX 0xfe00707f 2422 #define MATCH_CV_MAXU 0x5c00302b 2423 #define MASK_CV_MAXU 0xfe00707f 2424 #define MATCH_CV_EXTHS 0x6000302b 2425 #define MASK_CV_EXTHS 0xfff0707f 2426 #define MATCH_CV_EXTHZ 0x6200302b 2427 #define MASK_CV_EXTHZ 0xfff0707f 2428 #define MATCH_CV_EXTBS 0x6400302b 2429 #define MASK_CV_EXTBS 0xfff0707f 2430 #define MATCH_CV_EXTBZ 0x6600302b 2431 #define MASK_CV_EXTBZ 0xfff0707f 2432 #define MATCH_CV_CLIP 0x7000302b 2433 #define MASK_CV_CLIP 0xfe00707f 2434 #define MATCH_CV_CLIPU 0x7200302b 2435 #define MASK_CV_CLIPU 0xfe00707f 2436 #define MATCH_CV_CLIPR 0x7400302b 2437 #define MASK_CV_CLIPR 0xfe00707f 2438 #define MATCH_CV_CLIPUR 0x7600302b 2439 #define MASK_CV_CLIPUR 0xfe00707f 2440 #define MATCH_CV_ADDNR 0x8000302b 2441 #define MASK_CV_ADDNR 0xfe00707f 2442 #define MATCH_CV_ADDUNR 0x8200302b 2443 #define MASK_CV_ADDUNR 0xfe00707f 2444 #define MATCH_CV_ADDRNR 0x8400302b 2445 #define MASK_CV_ADDRNR 0xfe00707f 2446 #define MATCH_CV_ADDURNR 0x8600302b 2447 #define MASK_CV_ADDURNR 0xfe00707f 2448 #define MATCH_CV_SUBNR 0x8800302b 2449 #define MASK_CV_SUBNR 0xfe00707f 2450 #define MATCH_CV_SUBUNR 0x8a00302b 2451 #define MASK_CV_SUBUNR 0xfe00707f 2452 #define MATCH_CV_SUBRNR 0x8c00302b 2453 #define MASK_CV_SUBRNR 0xfe00707f 2454 #define MATCH_CV_SUBURNR 0x8e00302b 2455 #define MASK_CV_SUBURNR 0xfe00707f 2456 #define MATCH_CV_ADDN 0x205b 2457 #define MASK_CV_ADDN 0xc000707f 2458 #define MATCH_CV_ADDUN 0x4000205b 2459 #define MASK_CV_ADDUN 0xc000707f 2460 #define MATCH_CV_ADDRN 0x8000205b 2461 #define MASK_CV_ADDRN 0xc000707f 2462 #define MATCH_CV_ADDURN 0xc000205b 2463 #define MASK_CV_ADDURN 0xc000707f 2464 #define MATCH_CV_SUBN 0x305b 2465 #define MASK_CV_SUBN 0xc000707f 2466 #define MATCH_CV_SUBUN 0x4000305b 2467 #define MASK_CV_SUBUN 0xc000707f 2468 #define MATCH_CV_SUBRN 0x8000305b 2469 #define MASK_CV_SUBRN 0xc000707f 2470 #define MATCH_CV_SUBURN 0xc000305b 2471 #define MASK_CV_SUBURN 0xc000707f 2472 /* Vendor-specific (T-Head) XTheadBa instructions. */ 2473 #define MATCH_TH_ADDSL 0x0000100b 2474 #define MASK_TH_ADDSL 0xf800707f 2475 /* Vendor-specific (T-Head) XTheadBb instructions. */ 2476 #define MATCH_TH_SRRI 0x1000100b 2477 #define MASK_TH_SRRI 0xfc00707f 2478 #define MATCH_TH_SRRIW 0x1400100b 2479 #define MASK_TH_SRRIW 0xfe00707f 2480 #define MATCH_TH_EXT 0x0000200b 2481 #define MASK_TH_EXT 0x0000707f 2482 #define MATCH_TH_EXTU 0x0000300b 2483 #define MASK_TH_EXTU 0x0000707f 2484 #define MATCH_TH_FF0 0x8400100b 2485 #define MASK_TH_FF0 0xfff0707f 2486 #define MATCH_TH_FF1 0x8600100b 2487 #define MASK_TH_FF1 0xfff0707f 2488 #define MATCH_TH_REV 0x8200100b 2489 #define MASK_TH_REV 0xfff0707f 2490 #define MATCH_TH_REVW 0x9000100b 2491 #define MASK_TH_REVW 0xfff0707f 2492 #define MATCH_TH_TSTNBZ 0x8000100b 2493 #define MASK_TH_TSTNBZ 0xfff0707f 2494 /* Vendor-specific (T-Head) XTheadBs instructions. */ 2495 #define MATCH_TH_TST 0x8800100b 2496 #define MASK_TH_TST 0xfc00707f 2497 /* Vendor-specific (T-Head) XTheadCmo instructions. */ 2498 #define MATCH_TH_DCACHE_CALL 0x0010000b 2499 #define MASK_TH_DCACHE_CALL 0xffffffff 2500 #define MATCH_TH_DCACHE_CIALL 0x0030000b 2501 #define MASK_TH_DCACHE_CIALL 0xffffffff 2502 #define MATCH_TH_DCACHE_IALL 0x0020000b 2503 #define MASK_TH_DCACHE_IALL 0xffffffff 2504 #define MATCH_TH_DCACHE_CPA 0x0290000b 2505 #define MASK_TH_DCACHE_CPA 0xfff07fff 2506 #define MATCH_TH_DCACHE_CIPA 0x02b0000b 2507 #define MASK_TH_DCACHE_CIPA 0xfff07fff 2508 #define MATCH_TH_DCACHE_IPA 0x02a0000b 2509 #define MASK_TH_DCACHE_IPA 0xfff07fff 2510 #define MATCH_TH_DCACHE_CVA 0x0250000b 2511 #define MASK_TH_DCACHE_CVA 0xfff07fff 2512 #define MATCH_TH_DCACHE_CIVA 0x0270000b 2513 #define MASK_TH_DCACHE_CIVA 0xfff07fff 2514 #define MATCH_TH_DCACHE_IVA 0x0260000b 2515 #define MASK_TH_DCACHE_IVA 0xfff07fff 2516 #define MATCH_TH_DCACHE_CSW 0x0210000b 2517 #define MASK_TH_DCACHE_CSW 0xfff07fff 2518 #define MATCH_TH_DCACHE_CISW 0x0230000b 2519 #define MASK_TH_DCACHE_CISW 0xfff07fff 2520 #define MATCH_TH_DCACHE_ISW 0x0220000b 2521 #define MASK_TH_DCACHE_ISW 0xfff07fff 2522 #define MATCH_TH_DCACHE_CPAL1 0x0280000b 2523 #define MASK_TH_DCACHE_CPAL1 0xfff07fff 2524 #define MATCH_TH_DCACHE_CVAL1 0x0240000b 2525 #define MASK_TH_DCACHE_CVAL1 0xfff07fff 2526 #define MATCH_TH_ICACHE_IALL 0x0100000b 2527 #define MASK_TH_ICACHE_IALL 0xffffffff 2528 #define MATCH_TH_ICACHE_IALLS 0x0110000b 2529 #define MASK_TH_ICACHE_IALLS 0xffffffff 2530 #define MATCH_TH_ICACHE_IPA 0x0380000b 2531 #define MASK_TH_ICACHE_IPA 0xfff07fff 2532 #define MATCH_TH_ICACHE_IVA 0x0300000b 2533 #define MASK_TH_ICACHE_IVA 0xfff07fff 2534 #define MATCH_TH_L2CACHE_CALL 0x0150000b 2535 #define MASK_TH_L2CACHE_CALL 0xffffffff 2536 #define MATCH_TH_L2CACHE_CIALL 0x0170000b 2537 #define MASK_TH_L2CACHE_CIALL 0xffffffff 2538 #define MATCH_TH_L2CACHE_IALL 0x0160000b 2539 #define MASK_TH_L2CACHE_IALL 0xffffffff 2540 /* Vendor-specific (T-Head) XTheadCondMov instructions. */ 2541 #define MATCH_TH_MVEQZ 0x4000100b 2542 #define MASK_TH_MVEQZ 0xfe00707f 2543 #define MATCH_TH_MVNEZ 0x4200100b 2544 #define MASK_TH_MVNEZ 0xfe00707f 2545 /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ 2546 #define MATCH_TH_FLRD 0x6000600b 2547 #define MASK_TH_FLRD 0xf800707f 2548 #define MATCH_TH_FLRW 0x4000600b 2549 #define MASK_TH_FLRW 0xf800707f 2550 #define MATCH_TH_FLURD 0x7000600b 2551 #define MASK_TH_FLURD 0xf800707f 2552 #define MATCH_TH_FLURW 0x5000600b 2553 #define MASK_TH_FLURW 0xf800707f 2554 #define MATCH_TH_FSRD 0x6000700b 2555 #define MASK_TH_FSRD 0xf800707f 2556 #define MATCH_TH_FSRW 0x4000700b 2557 #define MASK_TH_FSRW 0xf800707f 2558 #define MATCH_TH_FSURD 0x7000700b 2559 #define MASK_TH_FSURD 0xf800707f 2560 #define MATCH_TH_FSURW 0x5000700b 2561 #define MASK_TH_FSURW 0xf800707f 2562 /* Vendor-specific (T-Head) XTheadFmv instructions. */ 2563 #define MATCH_TH_FMV_X_HW 0xc000100b 2564 #define MASK_TH_FMV_X_HW 0xfff0707f 2565 #define MATCH_TH_FMV_HW_X 0xa000100b 2566 #define MASK_TH_FMV_HW_X 0xfff0707f 2567 /* Vendor-specific (T-Head) XTheadInt instructions. */ 2568 #define MATCH_TH_IPOP 0x0050000b 2569 #define MASK_TH_IPOP 0xffffffff 2570 #define MATCH_TH_IPUSH 0x0040000b 2571 #define MASK_TH_IPUSH 0xffffffff 2572 /* Vendor-specific (T-Head) XTheadMac instructions. */ 2573 #define MATCH_TH_MULA 0x2000100b 2574 #define MASK_TH_MULA 0xfe00707f 2575 #define MATCH_TH_MULAH 0x2800100b 2576 #define MASK_TH_MULAH 0xfe00707f 2577 #define MATCH_TH_MULAW 0x2400100b 2578 #define MASK_TH_MULAW 0xfe00707f 2579 #define MATCH_TH_MULS 0x2200100b 2580 #define MASK_TH_MULS 0xfe00707f 2581 #define MATCH_TH_MULSH 0x2a00100b 2582 #define MASK_TH_MULSH 0xfe00707f 2583 #define MATCH_TH_MULSW 0x2600100b 2584 #define MASK_TH_MULSW 0xfe00707f 2585 /* Vendor-specific (T-Head) XTheadMemPair instructions. */ 2586 #define MATCH_TH_LDD 0xf800400b 2587 #define MASK_TH_LDD 0xf800707f 2588 #define MATCH_TH_LWD 0xe000400b 2589 #define MASK_TH_LWD 0xf800707f 2590 #define MATCH_TH_LWUD 0xf000400b 2591 #define MASK_TH_LWUD 0xf800707f 2592 #define MATCH_TH_SDD 0xf800500b 2593 #define MASK_TH_SDD 0xf800707f 2594 #define MATCH_TH_SWD 0xe000500b 2595 #define MASK_TH_SWD 0xf800707f 2596 /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ 2597 #define MATCH_TH_LDIA 0x7800400b 2598 #define MASK_TH_LDIA 0xf800707f 2599 #define MATCH_TH_LDIB 0x6800400b 2600 #define MASK_TH_LDIB 0xf800707f 2601 #define MATCH_TH_LWIA 0x5800400b 2602 #define MASK_TH_LWIA 0xf800707f 2603 #define MATCH_TH_LWIB 0x4800400b 2604 #define MASK_TH_LWIB 0xf800707f 2605 #define MATCH_TH_LWUIA 0xd800400b 2606 #define MASK_TH_LWUIA 0xf800707f 2607 #define MATCH_TH_LWUIB 0xc800400b 2608 #define MASK_TH_LWUIB 0xf800707f 2609 #define MATCH_TH_LHIA 0x3800400b 2610 #define MASK_TH_LHIA 0xf800707f 2611 #define MATCH_TH_LHIB 0x2800400b 2612 #define MASK_TH_LHIB 0xf800707f 2613 #define MATCH_TH_LHUIA 0xb800400b 2614 #define MASK_TH_LHUIA 0xf800707f 2615 #define MATCH_TH_LHUIB 0xa800400b 2616 #define MASK_TH_LHUIB 0xf800707f 2617 #define MATCH_TH_LBIA 0x1800400b 2618 #define MASK_TH_LBIA 0xf800707f 2619 #define MATCH_TH_LBIB 0x0800400b 2620 #define MASK_TH_LBIB 0xf800707f 2621 #define MATCH_TH_LBUIA 0x9800400b 2622 #define MASK_TH_LBUIA 0xf800707f 2623 #define MATCH_TH_LBUIB 0x8800400b 2624 #define MASK_TH_LBUIB 0xf800707f 2625 #define MATCH_TH_SDIA 0x7800500b 2626 #define MASK_TH_SDIA 0xf800707f 2627 #define MATCH_TH_SDIB 0x6800500b 2628 #define MASK_TH_SDIB 0xf800707f 2629 #define MATCH_TH_SWIA 0x5800500b 2630 #define MASK_TH_SWIA 0xf800707f 2631 #define MATCH_TH_SWIB 0x4800500b 2632 #define MASK_TH_SWIB 0xf800707f 2633 #define MATCH_TH_SHIA 0x3800500b 2634 #define MASK_TH_SHIA 0xf800707f 2635 #define MATCH_TH_SHIB 0x2800500b 2636 #define MASK_TH_SHIB 0xf800707f 2637 #define MATCH_TH_SBIA 0x1800500b 2638 #define MASK_TH_SBIA 0xf800707f 2639 #define MATCH_TH_SBIB 0x0800500b 2640 #define MASK_TH_SBIB 0xf800707f 2641 #define MATCH_TH_LRD 0x6000400b 2642 #define MASK_TH_LRD 0xf800707f 2643 #define MATCH_TH_LRW 0x4000400b 2644 #define MASK_TH_LRW 0xf800707f 2645 #define MATCH_TH_LRWU 0xc000400b 2646 #define MASK_TH_LRWU 0xf800707f 2647 #define MATCH_TH_LRH 0x2000400b 2648 #define MASK_TH_LRH 0xf800707f 2649 #define MATCH_TH_LRHU 0xa000400b 2650 #define MASK_TH_LRHU 0xf800707f 2651 #define MATCH_TH_LRB 0x0000400b 2652 #define MASK_TH_LRB 0xf800707f 2653 #define MATCH_TH_LRBU 0x8000400b 2654 #define MASK_TH_LRBU 0xf800707f 2655 #define MATCH_TH_SRD 0x6000500b 2656 #define MASK_TH_SRD 0xf800707f 2657 #define MATCH_TH_SRW 0x4000500b 2658 #define MASK_TH_SRW 0xf800707f 2659 #define MATCH_TH_SRH 0x2000500b 2660 #define MASK_TH_SRH 0xf800707f 2661 #define MATCH_TH_SRB 0x0000500b 2662 #define MASK_TH_SRB 0xf800707f 2663 #define MATCH_TH_LURD 0x7000400b 2664 #define MASK_TH_LURD 0xf800707f 2665 #define MATCH_TH_LURW 0x5000400b 2666 #define MASK_TH_LURW 0xf800707f 2667 #define MATCH_TH_LURWU 0xd000400b 2668 #define MASK_TH_LURWU 0xf800707f 2669 #define MATCH_TH_LURH 0x3000400b 2670 #define MASK_TH_LURH 0xf800707f 2671 #define MATCH_TH_LURHU 0xb000400b 2672 #define MASK_TH_LURHU 0xf800707f 2673 #define MATCH_TH_LURB 0x1000400b 2674 #define MASK_TH_LURB 0xf800707f 2675 #define MATCH_TH_LURBU 0x9000400b 2676 #define MASK_TH_LURBU 0xf800707f 2677 #define MATCH_TH_SURD 0x7000500b 2678 #define MASK_TH_SURD 0xf800707f 2679 #define MATCH_TH_SURW 0x5000500b 2680 #define MASK_TH_SURW 0xf800707f 2681 #define MATCH_TH_SURH 0x3000500b 2682 #define MASK_TH_SURH 0xf800707f 2683 #define MATCH_TH_SURB 0x1000500b 2684 #define MASK_TH_SURB 0xf800707f 2685 /* Vendor-specific (T-Head) XTheadSync instructions. */ 2686 #define MATCH_TH_SFENCE_VMAS 0x0400000b 2687 #define MASK_TH_SFENCE_VMAS 0xfe007fff 2688 #define MATCH_TH_SYNC 0x0180000b 2689 #define MASK_TH_SYNC 0xffffffff 2690 #define MATCH_TH_SYNC_I 0x01a0000b 2691 #define MASK_TH_SYNC_I 0xffffffff 2692 #define MATCH_TH_SYNC_IS 0x01b0000b 2693 #define MASK_TH_SYNC_IS 0xffffffff 2694 #define MATCH_TH_SYNC_S 0x0190000b 2695 #define MASK_TH_SYNC_S 0xffffffff 2696 /* Vendor-specific (T-Head) XTheadVector instructions. */ 2697 #define MATCH_TH_VLBV 0x10000007 2698 #define MASK_TH_VLBV 0xfdf0707f 2699 #define MATCH_TH_VLHV 0x10005007 2700 #define MASK_TH_VLHV 0xfdf0707f 2701 #define MATCH_TH_VLWV 0x10006007 2702 #define MASK_TH_VLWV 0xfdf0707f 2703 #define MATCH_TH_VLSBV 0x18000007 2704 #define MASK_TH_VLSBV 0xfc00707f 2705 #define MATCH_TH_VLSHV 0x18005007 2706 #define MASK_TH_VLSHV 0xfc00707f 2707 #define MATCH_TH_VLSWV 0x18006007 2708 #define MASK_TH_VLSWV 0xfc00707f 2709 #define MATCH_TH_VLXBV 0x1c000007 2710 #define MASK_TH_VLXBV 0xfc00707f 2711 #define MATCH_TH_VLXHV 0x1c005007 2712 #define MASK_TH_VLXHV 0xfc00707f 2713 #define MATCH_TH_VLXWV 0x1c006007 2714 #define MASK_TH_VLXWV 0xfc00707f 2715 #define MATCH_TH_VSUXBV 0x1c000027 2716 #define MASK_TH_VSUXBV 0xfc00707f 2717 #define MATCH_TH_VSUXHV 0x1c005027 2718 #define MASK_TH_VSUXHV 0xfc00707f 2719 #define MATCH_TH_VSUXWV 0x1c006027 2720 #define MASK_TH_VSUXWV 0xfc00707f 2721 #define MATCH_TH_VSUXEV 0x1c007027 2722 #define MASK_TH_VSUXEV 0xfc00707f 2723 #define MATCH_TH_VLBFFV 0x11000007 2724 #define MASK_TH_VLBFFV 0xfdf0707f 2725 #define MATCH_TH_VLHFFV 0x11005007 2726 #define MASK_TH_VLHFFV 0xfdf0707f 2727 #define MATCH_TH_VLWFFV 0x11006007 2728 #define MASK_TH_VLWFFV 0xfdf0707f 2729 #define MATCH_TH_VLSEG2BV 0x30000007 2730 #define MASK_TH_VLSEG2BV 0xfdf0707f 2731 #define MATCH_TH_VLSEG2HV 0x30005007 2732 #define MASK_TH_VLSEG2HV 0xfdf0707f 2733 #define MATCH_TH_VLSEG2WV 0x30006007 2734 #define MASK_TH_VLSEG2WV 0xfdf0707f 2735 #define MATCH_TH_VLSEG3BV 0x50000007 2736 #define MASK_TH_VLSEG3BV 0xfdf0707f 2737 #define MATCH_TH_VLSEG3HV 0x50005007 2738 #define MASK_TH_VLSEG3HV 0xfdf0707f 2739 #define MATCH_TH_VLSEG3WV 0x50006007 2740 #define MASK_TH_VLSEG3WV 0xfdf0707f 2741 #define MATCH_TH_VLSEG4BV 0x70000007 2742 #define MASK_TH_VLSEG4BV 0xfdf0707f 2743 #define MATCH_TH_VLSEG4HV 0x70005007 2744 #define MASK_TH_VLSEG4HV 0xfdf0707f 2745 #define MATCH_TH_VLSEG4WV 0x70006007 2746 #define MASK_TH_VLSEG4WV 0xfdf0707f 2747 #define MATCH_TH_VLSEG5BV 0x90000007 2748 #define MASK_TH_VLSEG5BV 0xfdf0707f 2749 #define MATCH_TH_VLSEG5HV 0x90005007 2750 #define MASK_TH_VLSEG5HV 0xfdf0707f 2751 #define MATCH_TH_VLSEG5WV 0x90006007 2752 #define MASK_TH_VLSEG5WV 0xfdf0707f 2753 #define MATCH_TH_VLSEG6BV 0xb0000007 2754 #define MASK_TH_VLSEG6BV 0xfdf0707f 2755 #define MATCH_TH_VLSEG6HV 0xb0005007 2756 #define MASK_TH_VLSEG6HV 0xfdf0707f 2757 #define MATCH_TH_VLSEG6WV 0xb0006007 2758 #define MASK_TH_VLSEG6WV 0xfdf0707f 2759 #define MATCH_TH_VLSEG7BV 0xd0000007 2760 #define MASK_TH_VLSEG7BV 0xfdf0707f 2761 #define MATCH_TH_VLSEG7HV 0xd0005007 2762 #define MASK_TH_VLSEG7HV 0xfdf0707f 2763 #define MATCH_TH_VLSEG7WV 0xd0006007 2764 #define MASK_TH_VLSEG7WV 0xfdf0707f 2765 #define MATCH_TH_VLSEG8BV 0xf0000007 2766 #define MASK_TH_VLSEG8BV 0xfdf0707f 2767 #define MATCH_TH_VLSEG8HV 0xf0005007 2768 #define MASK_TH_VLSEG8HV 0xfdf0707f 2769 #define MATCH_TH_VLSEG8WV 0xf0006007 2770 #define MASK_TH_VLSEG8WV 0xfdf0707f 2771 #define MATCH_TH_VLSSEG2BV 0x38000007 2772 #define MASK_TH_VLSSEG2BV 0xfc00707f 2773 #define MATCH_TH_VLSSEG2HV 0x38005007 2774 #define MASK_TH_VLSSEG2HV 0xfc00707f 2775 #define MATCH_TH_VLSSEG2WV 0x38006007 2776 #define MASK_TH_VLSSEG2WV 0xfc00707f 2777 #define MATCH_TH_VLSSEG3BV 0x58000007 2778 #define MASK_TH_VLSSEG3BV 0xfc00707f 2779 #define MATCH_TH_VLSSEG3HV 0x58005007 2780 #define MASK_TH_VLSSEG3HV 0xfc00707f 2781 #define MATCH_TH_VLSSEG3WV 0x58006007 2782 #define MASK_TH_VLSSEG3WV 0xfc00707f 2783 #define MATCH_TH_VLSSEG4BV 0x78000007 2784 #define MASK_TH_VLSSEG4BV 0xfc00707f 2785 #define MATCH_TH_VLSSEG4HV 0x78005007 2786 #define MASK_TH_VLSSEG4HV 0xfc00707f 2787 #define MATCH_TH_VLSSEG4WV 0x78006007 2788 #define MASK_TH_VLSSEG4WV 0xfc00707f 2789 #define MATCH_TH_VLSSEG5BV 0x98000007 2790 #define MASK_TH_VLSSEG5BV 0xfc00707f 2791 #define MATCH_TH_VLSSEG5HV 0x98005007 2792 #define MASK_TH_VLSSEG5HV 0xfc00707f 2793 #define MATCH_TH_VLSSEG5WV 0x98006007 2794 #define MASK_TH_VLSSEG5WV 0xfc00707f 2795 #define MATCH_TH_VLSSEG6BV 0xb8000007 2796 #define MASK_TH_VLSSEG6BV 0xfc00707f 2797 #define MATCH_TH_VLSSEG6HV 0xb8005007 2798 #define MASK_TH_VLSSEG6HV 0xfc00707f 2799 #define MATCH_TH_VLSSEG6WV 0xb8006007 2800 #define MASK_TH_VLSSEG6WV 0xfc00707f 2801 #define MATCH_TH_VLSSEG7BV 0xd8000007 2802 #define MASK_TH_VLSSEG7BV 0xfc00707f 2803 #define MATCH_TH_VLSSEG7HV 0xd8005007 2804 #define MASK_TH_VLSSEG7HV 0xfc00707f 2805 #define MATCH_TH_VLSSEG7WV 0xd8006007 2806 #define MASK_TH_VLSSEG7WV 0xfc00707f 2807 #define MATCH_TH_VLSSEG8BV 0xf8000007 2808 #define MASK_TH_VLSSEG8BV 0xfc00707f 2809 #define MATCH_TH_VLSSEG8HV 0xf8005007 2810 #define MASK_TH_VLSSEG8HV 0xfc00707f 2811 #define MATCH_TH_VLSSEG8WV 0xf8006007 2812 #define MASK_TH_VLSSEG8WV 0xfc00707f 2813 #define MATCH_TH_VLXSEG2BV 0x3c000007 2814 #define MASK_TH_VLXSEG2BV 0xfc00707f 2815 #define MATCH_TH_VLXSEG2HV 0x3c005007 2816 #define MASK_TH_VLXSEG2HV 0xfc00707f 2817 #define MATCH_TH_VLXSEG2WV 0x3c006007 2818 #define MASK_TH_VLXSEG2WV 0xfc00707f 2819 #define MATCH_TH_VLXSEG3BV 0x5c000007 2820 #define MASK_TH_VLXSEG3BV 0xfc00707f 2821 #define MATCH_TH_VLXSEG3HV 0x5c005007 2822 #define MASK_TH_VLXSEG3HV 0xfc00707f 2823 #define MATCH_TH_VLXSEG3WV 0x5c006007 2824 #define MASK_TH_VLXSEG3WV 0xfc00707f 2825 #define MATCH_TH_VLXSEG4BV 0x7c000007 2826 #define MASK_TH_VLXSEG4BV 0xfc00707f 2827 #define MATCH_TH_VLXSEG4HV 0x7c005007 2828 #define MASK_TH_VLXSEG4HV 0xfc00707f 2829 #define MATCH_TH_VLXSEG4WV 0x7c006007 2830 #define MASK_TH_VLXSEG4WV 0xfc00707f 2831 #define MATCH_TH_VLXSEG5BV 0x9c000007 2832 #define MASK_TH_VLXSEG5BV 0xfc00707f 2833 #define MATCH_TH_VLXSEG5HV 0x9c005007 2834 #define MASK_TH_VLXSEG5HV 0xfc00707f 2835 #define MATCH_TH_VLXSEG5WV 0x9c006007 2836 #define MASK_TH_VLXSEG5WV 0xfc00707f 2837 #define MATCH_TH_VLXSEG6BV 0xbc000007 2838 #define MASK_TH_VLXSEG6BV 0xfc00707f 2839 #define MATCH_TH_VLXSEG6HV 0xbc005007 2840 #define MASK_TH_VLXSEG6HV 0xfc00707f 2841 #define MATCH_TH_VLXSEG6WV 0xbc006007 2842 #define MASK_TH_VLXSEG6WV 0xfc00707f 2843 #define MATCH_TH_VLXSEG7BV 0xdc000007 2844 #define MASK_TH_VLXSEG7BV 0xfc00707f 2845 #define MATCH_TH_VLXSEG7HV 0xdc005007 2846 #define MASK_TH_VLXSEG7HV 0xfc00707f 2847 #define MATCH_TH_VLXSEG7WV 0xdc006007 2848 #define MASK_TH_VLXSEG7WV 0xfc00707f 2849 #define MATCH_TH_VLXSEG8BV 0xfc000007 2850 #define MASK_TH_VLXSEG8BV 0xfc00707f 2851 #define MATCH_TH_VLXSEG8HV 0xfc005007 2852 #define MASK_TH_VLXSEG8HV 0xfc00707f 2853 #define MATCH_TH_VLXSEG8WV 0xfc006007 2854 #define MASK_TH_VLXSEG8WV 0xfc00707f 2855 #define MATCH_TH_VLSEG2BFFV 0x31000007 2856 #define MASK_TH_VLSEG2BFFV 0xfdf0707f 2857 #define MATCH_TH_VLSEG2HFFV 0x31005007 2858 #define MASK_TH_VLSEG2HFFV 0xfdf0707f 2859 #define MATCH_TH_VLSEG2WFFV 0x31006007 2860 #define MASK_TH_VLSEG2WFFV 0xfdf0707f 2861 #define MATCH_TH_VLSEG3BFFV 0x51000007 2862 #define MASK_TH_VLSEG3BFFV 0xfdf0707f 2863 #define MATCH_TH_VLSEG3HFFV 0x51005007 2864 #define MASK_TH_VLSEG3HFFV 0xfdf0707f 2865 #define MATCH_TH_VLSEG3WFFV 0x51006007 2866 #define MASK_TH_VLSEG3WFFV 0xfdf0707f 2867 #define MATCH_TH_VLSEG4BFFV 0x71000007 2868 #define MASK_TH_VLSEG4BFFV 0xfdf0707f 2869 #define MATCH_TH_VLSEG4HFFV 0x71005007 2870 #define MASK_TH_VLSEG4HFFV 0xfdf0707f 2871 #define MATCH_TH_VLSEG4WFFV 0x71006007 2872 #define MASK_TH_VLSEG4WFFV 0xfdf0707f 2873 #define MATCH_TH_VLSEG5BFFV 0x91000007 2874 #define MASK_TH_VLSEG5BFFV 0xfdf0707f 2875 #define MATCH_TH_VLSEG5HFFV 0x91005007 2876 #define MASK_TH_VLSEG5HFFV 0xfdf0707f 2877 #define MATCH_TH_VLSEG5WFFV 0x91006007 2878 #define MASK_TH_VLSEG5WFFV 0xfdf0707f 2879 #define MATCH_TH_VLSEG6BFFV 0xb1000007 2880 #define MASK_TH_VLSEG6BFFV 0xfdf0707f 2881 #define MATCH_TH_VLSEG6HFFV 0xb1005007 2882 #define MASK_TH_VLSEG6HFFV 0xfdf0707f 2883 #define MATCH_TH_VLSEG6WFFV 0xb1006007 2884 #define MASK_TH_VLSEG6WFFV 0xfdf0707f 2885 #define MATCH_TH_VLSEG7BFFV 0xd1000007 2886 #define MASK_TH_VLSEG7BFFV 0xfdf0707f 2887 #define MATCH_TH_VLSEG7HFFV 0xd1005007 2888 #define MASK_TH_VLSEG7HFFV 0xfdf0707f 2889 #define MATCH_TH_VLSEG7WFFV 0xd1006007 2890 #define MASK_TH_VLSEG7WFFV 0xfdf0707f 2891 #define MATCH_TH_VLSEG8BFFV 0xf1000007 2892 #define MASK_TH_VLSEG8BFFV 0xfdf0707f 2893 #define MATCH_TH_VLSEG8HFFV 0xf1005007 2894 #define MASK_TH_VLSEG8HFFV 0xfdf0707f 2895 #define MATCH_TH_VLSEG8WFFV 0xf1006007 2896 #define MASK_TH_VLSEG8WFFV 0xfdf0707f 2897 #define MATCH_TH_VAMOADDWV 0x0000602f 2898 #define MASK_TH_VAMOADDWV 0xf800707f 2899 #define MATCH_TH_VAMOADDDV 0x0000702f 2900 #define MASK_TH_VAMOADDDV 0xf800707f 2901 #define MATCH_TH_VAMOSWAPWV 0x0800602f 2902 #define MASK_TH_VAMOSWAPWV 0xf800707f 2903 #define MATCH_TH_VAMOSWAPDV 0x0800702f 2904 #define MASK_TH_VAMOSWAPDV 0xf800707f 2905 #define MATCH_TH_VAMOXORWV 0x2000602f 2906 #define MASK_TH_VAMOXORWV 0xf800707f 2907 #define MATCH_TH_VAMOXORDV 0x2000702f 2908 #define MASK_TH_VAMOXORDV 0xf800707f 2909 #define MATCH_TH_VAMOANDWV 0x6000602f 2910 #define MASK_TH_VAMOANDWV 0xf800707f 2911 #define MATCH_TH_VAMOANDDV 0x6000702f 2912 #define MASK_TH_VAMOANDDV 0xf800707f 2913 #define MATCH_TH_VAMOORWV 0x4000602f 2914 #define MASK_TH_VAMOORWV 0xf800707f 2915 #define MATCH_TH_VAMOORDV 0x4000702f 2916 #define MASK_TH_VAMOORDV 0xf800707f 2917 #define MATCH_TH_VAMOMINWV 0x8000602f 2918 #define MASK_TH_VAMOMINWV 0xf800707f 2919 #define MATCH_TH_VAMOMINDV 0x8000702f 2920 #define MASK_TH_VAMOMINDV 0xf800707f 2921 #define MATCH_TH_VAMOMAXWV 0xa000602f 2922 #define MASK_TH_VAMOMAXWV 0xf800707f 2923 #define MATCH_TH_VAMOMAXDV 0xa000702f 2924 #define MASK_TH_VAMOMAXDV 0xf800707f 2925 #define MATCH_TH_VAMOMINUWV 0xc000602f 2926 #define MASK_TH_VAMOMINUWV 0xf800707f 2927 #define MATCH_TH_VAMOMINUDV 0xc000702f 2928 #define MASK_TH_VAMOMINUDV 0xf800707f 2929 #define MATCH_TH_VAMOMAXUWV 0xe000602f 2930 #define MASK_TH_VAMOMAXUWV 0xf800707f 2931 #define MATCH_TH_VAMOMAXUDV 0xe000702f 2932 #define MASK_TH_VAMOMAXUDV 0xf800707f 2933 #define MATCH_TH_VADCVVM 0x42000057 2934 #define MASK_TH_VADCVVM 0xfe00707f 2935 #define MATCH_TH_VADCVXM 0x42004057 2936 #define MASK_TH_VADCVXM 0xfe00707f 2937 #define MATCH_TH_VADCVIM 0x42003057 2938 #define MASK_TH_VADCVIM 0xfe00707f 2939 #define MATCH_TH_VSBCVVM 0x4a000057 2940 #define MASK_TH_VSBCVVM 0xfe00707f 2941 #define MATCH_TH_VSBCVXM 0x4a004057 2942 #define MASK_TH_VSBCVXM 0xfe00707f 2943 #define MATCH_TH_VWMACCSUVV 0xf8002057 2944 #define MASK_TH_VWMACCSUVV 0xfc00707f 2945 #define MATCH_TH_VAADDVV 0x90000057 2946 #define MASK_TH_VAADDVV 0xfc00707f 2947 #define MATCH_TH_VAADDVX 0x90004057 2948 #define MASK_TH_VAADDVX 0xfc00707f 2949 #define MATCH_TH_VAADDVI 0x90003057 2950 #define MASK_TH_VAADDVI 0xfc00707f 2951 #define MATCH_TH_VASUBVV 0x98000057 2952 #define MASK_TH_VASUBVV 0xfc00707f 2953 #define MATCH_TH_VASUBVX 0x98004057 2954 #define MASK_TH_VASUBVX 0xfc00707f 2955 #define MATCH_TH_VWSMACCSUVV 0xf8000057 2956 #define MASK_TH_VWSMACCSUVV 0xfc00707f 2957 #define MATCH_TH_VFSQRTV 0x8c001057 2958 #define MASK_TH_VFSQRTV 0xfc0ff07f 2959 #define MATCH_TH_VMFORDVV 0x68001057 2960 #define MASK_TH_VMFORDVV 0xfc00707f 2961 #define MATCH_TH_VMFORDVF 0x68005057 2962 #define MASK_TH_VMFORDVF 0xfc00707f 2963 #define MATCH_TH_VFCLASSV 0x8c081057 2964 #define MASK_TH_VFCLASSV 0xfc0ff07f 2965 #define MATCH_TH_VFCVTXUFV 0x88001057 2966 #define MASK_TH_VFCVTXUFV 0xfc0ff07f 2967 #define MATCH_TH_VFCVTXFV 0x88009057 2968 #define MASK_TH_VFCVTXFV 0xfc0ff07f 2969 #define MATCH_TH_VFCVTFXUV 0x88011057 2970 #define MASK_TH_VFCVTFXUV 0xfc0ff07f 2971 #define MATCH_TH_VFCVTFXV 0x88019057 2972 #define MASK_TH_VFCVTFXV 0xfc0ff07f 2973 #define MATCH_TH_VFWCVTXUFV 0x88041057 2974 #define MASK_TH_VFWCVTXUFV 0xfc0ff07f 2975 #define MATCH_TH_VFWCVTXFV 0x88049057 2976 #define MASK_TH_VFWCVTXFV 0xfc0ff07f 2977 #define MATCH_TH_VFWCVTFXUV 0x88051057 2978 #define MASK_TH_VFWCVTFXUV 0xfc0ff07f 2979 #define MATCH_TH_VFWCVTFXV 0x88059057 2980 #define MASK_TH_VFWCVTFXV 0xfc0ff07f 2981 #define MATCH_TH_VFWCVTFFV 0x88061057 2982 #define MASK_TH_VFWCVTFFV 0xfc0ff07f 2983 #define MATCH_TH_VFNCVTXUFV 0x88081057 2984 #define MASK_TH_VFNCVTXUFV 0xfc0ff07f 2985 #define MATCH_TH_VFNCVTXFV 0x88089057 2986 #define MASK_TH_VFNCVTXFV 0xfc0ff07f 2987 #define MATCH_TH_VFNCVTFXUV 0x88091057 2988 #define MASK_TH_VFNCVTFXUV 0xfc0ff07f 2989 #define MATCH_TH_VFNCVTFXV 0x88099057 2990 #define MASK_TH_VFNCVTFXV 0xfc0ff07f 2991 #define MATCH_TH_VFNCVTFFV 0x880a1057 2992 #define MASK_TH_VFNCVTFFV 0xfc0ff07f 2993 #define MATCH_TH_VMPOPCM 0x50002057 2994 #define MASK_TH_VMPOPCM 0xfc0ff07f 2995 #define MATCH_TH_VMFIRSTM 0x54002057 2996 #define MASK_TH_VMFIRSTM 0xfc0ff07f 2997 #define MATCH_TH_VMSBFM 0x5800a057 2998 #define MASK_TH_VMSBFM 0xfc0ff07f 2999 #define MATCH_TH_VMSIFM 0x5801a057 3000 #define MASK_TH_VMSIFM 0xfc0ff07f 3001 #define MATCH_TH_VMSOFM 0x58012057 3002 #define MASK_TH_VMSOFM 0xfc0ff07f 3003 #define MATCH_TH_VIOTAM 0x58082057 3004 #define MASK_TH_VIOTAM 0xfc0ff07f 3005 #define MATCH_TH_VIDV 0x5808a057 3006 #define MASK_TH_VIDV 0xfdfff07f 3007 #define MATCH_TH_VMVXS 0x32002057 3008 #define MASK_TH_VMVXS 0xfe0ff07f 3009 #define MATCH_TH_VEXTXV 0x32002057 3010 #define MASK_TH_VEXTXV 0xfe00707f 3011 #define MATCH_TH_VMVSX 0x36006057 3012 #define MASK_TH_VMVSX 0xfff0707f 3013 #define MATCH_TH_VFMVFS 0x32001057 3014 #define MASK_TH_VFMVFS 0xfe0ff07f 3015 #define MATCH_TH_VFMVSF 0x36005057 3016 #define MASK_TH_VFMVSF 0xfff0707f 3017 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ 3018 #define MATCH_VT_MASKC 0x607b 3019 #define MASK_VT_MASKC 0xfe00707f 3020 #define MATCH_VT_MASKCN 0x707b 3021 #define MASK_VT_MASKCN 0xfe00707f 3022 /* Vendor-specific (SiFive) vector coprocessor interface instructions. */ 3023 #define MATCH_SF_VC_X 0x0200405b 3024 #define MASK_SF_VC_X 0xf200707f 3025 #define MATCH_SF_VC_V_X 0x0000405b 3026 #define MASK_SF_VC_V_X 0xf200707f 3027 #define MATCH_SF_VC_I 0x0200305b 3028 #define MASK_SF_VC_I 0xf200707f 3029 #define MATCH_SF_VC_V_I 0x0000305b 3030 #define MASK_SF_VC_V_I 0xf200707f 3031 #define MATCH_SF_VC_VV 0x2200005b 3032 #define MASK_SF_VC_VV 0xf200707f 3033 #define MATCH_SF_VC_V_VV 0x2000005b 3034 #define MASK_SF_VC_V_VV 0xf200707f 3035 #define MATCH_SF_VC_XV 0x2200405b 3036 #define MASK_SF_VC_XV 0xf200707f 3037 #define MATCH_SF_VC_V_XV 0x2000405b 3038 #define MASK_SF_VC_V_XV 0xf200707f 3039 #define MATCH_SF_VC_IV 0x2200305b 3040 #define MASK_SF_VC_IV 0xf200707f 3041 #define MATCH_SF_VC_V_IV 0x2000305b 3042 #define MASK_SF_VC_V_IV 0xf200707f 3043 #define MATCH_SF_VC_FV 0x2a00505b 3044 #define MASK_SF_VC_FV 0xfa00707f 3045 #define MATCH_SF_VC_V_FV 0x2800505b 3046 #define MASK_SF_VC_V_FV 0xfa00707f 3047 #define MATCH_SF_VC_VVV 0xa200005b 3048 #define MASK_SF_VC_VVV 0xf200707f 3049 #define MATCH_SF_VC_V_VVV 0xa000005b 3050 #define MASK_SF_VC_V_VVV 0xf200707f 3051 #define MATCH_SF_VC_XVV 0xa200405b 3052 #define MASK_SF_VC_XVV 0xf200707f 3053 #define MATCH_SF_VC_V_XVV 0xa000405b 3054 #define MASK_SF_VC_V_XVV 0xf200707f 3055 #define MATCH_SF_VC_IVV 0xa200305b 3056 #define MASK_SF_VC_IVV 0xf200707f 3057 #define MATCH_SF_VC_V_IVV 0xa000305b 3058 #define MASK_SF_VC_V_IVV 0xf200707f 3059 #define MATCH_SF_VC_FVV 0xaa00505b 3060 #define MASK_SF_VC_FVV 0xfa00707f 3061 #define MATCH_SF_VC_V_FVV 0xa800505b 3062 #define MASK_SF_VC_V_FVV 0xfa00707f 3063 #define MATCH_SF_VC_VVW 0xf200005b 3064 #define MASK_SF_VC_VVW 0xf200707f 3065 #define MATCH_SF_VC_V_VVW 0xf000005b 3066 #define MASK_SF_VC_V_VVW 0xf200707f 3067 #define MATCH_SF_VC_XVW 0xf200405b 3068 #define MASK_SF_VC_XVW 0xf200707f 3069 #define MATCH_SF_VC_V_XVW 0xf000405b 3070 #define MASK_SF_VC_V_XVW 0xf200707f 3071 #define MATCH_SF_VC_IVW 0xf200305b 3072 #define MASK_SF_VC_IVW 0xf200707f 3073 #define MATCH_SF_VC_V_IVW 0xf000305b 3074 #define MASK_SF_VC_V_IVW 0xf200707f 3075 #define MATCH_SF_VC_FVW 0xfa00505b 3076 #define MASK_SF_VC_FVW 0xfa00707f 3077 #define MATCH_SF_VC_V_FVW 0xf800505b 3078 #define MASK_SF_VC_V_FVW 0xfa00707f 3079 /* Unprivileged Counter/Timers CSR addresses. */ 3080 #define CSR_CYCLE 0xc00 3081 #define CSR_TIME 0xc01 3082 #define CSR_INSTRET 0xc02 3083 #define CSR_HPMCOUNTER3 0xc03 3084 #define CSR_HPMCOUNTER4 0xc04 3085 #define CSR_HPMCOUNTER5 0xc05 3086 #define CSR_HPMCOUNTER6 0xc06 3087 #define CSR_HPMCOUNTER7 0xc07 3088 #define CSR_HPMCOUNTER8 0xc08 3089 #define CSR_HPMCOUNTER9 0xc09 3090 #define CSR_HPMCOUNTER10 0xc0a 3091 #define CSR_HPMCOUNTER11 0xc0b 3092 #define CSR_HPMCOUNTER12 0xc0c 3093 #define CSR_HPMCOUNTER13 0xc0d 3094 #define CSR_HPMCOUNTER14 0xc0e 3095 #define CSR_HPMCOUNTER15 0xc0f 3096 #define CSR_HPMCOUNTER16 0xc10 3097 #define CSR_HPMCOUNTER17 0xc11 3098 #define CSR_HPMCOUNTER18 0xc12 3099 #define CSR_HPMCOUNTER19 0xc13 3100 #define CSR_HPMCOUNTER20 0xc14 3101 #define CSR_HPMCOUNTER21 0xc15 3102 #define CSR_HPMCOUNTER22 0xc16 3103 #define CSR_HPMCOUNTER23 0xc17 3104 #define CSR_HPMCOUNTER24 0xc18 3105 #define CSR_HPMCOUNTER25 0xc19 3106 #define CSR_HPMCOUNTER26 0xc1a 3107 #define CSR_HPMCOUNTER27 0xc1b 3108 #define CSR_HPMCOUNTER28 0xc1c 3109 #define CSR_HPMCOUNTER29 0xc1d 3110 #define CSR_HPMCOUNTER30 0xc1e 3111 #define CSR_HPMCOUNTER31 0xc1f 3112 #define CSR_CYCLEH 0xc80 3113 #define CSR_TIMEH 0xc81 3114 #define CSR_INSTRETH 0xc82 3115 #define CSR_HPMCOUNTER3H 0xc83 3116 #define CSR_HPMCOUNTER4H 0xc84 3117 #define CSR_HPMCOUNTER5H 0xc85 3118 #define CSR_HPMCOUNTER6H 0xc86 3119 #define CSR_HPMCOUNTER7H 0xc87 3120 #define CSR_HPMCOUNTER8H 0xc88 3121 #define CSR_HPMCOUNTER9H 0xc89 3122 #define CSR_HPMCOUNTER10H 0xc8a 3123 #define CSR_HPMCOUNTER11H 0xc8b 3124 #define CSR_HPMCOUNTER12H 0xc8c 3125 #define CSR_HPMCOUNTER13H 0xc8d 3126 #define CSR_HPMCOUNTER14H 0xc8e 3127 #define CSR_HPMCOUNTER15H 0xc8f 3128 #define CSR_HPMCOUNTER16H 0xc90 3129 #define CSR_HPMCOUNTER17H 0xc91 3130 #define CSR_HPMCOUNTER18H 0xc92 3131 #define CSR_HPMCOUNTER19H 0xc93 3132 #define CSR_HPMCOUNTER20H 0xc94 3133 #define CSR_HPMCOUNTER21H 0xc95 3134 #define CSR_HPMCOUNTER22H 0xc96 3135 #define CSR_HPMCOUNTER23H 0xc97 3136 #define CSR_HPMCOUNTER24H 0xc98 3137 #define CSR_HPMCOUNTER25H 0xc99 3138 #define CSR_HPMCOUNTER26H 0xc9a 3139 #define CSR_HPMCOUNTER27H 0xc9b 3140 #define CSR_HPMCOUNTER28H 0xc9c 3141 #define CSR_HPMCOUNTER29H 0xc9d 3142 #define CSR_HPMCOUNTER30H 0xc9e 3143 #define CSR_HPMCOUNTER31H 0xc9f 3144 /* Privileged Supervisor CSR addresses. */ 3145 #define CSR_SSTATUS 0x100 3146 #define CSR_SIE 0x104 3147 #define CSR_STVEC 0x105 3148 #define CSR_SCOUNTEREN 0x106 3149 #define CSR_SENVCFG 0x10a 3150 #define CSR_SSCRATCH 0x140 3151 #define CSR_SEPC 0x141 3152 #define CSR_SCAUSE 0x142 3153 #define CSR_STVAL 0x143 3154 #define CSR_SIP 0x144 3155 #define CSR_SATP 0x180 3156 /* Privileged Machine CSR addresses. */ 3157 #define CSR_MVENDORID 0xf11 3158 #define CSR_MARCHID 0xf12 3159 #define CSR_MIMPID 0xf13 3160 #define CSR_MHARTID 0xf14 3161 #define CSR_MCONFIGPTR 0xf15 3162 #define CSR_MSTATUS 0x300 3163 #define CSR_MISA 0x301 3164 #define CSR_MEDELEG 0x302 3165 #define CSR_MIDELEG 0x303 3166 #define CSR_MIE 0x304 3167 #define CSR_MTVEC 0x305 3168 #define CSR_MCOUNTEREN 0x306 3169 #define CSR_MSTATUSH 0x310 3170 #define CSR_MSCRATCH 0x340 3171 #define CSR_MEPC 0x341 3172 #define CSR_MCAUSE 0x342 3173 #define CSR_MTVAL 0x343 3174 #define CSR_MIP 0x344 3175 #define CSR_MTINST 0x34a 3176 #define CSR_MTVAL2 0x34b 3177 #define CSR_MENVCFG 0x30a 3178 #define CSR_MENVCFGH 0x31a 3179 #define CSR_MSECCFG 0x747 3180 #define CSR_MSECCFGH 0x757 3181 #define CSR_PMPCFG0 0x3a0 3182 #define CSR_PMPCFG1 0x3a1 3183 #define CSR_PMPCFG2 0x3a2 3184 #define CSR_PMPCFG3 0x3a3 3185 #define CSR_PMPCFG4 0x3a4 3186 #define CSR_PMPCFG5 0x3a5 3187 #define CSR_PMPCFG6 0x3a6 3188 #define CSR_PMPCFG7 0x3a7 3189 #define CSR_PMPCFG8 0x3a8 3190 #define CSR_PMPCFG9 0x3a9 3191 #define CSR_PMPCFG10 0x3aa 3192 #define CSR_PMPCFG11 0x3ab 3193 #define CSR_PMPCFG12 0x3ac 3194 #define CSR_PMPCFG13 0x3ad 3195 #define CSR_PMPCFG14 0x3ae 3196 #define CSR_PMPCFG15 0x3af 3197 #define CSR_PMPADDR0 0x3b0 3198 #define CSR_PMPADDR1 0x3b1 3199 #define CSR_PMPADDR2 0x3b2 3200 #define CSR_PMPADDR3 0x3b3 3201 #define CSR_PMPADDR4 0x3b4 3202 #define CSR_PMPADDR5 0x3b5 3203 #define CSR_PMPADDR6 0x3b6 3204 #define CSR_PMPADDR7 0x3b7 3205 #define CSR_PMPADDR8 0x3b8 3206 #define CSR_PMPADDR9 0x3b9 3207 #define CSR_PMPADDR10 0x3ba 3208 #define CSR_PMPADDR11 0x3bb 3209 #define CSR_PMPADDR12 0x3bc 3210 #define CSR_PMPADDR13 0x3bd 3211 #define CSR_PMPADDR14 0x3be 3212 #define CSR_PMPADDR15 0x3bf 3213 #define CSR_PMPADDR16 0x3c0 3214 #define CSR_PMPADDR17 0x3c1 3215 #define CSR_PMPADDR18 0x3c2 3216 #define CSR_PMPADDR19 0x3c3 3217 #define CSR_PMPADDR20 0x3c4 3218 #define CSR_PMPADDR21 0x3c5 3219 #define CSR_PMPADDR22 0x3c6 3220 #define CSR_PMPADDR23 0x3c7 3221 #define CSR_PMPADDR24 0x3c8 3222 #define CSR_PMPADDR25 0x3c9 3223 #define CSR_PMPADDR26 0x3ca 3224 #define CSR_PMPADDR27 0x3cb 3225 #define CSR_PMPADDR28 0x3cc 3226 #define CSR_PMPADDR29 0x3cd 3227 #define CSR_PMPADDR30 0x3ce 3228 #define CSR_PMPADDR31 0x3cf 3229 #define CSR_PMPADDR32 0x3d0 3230 #define CSR_PMPADDR33 0x3d1 3231 #define CSR_PMPADDR34 0x3d2 3232 #define CSR_PMPADDR35 0x3d3 3233 #define CSR_PMPADDR36 0x3d4 3234 #define CSR_PMPADDR37 0x3d5 3235 #define CSR_PMPADDR38 0x3d6 3236 #define CSR_PMPADDR39 0x3d7 3237 #define CSR_PMPADDR40 0x3d8 3238 #define CSR_PMPADDR41 0x3d9 3239 #define CSR_PMPADDR42 0x3da 3240 #define CSR_PMPADDR43 0x3db 3241 #define CSR_PMPADDR44 0x3dc 3242 #define CSR_PMPADDR45 0x3dd 3243 #define CSR_PMPADDR46 0x3de 3244 #define CSR_PMPADDR47 0x3df 3245 #define CSR_PMPADDR48 0x3e0 3246 #define CSR_PMPADDR49 0x3e1 3247 #define CSR_PMPADDR50 0x3e2 3248 #define CSR_PMPADDR51 0x3e3 3249 #define CSR_PMPADDR52 0x3e4 3250 #define CSR_PMPADDR53 0x3e5 3251 #define CSR_PMPADDR54 0x3e6 3252 #define CSR_PMPADDR55 0x3e7 3253 #define CSR_PMPADDR56 0x3e8 3254 #define CSR_PMPADDR57 0x3e9 3255 #define CSR_PMPADDR58 0x3ea 3256 #define CSR_PMPADDR59 0x3eb 3257 #define CSR_PMPADDR60 0x3ec 3258 #define CSR_PMPADDR61 0x3ed 3259 #define CSR_PMPADDR62 0x3ee 3260 #define CSR_PMPADDR63 0x3ef 3261 #define CSR_MCYCLE 0xb00 3262 #define CSR_MINSTRET 0xb02 3263 #define CSR_MHPMCOUNTER3 0xb03 3264 #define CSR_MHPMCOUNTER4 0xb04 3265 #define CSR_MHPMCOUNTER5 0xb05 3266 #define CSR_MHPMCOUNTER6 0xb06 3267 #define CSR_MHPMCOUNTER7 0xb07 3268 #define CSR_MHPMCOUNTER8 0xb08 3269 #define CSR_MHPMCOUNTER9 0xb09 3270 #define CSR_MHPMCOUNTER10 0xb0a 3271 #define CSR_MHPMCOUNTER11 0xb0b 3272 #define CSR_MHPMCOUNTER12 0xb0c 3273 #define CSR_MHPMCOUNTER13 0xb0d 3274 #define CSR_MHPMCOUNTER14 0xb0e 3275 #define CSR_MHPMCOUNTER15 0xb0f 3276 #define CSR_MHPMCOUNTER16 0xb10 3277 #define CSR_MHPMCOUNTER17 0xb11 3278 #define CSR_MHPMCOUNTER18 0xb12 3279 #define CSR_MHPMCOUNTER19 0xb13 3280 #define CSR_MHPMCOUNTER20 0xb14 3281 #define CSR_MHPMCOUNTER21 0xb15 3282 #define CSR_MHPMCOUNTER22 0xb16 3283 #define CSR_MHPMCOUNTER23 0xb17 3284 #define CSR_MHPMCOUNTER24 0xb18 3285 #define CSR_MHPMCOUNTER25 0xb19 3286 #define CSR_MHPMCOUNTER26 0xb1a 3287 #define CSR_MHPMCOUNTER27 0xb1b 3288 #define CSR_MHPMCOUNTER28 0xb1c 3289 #define CSR_MHPMCOUNTER29 0xb1d 3290 #define CSR_MHPMCOUNTER30 0xb1e 3291 #define CSR_MHPMCOUNTER31 0xb1f 3292 #define CSR_MCYCLEH 0xb80 3293 #define CSR_MINSTRETH 0xb82 3294 #define CSR_MHPMCOUNTER3H 0xb83 3295 #define CSR_MHPMCOUNTER4H 0xb84 3296 #define CSR_MHPMCOUNTER5H 0xb85 3297 #define CSR_MHPMCOUNTER6H 0xb86 3298 #define CSR_MHPMCOUNTER7H 0xb87 3299 #define CSR_MHPMCOUNTER8H 0xb88 3300 #define CSR_MHPMCOUNTER9H 0xb89 3301 #define CSR_MHPMCOUNTER10H 0xb8a 3302 #define CSR_MHPMCOUNTER11H 0xb8b 3303 #define CSR_MHPMCOUNTER12H 0xb8c 3304 #define CSR_MHPMCOUNTER13H 0xb8d 3305 #define CSR_MHPMCOUNTER14H 0xb8e 3306 #define CSR_MHPMCOUNTER15H 0xb8f 3307 #define CSR_MHPMCOUNTER16H 0xb90 3308 #define CSR_MHPMCOUNTER17H 0xb91 3309 #define CSR_MHPMCOUNTER18H 0xb92 3310 #define CSR_MHPMCOUNTER19H 0xb93 3311 #define CSR_MHPMCOUNTER20H 0xb94 3312 #define CSR_MHPMCOUNTER21H 0xb95 3313 #define CSR_MHPMCOUNTER22H 0xb96 3314 #define CSR_MHPMCOUNTER23H 0xb97 3315 #define CSR_MHPMCOUNTER24H 0xb98 3316 #define CSR_MHPMCOUNTER25H 0xb99 3317 #define CSR_MHPMCOUNTER26H 0xb9a 3318 #define CSR_MHPMCOUNTER27H 0xb9b 3319 #define CSR_MHPMCOUNTER28H 0xb9c 3320 #define CSR_MHPMCOUNTER29H 0xb9d 3321 #define CSR_MHPMCOUNTER30H 0xb9e 3322 #define CSR_MHPMCOUNTER31H 0xb9f 3323 #define CSR_MCOUNTINHIBIT 0x320 3324 #define CSR_MHPMEVENT3 0x323 3325 #define CSR_MHPMEVENT4 0x324 3326 #define CSR_MHPMEVENT5 0x325 3327 #define CSR_MHPMEVENT6 0x326 3328 #define CSR_MHPMEVENT7 0x327 3329 #define CSR_MHPMEVENT8 0x328 3330 #define CSR_MHPMEVENT9 0x329 3331 #define CSR_MHPMEVENT10 0x32a 3332 #define CSR_MHPMEVENT11 0x32b 3333 #define CSR_MHPMEVENT12 0x32c 3334 #define CSR_MHPMEVENT13 0x32d 3335 #define CSR_MHPMEVENT14 0x32e 3336 #define CSR_MHPMEVENT15 0x32f 3337 #define CSR_MHPMEVENT16 0x330 3338 #define CSR_MHPMEVENT17 0x331 3339 #define CSR_MHPMEVENT18 0x332 3340 #define CSR_MHPMEVENT19 0x333 3341 #define CSR_MHPMEVENT20 0x334 3342 #define CSR_MHPMEVENT21 0x335 3343 #define CSR_MHPMEVENT22 0x336 3344 #define CSR_MHPMEVENT23 0x337 3345 #define CSR_MHPMEVENT24 0x338 3346 #define CSR_MHPMEVENT25 0x339 3347 #define CSR_MHPMEVENT26 0x33a 3348 #define CSR_MHPMEVENT27 0x33b 3349 #define CSR_MHPMEVENT28 0x33c 3350 #define CSR_MHPMEVENT29 0x33d 3351 #define CSR_MHPMEVENT30 0x33e 3352 #define CSR_MHPMEVENT31 0x33f 3353 /* Privileged Hypervisor CSR addresses. */ 3354 #define CSR_HSTATUS 0x600 3355 #define CSR_HEDELEG 0x602 3356 #define CSR_HIDELEG 0x603 3357 #define CSR_HIE 0x604 3358 #define CSR_HCOUNTEREN 0x606 3359 #define CSR_HGEIE 0x607 3360 #define CSR_HTVAL 0x643 3361 #define CSR_HIP 0x644 3362 #define CSR_HVIP 0x645 3363 #define CSR_HTINST 0x64a 3364 #define CSR_HGEIP 0xe12 3365 #define CSR_HENVCFG 0x60a 3366 #define CSR_HENVCFGH 0x61a 3367 #define CSR_HGATP 0x680 3368 #define CSR_HTIMEDELTA 0x605 3369 #define CSR_HTIMEDELTAH 0x615 3370 #define CSR_VSSTATUS 0x200 3371 #define CSR_VSIE 0x204 3372 #define CSR_VSTVEC 0x205 3373 #define CSR_VSSCRATCH 0x240 3374 #define CSR_VSEPC 0x241 3375 #define CSR_VSCAUSE 0x242 3376 #define CSR_VSTVAL 0x243 3377 #define CSR_VSIP 0x244 3378 #define CSR_VSATP 0x280 3379 /* Droppped CSR addresses. */ 3380 #define CSR_USTATUS 0x0 3381 #define CSR_UIE 0x4 3382 #define CSR_UTVEC 0x5 3383 #define CSR_USCRATCH 0x40 3384 #define CSR_UEPC 0x41 3385 #define CSR_UCAUSE 0x42 3386 #define CSR_UTVAL 0x43 3387 #define CSR_UIP 0x44 3388 #define CSR_SEDELEG 0x102 3389 #define CSR_SIDELEG 0x103 3390 /* Smaia extension */ 3391 #define CSR_MISELECT 0x350 3392 #define CSR_MIREG 0x351 3393 #define CSR_MTOPEI 0x35c 3394 #define CSR_MTOPI 0xfb0 3395 #define CSR_MVIEN 0x308 3396 #define CSR_MVIP 0x309 3397 #define CSR_MIDELEGH 0x313 3398 #define CSR_MIEH 0x314 3399 #define CSR_MVIENH 0x318 3400 #define CSR_MVIPH 0x319 3401 #define CSR_MIPH 0x354 3402 /* Smcntrpmf extension. */ 3403 #define CSR_MCYCLECFG 0x321 3404 #define CSR_MINSTRETCFG 0x322 3405 #define CSR_MCYCLECFGH 0x721 3406 #define CSR_MINSTRETCFGH 0x722 3407 /* Smstateen extension */ 3408 #define CSR_MSTATEEN0 0x30c 3409 #define CSR_MSTATEEN1 0x30d 3410 #define CSR_MSTATEEN2 0x30e 3411 #define CSR_MSTATEEN3 0x30f 3412 #define CSR_SSTATEEN0 0x10c 3413 #define CSR_SSTATEEN1 0x10d 3414 #define CSR_SSTATEEN2 0x10e 3415 #define CSR_SSTATEEN3 0x10f 3416 #define CSR_HSTATEEN0 0x60c 3417 #define CSR_HSTATEEN1 0x60d 3418 #define CSR_HSTATEEN2 0x60e 3419 #define CSR_HSTATEEN3 0x60f 3420 #define CSR_MSTATEEN0H 0x31c 3421 #define CSR_MSTATEEN1H 0x31d 3422 #define CSR_MSTATEEN2H 0x31e 3423 #define CSR_MSTATEEN3H 0x31f 3424 #define CSR_HSTATEEN0H 0x61c 3425 #define CSR_HSTATEEN1H 0x61d 3426 #define CSR_HSTATEEN2H 0x61e 3427 #define CSR_HSTATEEN3H 0x61f 3428 /* Ssaia extension */ 3429 #define CSR_SISELECT 0x150 3430 #define CSR_SIREG 0x151 3431 #define CSR_STOPEI 0x15c 3432 #define CSR_STOPI 0xdb0 3433 #define CSR_SIEH 0x114 3434 #define CSR_SIPH 0x154 3435 #define CSR_HVIEN 0x608 3436 #define CSR_HVICTL 0x609 3437 #define CSR_HVIPRIO1 0x646 3438 #define CSR_HVIPRIO2 0x647 3439 #define CSR_VSISELECT 0x250 3440 #define CSR_VSIREG 0x251 3441 #define CSR_VSTOPEI 0x25c 3442 #define CSR_VSTOPI 0xeb0 3443 #define CSR_HIDELEGH 0x613 3444 #define CSR_HVIENH 0x618 3445 #define CSR_HVIPH 0x655 3446 #define CSR_HVIPRIO1H 0x656 3447 #define CSR_HVIPRIO2H 0x657 3448 #define CSR_VSIEH 0x214 3449 #define CSR_VSIPH 0x254 3450 /* Sscofpmf extension */ 3451 #define CSR_SCOUNTOVF 0xda0 3452 #define CSR_MHPMEVENT3H 0x723 3453 #define CSR_MHPMEVENT4H 0x724 3454 #define CSR_MHPMEVENT5H 0x725 3455 #define CSR_MHPMEVENT6H 0x726 3456 #define CSR_MHPMEVENT7H 0x727 3457 #define CSR_MHPMEVENT8H 0x728 3458 #define CSR_MHPMEVENT9H 0x729 3459 #define CSR_MHPMEVENT10H 0x72a 3460 #define CSR_MHPMEVENT11H 0x72b 3461 #define CSR_MHPMEVENT12H 0x72c 3462 #define CSR_MHPMEVENT13H 0x72d 3463 #define CSR_MHPMEVENT14H 0x72e 3464 #define CSR_MHPMEVENT15H 0x72f 3465 #define CSR_MHPMEVENT16H 0x730 3466 #define CSR_MHPMEVENT17H 0x731 3467 #define CSR_MHPMEVENT18H 0x732 3468 #define CSR_MHPMEVENT19H 0x733 3469 #define CSR_MHPMEVENT20H 0x734 3470 #define CSR_MHPMEVENT21H 0x735 3471 #define CSR_MHPMEVENT22H 0x736 3472 #define CSR_MHPMEVENT23H 0x737 3473 #define CSR_MHPMEVENT24H 0x738 3474 #define CSR_MHPMEVENT25H 0x739 3475 #define CSR_MHPMEVENT26H 0x73a 3476 #define CSR_MHPMEVENT27H 0x73b 3477 #define CSR_MHPMEVENT28H 0x73c 3478 #define CSR_MHPMEVENT29H 0x73d 3479 #define CSR_MHPMEVENT30H 0x73e 3480 #define CSR_MHPMEVENT31H 0x73f 3481 /* Sstc extension */ 3482 #define CSR_STIMECMP 0x14d 3483 #define CSR_STIMECMPH 0x15d 3484 #define CSR_VSTIMECMP 0x24d 3485 #define CSR_VSTIMECMPH 0x25d 3486 /* Unprivileged Floating-Point CSR addresses. */ 3487 #define CSR_FFLAGS 0x1 3488 #define CSR_FRM 0x2 3489 #define CSR_FCSR 0x3 3490 /* Unprivileged Debug CSR addresses. */ 3491 #define CSR_DCSR 0x7b0 3492 #define CSR_DPC 0x7b1 3493 #define CSR_DSCRATCH0 0x7b2 3494 #define CSR_DSCRATCH1 0x7b3 3495 #define CSR_TSELECT 0x7a0 3496 #define CSR_TDATA1 0x7a1 3497 #define CSR_TDATA2 0x7a2 3498 #define CSR_TDATA3 0x7a3 3499 #define CSR_TINFO 0x7a4 3500 #define CSR_TCONTROL 0x7a5 3501 #define CSR_HCONTEXT 0x6a8 3502 #define CSR_SCONTEXT 0x5a8 3503 #define CSR_MCONTEXT 0x7a8 3504 #define CSR_MSCONTEXT 0x7aa 3505 /* Unprivileged Scalar Crypto CSR addresses. */ 3506 #define CSR_SEED 0x015 3507 /* Unprivileged Vector CSR addresses. */ 3508 #define CSR_VSTART 0x008 3509 #define CSR_VXSAT 0x009 3510 #define CSR_VXRM 0x00a 3511 #define CSR_VCSR 0x00f 3512 #define CSR_VL 0xc20 3513 #define CSR_VTYPE 0xc21 3514 #define CSR_VLENB 0xc22 3515 #endif /* RISCV_ENCODING_H */ 3516 #ifdef DECLARE_INSN 3517 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) 3518 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) 3519 DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) 3520 DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) 3521 DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) 3522 DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) 3523 DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) 3524 DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) 3525 DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) 3526 DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) 3527 DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) 3528 DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) 3529 DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) 3530 DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) 3531 DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) 3532 DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) 3533 DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) 3534 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) 3535 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) 3536 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 3537 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 3538 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 3539 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 3540 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 3541 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 3542 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 3543 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 3544 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 3545 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 3546 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 3547 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 3548 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 3549 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 3550 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 3551 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 3552 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 3553 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 3554 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 3555 DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 3556 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 3557 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 3558 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 3559 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 3560 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 3561 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 3562 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 3563 DECLARE_INSN(or, MATCH_OR, MASK_OR) 3564 DECLARE_INSN(and, MATCH_AND, MASK_AND) 3565 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 3566 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 3567 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 3568 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 3569 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 3570 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 3571 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 3572 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 3573 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 3574 DECLARE_INSN(lb, MATCH_LB, MASK_LB) 3575 DECLARE_INSN(lh, MATCH_LH, MASK_LH) 3576 DECLARE_INSN(lw, MATCH_LW, MASK_LW) 3577 DECLARE_INSN(ld, MATCH_LD, MASK_LD) 3578 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 3579 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 3580 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 3581 DECLARE_INSN(sb, MATCH_SB, MASK_SB) 3582 DECLARE_INSN(sh, MATCH_SH, MASK_SH) 3583 DECLARE_INSN(sw, MATCH_SW, MASK_SW) 3584 DECLARE_INSN(sd, MATCH_SD, MASK_SD) 3585 DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) 3586 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 3587 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 3588 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 3589 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 3590 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 3591 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 3592 DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 3593 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 3594 DECLARE_INSN(rem, MATCH_REM, MASK_REM) 3595 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 3596 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 3597 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 3598 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 3599 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 3600 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 3601 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 3602 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 3603 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 3604 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 3605 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 3606 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 3607 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 3608 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 3609 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 3610 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 3611 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 3612 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 3613 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 3614 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 3615 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 3616 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 3617 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 3618 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 3619 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 3620 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 3621 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 3622 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 3623 DECLARE_INSN(amoadd_b, MATCH_AMOADD_B, MASK_AMOADD_B) 3624 DECLARE_INSN(amoxor_b, MATCH_AMOXOR_B, MASK_AMOXOR_B) 3625 DECLARE_INSN(amoor_b, MATCH_AMOOR_B, MASK_AMOOR_B) 3626 DECLARE_INSN(amoand_b, MATCH_AMOAND_B, MASK_AMOAND_B) 3627 DECLARE_INSN(amomin_b, MATCH_AMOMIN_B, MASK_AMOMIN_B) 3628 DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) 3629 DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) 3630 DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) 3631 DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) 3632 DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) 3633 DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) 3634 DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) 3635 DECLARE_INSN(amoand_h, MATCH_AMOAND_H, MASK_AMOAND_H) 3636 DECLARE_INSN(amomin_h, MATCH_AMOMIN_H, MASK_AMOMIN_H) 3637 DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) 3638 DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) 3639 DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) 3640 DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) 3641 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 3642 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 3643 DECLARE_INSN(uret, MATCH_URET, MASK_URET) 3644 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 3645 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) 3646 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 3647 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 3648 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) 3649 DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 3650 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 3651 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 3652 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 3653 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 3654 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 3655 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 3656 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 3657 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 3658 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 3659 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 3660 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 3661 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 3662 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 3663 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 3664 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 3665 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 3666 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 3667 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 3668 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 3669 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 3670 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 3671 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 3672 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 3673 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 3674 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 3675 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 3676 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 3677 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 3678 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 3679 DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 3680 DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 3681 DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 3682 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 3683 DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 3684 DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 3685 DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 3686 DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 3687 DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 3688 DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 3689 DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 3690 DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 3691 DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 3692 DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 3693 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 3694 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 3695 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 3696 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 3697 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 3698 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 3699 DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 3700 DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 3701 DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 3702 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 3703 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 3704 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 3705 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 3706 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 3707 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 3708 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 3709 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 3710 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 3711 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 3712 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 3713 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 3714 DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 3715 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 3716 DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 3717 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 3718 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 3719 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 3720 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 3721 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 3722 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 3723 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 3724 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 3725 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 3726 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 3727 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 3728 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 3729 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 3730 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 3731 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 3732 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 3733 DECLARE_INSN(fli_h, MATCH_FLI_H, MASK_FLI_H) 3734 DECLARE_INSN(fminm_h, MATCH_FMINM_H, MASK_FMINM_H) 3735 DECLARE_INSN(fmaxm_h, MATCH_FMAXM_H, MASK_FMAXM_H) 3736 DECLARE_INSN(fround_h, MATCH_FROUND_H, MASK_FROUND_H) 3737 DECLARE_INSN(fround_nx_h, MATCH_FROUNDNX_H, MASK_FROUNDNX_H) 3738 DECLARE_INSN(fltq_h, MATCH_FLTQ_H, MASK_FLTQ_H) 3739 DECLARE_INSN(fleq_h, MATCH_FLEQ_H, MASK_FLEQ_H) 3740 DECLARE_INSN(fli_s, MATCH_FLI_S, MASK_FLI_S) 3741 DECLARE_INSN(fminm_s, MATCH_FMINM_S, MASK_FMINM_S) 3742 DECLARE_INSN(fmaxm_s, MATCH_FMAXM_S, MASK_FMAXM_S) 3743 DECLARE_INSN(fround_s, MATCH_FROUND_S, MASK_FROUND_S) 3744 DECLARE_INSN(fround_nx_s, MATCH_FROUNDNX_S, MASK_FROUNDNX_S) 3745 DECLARE_INSN(fltq_s, MATCH_FLTQ_S, MASK_FLTQ_S) 3746 DECLARE_INSN(fleq_s, MATCH_FLEQ_S, MASK_FLEQ_S) 3747 DECLARE_INSN(fli_d, MATCH_FLI_D, MASK_FLI_D) 3748 DECLARE_INSN(fminm_d, MATCH_FMINM_D, MASK_FMINM_D) 3749 DECLARE_INSN(fmaxm_d, MATCH_FMAXM_D, MASK_FMAXM_D) 3750 DECLARE_INSN(fround_d, MATCH_FROUND_D, MASK_FROUND_D) 3751 DECLARE_INSN(fround_nx_d, MATCH_FROUNDNX_D, MASK_FROUNDNX_D) 3752 DECLARE_INSN(fltq_d, MATCH_FLTQ_D, MASK_FLTQ_D) 3753 DECLARE_INSN(fleq_d, MATCH_FLEQ_D, MASK_FLEQ_D) 3754 DECLARE_INSN(fli_q, MATCH_FLI_Q, MASK_FLI_Q) 3755 DECLARE_INSN(fminm_q, MATCH_FMINM_Q, MASK_FMINM_Q) 3756 DECLARE_INSN(fmaxm_q, MATCH_FMAXM_Q, MASK_FMAXM_Q) 3757 DECLARE_INSN(fround_q, MATCH_FROUND_Q, MASK_FROUND_Q) 3758 DECLARE_INSN(fround_nx_q, MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q) 3759 DECLARE_INSN(fltq_q, MATCH_FLTQ_Q, MASK_FLTQ_Q) 3760 DECLARE_INSN(fleq_q, MATCH_FLEQ_Q, MASK_FLEQ_Q) 3761 DECLARE_INSN(fcvtmod_w_d, MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D) 3762 DECLARE_INSN(fmvh_x_d, MATCH_FMVH_X_D, MASK_FMVH_X_D) 3763 DECLARE_INSN(fmvh_x_q, MATCH_FMVH_X_Q, MASK_FMVH_X_Q) 3764 DECLARE_INSN(fmvp_d_x, MATCH_FMVP_D_X, MASK_FMVP_D_X) 3765 DECLARE_INSN(fmvp_q_x, MATCH_FMVP_Q_X, MASK_FMVP_Q_X) 3766 DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) 3767 DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) 3768 DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) 3769 DECLARE_INSN(min, MATCH_MIN, MASK_MIN) 3770 DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) 3771 DECLARE_INSN(max, MATCH_MAX, MASK_MAX) 3772 DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) 3773 DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) 3774 DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) 3775 DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) 3776 DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) 3777 DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) 3778 DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) 3779 DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) 3780 DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) 3781 DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) 3782 DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) 3783 DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) 3784 DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) 3785 DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) 3786 DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) 3787 DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) 3788 DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) 3789 DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) 3790 DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) 3791 DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) 3792 DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) 3793 DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) 3794 DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) 3795 DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) 3796 DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) 3797 DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) 3798 DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) 3799 DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) 3800 DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) 3801 DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) 3802 DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) 3803 DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) 3804 DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) 3805 DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) 3806 DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) 3807 DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) 3808 DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) 3809 DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) 3810 DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) 3811 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 3812 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 3813 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 3814 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 3815 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 3816 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 3817 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 3818 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 3819 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 3820 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 3821 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 3822 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 3823 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 3824 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 3825 DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 3826 DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 3827 DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 3828 DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 3829 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 3830 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 3831 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 3832 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 3833 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 3834 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 3835 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 3836 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 3837 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 3838 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 3839 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 3840 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 3841 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 3842 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 3843 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 3844 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 3845 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 3846 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 3847 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 3848 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 3849 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 3850 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 3851 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 3852 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 3853 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 3854 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 3855 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 3856 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 3857 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 3858 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 3859 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 3860 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 3861 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 3862 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 3863 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 3864 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 3865 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 3866 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 3867 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 3868 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 3869 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 3870 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 3871 DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) 3872 DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) 3873 DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) 3874 DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) 3875 DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) 3876 DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) 3877 DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) 3878 DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) 3879 DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) 3880 DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) 3881 DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) 3882 DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) 3883 DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) 3884 DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) 3885 DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) 3886 DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) 3887 DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) 3888 DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) 3889 DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) 3890 DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) 3891 /* Zicbop instructions. */ 3892 DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) 3893 DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) 3894 DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) 3895 /* Zicbom/Zicboz instructions. */ 3896 DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN) 3897 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH) 3898 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL) 3899 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) 3900 /* Zicond instructions. */ 3901 DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ) 3902 DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) 3903 /* Zihintntl hint instructions. */ 3904 DECLARE_INSN(ntl_p1, MATCH_NTL_P1, MASK_NTL_P1) 3905 DECLARE_INSN(ntl_pall, MATCH_NTL_PALL, MASK_NTL_PALL) 3906 DECLARE_INSN(ntl_s1, MATCH_NTL_S1, MASK_NTL_S1) 3907 DECLARE_INSN(ntl_all, MATCH_NTL_ALL, MASK_NTL_ALL) 3908 DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) 3909 DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) 3910 DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) 3911 DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) 3912 /* Zawrs instructions. */ 3913 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) 3914 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) 3915 /* Zvbb/Zvkb instructions. */ 3916 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) 3917 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) 3918 DECLARE_INSN(vbrev8_v, MATCH_VBREV8_V, MASK_VBREV8_V) 3919 DECLARE_INSN(vbrev_v, MATCH_VBREV_V, MASK_VBREV_V) 3920 DECLARE_INSN(vclz_v, MATCH_VCLZ_V, MASK_VCLZ_V) 3921 DECLARE_INSN(vcpop_v, MATCH_VCPOP_V, MASK_VCPOP_V) 3922 DECLARE_INSN(vctz_v, MATCH_VCTZ_V, MASK_VCTZ_V) 3923 DECLARE_INSN(vrev8_v, MATCH_VREV8_V, MASK_VREV8_V) 3924 DECLARE_INSN(vrol_vv, MATCH_VROL_VV, MASK_VROL_VV) 3925 DECLARE_INSN(vrol_vx, MATCH_VROL_VX, MASK_VROL_VX) 3926 DECLARE_INSN(vror_vi, MATCH_VROR_VI, MASK_VROR_VI) 3927 DECLARE_INSN(vror_vv, MATCH_VROR_VV, MASK_VROR_VV) 3928 DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX) 3929 DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI) 3930 DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV) 3931 DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX) 3932 /* Zvbc instructions. */ 3933 DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV) 3934 DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX) 3935 DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV) 3936 DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX) 3937 /* Zvkg instructions. */ 3938 DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) 3939 DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) 3940 /* Zvkned instructions. */ 3941 DECLARE_INSN(vaesdf_vs, MATCH_VAESDF_VS, MASK_VAESDF_VS) 3942 DECLARE_INSN(vaesdf_vv, MATCH_VAESDF_VV, MASK_VAESDF_VV) 3943 DECLARE_INSN(vaesdm_vs, MATCH_VAESDM_VS, MASK_VAESDM_VS) 3944 DECLARE_INSN(vaesdm_vv, MATCH_VAESDM_VV, MASK_VAESDM_VV) 3945 DECLARE_INSN(vaesef_vs, MATCH_VAESEF_VS, MASK_VAESEF_VS) 3946 DECLARE_INSN(vaesef_vv, MATCH_VAESEF_VV, MASK_VAESEF_VV) 3947 DECLARE_INSN(vaesem_vs, MATCH_VAESEM_VS, MASK_VAESEM_VS) 3948 DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV) 3949 DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI) 3950 DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI) 3951 DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) 3952 /* Zvknh[a,b] instructions. */ 3953 DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV) 3954 DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV) 3955 DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV) 3956 /* Zvksed instructions. */ 3957 DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI) 3958 DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS) 3959 DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV) 3960 /* Zvksh instructions. */ 3961 DECLARE_INSN(vsm3c_vi, MATCH_VSM3C_VI, MASK_VSM3C_VI) 3962 DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV) 3963 /* Zcb instructions. */ 3964 DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) 3965 DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) 3966 DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) 3967 DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) 3968 DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) 3969 DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL) 3970 DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT) 3971 DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) 3972 DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) 3973 DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) 3974 DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) 3975 DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) 3976 /* Zcmp instructions. */ 3977 DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) 3978 DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) 3979 DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) 3980 DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) 3981 /* Vendor-specific (T-Head) XTheadBa instructions. */ 3982 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) 3983 /* Vendor-specific (T-Head) XTheadBb instructions. */ 3984 DECLARE_INSN(th_srri, MATCH_TH_SRRI, MASK_TH_SRRI) 3985 DECLARE_INSN(th_srriw, MATCH_TH_SRRIW, MASK_TH_SRRIW) 3986 DECLARE_INSN(th_ext, MATCH_TH_EXT, MASK_TH_EXT) 3987 DECLARE_INSN(th_extu, MATCH_TH_EXTU, MASK_TH_EXTU) 3988 DECLARE_INSN(th_ff0, MATCH_TH_FF0, MASK_TH_FF0) 3989 DECLARE_INSN(th_ff1, MATCH_TH_FF1, MASK_TH_FF1) 3990 DECLARE_INSN(th_rev, MATCH_TH_REV, MASK_TH_REV) 3991 DECLARE_INSN(th_revw, MATCH_TH_REVW, MASK_TH_REVW) 3992 DECLARE_INSN(th_tstbnz, MATCH_TH_TSTNBZ, MASK_TH_TSTNBZ) 3993 /* Vendor-specific (T-Head) XTheadBs instructions. */ 3994 DECLARE_INSN(th_tst, MATCH_TH_TST, MASK_TH_TST) 3995 /* Vendor-specific (T-Head) XTheadCmo instructions. */ 3996 DECLARE_INSN(th_dcache_call, MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL) 3997 DECLARE_INSN(th_dcache_ciall, MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL) 3998 DECLARE_INSN(th_dcache_iall, MATCH_TH_DCACHE_IALL, MASK_TH_DCACHE_IALL) 3999 DECLARE_INSN(th_dcache_cpa, MATCH_TH_DCACHE_CPA, MASK_TH_DCACHE_CPA) 4000 DECLARE_INSN(th_dcache_cipa, MATCH_TH_DCACHE_CIPA, MASK_TH_DCACHE_CIPA) 4001 DECLARE_INSN(th_dcache_ipa, MATCH_TH_DCACHE_IPA, MASK_TH_DCACHE_IPA) 4002 DECLARE_INSN(th_dcache_cva, MATCH_TH_DCACHE_CVA, MASK_TH_DCACHE_CVA) 4003 DECLARE_INSN(th_dcache_civa, MATCH_TH_DCACHE_CIVA, MASK_TH_DCACHE_CIVA) 4004 DECLARE_INSN(th_dcache_iva, MATCH_TH_DCACHE_IVA, MASK_TH_DCACHE_IVA) 4005 DECLARE_INSN(th_dcache_csw, MATCH_TH_DCACHE_CSW, MASK_TH_DCACHE_CSW) 4006 DECLARE_INSN(th_dcache_cisw, MATCH_TH_DCACHE_CISW, MASK_TH_DCACHE_CISW) 4007 DECLARE_INSN(th_dcache_isw, MATCH_TH_DCACHE_ISW, MASK_TH_DCACHE_ISW) 4008 DECLARE_INSN(th_dcache_cpal1, MATCH_TH_DCACHE_CPAL1, MASK_TH_DCACHE_CPAL1) 4009 DECLARE_INSN(th_dcache_cval1, MATCH_TH_DCACHE_CVAL1, MASK_TH_DCACHE_CVAL1) 4010 DECLARE_INSN(th_icache_iall, MATCH_TH_ICACHE_IALL, MASK_TH_ICACHE_IALL) 4011 DECLARE_INSN(th_icache_ialls, MATCH_TH_ICACHE_IALLS, MASK_TH_ICACHE_IALLS) 4012 DECLARE_INSN(th_icache_ipa, MATCH_TH_ICACHE_IPA, MASK_TH_ICACHE_IPA) 4013 DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA) 4014 DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL) 4015 DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL) 4016 DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) 4017 /* Vendor-specific (T-Head) XTheadCondMov instructions. */ 4018 DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) 4019 DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) 4020 /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ 4021 DECLARE_INSN(th_flrd, MATCH_TH_FLRD, MASK_TH_FLRD) 4022 DECLARE_INSN(th_flrw, MATCH_TH_FLRW, MASK_TH_FLRW) 4023 DECLARE_INSN(th_flurd, MATCH_TH_FLURD, MASK_TH_FLURD) 4024 DECLARE_INSN(th_flurw, MATCH_TH_FLURW, MASK_TH_FLURW) 4025 DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD) 4026 DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW) 4027 DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD) 4028 DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW) 4029 /* Vendor-specific (T-Head) XTheadFmv instructions. */ 4030 DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X) 4031 DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW) 4032 /* Vendor-specific (T-Head) XTheadInt instructions. */ 4033 DECLARE_INSN(th_ipop, MATCH_TH_IPOP, MASK_TH_IPOP) 4034 DECLARE_INSN(th_ipush, MATCH_TH_IPUSH, MASK_TH_IPUSH) 4035 /* Vendor-specific (T-Head) XTheadMac instructions. */ 4036 DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) 4037 DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) 4038 DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW) 4039 DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS) 4040 DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH) 4041 DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW) 4042 /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ 4043 DECLARE_INSN(th_ldia, MATCH_TH_LDIA, MASK_TH_LDIA) 4044 DECLARE_INSN(th_ldib, MATCH_TH_LDIB, MASK_TH_LDIB) 4045 DECLARE_INSN(th_lwia, MATCH_TH_LWIA, MASK_TH_LWIA) 4046 DECLARE_INSN(th_lwib, MATCH_TH_LWIB, MASK_TH_LWIB) 4047 DECLARE_INSN(th_lwuia, MATCH_TH_LWUIA, MASK_TH_LWUIA) 4048 DECLARE_INSN(th_lwuib, MATCH_TH_LWUIB, MASK_TH_LWUIB) 4049 DECLARE_INSN(th_lhia, MATCH_TH_LHIA, MASK_TH_LHIA) 4050 DECLARE_INSN(th_lhib, MATCH_TH_LHIB, MASK_TH_LHIB) 4051 DECLARE_INSN(th_lhuia, MATCH_TH_LHUIA, MASK_TH_LHUIA) 4052 DECLARE_INSN(th_lhuib, MATCH_TH_LHUIB, MASK_TH_LHUIB) 4053 DECLARE_INSN(th_lbia, MATCH_TH_LBIA, MASK_TH_LBIA) 4054 DECLARE_INSN(th_lbib, MATCH_TH_LBIB, MASK_TH_LBIB) 4055 DECLARE_INSN(th_lbuia, MATCH_TH_LBUIA, MASK_TH_LBUIA) 4056 DECLARE_INSN(th_lbuib, MATCH_TH_LBUIB, MASK_TH_LBUIB) 4057 DECLARE_INSN(th_sdia, MATCH_TH_SDIA, MASK_TH_SDIA) 4058 DECLARE_INSN(th_sdib, MATCH_TH_SDIB, MASK_TH_SDIB) 4059 DECLARE_INSN(th_swia, MATCH_TH_SWIA, MASK_TH_SWIA) 4060 DECLARE_INSN(th_swib, MATCH_TH_SWIB, MASK_TH_SWIB) 4061 DECLARE_INSN(th_shia, MATCH_TH_SHIA, MASK_TH_SHIA) 4062 DECLARE_INSN(th_shib, MATCH_TH_SHIB, MASK_TH_SHIB) 4063 DECLARE_INSN(th_sbia, MATCH_TH_SBIA, MASK_TH_SBIA) 4064 DECLARE_INSN(th_sbib, MATCH_TH_SBIB, MASK_TH_SBIB) 4065 DECLARE_INSN(th_lrd, MATCH_TH_LRD, MASK_TH_LRD) 4066 DECLARE_INSN(th_lrw, MATCH_TH_LRW, MASK_TH_LRW) 4067 DECLARE_INSN(th_lrwu, MATCH_TH_LRWU, MASK_TH_LRWU) 4068 DECLARE_INSN(th_lrh, MATCH_TH_LRH, MASK_TH_LRH) 4069 DECLARE_INSN(th_lrhu, MATCH_TH_LRHU, MASK_TH_LRHU) 4070 DECLARE_INSN(th_lrb, MATCH_TH_LRB, MASK_TH_LRB) 4071 DECLARE_INSN(th_lrbu, MATCH_TH_LRBU, MASK_TH_LRBU) 4072 DECLARE_INSN(th_srd, MATCH_TH_SRD, MASK_TH_SRD) 4073 DECLARE_INSN(th_srw, MATCH_TH_SRW, MASK_TH_SRW) 4074 DECLARE_INSN(th_srh, MATCH_TH_SRH, MASK_TH_SRH) 4075 DECLARE_INSN(th_srb, MATCH_TH_SRB, MASK_TH_SRB) 4076 DECLARE_INSN(th_lurd, MATCH_TH_LURD, MASK_TH_LURD) 4077 DECLARE_INSN(th_lurw, MATCH_TH_LURW, MASK_TH_LURW) 4078 DECLARE_INSN(th_lurwu, MATCH_TH_LURWU, MASK_TH_LURWU) 4079 DECLARE_INSN(th_lurh, MATCH_TH_LURH, MASK_TH_LURH) 4080 DECLARE_INSN(th_lurhu, MATCH_TH_LURHU, MASK_TH_LURHU) 4081 DECLARE_INSN(th_lurb, MATCH_TH_LURB, MASK_TH_LURB) 4082 DECLARE_INSN(th_lurbu, MATCH_TH_LURBU, MASK_TH_LURBU) 4083 DECLARE_INSN(th_surd, MATCH_TH_SURD, MASK_TH_SURD) 4084 DECLARE_INSN(th_surw, MATCH_TH_SURW, MASK_TH_SURW) 4085 DECLARE_INSN(th_surh, MATCH_TH_SURH, MASK_TH_SURH) 4086 DECLARE_INSN(th_surb, MATCH_TH_SURB, MASK_TH_SURB) 4087 /* Vendor-specific (T-Head) XTheadMemPair instructions. */ 4088 DECLARE_INSN(th_ldd, MATCH_TH_LDD, MASK_TH_LDD) 4089 DECLARE_INSN(th_lwd, MATCH_TH_LWD, MASK_TH_LWD) 4090 DECLARE_INSN(th_lwud, MATCH_TH_LWUD, MASK_TH_LWUD) 4091 DECLARE_INSN(th_sdd, MATCH_TH_SDD, MASK_TH_SDD) 4092 DECLARE_INSN(th_swd, MATCH_TH_SWD, MASK_TH_SWD) 4093 /* Vendor-specific (T-Head) XTheadSync instructions. */ 4094 DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) 4095 DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) 4096 DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I) 4097 DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS) 4098 DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S) 4099 /* XVentanaCondOps instructions. */ 4100 DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC) 4101 DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN) 4102 #endif /* DECLARE_INSN */ 4103 #ifdef DECLARE_CSR 4104 /* Unprivileged Counter/Timers CSRs. */ 4105 DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4106 DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4107 DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4108 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4109 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4110 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4111 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4112 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4113 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4114 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4115 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4116 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4117 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4118 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4119 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4120 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4121 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4122 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4123 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4124 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4125 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4126 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4127 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4128 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4129 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4130 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4131 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4132 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4133 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4134 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4135 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4136 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4137 DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4138 DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4139 DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4140 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4141 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4142 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4143 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4144 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4145 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4146 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4147 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4148 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4149 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4150 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4151 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4152 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4153 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4154 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4155 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4156 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4157 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4158 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4159 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4160 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4161 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4162 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4163 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4164 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4165 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4166 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4167 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4168 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4169 /* Privileged Supervisor CSRs. */ 4170 DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4171 DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4172 DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4173 DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4174 DECLARE_CSR(senvcfg, CSR_SENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4175 DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4176 DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4177 DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4178 DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4179 DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4180 DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4181 /* Privileged Machine CSRs. */ 4182 DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4183 DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4184 DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4185 DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4186 DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4187 DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4188 DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4189 DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4190 DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4191 DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4192 DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4193 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4194 DECLARE_CSR(mstatush, CSR_MSTATUSH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4195 DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4196 DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4197 DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4198 DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4199 DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4200 DECLARE_CSR(mtinst, CSR_MTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4201 DECLARE_CSR(mtval2, CSR_MTVAL2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4202 DECLARE_CSR(menvcfg, CSR_MENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4203 DECLARE_CSR(menvcfgh, CSR_MENVCFGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4204 DECLARE_CSR(mseccfg, CSR_MSECCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4205 DECLARE_CSR(mseccfgh, CSR_MSECCFGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4206 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4207 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4208 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4209 DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4210 DECLARE_CSR(pmpcfg4, CSR_PMPCFG4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4211 DECLARE_CSR(pmpcfg5, CSR_PMPCFG5, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4212 DECLARE_CSR(pmpcfg6, CSR_PMPCFG6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4213 DECLARE_CSR(pmpcfg7, CSR_PMPCFG7, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4214 DECLARE_CSR(pmpcfg8, CSR_PMPCFG8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4215 DECLARE_CSR(pmpcfg9, CSR_PMPCFG9, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4216 DECLARE_CSR(pmpcfg10, CSR_PMPCFG10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4217 DECLARE_CSR(pmpcfg11, CSR_PMPCFG11, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4218 DECLARE_CSR(pmpcfg12, CSR_PMPCFG12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4219 DECLARE_CSR(pmpcfg13, CSR_PMPCFG13, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4220 DECLARE_CSR(pmpcfg14, CSR_PMPCFG14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4221 DECLARE_CSR(pmpcfg15, CSR_PMPCFG15, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4222 DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4223 DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4224 DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4225 DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4226 DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4227 DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4228 DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4229 DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4230 DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4231 DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4232 DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4233 DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4234 DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4235 DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4236 DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4237 DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4238 DECLARE_CSR(pmpaddr16, CSR_PMPADDR16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4239 DECLARE_CSR(pmpaddr17, CSR_PMPADDR17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4240 DECLARE_CSR(pmpaddr18, CSR_PMPADDR18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4241 DECLARE_CSR(pmpaddr19, CSR_PMPADDR19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4242 DECLARE_CSR(pmpaddr20, CSR_PMPADDR20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4243 DECLARE_CSR(pmpaddr21, CSR_PMPADDR21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4244 DECLARE_CSR(pmpaddr22, CSR_PMPADDR22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4245 DECLARE_CSR(pmpaddr23, CSR_PMPADDR23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4246 DECLARE_CSR(pmpaddr24, CSR_PMPADDR24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4247 DECLARE_CSR(pmpaddr25, CSR_PMPADDR25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4248 DECLARE_CSR(pmpaddr26, CSR_PMPADDR26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4249 DECLARE_CSR(pmpaddr27, CSR_PMPADDR27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4250 DECLARE_CSR(pmpaddr28, CSR_PMPADDR28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4251 DECLARE_CSR(pmpaddr29, CSR_PMPADDR29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4252 DECLARE_CSR(pmpaddr30, CSR_PMPADDR30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4253 DECLARE_CSR(pmpaddr31, CSR_PMPADDR31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4254 DECLARE_CSR(pmpaddr32, CSR_PMPADDR32, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4255 DECLARE_CSR(pmpaddr33, CSR_PMPADDR33, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4256 DECLARE_CSR(pmpaddr34, CSR_PMPADDR34, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4257 DECLARE_CSR(pmpaddr35, CSR_PMPADDR35, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4258 DECLARE_CSR(pmpaddr36, CSR_PMPADDR36, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4259 DECLARE_CSR(pmpaddr37, CSR_PMPADDR37, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4260 DECLARE_CSR(pmpaddr38, CSR_PMPADDR38, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4261 DECLARE_CSR(pmpaddr39, CSR_PMPADDR39, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4262 DECLARE_CSR(pmpaddr40, CSR_PMPADDR40, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4263 DECLARE_CSR(pmpaddr41, CSR_PMPADDR41, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4264 DECLARE_CSR(pmpaddr42, CSR_PMPADDR42, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4265 DECLARE_CSR(pmpaddr43, CSR_PMPADDR43, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4266 DECLARE_CSR(pmpaddr44, CSR_PMPADDR44, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4267 DECLARE_CSR(pmpaddr45, CSR_PMPADDR45, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4268 DECLARE_CSR(pmpaddr46, CSR_PMPADDR46, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4269 DECLARE_CSR(pmpaddr47, CSR_PMPADDR47, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4270 DECLARE_CSR(pmpaddr48, CSR_PMPADDR48, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4271 DECLARE_CSR(pmpaddr49, CSR_PMPADDR49, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4272 DECLARE_CSR(pmpaddr50, CSR_PMPADDR50, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4273 DECLARE_CSR(pmpaddr51, CSR_PMPADDR51, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4274 DECLARE_CSR(pmpaddr52, CSR_PMPADDR52, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4275 DECLARE_CSR(pmpaddr53, CSR_PMPADDR53, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4276 DECLARE_CSR(pmpaddr54, CSR_PMPADDR54, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4277 DECLARE_CSR(pmpaddr55, CSR_PMPADDR55, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4278 DECLARE_CSR(pmpaddr56, CSR_PMPADDR56, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4279 DECLARE_CSR(pmpaddr57, CSR_PMPADDR57, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4280 DECLARE_CSR(pmpaddr58, CSR_PMPADDR58, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4281 DECLARE_CSR(pmpaddr59, CSR_PMPADDR59, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4282 DECLARE_CSR(pmpaddr60, CSR_PMPADDR60, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4283 DECLARE_CSR(pmpaddr61, CSR_PMPADDR61, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4284 DECLARE_CSR(pmpaddr62, CSR_PMPADDR62, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4285 DECLARE_CSR(pmpaddr63, CSR_PMPADDR63, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 4286 DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4287 DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4288 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4289 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4290 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4291 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4292 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4293 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4294 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4295 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4296 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4297 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4298 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4299 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4300 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4301 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4302 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4303 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4304 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4305 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4306 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4307 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4308 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4309 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4310 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4311 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4312 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4313 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4314 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4315 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4316 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4317 DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4318 DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4319 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4320 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4321 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4322 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4323 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4324 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4325 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4326 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4327 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4328 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4329 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4330 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4331 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4332 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4333 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4334 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4335 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4336 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4337 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4338 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4339 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4340 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4341 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4342 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4343 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4344 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4345 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4346 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4347 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4348 DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) 4349 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4350 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4351 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4352 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4353 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4354 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4355 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4356 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4357 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4358 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4359 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4360 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4361 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4362 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4363 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4364 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4365 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4366 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4367 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4368 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4369 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4370 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4371 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4372 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4373 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4374 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4375 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4376 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4377 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4378 /* Privileged Hypervisor CSRs. */ 4379 DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4380 DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4381 DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4382 DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4383 DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4384 DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4385 DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4386 DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4387 DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4388 DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4389 DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4390 DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4391 DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4392 DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4393 DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4394 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4395 DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4396 DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4397 DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4398 DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4399 DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4400 DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4401 DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4402 DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4403 DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4404 /* Smaia extension */ 4405 DECLARE_CSR(miselect, CSR_MISELECT, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4406 DECLARE_CSR(mireg, CSR_MIREG, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4407 DECLARE_CSR(mtopei, CSR_MTOPEI, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4408 DECLARE_CSR(mtopi, CSR_MTOPI, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4409 DECLARE_CSR(mvien, CSR_MVIEN, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4410 DECLARE_CSR(mvip, CSR_MVIP, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4411 DECLARE_CSR(midelegh, CSR_MIDELEGH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4412 DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4413 DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4414 DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4415 DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4416 /* Smcntrpmf extension (incompatible with the privileged spec v1.9.1). */ 4417 DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4418 DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4419 DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4420 DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 4421 /* Smstateen/Ssstateen extensions. */ 4422 DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4423 DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4424 DECLARE_CSR(mstateen2, CSR_MSTATEEN2, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4425 DECLARE_CSR(mstateen3, CSR_MSTATEEN3, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4426 DECLARE_CSR(sstateen0, CSR_SSTATEEN0, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4427 DECLARE_CSR(sstateen1, CSR_SSTATEEN1, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4428 DECLARE_CSR(sstateen2, CSR_SSTATEEN2, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4429 DECLARE_CSR(sstateen3, CSR_SSTATEEN3, CSR_CLASS_SSSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4430 DECLARE_CSR(hstateen0, CSR_HSTATEEN0, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4431 DECLARE_CSR(hstateen1, CSR_HSTATEEN1, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4432 DECLARE_CSR(hstateen2, CSR_HSTATEEN2, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4433 DECLARE_CSR(hstateen3, CSR_HSTATEEN3, CSR_CLASS_SSSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4434 DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4435 DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4436 DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4437 DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4438 DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4439 DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4440 DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4441 DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4442 /* Ssaia extension */ 4443 DECLARE_CSR(siselect, CSR_SISELECT, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4444 DECLARE_CSR(sireg, CSR_SIREG, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4445 DECLARE_CSR(stopei, CSR_STOPEI, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4446 DECLARE_CSR(stopi, CSR_STOPI, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4447 DECLARE_CSR(sieh, CSR_SIEH, CSR_CLASS_SSAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4448 DECLARE_CSR(siph, CSR_SIPH, CSR_CLASS_SSAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4449 DECLARE_CSR(hvien, CSR_HVIEN, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4450 DECLARE_CSR(hvictl, CSR_HVICTL, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4451 DECLARE_CSR(hviprio1, CSR_HVIPRIO1, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4452 DECLARE_CSR(hviprio2, CSR_HVIPRIO2, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4453 DECLARE_CSR(vsiselect, CSR_VSISELECT, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4454 DECLARE_CSR(vsireg, CSR_VSIREG, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4455 DECLARE_CSR(vstopei, CSR_VSTOPEI, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4456 DECLARE_CSR(vstopi, CSR_VSTOPI, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4457 DECLARE_CSR(hidelegh, CSR_HIDELEGH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4458 DECLARE_CSR(hvienh, CSR_HVIENH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4459 DECLARE_CSR(hviph, CSR_HVIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4460 DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4461 DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4462 DECLARE_CSR(vsieh, CSR_VSIEH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4463 DECLARE_CSR(vsiph, CSR_VSIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4464 /* Sscofpmf extension */ 4465 DECLARE_CSR(scountovf, CSR_SCOUNTOVF, CSR_CLASS_SSCOFPMF, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4466 DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4467 DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4468 DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4469 DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4470 DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4471 DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4472 DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4473 DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4474 DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4475 DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4476 DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4477 DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4478 DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4479 DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4480 DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4481 DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4482 DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4483 DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4484 DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4485 DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4486 DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4487 DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4488 DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4489 DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4490 DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4491 DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4492 DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4493 DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4494 DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4495 /* Sstc extension */ 4496 DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4497 DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4498 DECLARE_CSR(vstimecmp, CSR_VSTIMECMP, CSR_CLASS_SSTC_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4499 DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH, CSR_CLASS_SSTC_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4500 /* Dropped CSRs. */ 4501 DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4502 DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4503 DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4504 DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4505 DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4506 DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4507 DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4508 DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4509 DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4510 DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 4511 /* Unprivileged Floating-Point CSRs. */ 4512 DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4513 DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4514 DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4515 /* Unprivileged Debug CSRs. */ 4516 DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4517 DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4518 DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4519 DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4520 DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4521 DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4522 DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4523 DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4524 DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4525 DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4526 DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4527 DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4528 DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4529 DECLARE_CSR(mscontext, CSR_MSCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4530 /* Unprivileged Scalar Crypto CSRs. */ 4531 DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4532 /* Unprivileged Vector CSRs. */ 4533 DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4534 DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4535 DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4536 DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4537 DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4538 DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4539 DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4540 #endif /* DECLARE_CSR */ 4541 #ifdef DECLARE_CSR_ALIAS 4542 DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4543 DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4544 DECLARE_CSR_ALIAS(mcontrol6, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4545 DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4546 DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4547 DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4548 DECLARE_CSR_ALIAS(tmexttrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4549 DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4550 DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4551 /* Unprivileged T-Head Vector CSRs. */ 4552 DECLARE_CSR_ALIAS(th.vstart, CSR_VSTART, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4553 DECLARE_CSR_ALIAS(th.vxsat, CSR_VXSAT, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4554 DECLARE_CSR_ALIAS(th.vxrm, CSR_VXRM, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4555 DECLARE_CSR_ALIAS(th.vl, CSR_VL, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4556 DECLARE_CSR_ALIAS(th.vtype, CSR_VTYPE, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4557 DECLARE_CSR_ALIAS(th.vlenb, CSR_VLENB, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 4558 #endif /* DECLARE_CSR_ALIAS */ 4559