1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for 2 GDB. 3 Copyright (C) 1995-2024 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "linux-low.h" 21 22 #include "elf/common.h" 23 #include <sys/uio.h> 24 #include <elf.h> 25 #include <asm/ptrace.h> 26 27 #include "arch/ppc-linux-common.h" 28 #include "arch/ppc-linux-tdesc.h" 29 #include "nat/ppc-linux.h" 30 #include "nat/linux-ptrace.h" 31 #include "linux-ppc-tdesc-init.h" 32 #include "ax.h" 33 #include "tracepoint.h" 34 35 #define PPC_FIELD(value, from, len) \ 36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) 37 #define PPC_SEXT(v, bs) \ 38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ 39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ 40 - ((CORE_ADDR) 1 << ((bs) - 1))) 41 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) 42 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) 43 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2) 44 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2) 45 46 /* Linux target op definitions for the PowerPC architecture. */ 47 48 class ppc_target : public linux_process_target 49 { 50 public: 51 52 const regs_info *get_regs_info () override; 53 54 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; 55 56 bool supports_z_point_type (char z_type) override; 57 58 59 void low_collect_ptrace_register (regcache *regcache, int regno, 60 char *buf) override; 61 62 void low_supply_ptrace_register (regcache *regcache, int regno, 63 const char *buf) override; 64 65 bool supports_tracepoints () override; 66 67 bool supports_fast_tracepoints () override; 68 69 int install_fast_tracepoint_jump_pad 70 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector, 71 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry, 72 CORE_ADDR *trampoline, ULONGEST *trampoline_size, 73 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size, 74 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end, 75 char *err) override; 76 77 int get_min_fast_tracepoint_insn_len () override; 78 79 struct emit_ops *emit_ops () override; 80 81 int get_ipa_tdesc_idx () override; 82 83 protected: 84 85 void low_arch_setup () override; 86 87 bool low_cannot_fetch_register (int regno) override; 88 89 bool low_cannot_store_register (int regno) override; 90 91 bool low_supports_breakpoints () override; 92 93 CORE_ADDR low_get_pc (regcache *regcache) override; 94 95 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; 96 97 bool low_breakpoint_at (CORE_ADDR pc) override; 98 99 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 100 int size, raw_breakpoint *bp) override; 101 102 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 103 int size, raw_breakpoint *bp) override; 104 105 int low_get_thread_area (int lwpid, CORE_ADDR *addrp) override; 106 }; 107 108 /* The singleton target ops object. */ 109 110 static ppc_target the_ppc_target; 111 112 /* Holds the AT_HWCAP auxv entry. */ 113 114 static unsigned long ppc_hwcap; 115 116 /* Holds the AT_HWCAP2 auxv entry. */ 117 118 static unsigned long ppc_hwcap2; 119 120 121 #define ppc_num_regs 73 122 123 #ifdef __powerpc64__ 124 /* We use a constant for FPSCR instead of PT_FPSCR, because 125 many shipped PPC64 kernels had the wrong value in ptrace.h. */ 126 static int ppc_regmap[] = 127 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8, 128 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8, 129 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8, 130 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8, 131 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8, 132 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8, 133 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8, 134 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8, 135 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24, 136 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56, 137 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88, 138 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120, 139 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152, 140 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184, 141 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216, 142 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248, 143 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8, 144 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256, 145 PT_ORIG_R3 * 8, PT_TRAP * 8 }; 146 #else 147 /* Currently, don't check/send MQ. */ 148 static int ppc_regmap[] = 149 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, 150 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, 151 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, 152 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, 153 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, 154 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, 155 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, 156 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, 157 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24, 158 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56, 159 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88, 160 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120, 161 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152, 162 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184, 163 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216, 164 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248, 165 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, 166 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4, 167 PT_ORIG_R3 * 4, PT_TRAP * 4 168 }; 169 170 static int ppc_regmap_e500[] = 171 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, 172 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, 173 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, 174 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, 175 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, 176 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, 177 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, 178 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, 179 -1, -1, -1, -1, 180 -1, -1, -1, -1, 181 -1, -1, -1, -1, 182 -1, -1, -1, -1, 183 -1, -1, -1, -1, 184 -1, -1, -1, -1, 185 -1, -1, -1, -1, 186 -1, -1, -1, -1, 187 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, 188 PT_CTR * 4, PT_XER * 4, -1, 189 PT_ORIG_R3 * 4, PT_TRAP * 4 190 }; 191 #endif 192 193 /* Check whether the kernel provides a register set with number 194 REGSET_ID of size REGSETSIZE for process/thread TID. */ 195 196 static int 197 ppc_check_regset (int tid, int regset_id, int regsetsize) 198 { 199 void *buf = alloca (regsetsize); 200 struct iovec iov; 201 202 iov.iov_base = buf; 203 iov.iov_len = regsetsize; 204 205 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 206 || errno == ENODATA) 207 return 1; 208 return 0; 209 } 210 211 bool 212 ppc_target::low_cannot_store_register (int regno) 213 { 214 const struct target_desc *tdesc = current_process ()->tdesc; 215 216 #ifndef __powerpc64__ 217 /* Some kernels do not allow us to store fpscr. */ 218 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE) 219 && regno == find_regno (tdesc, "fpscr")) 220 return true; 221 #endif 222 223 /* Some kernels do not allow us to store orig_r3 or trap. */ 224 if (regno == find_regno (tdesc, "orig_r3") 225 || regno == find_regno (tdesc, "trap")) 226 return true; 227 228 return false; 229 } 230 231 bool 232 ppc_target::low_cannot_fetch_register (int regno) 233 { 234 return false; 235 } 236 237 void 238 ppc_target::low_collect_ptrace_register (regcache *regcache, int regno, 239 char *buf) 240 { 241 memset (buf, 0, sizeof (long)); 242 243 if (__BYTE_ORDER == __LITTLE_ENDIAN) 244 { 245 /* Little-endian values always sit at the left end of the buffer. */ 246 collect_register (regcache, regno, buf); 247 } 248 else if (__BYTE_ORDER == __BIG_ENDIAN) 249 { 250 /* Big-endian values sit at the right end of the buffer. In case of 251 registers whose sizes are smaller than sizeof (long), we must use a 252 padding to access them correctly. */ 253 int size = register_size (regcache->tdesc, regno); 254 255 if (size < sizeof (long)) 256 collect_register (regcache, regno, buf + sizeof (long) - size); 257 else 258 collect_register (regcache, regno, buf); 259 } 260 else 261 perror_with_name ("Unexpected byte order"); 262 } 263 264 void 265 ppc_target::low_supply_ptrace_register (regcache *regcache, int regno, 266 const char *buf) 267 { 268 if (__BYTE_ORDER == __LITTLE_ENDIAN) 269 { 270 /* Little-endian values always sit at the left end of the buffer. */ 271 supply_register (regcache, regno, buf); 272 } 273 else if (__BYTE_ORDER == __BIG_ENDIAN) 274 { 275 /* Big-endian values sit at the right end of the buffer. In case of 276 registers whose sizes are smaller than sizeof (long), we must use a 277 padding to access them correctly. */ 278 int size = register_size (regcache->tdesc, regno); 279 280 if (size < sizeof (long)) 281 supply_register (regcache, regno, buf + sizeof (long) - size); 282 else 283 supply_register (regcache, regno, buf); 284 } 285 else 286 perror_with_name ("Unexpected byte order"); 287 } 288 289 bool 290 ppc_target::low_supports_breakpoints () 291 { 292 return true; 293 } 294 295 CORE_ADDR 296 ppc_target::low_get_pc (regcache *regcache) 297 { 298 if (register_size (regcache->tdesc, 0) == 4) 299 { 300 unsigned int pc; 301 collect_register_by_name (regcache, "pc", &pc); 302 return (CORE_ADDR) pc; 303 } 304 else 305 { 306 unsigned long pc; 307 collect_register_by_name (regcache, "pc", &pc); 308 return (CORE_ADDR) pc; 309 } 310 } 311 312 void 313 ppc_target::low_set_pc (regcache *regcache, CORE_ADDR pc) 314 { 315 if (register_size (regcache->tdesc, 0) == 4) 316 { 317 unsigned int newpc = pc; 318 supply_register_by_name (regcache, "pc", &newpc); 319 } 320 else 321 { 322 unsigned long newpc = pc; 323 supply_register_by_name (regcache, "pc", &newpc); 324 } 325 } 326 327 #ifndef __powerpc64__ 328 static int ppc_regmap_adjusted; 329 #endif 330 331 332 /* Correct in either endianness. 333 This instruction is "twge r2, r2", which GDB uses as a software 334 breakpoint. */ 335 static const unsigned int ppc_breakpoint = 0x7d821008; 336 #define ppc_breakpoint_len 4 337 338 /* Implementation of target ops method "sw_breakpoint_from_kind". */ 339 340 const gdb_byte * 341 ppc_target::sw_breakpoint_from_kind (int kind, int *size) 342 { 343 *size = ppc_breakpoint_len; 344 return (const gdb_byte *) &ppc_breakpoint; 345 } 346 347 bool 348 ppc_target::low_breakpoint_at (CORE_ADDR where) 349 { 350 unsigned int insn; 351 352 read_memory (where, (unsigned char *) &insn, 4); 353 if (insn == ppc_breakpoint) 354 return true; 355 /* If necessary, recognize more trap instructions here. GDB only uses 356 the one. */ 357 358 return false; 359 } 360 361 /* Implement supports_z_point_type target-ops. 362 Returns true if type Z_TYPE breakpoint is supported. 363 364 Handling software breakpoint at server side, so tracepoints 365 and breakpoints can be inserted at the same location. */ 366 367 bool 368 ppc_target::supports_z_point_type (char z_type) 369 { 370 switch (z_type) 371 { 372 case Z_PACKET_SW_BP: 373 return true; 374 case Z_PACKET_HW_BP: 375 case Z_PACKET_WRITE_WP: 376 case Z_PACKET_ACCESS_WP: 377 default: 378 return false; 379 } 380 } 381 382 /* Implement the low_insert_point linux target op. 383 Returns 0 on success, -1 on failure and 1 on unsupported. */ 384 385 int 386 ppc_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 387 int size, raw_breakpoint *bp) 388 { 389 switch (type) 390 { 391 case raw_bkpt_type_sw: 392 return insert_memory_breakpoint (bp); 393 394 case raw_bkpt_type_hw: 395 case raw_bkpt_type_write_wp: 396 case raw_bkpt_type_access_wp: 397 default: 398 /* Unsupported. */ 399 return 1; 400 } 401 } 402 403 /* Implement the low_remove_point linux target op. 404 Returns 0 on success, -1 on failure and 1 on unsupported. */ 405 406 int 407 ppc_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 408 int size, raw_breakpoint *bp) 409 { 410 switch (type) 411 { 412 case raw_bkpt_type_sw: 413 return remove_memory_breakpoint (bp); 414 415 case raw_bkpt_type_hw: 416 case raw_bkpt_type_write_wp: 417 case raw_bkpt_type_access_wp: 418 default: 419 /* Unsupported. */ 420 return 1; 421 } 422 } 423 424 /* Provide only a fill function for the general register set. ps_lgetregs 425 will use this for NPTL support. */ 426 427 static void ppc_fill_gregset (struct regcache *regcache, void *buf) 428 { 429 int i; 430 431 ppc_target *my_ppc_target = (ppc_target *) the_linux_target; 432 433 for (i = 0; i < 32; i++) 434 my_ppc_target->low_collect_ptrace_register (regcache, i, 435 (char *) buf + ppc_regmap[i]); 436 437 for (i = 64; i < 70; i++) 438 my_ppc_target->low_collect_ptrace_register (regcache, i, 439 (char *) buf + ppc_regmap[i]); 440 441 for (i = 71; i < 73; i++) 442 my_ppc_target->low_collect_ptrace_register (regcache, i, 443 (char *) buf + ppc_regmap[i]); 444 } 445 446 /* Program Priority Register regset fill function. */ 447 448 static void 449 ppc_fill_pprregset (struct regcache *regcache, void *buf) 450 { 451 char *ppr = (char *) buf; 452 453 collect_register_by_name (regcache, "ppr", ppr); 454 } 455 456 /* Program Priority Register regset store function. */ 457 458 static void 459 ppc_store_pprregset (struct regcache *regcache, const void *buf) 460 { 461 const char *ppr = (const char *) buf; 462 463 supply_register_by_name (regcache, "ppr", ppr); 464 } 465 466 /* Data Stream Control Register regset fill function. */ 467 468 static void 469 ppc_fill_dscrregset (struct regcache *regcache, void *buf) 470 { 471 char *dscr = (char *) buf; 472 473 collect_register_by_name (regcache, "dscr", dscr); 474 } 475 476 /* Data Stream Control Register regset store function. */ 477 478 static void 479 ppc_store_dscrregset (struct regcache *regcache, const void *buf) 480 { 481 const char *dscr = (const char *) buf; 482 483 supply_register_by_name (regcache, "dscr", dscr); 484 } 485 486 /* Target Address Register regset fill function. */ 487 488 static void 489 ppc_fill_tarregset (struct regcache *regcache, void *buf) 490 { 491 char *tar = (char *) buf; 492 493 collect_register_by_name (regcache, "tar", tar); 494 } 495 496 /* Target Address Register regset store function. */ 497 498 static void 499 ppc_store_tarregset (struct regcache *regcache, const void *buf) 500 { 501 const char *tar = (const char *) buf; 502 503 supply_register_by_name (regcache, "tar", tar); 504 } 505 506 /* Event-Based Branching regset store function. Unless the inferior 507 has a perf event open, ptrace can return in error when reading and 508 writing to the regset, with ENODATA. For reading, the registers 509 will correctly show as unavailable. For writing, gdbserver 510 currently only caches any register writes from P and G packets and 511 the stub always tries to write all the regsets when resuming the 512 inferior, which would result in frequent warnings. For this 513 reason, we don't define a fill function. This also means that the 514 client-side regcache will be dirty if the user tries to write to 515 the EBB registers. G packets that the client sends to write to 516 unrelated registers will also include data for EBB registers, even 517 if they are unavailable. */ 518 519 static void 520 ppc_store_ebbregset (struct regcache *regcache, const void *buf) 521 { 522 const char *regset = (const char *) buf; 523 524 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the 525 .dat file is BESCR, EBBHR, EBBRR. */ 526 supply_register_by_name (regcache, "ebbrr", ®set[0]); 527 supply_register_by_name (regcache, "ebbhr", ®set[8]); 528 supply_register_by_name (regcache, "bescr", ®set[16]); 529 } 530 531 /* Performance Monitoring Unit regset fill function. */ 532 533 static void 534 ppc_fill_pmuregset (struct regcache *regcache, void *buf) 535 { 536 char *regset = (char *) buf; 537 538 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0. 539 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */ 540 collect_register_by_name (regcache, "siar", ®set[0]); 541 collect_register_by_name (regcache, "sdar", ®set[8]); 542 collect_register_by_name (regcache, "sier", ®set[16]); 543 collect_register_by_name (regcache, "mmcr2", ®set[24]); 544 collect_register_by_name (regcache, "mmcr0", ®set[32]); 545 } 546 547 /* Performance Monitoring Unit regset store function. */ 548 549 static void 550 ppc_store_pmuregset (struct regcache *regcache, const void *buf) 551 { 552 const char *regset = (const char *) buf; 553 554 supply_register_by_name (regcache, "siar", ®set[0]); 555 supply_register_by_name (regcache, "sdar", ®set[8]); 556 supply_register_by_name (regcache, "sier", ®set[16]); 557 supply_register_by_name (regcache, "mmcr2", ®set[24]); 558 supply_register_by_name (regcache, "mmcr0", ®set[32]); 559 } 560 561 /* Hardware Transactional Memory special-purpose register regset fill 562 function. */ 563 564 static void 565 ppc_fill_tm_sprregset (struct regcache *regcache, void *buf) 566 { 567 int i, base; 568 char *regset = (char *) buf; 569 570 base = find_regno (regcache->tdesc, "tfhar"); 571 for (i = 0; i < 3; i++) 572 collect_register (regcache, base + i, ®set[i * 8]); 573 } 574 575 /* Hardware Transactional Memory special-purpose register regset store 576 function. */ 577 578 static void 579 ppc_store_tm_sprregset (struct regcache *regcache, const void *buf) 580 { 581 int i, base; 582 const char *regset = (const char *) buf; 583 584 base = find_regno (regcache->tdesc, "tfhar"); 585 for (i = 0; i < 3; i++) 586 supply_register (regcache, base + i, ®set[i * 8]); 587 } 588 589 /* For the same reasons as the EBB regset, none of the HTM 590 checkpointed regsets have a fill function. These registers are 591 only available if the inferior is in a transaction. */ 592 593 /* Hardware Transactional Memory checkpointed general-purpose regset 594 store function. */ 595 596 static void 597 ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf) 598 { 599 int i, base, size, endian_offset; 600 const char *regset = (const char *) buf; 601 602 base = find_regno (regcache->tdesc, "cr0"); 603 size = register_size (regcache->tdesc, base); 604 605 gdb_assert (size == 4 || size == 8); 606 607 for (i = 0; i < 32; i++) 608 supply_register (regcache, base + i, ®set[i * size]); 609 610 endian_offset = 0; 611 612 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN)) 613 endian_offset = 4; 614 615 supply_register_by_name (regcache, "ccr", 616 ®set[PT_CCR * size + endian_offset]); 617 618 supply_register_by_name (regcache, "cxer", 619 ®set[PT_XER * size + endian_offset]); 620 621 supply_register_by_name (regcache, "clr", ®set[PT_LNK * size]); 622 supply_register_by_name (regcache, "cctr", ®set[PT_CTR * size]); 623 } 624 625 /* Hardware Transactional Memory checkpointed floating-point regset 626 store function. */ 627 628 static void 629 ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf) 630 { 631 int i, base; 632 const char *regset = (const char *) buf; 633 634 base = find_regno (regcache->tdesc, "cf0"); 635 636 for (i = 0; i < 32; i++) 637 supply_register (regcache, base + i, ®set[i * 8]); 638 639 supply_register_by_name (regcache, "cfpscr", ®set[32 * 8]); 640 } 641 642 /* Hardware Transactional Memory checkpointed vector regset store 643 function. */ 644 645 static void 646 ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf) 647 { 648 int i, base; 649 const char *regset = (const char *) buf; 650 int vscr_offset = 0; 651 652 base = find_regno (regcache->tdesc, "cvr0"); 653 654 for (i = 0; i < 32; i++) 655 supply_register (regcache, base + i, ®set[i * 16]); 656 657 if (__BYTE_ORDER == __BIG_ENDIAN) 658 vscr_offset = 12; 659 660 supply_register_by_name (regcache, "cvscr", 661 ®set[32 * 16 + vscr_offset]); 662 663 supply_register_by_name (regcache, "cvrsave", ®set[33 * 16]); 664 } 665 666 /* Hardware Transactional Memory checkpointed vector-scalar regset 667 store function. */ 668 669 static void 670 ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf) 671 { 672 int i, base; 673 const char *regset = (const char *) buf; 674 675 base = find_regno (regcache->tdesc, "cvs0h"); 676 for (i = 0; i < 32; i++) 677 supply_register (regcache, base + i, ®set[i * 8]); 678 } 679 680 /* Hardware Transactional Memory checkpointed Program Priority 681 Register regset store function. */ 682 683 static void 684 ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf) 685 { 686 const char *cppr = (const char *) buf; 687 688 supply_register_by_name (regcache, "cppr", cppr); 689 } 690 691 /* Hardware Transactional Memory checkpointed Data Stream Control 692 Register regset store function. */ 693 694 static void 695 ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf) 696 { 697 const char *cdscr = (const char *) buf; 698 699 supply_register_by_name (regcache, "cdscr", cdscr); 700 } 701 702 /* Hardware Transactional Memory checkpointed Target Address Register 703 regset store function. */ 704 705 static void 706 ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf) 707 { 708 const char *ctar = (const char *) buf; 709 710 supply_register_by_name (regcache, "ctar", ctar); 711 } 712 713 static void 714 ppc_fill_vsxregset (struct regcache *regcache, void *buf) 715 { 716 int i, base; 717 char *regset = (char *) buf; 718 719 base = find_regno (regcache->tdesc, "vs0h"); 720 for (i = 0; i < 32; i++) 721 collect_register (regcache, base + i, ®set[i * 8]); 722 } 723 724 static void 725 ppc_store_vsxregset (struct regcache *regcache, const void *buf) 726 { 727 int i, base; 728 const char *regset = (const char *) buf; 729 730 base = find_regno (regcache->tdesc, "vs0h"); 731 for (i = 0; i < 32; i++) 732 supply_register (regcache, base + i, ®set[i * 8]); 733 } 734 735 static void 736 ppc_fill_vrregset (struct regcache *regcache, void *buf) 737 { 738 int i, base; 739 char *regset = (char *) buf; 740 int vscr_offset = 0; 741 742 base = find_regno (regcache->tdesc, "vr0"); 743 for (i = 0; i < 32; i++) 744 collect_register (regcache, base + i, ®set[i * 16]); 745 746 if (__BYTE_ORDER == __BIG_ENDIAN) 747 vscr_offset = 12; 748 749 collect_register_by_name (regcache, "vscr", 750 ®set[32 * 16 + vscr_offset]); 751 752 collect_register_by_name (regcache, "vrsave", ®set[33 * 16]); 753 } 754 755 static void 756 ppc_store_vrregset (struct regcache *regcache, const void *buf) 757 { 758 int i, base; 759 const char *regset = (const char *) buf; 760 int vscr_offset = 0; 761 762 base = find_regno (regcache->tdesc, "vr0"); 763 for (i = 0; i < 32; i++) 764 supply_register (regcache, base + i, ®set[i * 16]); 765 766 if (__BYTE_ORDER == __BIG_ENDIAN) 767 vscr_offset = 12; 768 769 supply_register_by_name (regcache, "vscr", 770 ®set[32 * 16 + vscr_offset]); 771 supply_register_by_name (regcache, "vrsave", ®set[33 * 16]); 772 } 773 774 struct gdb_evrregset_t 775 { 776 unsigned long evr[32]; 777 unsigned long long acc; 778 unsigned long spefscr; 779 }; 780 781 static void 782 ppc_fill_evrregset (struct regcache *regcache, void *buf) 783 { 784 int i, ev0; 785 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf; 786 787 ev0 = find_regno (regcache->tdesc, "ev0h"); 788 for (i = 0; i < 32; i++) 789 collect_register (regcache, ev0 + i, ®set->evr[i]); 790 791 collect_register_by_name (regcache, "acc", ®set->acc); 792 collect_register_by_name (regcache, "spefscr", ®set->spefscr); 793 } 794 795 static void 796 ppc_store_evrregset (struct regcache *regcache, const void *buf) 797 { 798 int i, ev0; 799 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf; 800 801 ev0 = find_regno (regcache->tdesc, "ev0h"); 802 for (i = 0; i < 32; i++) 803 supply_register (regcache, ev0 + i, ®set->evr[i]); 804 805 supply_register_by_name (regcache, "acc", ®set->acc); 806 supply_register_by_name (regcache, "spefscr", ®set->spefscr); 807 } 808 809 static struct regset_info ppc_regsets[] = { 810 /* List the extra register sets before GENERAL_REGS. That way we will 811 fetch them every time, but still fall back to PTRACE_PEEKUSER for the 812 general registers. Some kernels support these, but not the newer 813 PPC_PTRACE_GETREGS. */ 814 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS, 815 NULL, ppc_store_tm_ctarregset }, 816 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS, 817 NULL, ppc_store_tm_cdscrregset }, 818 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS, 819 NULL, ppc_store_tm_cpprregset }, 820 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS, 821 NULL, ppc_store_tm_cvsxregset }, 822 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS, 823 NULL, ppc_store_tm_cvrregset }, 824 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS, 825 NULL, ppc_store_tm_cfprregset }, 826 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS, 827 NULL, ppc_store_tm_cgprregset }, 828 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS, 829 ppc_fill_tm_sprregset, ppc_store_tm_sprregset }, 830 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS, 831 NULL, ppc_store_ebbregset }, 832 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS, 833 ppc_fill_pmuregset, ppc_store_pmuregset }, 834 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS, 835 ppc_fill_tarregset, ppc_store_tarregset }, 836 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS, 837 ppc_fill_pprregset, ppc_store_pprregset }, 838 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS, 839 ppc_fill_dscrregset, ppc_store_dscrregset }, 840 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS, 841 ppc_fill_vsxregset, ppc_store_vsxregset }, 842 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS, 843 ppc_fill_vrregset, ppc_store_vrregset }, 844 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS, 845 ppc_fill_evrregset, ppc_store_evrregset }, 846 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL }, 847 NULL_REGSET 848 }; 849 850 static struct usrregs_info ppc_usrregs_info = 851 { 852 ppc_num_regs, 853 ppc_regmap, 854 }; 855 856 static struct regsets_info ppc_regsets_info = 857 { 858 ppc_regsets, /* regsets */ 859 0, /* num_regsets */ 860 NULL, /* disabled_regsets */ 861 }; 862 863 static struct regs_info myregs_info = 864 { 865 NULL, /* regset_bitmap */ 866 &ppc_usrregs_info, 867 &ppc_regsets_info 868 }; 869 870 const regs_info * 871 ppc_target::get_regs_info () 872 { 873 return &myregs_info; 874 } 875 876 void 877 ppc_target::low_arch_setup () 878 { 879 const struct target_desc *tdesc; 880 struct regset_info *regset; 881 struct ppc_linux_features features = ppc_linux_no_features; 882 883 int tid = lwpid_of (current_thread); 884 885 features.wordsize = ppc_linux_target_wordsize (tid); 886 887 if (features.wordsize == 4) 888 tdesc = tdesc_powerpc_32l; 889 else 890 tdesc = tdesc_powerpc_64l; 891 892 current_process ()->tdesc = tdesc; 893 894 /* The value of current_process ()->tdesc needs to be set for this 895 call. */ 896 ppc_hwcap = linux_get_hwcap (current_thread->id.pid (), features.wordsize); 897 ppc_hwcap2 = linux_get_hwcap2 (current_thread->id.pid (), features.wordsize); 898 899 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap); 900 901 if (ppc_hwcap & PPC_FEATURE_HAS_VSX) 902 features.vsx = true; 903 904 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC) 905 features.altivec = true; 906 907 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR) 908 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET) 909 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)) 910 { 911 features.ppr_dscr = true; 912 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07) 913 && (ppc_hwcap2 & PPC_FEATURE2_TAR) 914 && (ppc_hwcap2 & PPC_FEATURE2_EBB) 915 && ppc_check_regset (tid, NT_PPC_TAR, 916 PPC_LINUX_SIZEOF_TARREGSET) 917 && ppc_check_regset (tid, NT_PPC_EBB, 918 PPC_LINUX_SIZEOF_EBBREGSET) 919 && ppc_check_regset (tid, NT_PPC_PMU, 920 PPC_LINUX_SIZEOF_PMUREGSET)) 921 { 922 features.isa207 = true; 923 if ((ppc_hwcap2 & PPC_FEATURE2_HTM) 924 && ppc_check_regset (tid, NT_PPC_TM_SPR, 925 PPC_LINUX_SIZEOF_TM_SPRREGSET)) 926 features.htm = true; 927 } 928 } 929 930 tdesc = ppc_linux_match_description (features); 931 932 /* On 32-bit machines, check for SPE registers. 933 Set the low target's regmap field as appropriately. */ 934 #ifndef __powerpc64__ 935 if (ppc_hwcap & PPC_FEATURE_HAS_SPE) 936 tdesc = tdesc_powerpc_e500l; 937 938 if (!ppc_regmap_adjusted) 939 { 940 if (ppc_hwcap & PPC_FEATURE_HAS_SPE) 941 ppc_usrregs_info.regmap = ppc_regmap_e500; 942 943 /* If the FPSCR is 64-bit wide, we need to fetch the whole 944 64-bit slot and not just its second word. The PT_FPSCR 945 supplied in a 32-bit GDB compilation doesn't reflect 946 this. */ 947 if (register_size (tdesc, 70) == 8) 948 ppc_regmap[70] = (48 + 2*32) * sizeof (long); 949 950 ppc_regmap_adjusted = 1; 951 } 952 #endif 953 954 current_process ()->tdesc = tdesc; 955 956 for (regset = ppc_regsets; regset->size >= 0; regset++) 957 switch (regset->get_request) 958 { 959 case PTRACE_GETVRREGS: 960 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0; 961 break; 962 case PTRACE_GETVSXREGS: 963 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0; 964 break; 965 case PTRACE_GETEVRREGS: 966 if (ppc_hwcap & PPC_FEATURE_HAS_SPE) 967 regset->size = 32 * 4 + 8 + 4; 968 else 969 regset->size = 0; 970 break; 971 case PTRACE_GETREGSET: 972 switch (regset->nt_type) 973 { 974 case NT_PPC_PPR: 975 regset->size = (features.ppr_dscr ? 976 PPC_LINUX_SIZEOF_PPRREGSET : 0); 977 break; 978 case NT_PPC_DSCR: 979 regset->size = (features.ppr_dscr ? 980 PPC_LINUX_SIZEOF_DSCRREGSET : 0); 981 break; 982 case NT_PPC_TAR: 983 regset->size = (features.isa207 ? 984 PPC_LINUX_SIZEOF_TARREGSET : 0); 985 break; 986 case NT_PPC_EBB: 987 regset->size = (features.isa207 ? 988 PPC_LINUX_SIZEOF_EBBREGSET : 0); 989 break; 990 case NT_PPC_PMU: 991 regset->size = (features.isa207 ? 992 PPC_LINUX_SIZEOF_PMUREGSET : 0); 993 break; 994 case NT_PPC_TM_SPR: 995 regset->size = (features.htm ? 996 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0); 997 break; 998 case NT_PPC_TM_CGPR: 999 if (features.wordsize == 4) 1000 regset->size = (features.htm ? 1001 PPC32_LINUX_SIZEOF_CGPRREGSET : 0); 1002 else 1003 regset->size = (features.htm ? 1004 PPC64_LINUX_SIZEOF_CGPRREGSET : 0); 1005 break; 1006 case NT_PPC_TM_CFPR: 1007 regset->size = (features.htm ? 1008 PPC_LINUX_SIZEOF_CFPRREGSET : 0); 1009 break; 1010 case NT_PPC_TM_CVMX: 1011 regset->size = (features.htm ? 1012 PPC_LINUX_SIZEOF_CVMXREGSET : 0); 1013 break; 1014 case NT_PPC_TM_CVSX: 1015 regset->size = (features.htm ? 1016 PPC_LINUX_SIZEOF_CVSXREGSET : 0); 1017 break; 1018 case NT_PPC_TM_CPPR: 1019 regset->size = (features.htm ? 1020 PPC_LINUX_SIZEOF_CPPRREGSET : 0); 1021 break; 1022 case NT_PPC_TM_CDSCR: 1023 regset->size = (features.htm ? 1024 PPC_LINUX_SIZEOF_CDSCRREGSET : 0); 1025 break; 1026 case NT_PPC_TM_CTAR: 1027 regset->size = (features.htm ? 1028 PPC_LINUX_SIZEOF_CTARREGSET : 0); 1029 break; 1030 default: 1031 break; 1032 } 1033 break; 1034 default: 1035 break; 1036 } 1037 } 1038 1039 /* Implementation of target ops method "supports_tracepoints". */ 1040 1041 bool 1042 ppc_target::supports_tracepoints () 1043 { 1044 return true; 1045 } 1046 1047 /* Get the thread area address. This is used to recognize which 1048 thread is which when tracing with the in-process agent library. We 1049 don't read anything from the address, and treat it as opaque; it's 1050 the address itself that we assume is unique per-thread. */ 1051 1052 int 1053 ppc_target::low_get_thread_area (int lwpid, CORE_ADDR *addr) 1054 { 1055 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid)); 1056 struct thread_info *thr = get_lwp_thread (lwp); 1057 struct regcache *regcache = get_thread_regcache (thr, 1); 1058 ULONGEST tp = 0; 1059 1060 #ifdef __powerpc64__ 1061 if (register_size (regcache->tdesc, 0) == 8) 1062 collect_register_by_name (regcache, "r13", &tp); 1063 else 1064 #endif 1065 collect_register_by_name (regcache, "r2", &tp); 1066 1067 *addr = tp; 1068 1069 return 0; 1070 } 1071 1072 #ifdef __powerpc64__ 1073 1074 /* Older glibc doesn't provide this. */ 1075 1076 #ifndef EF_PPC64_ABI 1077 #define EF_PPC64_ABI 3 1078 #endif 1079 1080 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit 1081 inferiors. */ 1082 1083 static int 1084 is_elfv2_inferior (void) 1085 { 1086 /* To be used as fallback if we're unable to determine the right result - 1087 assume inferior uses the same ABI as gdbserver. */ 1088 #if _CALL_ELF == 2 1089 const int def_res = 1; 1090 #else 1091 const int def_res = 0; 1092 #endif 1093 CORE_ADDR phdr; 1094 Elf64_Ehdr ehdr; 1095 1096 const struct target_desc *tdesc = current_process ()->tdesc; 1097 int wordsize = register_size (tdesc, 0); 1098 1099 if (!linux_get_auxv (current_thread->id.pid (), wordsize, AT_PHDR, &phdr)) 1100 return def_res; 1101 1102 /* Assume ELF header is at the beginning of the page where program headers 1103 are located. If it doesn't look like one, bail. */ 1104 1105 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr); 1106 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG)) 1107 return def_res; 1108 1109 return (ehdr.e_flags & EF_PPC64_ABI) == 2; 1110 } 1111 1112 #endif 1113 1114 /* Generate a ds-form instruction in BUF and return the number of bytes written 1115 1116 0 6 11 16 30 32 1117 | OPCD | RST | RA | DS |XO| */ 1118 1119 __attribute__((unused)) /* Maybe unused due to conditional compilation. */ 1120 static int 1121 gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo) 1122 { 1123 uint32_t insn; 1124 1125 gdb_assert ((opcd & ~0x3f) == 0); 1126 gdb_assert ((rst & ~0x1f) == 0); 1127 gdb_assert ((ra & ~0x1f) == 0); 1128 gdb_assert ((xo & ~0x3) == 0); 1129 1130 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3); 1131 *buf = (opcd << 26) | insn; 1132 return 1; 1133 } 1134 1135 /* Followings are frequently used ds-form instructions. */ 1136 1137 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0) 1138 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1) 1139 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0) 1140 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1) 1141 1142 /* Generate a d-form instruction in BUF. 1143 1144 0 6 11 16 32 1145 | OPCD | RST | RA | D | */ 1146 1147 static int 1148 gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si) 1149 { 1150 uint32_t insn; 1151 1152 gdb_assert ((opcd & ~0x3f) == 0); 1153 gdb_assert ((rst & ~0x1f) == 0); 1154 gdb_assert ((ra & ~0x1f) == 0); 1155 1156 insn = (rst << 21) | (ra << 16) | (si & 0xffff); 1157 *buf = (opcd << 26) | insn; 1158 return 1; 1159 } 1160 1161 /* Followings are frequently used d-form instructions. */ 1162 1163 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si) 1164 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si) 1165 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si) 1166 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si) 1167 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si) 1168 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si) 1169 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si) 1170 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si) 1171 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si) 1172 1173 /* Generate a xfx-form instruction in BUF and return the number of bytes 1174 written. 1175 1176 0 6 11 21 31 32 1177 | OPCD | RST | RI | XO |/| */ 1178 1179 static int 1180 gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo) 1181 { 1182 uint32_t insn; 1183 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f); 1184 1185 gdb_assert ((opcd & ~0x3f) == 0); 1186 gdb_assert ((rst & ~0x1f) == 0); 1187 gdb_assert ((xo & ~0x3ff) == 0); 1188 1189 insn = (rst << 21) | (n << 11) | (xo << 1); 1190 *buf = (opcd << 26) | insn; 1191 return 1; 1192 } 1193 1194 /* Followings are frequently used xfx-form instructions. */ 1195 1196 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339) 1197 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467) 1198 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19) 1199 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144) 1200 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \ 1201 E & 0xf, 598) 1202 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0) 1203 1204 1205 /* Generate a x-form instruction in BUF and return the number of bytes written. 1206 1207 0 6 11 16 21 31 32 1208 | OPCD | RST | RA | RB | XO |RC| */ 1209 1210 static int 1211 gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc) 1212 { 1213 uint32_t insn; 1214 1215 gdb_assert ((opcd & ~0x3f) == 0); 1216 gdb_assert ((rst & ~0x1f) == 0); 1217 gdb_assert ((ra & ~0x1f) == 0); 1218 gdb_assert ((rb & ~0x1f) == 0); 1219 gdb_assert ((xo & ~0x3ff) == 0); 1220 gdb_assert ((rc & ~1) == 0); 1221 1222 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc; 1223 *buf = (opcd << 26) | insn; 1224 return 1; 1225 } 1226 1227 /* Followings are frequently used x-form instructions. */ 1228 1229 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0) 1230 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs) 1231 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0) 1232 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1) 1233 /* Assume bf = cr7. */ 1234 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0) 1235 1236 1237 /* Generate a md-form instruction in BUF and return the number of bytes written. 1238 1239 0 6 11 16 21 27 30 31 32 1240 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */ 1241 1242 static int 1243 gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb, 1244 int xo, int rc) 1245 { 1246 uint32_t insn; 1247 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1); 1248 unsigned int sh0_4 = sh & 0x1f; 1249 unsigned int sh5 = (sh >> 5) & 1; 1250 1251 gdb_assert ((opcd & ~0x3f) == 0); 1252 gdb_assert ((rs & ~0x1f) == 0); 1253 gdb_assert ((ra & ~0x1f) == 0); 1254 gdb_assert ((sh & ~0x3f) == 0); 1255 gdb_assert ((mb & ~0x3f) == 0); 1256 gdb_assert ((xo & ~0x7) == 0); 1257 gdb_assert ((rc & ~0x1) == 0); 1258 1259 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5) 1260 | (sh5 << 1) | (xo << 2) | (rc & 1); 1261 *buf = (opcd << 26) | insn; 1262 return 1; 1263 } 1264 1265 /* The following are frequently used md-form instructions. */ 1266 1267 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \ 1268 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0) 1269 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \ 1270 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0) 1271 1272 /* Generate a i-form instruction in BUF and return the number of bytes written. 1273 1274 0 6 30 31 32 1275 | OPCD | LI |AA|LK| */ 1276 1277 static int 1278 gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk) 1279 { 1280 uint32_t insn; 1281 1282 gdb_assert ((opcd & ~0x3f) == 0); 1283 1284 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1); 1285 *buf = (opcd << 26) | insn; 1286 return 1; 1287 } 1288 1289 /* The following are frequently used i-form instructions. */ 1290 1291 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0) 1292 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1) 1293 1294 /* Generate a b-form instruction in BUF and return the number of bytes written. 1295 1296 0 6 11 16 30 31 32 1297 | OPCD | BO | BI | BD |AA|LK| */ 1298 1299 static int 1300 gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd, 1301 int aa, int lk) 1302 { 1303 uint32_t insn; 1304 1305 gdb_assert ((opcd & ~0x3f) == 0); 1306 gdb_assert ((bo & ~0x1f) == 0); 1307 gdb_assert ((bi & ~0x1f) == 0); 1308 1309 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1); 1310 *buf = (opcd << 26) | insn; 1311 return 1; 1312 } 1313 1314 /* The following are frequently used b-form instructions. */ 1315 /* Assume bi = cr7. */ 1316 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0) 1317 1318 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32 1319 respectively. They are primary used for save/restore GPRs in jump-pad, 1320 not used for bytecode compiling. */ 1321 1322 #ifdef __powerpc64__ 1323 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \ 1324 GEN_LD (buf, rt, ra, si) : \ 1325 GEN_LWZ (buf, rt, ra, si)) 1326 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \ 1327 GEN_STD (buf, rt, ra, si) : \ 1328 GEN_STW (buf, rt, ra, si)) 1329 #else 1330 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si) 1331 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si) 1332 #endif 1333 1334 /* Generate a sequence of instructions to load IMM in the register REG. 1335 Write the instructions in BUF and return the number of bytes written. */ 1336 1337 static int 1338 gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64) 1339 { 1340 uint32_t *p = buf; 1341 1342 if ((imm + 32768) < 65536) 1343 { 1344 /* li reg, imm[15:0] */ 1345 p += GEN_LI (p, reg, imm); 1346 } 1347 else if ((imm >> 32) == 0) 1348 { 1349 /* lis reg, imm[31:16] 1350 ori reg, reg, imm[15:0] 1351 rldicl reg, reg, 0, 32 */ 1352 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff); 1353 if ((imm & 0xffff) != 0) 1354 p += GEN_ORI (p, reg, reg, imm & 0xffff); 1355 /* Clear upper 32-bit if sign-bit is set. */ 1356 if (imm & (1u << 31) && is_64) 1357 p += GEN_RLDICL (p, reg, reg, 0, 32); 1358 } 1359 else 1360 { 1361 gdb_assert (is_64); 1362 /* lis reg, <imm[63:48]> 1363 ori reg, reg, <imm[48:32]> 1364 rldicr reg, reg, 32, 31 1365 oris reg, reg, <imm[31:16]> 1366 ori reg, reg, <imm[15:0]> */ 1367 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff)); 1368 if (((imm >> 32) & 0xffff) != 0) 1369 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff)); 1370 p += GEN_RLDICR (p, reg, reg, 32, 31); 1371 if (((imm >> 16) & 0xffff) != 0) 1372 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff)); 1373 if ((imm & 0xffff) != 0) 1374 p += GEN_ORI (p, reg, reg, (imm & 0xffff)); 1375 } 1376 1377 return p - buf; 1378 } 1379 1380 /* Generate a sequence for atomically exchange at location LOCK. 1381 This code sequence clobbers r6, r7, r8. LOCK is the location for 1382 the atomic-xchg, OLD_VALUE is expected old value stored in the 1383 location, and R_NEW is a register for the new value. */ 1384 1385 static int 1386 gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new, 1387 int is_64) 1388 { 1389 const int r_lock = 6; 1390 const int r_old = 7; 1391 const int r_tmp = 8; 1392 uint32_t *p = buf; 1393 1394 /* 1395 1: lwarx TMP, 0, LOCK 1396 cmpwi TMP, OLD 1397 bne 1b 1398 stwcx. NEW, 0, LOCK 1399 bne 1b */ 1400 1401 p += gen_limm (p, r_lock, lock, is_64); 1402 p += gen_limm (p, r_old, old_value, is_64); 1403 1404 p += GEN_LWARX (p, r_tmp, 0, r_lock); 1405 p += GEN_CMPW (p, r_tmp, r_old); 1406 p += GEN_BNE (p, -8); 1407 p += GEN_STWCX (p, r_new, 0, r_lock); 1408 p += GEN_BNE (p, -16); 1409 1410 return p - buf; 1411 } 1412 1413 /* Generate a sequence of instructions for calling a function 1414 at address of FN. Return the number of bytes are written in BUF. */ 1415 1416 static int 1417 gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd) 1418 { 1419 uint32_t *p = buf; 1420 1421 /* Must be called by r12 for caller to calculate TOC address. */ 1422 p += gen_limm (p, 12, fn, is_64); 1423 if (is_opd) 1424 { 1425 p += GEN_LOAD (p, 11, 12, 16, is_64); 1426 p += GEN_LOAD (p, 2, 12, 8, is_64); 1427 p += GEN_LOAD (p, 12, 12, 0, is_64); 1428 } 1429 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */ 1430 *p++ = 0x4e800421; /* bctrl */ 1431 1432 return p - buf; 1433 } 1434 1435 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size 1436 of instruction. This function is used to adjust pc-relative instructions 1437 when copying. */ 1438 1439 static void 1440 ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc) 1441 { 1442 uint32_t insn, op6; 1443 long rel, newrel; 1444 1445 read_inferior_memory (oldloc, (unsigned char *) &insn, 4); 1446 op6 = PPC_OP6 (insn); 1447 1448 if (op6 == 18 && (insn & 2) == 0) 1449 { 1450 /* branch && AA = 0 */ 1451 rel = PPC_LI (insn); 1452 newrel = (oldloc - *to) + rel; 1453 1454 /* Out of range. Cannot relocate instruction. */ 1455 if (newrel >= (1 << 25) || newrel < -(1 << 25)) 1456 return; 1457 1458 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc); 1459 } 1460 else if (op6 == 16 && (insn & 2) == 0) 1461 { 1462 /* conditional branch && AA = 0 */ 1463 1464 /* If the new relocation is too big for even a 26-bit unconditional 1465 branch, there is nothing we can do. Just abort. 1466 1467 Otherwise, if it can be fit in 16-bit conditional branch, just 1468 copy the instruction and relocate the address. 1469 1470 If the it's big for conditional-branch (16-bit), try to invert the 1471 condition and jump with 26-bit branch. For example, 1472 1473 beq .Lgoto 1474 INSN1 1475 1476 => 1477 1478 bne 1f (+8) 1479 b .Lgoto 1480 1:INSN1 1481 1482 After this transform, we are actually jump from *TO+4 instead of *TO, 1483 so check the relocation again because it will be 1-insn farther then 1484 before if *TO is after OLDLOC. 1485 1486 1487 For BDNZT (or so) is transformed from 1488 1489 bdnzt eq, .Lgoto 1490 INSN1 1491 1492 => 1493 1494 bdz 1f (+12) 1495 bf eq, 1f (+8) 1496 b .Lgoto 1497 1:INSN1 1498 1499 See also "BO field encodings". */ 1500 1501 rel = PPC_BD (insn); 1502 newrel = (oldloc - *to) + rel; 1503 1504 if (newrel < (1 << 15) && newrel >= -(1 << 15)) 1505 insn = (insn & ~0xfffc) | (newrel & 0xfffc); 1506 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10) 1507 { 1508 newrel -= 4; 1509 1510 /* Out of range. Cannot relocate instruction. */ 1511 if (newrel >= (1 << 25) || newrel < -(1 << 25)) 1512 return; 1513 1514 if ((PPC_BO (insn) & 0x14) == 0x4) 1515 insn ^= (1 << 24); 1516 else if ((PPC_BO (insn) & 0x14) == 0x10) 1517 insn ^= (1 << 22); 1518 1519 /* Jump over the unconditional branch. */ 1520 insn = (insn & ~0xfffc) | 0x8; 1521 target_write_memory (*to, (unsigned char *) &insn, 4); 1522 *to += 4; 1523 1524 /* Build a unconditional branch and copy LK bit. */ 1525 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3); 1526 target_write_memory (*to, (unsigned char *) &insn, 4); 1527 *to += 4; 1528 1529 return; 1530 } 1531 else if ((PPC_BO (insn) & 0x14) == 0) 1532 { 1533 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12; 1534 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8; 1535 1536 newrel -= 8; 1537 1538 /* Out of range. Cannot relocate instruction. */ 1539 if (newrel >= (1 << 25) || newrel < -(1 << 25)) 1540 return; 1541 1542 /* Copy BI field. */ 1543 bf_insn |= (insn & 0x1f0000); 1544 1545 /* Invert condition. */ 1546 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22); 1547 bf_insn |= (insn ^ (1 << 24)) & (1 << 24); 1548 1549 target_write_memory (*to, (unsigned char *) &bdnz_insn, 4); 1550 *to += 4; 1551 target_write_memory (*to, (unsigned char *) &bf_insn, 4); 1552 *to += 4; 1553 1554 /* Build a unconditional branch and copy LK bit. */ 1555 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3); 1556 target_write_memory (*to, (unsigned char *) &insn, 4); 1557 *to += 4; 1558 1559 return; 1560 } 1561 else /* (BO & 0x14) == 0x14, branch always. */ 1562 { 1563 /* Out of range. Cannot relocate instruction. */ 1564 if (newrel >= (1 << 25) || newrel < -(1 << 25)) 1565 return; 1566 1567 /* Build a unconditional branch and copy LK bit. */ 1568 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3); 1569 target_write_memory (*to, (unsigned char *) &insn, 4); 1570 *to += 4; 1571 1572 return; 1573 } 1574 } 1575 1576 target_write_memory (*to, (unsigned char *) &insn, 4); 1577 *to += 4; 1578 } 1579 1580 bool 1581 ppc_target::supports_fast_tracepoints () 1582 { 1583 return true; 1584 } 1585 1586 /* Implement install_fast_tracepoint_jump_pad of target_ops. 1587 See target.h for details. */ 1588 1589 int 1590 ppc_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, 1591 CORE_ADDR tpaddr, 1592 CORE_ADDR collector, 1593 CORE_ADDR lockaddr, 1594 ULONGEST orig_size, 1595 CORE_ADDR *jump_entry, 1596 CORE_ADDR *trampoline, 1597 ULONGEST *trampoline_size, 1598 unsigned char *jjump_pad_insn, 1599 ULONGEST *jjump_pad_insn_size, 1600 CORE_ADDR *adjusted_insn_addr, 1601 CORE_ADDR *adjusted_insn_addr_end, 1602 char *err) 1603 { 1604 uint32_t buf[256]; 1605 uint32_t *p = buf; 1606 int j, offset; 1607 CORE_ADDR buildaddr = *jump_entry; 1608 const CORE_ADDR entryaddr = *jump_entry; 1609 int rsz, min_frame, frame_size, tp_reg; 1610 #ifdef __powerpc64__ 1611 struct regcache *regcache = get_thread_regcache (current_thread, 0); 1612 int is_64 = register_size (regcache->tdesc, 0) == 8; 1613 int is_opd = is_64 && !is_elfv2_inferior (); 1614 #else 1615 int is_64 = 0, is_opd = 0; 1616 #endif 1617 1618 #ifdef __powerpc64__ 1619 if (is_64) 1620 { 1621 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */ 1622 rsz = 8; 1623 min_frame = 112; 1624 frame_size = (40 * rsz) + min_frame; 1625 tp_reg = 13; 1626 } 1627 else 1628 { 1629 #endif 1630 rsz = 4; 1631 min_frame = 16; 1632 frame_size = (40 * rsz) + min_frame; 1633 tp_reg = 2; 1634 #ifdef __powerpc64__ 1635 } 1636 #endif 1637 1638 /* Stack frame layout for this jump pad, 1639 1640 High thread_area (r13/r2) | 1641 tpoint - collecting_t obj 1642 PC/<tpaddr> | +36 1643 CTR | +35 1644 LR | +34 1645 XER | +33 1646 CR | +32 1647 R31 | 1648 R29 | 1649 ... | 1650 R1 | +1 1651 R0 - collected registers 1652 ... | 1653 ... | 1654 Low Back-chain - 1655 1656 1657 The code flow of this jump pad, 1658 1659 1. Adjust SP 1660 2. Save GPR and SPR 1661 3. Prepare argument 1662 4. Call gdb_collector 1663 5. Restore GPR and SPR 1664 6. Restore SP 1665 7. Build a jump for back to the program 1666 8. Copy/relocate original instruction 1667 9. Build a jump for replacing original instruction. */ 1668 1669 /* Adjust stack pointer. */ 1670 if (is_64) 1671 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */ 1672 else 1673 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */ 1674 1675 /* Store GPRs. Save R1 later, because it had just been modified, but 1676 we want the original value. */ 1677 for (j = 2; j < 32; j++) 1678 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64); 1679 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64); 1680 /* Set r0 to the original value of r1 before adjusting stack frame, 1681 and then save it. */ 1682 p += GEN_ADDI (p, 0, 1, frame_size); 1683 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64); 1684 1685 /* Save CR, XER, LR, and CTR. */ 1686 p += GEN_MFCR (p, 3); /* mfcr r3 */ 1687 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */ 1688 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */ 1689 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */ 1690 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */ 1691 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */ 1692 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */ 1693 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */ 1694 1695 /* Save PC<tpaddr> */ 1696 p += gen_limm (p, 3, tpaddr, is_64); 1697 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64); 1698 1699 1700 /* Setup arguments to collector. */ 1701 /* Set r4 to collected registers. */ 1702 p += GEN_ADDI (p, 4, 1, min_frame); 1703 /* Set r3 to TPOINT. */ 1704 p += gen_limm (p, 3, tpoint, is_64); 1705 1706 /* Prepare collecting_t object for lock. */ 1707 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64); 1708 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64); 1709 /* Set R5 to collecting object. */ 1710 p += GEN_ADDI (p, 5, 1, 37 * rsz); 1711 1712 p += GEN_LWSYNC (p); 1713 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64); 1714 p += GEN_LWSYNC (p); 1715 1716 /* Call to collector. */ 1717 p += gen_call (p, collector, is_64, is_opd); 1718 1719 /* Simply write 0 to release the lock. */ 1720 p += gen_limm (p, 3, lockaddr, is_64); 1721 p += gen_limm (p, 4, 0, is_64); 1722 p += GEN_LWSYNC (p); 1723 p += GEN_STORE (p, 4, 3, 0, is_64); 1724 1725 /* Restore stack and registers. */ 1726 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */ 1727 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */ 1728 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */ 1729 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */ 1730 p += GEN_MTCR (p, 3); /* mtcr r3 */ 1731 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */ 1732 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */ 1733 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */ 1734 1735 /* Restore GPRs. */ 1736 for (j = 2; j < 32; j++) 1737 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64); 1738 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64); 1739 /* Restore SP. */ 1740 p += GEN_ADDI (p, 1, 1, frame_size); 1741 1742 /* Flush instructions to inferior memory. */ 1743 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4); 1744 1745 /* Now, insert the original instruction to execute in the jump pad. */ 1746 *adjusted_insn_addr = buildaddr + (p - buf) * 4; 1747 *adjusted_insn_addr_end = *adjusted_insn_addr; 1748 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr); 1749 1750 /* Verify the relocation size. If should be 4 for normal copy, 1751 8 or 12 for some conditional branch. */ 1752 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0) 1753 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12)) 1754 { 1755 sprintf (err, "E.Unexpected instruction length = %d" 1756 "when relocate instruction.", 1757 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr)); 1758 return 1; 1759 } 1760 1761 buildaddr = *adjusted_insn_addr_end; 1762 p = buf; 1763 /* Finally, write a jump back to the program. */ 1764 offset = (tpaddr + 4) - buildaddr; 1765 if (offset >= (1 << 25) || offset < -(1 << 25)) 1766 { 1767 sprintf (err, "E.Jump back from jump pad too far from tracepoint " 1768 "(offset 0x%x > 26-bit).", offset); 1769 return 1; 1770 } 1771 /* b <tpaddr+4> */ 1772 p += GEN_B (p, offset); 1773 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4); 1774 *jump_entry = buildaddr + (p - buf) * 4; 1775 1776 /* The jump pad is now built. Wire in a jump to our jump pad. This 1777 is always done last (by our caller actually), so that we can 1778 install fast tracepoints with threads running. This relies on 1779 the agent's atomic write support. */ 1780 offset = entryaddr - tpaddr; 1781 if (offset >= (1 << 25) || offset < -(1 << 25)) 1782 { 1783 sprintf (err, "E.Jump back from jump pad too far from tracepoint " 1784 "(offset 0x%x > 26-bit).", offset); 1785 return 1; 1786 } 1787 /* b <jentry> */ 1788 GEN_B ((uint32_t *) jjump_pad_insn, offset); 1789 *jjump_pad_insn_size = 4; 1790 1791 return 0; 1792 } 1793 1794 /* Returns the minimum instruction length for installing a tracepoint. */ 1795 1796 int 1797 ppc_target::get_min_fast_tracepoint_insn_len () 1798 { 1799 return 4; 1800 } 1801 1802 /* Emits a given buffer into the target at current_insn_ptr. Length 1803 is in units of 32-bit words. */ 1804 1805 static void 1806 emit_insns (uint32_t *buf, int n) 1807 { 1808 n = n * sizeof (uint32_t); 1809 target_write_memory (current_insn_ptr, (unsigned char *) buf, n); 1810 current_insn_ptr += n; 1811 } 1812 1813 #define __EMIT_ASM(NAME, INSNS) \ 1814 do \ 1815 { \ 1816 extern uint32_t start_bcax_ ## NAME []; \ 1817 extern uint32_t end_bcax_ ## NAME []; \ 1818 emit_insns (start_bcax_ ## NAME, \ 1819 end_bcax_ ## NAME - start_bcax_ ## NAME); \ 1820 __asm__ (".section .text.__ppcbcax\n\t" \ 1821 "start_bcax_" #NAME ":\n\t" \ 1822 INSNS "\n\t" \ 1823 "end_bcax_" #NAME ":\n\t" \ 1824 ".previous\n\t"); \ 1825 } while (0) 1826 1827 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS) 1828 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS) 1829 1830 /* 1831 1832 Bytecode execution stack frame - 32-bit 1833 1834 | LR save area (SP + 4) 1835 SP' -> +- Back chain (SP + 0) 1836 | Save r31 for access saved arguments 1837 | Save r30 for bytecode stack pointer 1838 | Save r4 for incoming argument *value 1839 | Save r3 for incoming argument regs 1840 r30 -> +- Bytecode execution stack 1841 | 1842 | 64-byte (8 doublewords) at initial. 1843 | Expand stack as needed. 1844 | 1845 +- 1846 | Some padding for minimum stack frame and 16-byte alignment. 1847 | 16 bytes. 1848 SP +- Back-chain (SP') 1849 1850 initial frame size 1851 = 16 + (4 * 4) + 64 1852 = 96 1853 1854 r30 is the stack-pointer for bytecode machine. 1855 It should point to next-empty, so we can use LDU for pop. 1856 r3 is used for cache of the high part of TOP value. 1857 It was the first argument, pointer to regs. 1858 r4 is used for cache of the low part of TOP value. 1859 It was the second argument, pointer to the result. 1860 We should set *result = TOP after leaving this function. 1861 1862 Note: 1863 * To restore stack at epilogue 1864 => sp = r31 1865 * To check stack is big enough for bytecode execution. 1866 => r30 - 8 > SP + 8 1867 * To return execution result. 1868 => 0(r4) = TOP 1869 1870 */ 1871 1872 /* Regardless of endian, register 3 is always high part, 4 is low part. 1873 These defines are used when the register pair is stored/loaded. 1874 Likewise, to simplify code, have a similar define for 5:6. */ 1875 1876 #if __BYTE_ORDER == __LITTLE_ENDIAN 1877 #define TOP_FIRST "4" 1878 #define TOP_SECOND "3" 1879 #define TMP_FIRST "6" 1880 #define TMP_SECOND "5" 1881 #else 1882 #define TOP_FIRST "3" 1883 #define TOP_SECOND "4" 1884 #define TMP_FIRST "5" 1885 #define TMP_SECOND "6" 1886 #endif 1887 1888 /* Emit prologue in inferior memory. See above comments. */ 1889 1890 static void 1891 ppc_emit_prologue (void) 1892 { 1893 EMIT_ASM (/* Save return address. */ 1894 "mflr 0 \n" 1895 "stw 0, 4(1) \n" 1896 /* Adjust SP. 96 is the initial frame size. */ 1897 "stwu 1, -96(1) \n" 1898 /* Save r30 and incoming arguments. */ 1899 "stw 31, 96-4(1) \n" 1900 "stw 30, 96-8(1) \n" 1901 "stw 4, 96-12(1) \n" 1902 "stw 3, 96-16(1) \n" 1903 /* Point r31 to original r1 for access arguments. */ 1904 "addi 31, 1, 96 \n" 1905 /* Set r30 to pointing stack-top. */ 1906 "addi 30, 1, 64 \n" 1907 /* Initial r3/TOP to 0. */ 1908 "li 3, 0 \n" 1909 "li 4, 0 \n"); 1910 } 1911 1912 /* Emit epilogue in inferior memory. See above comments. */ 1913 1914 static void 1915 ppc_emit_epilogue (void) 1916 { 1917 EMIT_ASM (/* *result = TOP */ 1918 "lwz 5, -12(31) \n" 1919 "stw " TOP_FIRST ", 0(5) \n" 1920 "stw " TOP_SECOND ", 4(5) \n" 1921 /* Restore registers. */ 1922 "lwz 31, -4(31) \n" 1923 "lwz 30, -8(31) \n" 1924 /* Restore SP. */ 1925 "lwz 1, 0(1) \n" 1926 /* Restore LR. */ 1927 "lwz 0, 4(1) \n" 1928 /* Return 0 for no-error. */ 1929 "li 3, 0 \n" 1930 "mtlr 0 \n" 1931 "blr \n"); 1932 } 1933 1934 /* TOP = stack[--sp] + TOP */ 1935 1936 static void 1937 ppc_emit_add (void) 1938 { 1939 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 1940 "lwz " TMP_SECOND ", 4(30)\n" 1941 "addc 4, 6, 4 \n" 1942 "adde 3, 5, 3 \n"); 1943 } 1944 1945 /* TOP = stack[--sp] - TOP */ 1946 1947 static void 1948 ppc_emit_sub (void) 1949 { 1950 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 1951 "lwz " TMP_SECOND ", 4(30) \n" 1952 "subfc 4, 4, 6 \n" 1953 "subfe 3, 3, 5 \n"); 1954 } 1955 1956 /* TOP = stack[--sp] * TOP */ 1957 1958 static void 1959 ppc_emit_mul (void) 1960 { 1961 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 1962 "lwz " TMP_SECOND ", 4(30) \n" 1963 "mulhwu 7, 6, 4 \n" 1964 "mullw 3, 6, 3 \n" 1965 "mullw 5, 4, 5 \n" 1966 "mullw 4, 6, 4 \n" 1967 "add 3, 5, 3 \n" 1968 "add 3, 7, 3 \n"); 1969 } 1970 1971 /* TOP = stack[--sp] << TOP */ 1972 1973 static void 1974 ppc_emit_lsh (void) 1975 { 1976 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 1977 "lwz " TMP_SECOND ", 4(30) \n" 1978 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */ 1979 "addi 7, 4, -32\n" /* r7 = TOP - 32 */ 1980 "slw 5, 5, 4\n" /* Shift high part left */ 1981 "slw 4, 6, 4\n" /* Shift low part left */ 1982 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */ 1983 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */ 1984 "or 3, 5, 3\n" 1985 "or 3, 7, 3\n"); /* Assemble high part */ 1986 } 1987 1988 /* Top = stack[--sp] >> TOP 1989 (Arithmetic shift right) */ 1990 1991 static void 1992 ppc_emit_rsh_signed (void) 1993 { 1994 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 1995 "lwz " TMP_SECOND ", 4(30) \n" 1996 "addi 7, 4, -32\n" /* r7 = TOP - 32 */ 1997 "sraw 3, 5, 4\n" /* Shift high part right */ 1998 "cmpwi 7, 1\n" 1999 "blt 0, 1f\n" /* If shift <= 32, goto 1: */ 2000 "sraw 4, 5, 7\n" /* Shift high to low */ 2001 "b 2f\n" 2002 "1:\n" 2003 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */ 2004 "srw 4, 6, 4\n" /* Shift low part right */ 2005 "slw 5, 5, 7\n" /* Shift high to low */ 2006 "or 4, 4, 5\n" /* Assemble low part */ 2007 "2:\n"); 2008 } 2009 2010 /* Top = stack[--sp] >> TOP 2011 (Logical shift right) */ 2012 2013 static void 2014 ppc_emit_rsh_unsigned (void) 2015 { 2016 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2017 "lwz " TMP_SECOND ", 4(30) \n" 2018 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */ 2019 "addi 7, 4, -32\n" /* r7 = TOP - 32 */ 2020 "srw 6, 6, 4\n" /* Shift low part right */ 2021 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */ 2022 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */ 2023 "or 6, 6, 3\n" 2024 "srw 3, 5, 4\n" /* Shift high part right */ 2025 "or 4, 6, 7\n"); /* Assemble low part */ 2026 } 2027 2028 /* Emit code for signed-extension specified by ARG. */ 2029 2030 static void 2031 ppc_emit_ext (int arg) 2032 { 2033 switch (arg) 2034 { 2035 case 8: 2036 EMIT_ASM ("extsb 4, 4\n" 2037 "srawi 3, 4, 31"); 2038 break; 2039 case 16: 2040 EMIT_ASM ("extsh 4, 4\n" 2041 "srawi 3, 4, 31"); 2042 break; 2043 case 32: 2044 EMIT_ASM ("srawi 3, 4, 31"); 2045 break; 2046 default: 2047 emit_error = 1; 2048 } 2049 } 2050 2051 /* Emit code for zero-extension specified by ARG. */ 2052 2053 static void 2054 ppc_emit_zero_ext (int arg) 2055 { 2056 switch (arg) 2057 { 2058 case 8: 2059 EMIT_ASM ("clrlwi 4,4,24\n" 2060 "li 3, 0\n"); 2061 break; 2062 case 16: 2063 EMIT_ASM ("clrlwi 4,4,16\n" 2064 "li 3, 0\n"); 2065 break; 2066 case 32: 2067 EMIT_ASM ("li 3, 0"); 2068 break; 2069 default: 2070 emit_error = 1; 2071 } 2072 } 2073 2074 /* TOP = !TOP 2075 i.e., TOP = (TOP == 0) ? 1 : 0; */ 2076 2077 static void 2078 ppc_emit_log_not (void) 2079 { 2080 EMIT_ASM ("or 4, 3, 4 \n" 2081 "cntlzw 4, 4 \n" 2082 "srwi 4, 4, 5 \n" 2083 "li 3, 0 \n"); 2084 } 2085 2086 /* TOP = stack[--sp] & TOP */ 2087 2088 static void 2089 ppc_emit_bit_and (void) 2090 { 2091 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2092 "lwz " TMP_SECOND ", 4(30) \n" 2093 "and 4, 6, 4 \n" 2094 "and 3, 5, 3 \n"); 2095 } 2096 2097 /* TOP = stack[--sp] | TOP */ 2098 2099 static void 2100 ppc_emit_bit_or (void) 2101 { 2102 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2103 "lwz " TMP_SECOND ", 4(30) \n" 2104 "or 4, 6, 4 \n" 2105 "or 3, 5, 3 \n"); 2106 } 2107 2108 /* TOP = stack[--sp] ^ TOP */ 2109 2110 static void 2111 ppc_emit_bit_xor (void) 2112 { 2113 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2114 "lwz " TMP_SECOND ", 4(30) \n" 2115 "xor 4, 6, 4 \n" 2116 "xor 3, 5, 3 \n"); 2117 } 2118 2119 /* TOP = ~TOP 2120 i.e., TOP = ~(TOP | TOP) */ 2121 2122 static void 2123 ppc_emit_bit_not (void) 2124 { 2125 EMIT_ASM ("nor 3, 3, 3 \n" 2126 "nor 4, 4, 4 \n"); 2127 } 2128 2129 /* TOP = stack[--sp] == TOP */ 2130 2131 static void 2132 ppc_emit_equal (void) 2133 { 2134 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2135 "lwz " TMP_SECOND ", 4(30) \n" 2136 "xor 4, 6, 4 \n" 2137 "xor 3, 5, 3 \n" 2138 "or 4, 3, 4 \n" 2139 "cntlzw 4, 4 \n" 2140 "srwi 4, 4, 5 \n" 2141 "li 3, 0 \n"); 2142 } 2143 2144 /* TOP = stack[--sp] < TOP 2145 (Signed comparison) */ 2146 2147 static void 2148 ppc_emit_less_signed (void) 2149 { 2150 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2151 "lwz " TMP_SECOND ", 4(30) \n" 2152 "cmplw 6, 6, 4 \n" 2153 "cmpw 7, 5, 3 \n" 2154 /* CR6 bit 0 = low less and high equal */ 2155 "crand 6*4+0, 6*4+0, 7*4+2\n" 2156 /* CR7 bit 0 = (low less and high equal) or high less */ 2157 "cror 7*4+0, 7*4+0, 6*4+0\n" 2158 "mfcr 4 \n" 2159 "rlwinm 4, 4, 29, 31, 31 \n" 2160 "li 3, 0 \n"); 2161 } 2162 2163 /* TOP = stack[--sp] < TOP 2164 (Unsigned comparison) */ 2165 2166 static void 2167 ppc_emit_less_unsigned (void) 2168 { 2169 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2170 "lwz " TMP_SECOND ", 4(30) \n" 2171 "cmplw 6, 6, 4 \n" 2172 "cmplw 7, 5, 3 \n" 2173 /* CR6 bit 0 = low less and high equal */ 2174 "crand 6*4+0, 6*4+0, 7*4+2\n" 2175 /* CR7 bit 0 = (low less and high equal) or high less */ 2176 "cror 7*4+0, 7*4+0, 6*4+0\n" 2177 "mfcr 4 \n" 2178 "rlwinm 4, 4, 29, 31, 31 \n" 2179 "li 3, 0 \n"); 2180 } 2181 2182 /* Access the memory address in TOP in size of SIZE. 2183 Zero-extend the read value. */ 2184 2185 static void 2186 ppc_emit_ref (int size) 2187 { 2188 switch (size) 2189 { 2190 case 1: 2191 EMIT_ASM ("lbz 4, 0(4)\n" 2192 "li 3, 0"); 2193 break; 2194 case 2: 2195 EMIT_ASM ("lhz 4, 0(4)\n" 2196 "li 3, 0"); 2197 break; 2198 case 4: 2199 EMIT_ASM ("lwz 4, 0(4)\n" 2200 "li 3, 0"); 2201 break; 2202 case 8: 2203 if (__BYTE_ORDER == __LITTLE_ENDIAN) 2204 EMIT_ASM ("lwz 3, 4(4)\n" 2205 "lwz 4, 0(4)"); 2206 else 2207 EMIT_ASM ("lwz 3, 0(4)\n" 2208 "lwz 4, 4(4)"); 2209 break; 2210 } 2211 } 2212 2213 /* TOP = NUM */ 2214 2215 static void 2216 ppc_emit_const (LONGEST num) 2217 { 2218 uint32_t buf[10]; 2219 uint32_t *p = buf; 2220 2221 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0); 2222 p += gen_limm (p, 4, num & 0xffffffff, 0); 2223 2224 emit_insns (buf, p - buf); 2225 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2226 } 2227 2228 /* Set TOP to the value of register REG by calling get_raw_reg function 2229 with two argument, collected buffer and register number. */ 2230 2231 static void 2232 ppc_emit_reg (int reg) 2233 { 2234 uint32_t buf[13]; 2235 uint32_t *p = buf; 2236 2237 /* fctx->regs is passed in r3 and then saved in -16(31). */ 2238 p += GEN_LWZ (p, 3, 31, -16); 2239 p += GEN_LI (p, 4, reg); /* li r4, reg */ 2240 p += gen_call (p, get_raw_reg_func_addr (), 0, 0); 2241 2242 emit_insns (buf, p - buf); 2243 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2244 2245 if (__BYTE_ORDER == __LITTLE_ENDIAN) 2246 { 2247 EMIT_ASM ("mr 5, 4\n" 2248 "mr 4, 3\n" 2249 "mr 3, 5\n"); 2250 } 2251 } 2252 2253 /* TOP = stack[--sp] */ 2254 2255 static void 2256 ppc_emit_pop (void) 2257 { 2258 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n" 2259 "lwz " TOP_SECOND ", 4(30) \n"); 2260 } 2261 2262 /* stack[sp++] = TOP 2263 2264 Because we may use up bytecode stack, expand 8 doublewords more 2265 if needed. */ 2266 2267 static void 2268 ppc_emit_stack_flush (void) 2269 { 2270 /* Make sure bytecode stack is big enough before push. 2271 Otherwise, expand 64-byte more. */ 2272 2273 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n" 2274 " stw " TOP_SECOND ", 4(30)\n" 2275 " addi 5, 30, -(8 + 8) \n" 2276 " cmpw 7, 5, 1 \n" 2277 " bgt 7, 1f \n" 2278 " stwu 31, -64(1) \n" 2279 "1:addi 30, 30, -8 \n"); 2280 } 2281 2282 /* Swap TOP and stack[sp-1] */ 2283 2284 static void 2285 ppc_emit_swap (void) 2286 { 2287 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n" 2288 "lwz " TMP_SECOND ", 12(30) \n" 2289 "stw " TOP_FIRST ", 8(30) \n" 2290 "stw " TOP_SECOND ", 12(30) \n" 2291 "mr 3, 5 \n" 2292 "mr 4, 6 \n"); 2293 } 2294 2295 /* Discard N elements in the stack. Also used for ppc64. */ 2296 2297 static void 2298 ppc_emit_stack_adjust (int n) 2299 { 2300 uint32_t buf[6]; 2301 uint32_t *p = buf; 2302 2303 n = n << 3; 2304 if ((n >> 15) != 0) 2305 { 2306 emit_error = 1; 2307 return; 2308 } 2309 2310 p += GEN_ADDI (p, 30, 30, n); 2311 2312 emit_insns (buf, p - buf); 2313 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2314 } 2315 2316 /* Call function FN. */ 2317 2318 static void 2319 ppc_emit_call (CORE_ADDR fn) 2320 { 2321 uint32_t buf[11]; 2322 uint32_t *p = buf; 2323 2324 p += gen_call (p, fn, 0, 0); 2325 2326 emit_insns (buf, p - buf); 2327 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2328 } 2329 2330 /* FN's prototype is `LONGEST(*fn)(int)'. 2331 TOP = fn (arg1) 2332 */ 2333 2334 static void 2335 ppc_emit_int_call_1 (CORE_ADDR fn, int arg1) 2336 { 2337 uint32_t buf[15]; 2338 uint32_t *p = buf; 2339 2340 /* Setup argument. arg1 is a 16-bit value. */ 2341 p += gen_limm (p, 3, (uint32_t) arg1, 0); 2342 p += gen_call (p, fn, 0, 0); 2343 2344 emit_insns (buf, p - buf); 2345 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2346 2347 if (__BYTE_ORDER == __LITTLE_ENDIAN) 2348 { 2349 EMIT_ASM ("mr 5, 4\n" 2350 "mr 4, 3\n" 2351 "mr 3, 5\n"); 2352 } 2353 } 2354 2355 /* FN's prototype is `void(*fn)(int,LONGEST)'. 2356 fn (arg1, TOP) 2357 2358 TOP should be preserved/restored before/after the call. */ 2359 2360 static void 2361 ppc_emit_void_call_2 (CORE_ADDR fn, int arg1) 2362 { 2363 uint32_t buf[21]; 2364 uint32_t *p = buf; 2365 2366 /* Save TOP. 0(30) is next-empty. */ 2367 p += GEN_STW (p, 3, 30, 0); 2368 p += GEN_STW (p, 4, 30, 4); 2369 2370 /* Setup argument. arg1 is a 16-bit value. */ 2371 if (__BYTE_ORDER == __LITTLE_ENDIAN) 2372 { 2373 p += GEN_MR (p, 5, 4); 2374 p += GEN_MR (p, 6, 3); 2375 } 2376 else 2377 { 2378 p += GEN_MR (p, 5, 3); 2379 p += GEN_MR (p, 6, 4); 2380 } 2381 p += gen_limm (p, 3, (uint32_t) arg1, 0); 2382 p += gen_call (p, fn, 0, 0); 2383 2384 /* Restore TOP */ 2385 p += GEN_LWZ (p, 3, 30, 0); 2386 p += GEN_LWZ (p, 4, 30, 4); 2387 2388 emit_insns (buf, p - buf); 2389 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2390 } 2391 2392 /* Note in the following goto ops: 2393 2394 When emitting goto, the target address is later relocated by 2395 write_goto_address. OFFSET_P is the offset of the branch instruction 2396 in the code sequence, and SIZE_P is how to relocate the instruction, 2397 recognized by ppc_write_goto_address. In current implementation, 2398 SIZE can be either 24 or 14 for branch of conditional-branch instruction. 2399 */ 2400 2401 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */ 2402 2403 static void 2404 ppc_emit_if_goto (int *offset_p, int *size_p) 2405 { 2406 EMIT_ASM ("or. 3, 3, 4 \n" 2407 "lwzu " TOP_FIRST ", 8(30) \n" 2408 "lwz " TOP_SECOND ", 4(30) \n" 2409 "1:bne 0, 1b \n"); 2410 2411 if (offset_p) 2412 *offset_p = 12; 2413 if (size_p) 2414 *size_p = 14; 2415 } 2416 2417 /* Unconditional goto. Also used for ppc64. */ 2418 2419 static void 2420 ppc_emit_goto (int *offset_p, int *size_p) 2421 { 2422 EMIT_ASM ("1:b 1b"); 2423 2424 if (offset_p) 2425 *offset_p = 0; 2426 if (size_p) 2427 *size_p = 24; 2428 } 2429 2430 /* Goto if stack[--sp] == TOP */ 2431 2432 static void 2433 ppc_emit_eq_goto (int *offset_p, int *size_p) 2434 { 2435 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2436 "lwz " TMP_SECOND ", 4(30) \n" 2437 "xor 4, 6, 4 \n" 2438 "xor 3, 5, 3 \n" 2439 "or. 3, 3, 4 \n" 2440 "lwzu " TOP_FIRST ", 8(30) \n" 2441 "lwz " TOP_SECOND ", 4(30) \n" 2442 "1:beq 0, 1b \n"); 2443 2444 if (offset_p) 2445 *offset_p = 28; 2446 if (size_p) 2447 *size_p = 14; 2448 } 2449 2450 /* Goto if stack[--sp] != TOP */ 2451 2452 static void 2453 ppc_emit_ne_goto (int *offset_p, int *size_p) 2454 { 2455 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2456 "lwz " TMP_SECOND ", 4(30) \n" 2457 "xor 4, 6, 4 \n" 2458 "xor 3, 5, 3 \n" 2459 "or. 3, 3, 4 \n" 2460 "lwzu " TOP_FIRST ", 8(30) \n" 2461 "lwz " TOP_SECOND ", 4(30) \n" 2462 "1:bne 0, 1b \n"); 2463 2464 if (offset_p) 2465 *offset_p = 28; 2466 if (size_p) 2467 *size_p = 14; 2468 } 2469 2470 /* Goto if stack[--sp] < TOP */ 2471 2472 static void 2473 ppc_emit_lt_goto (int *offset_p, int *size_p) 2474 { 2475 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2476 "lwz " TMP_SECOND ", 4(30) \n" 2477 "cmplw 6, 6, 4 \n" 2478 "cmpw 7, 5, 3 \n" 2479 /* CR6 bit 0 = low less and high equal */ 2480 "crand 6*4+0, 6*4+0, 7*4+2\n" 2481 /* CR7 bit 0 = (low less and high equal) or high less */ 2482 "cror 7*4+0, 7*4+0, 6*4+0\n" 2483 "lwzu " TOP_FIRST ", 8(30) \n" 2484 "lwz " TOP_SECOND ", 4(30)\n" 2485 "1:blt 7, 1b \n"); 2486 2487 if (offset_p) 2488 *offset_p = 32; 2489 if (size_p) 2490 *size_p = 14; 2491 } 2492 2493 /* Goto if stack[--sp] <= TOP */ 2494 2495 static void 2496 ppc_emit_le_goto (int *offset_p, int *size_p) 2497 { 2498 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2499 "lwz " TMP_SECOND ", 4(30) \n" 2500 "cmplw 6, 6, 4 \n" 2501 "cmpw 7, 5, 3 \n" 2502 /* CR6 bit 0 = low less/equal and high equal */ 2503 "crandc 6*4+0, 7*4+2, 6*4+1\n" 2504 /* CR7 bit 0 = (low less/eq and high equal) or high less */ 2505 "cror 7*4+0, 7*4+0, 6*4+0\n" 2506 "lwzu " TOP_FIRST ", 8(30) \n" 2507 "lwz " TOP_SECOND ", 4(30)\n" 2508 "1:blt 7, 1b \n"); 2509 2510 if (offset_p) 2511 *offset_p = 32; 2512 if (size_p) 2513 *size_p = 14; 2514 } 2515 2516 /* Goto if stack[--sp] > TOP */ 2517 2518 static void 2519 ppc_emit_gt_goto (int *offset_p, int *size_p) 2520 { 2521 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2522 "lwz " TMP_SECOND ", 4(30) \n" 2523 "cmplw 6, 6, 4 \n" 2524 "cmpw 7, 5, 3 \n" 2525 /* CR6 bit 0 = low greater and high equal */ 2526 "crand 6*4+0, 6*4+1, 7*4+2\n" 2527 /* CR7 bit 0 = (low greater and high equal) or high greater */ 2528 "cror 7*4+0, 7*4+1, 6*4+0\n" 2529 "lwzu " TOP_FIRST ", 8(30) \n" 2530 "lwz " TOP_SECOND ", 4(30)\n" 2531 "1:blt 7, 1b \n"); 2532 2533 if (offset_p) 2534 *offset_p = 32; 2535 if (size_p) 2536 *size_p = 14; 2537 } 2538 2539 /* Goto if stack[--sp] >= TOP */ 2540 2541 static void 2542 ppc_emit_ge_goto (int *offset_p, int *size_p) 2543 { 2544 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n" 2545 "lwz " TMP_SECOND ", 4(30) \n" 2546 "cmplw 6, 6, 4 \n" 2547 "cmpw 7, 5, 3 \n" 2548 /* CR6 bit 0 = low ge and high equal */ 2549 "crandc 6*4+0, 7*4+2, 6*4+0\n" 2550 /* CR7 bit 0 = (low ge and high equal) or high greater */ 2551 "cror 7*4+0, 7*4+1, 6*4+0\n" 2552 "lwzu " TOP_FIRST ", 8(30)\n" 2553 "lwz " TOP_SECOND ", 4(30)\n" 2554 "1:blt 7, 1b \n"); 2555 2556 if (offset_p) 2557 *offset_p = 32; 2558 if (size_p) 2559 *size_p = 14; 2560 } 2561 2562 /* Relocate previous emitted branch instruction. FROM is the address 2563 of the branch instruction, TO is the goto target address, and SIZE 2564 if the value we set by *SIZE_P before. Currently, it is either 2565 24 or 14 of branch and conditional-branch instruction. 2566 Also used for ppc64. */ 2567 2568 static void 2569 ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) 2570 { 2571 long rel = to - from; 2572 uint32_t insn; 2573 int opcd; 2574 2575 read_inferior_memory (from, (unsigned char *) &insn, 4); 2576 opcd = (insn >> 26) & 0x3f; 2577 2578 switch (size) 2579 { 2580 case 14: 2581 if (opcd != 16 2582 || (rel >= (1 << 15) || rel < -(1 << 15))) 2583 emit_error = 1; 2584 insn = (insn & ~0xfffc) | (rel & 0xfffc); 2585 break; 2586 case 24: 2587 if (opcd != 18 2588 || (rel >= (1 << 25) || rel < -(1 << 25))) 2589 emit_error = 1; 2590 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc); 2591 break; 2592 default: 2593 emit_error = 1; 2594 } 2595 2596 if (!emit_error) 2597 target_write_memory (from, (unsigned char *) &insn, 4); 2598 } 2599 2600 /* Table of emit ops for 32-bit. */ 2601 2602 static struct emit_ops ppc_emit_ops_impl = 2603 { 2604 ppc_emit_prologue, 2605 ppc_emit_epilogue, 2606 ppc_emit_add, 2607 ppc_emit_sub, 2608 ppc_emit_mul, 2609 ppc_emit_lsh, 2610 ppc_emit_rsh_signed, 2611 ppc_emit_rsh_unsigned, 2612 ppc_emit_ext, 2613 ppc_emit_log_not, 2614 ppc_emit_bit_and, 2615 ppc_emit_bit_or, 2616 ppc_emit_bit_xor, 2617 ppc_emit_bit_not, 2618 ppc_emit_equal, 2619 ppc_emit_less_signed, 2620 ppc_emit_less_unsigned, 2621 ppc_emit_ref, 2622 ppc_emit_if_goto, 2623 ppc_emit_goto, 2624 ppc_write_goto_address, 2625 ppc_emit_const, 2626 ppc_emit_call, 2627 ppc_emit_reg, 2628 ppc_emit_pop, 2629 ppc_emit_stack_flush, 2630 ppc_emit_zero_ext, 2631 ppc_emit_swap, 2632 ppc_emit_stack_adjust, 2633 ppc_emit_int_call_1, 2634 ppc_emit_void_call_2, 2635 ppc_emit_eq_goto, 2636 ppc_emit_ne_goto, 2637 ppc_emit_lt_goto, 2638 ppc_emit_le_goto, 2639 ppc_emit_gt_goto, 2640 ppc_emit_ge_goto 2641 }; 2642 2643 #ifdef __powerpc64__ 2644 2645 /* 2646 2647 Bytecode execution stack frame - 64-bit 2648 2649 | LR save area (SP + 16) 2650 | CR save area (SP + 8) 2651 SP' -> +- Back chain (SP + 0) 2652 | Save r31 for access saved arguments 2653 | Save r30 for bytecode stack pointer 2654 | Save r4 for incoming argument *value 2655 | Save r3 for incoming argument regs 2656 r30 -> +- Bytecode execution stack 2657 | 2658 | 64-byte (8 doublewords) at initial. 2659 | Expand stack as needed. 2660 | 2661 +- 2662 | Some padding for minimum stack frame. 2663 | 112 for ELFv1. 2664 SP +- Back-chain (SP') 2665 2666 initial frame size 2667 = 112 + (4 * 8) + 64 2668 = 208 2669 2670 r30 is the stack-pointer for bytecode machine. 2671 It should point to next-empty, so we can use LDU for pop. 2672 r3 is used for cache of TOP value. 2673 It was the first argument, pointer to regs. 2674 r4 is the second argument, pointer to the result. 2675 We should set *result = TOP after leaving this function. 2676 2677 Note: 2678 * To restore stack at epilogue 2679 => sp = r31 2680 * To check stack is big enough for bytecode execution. 2681 => r30 - 8 > SP + 112 2682 * To return execution result. 2683 => 0(r4) = TOP 2684 2685 */ 2686 2687 /* Emit prologue in inferior memory. See above comments. */ 2688 2689 static void 2690 ppc64v1_emit_prologue (void) 2691 { 2692 /* On ELFv1, function pointers really point to function descriptor, 2693 so emit one here. We don't care about contents of words 1 and 2, 2694 so let them just overlap out code. */ 2695 uint64_t opd = current_insn_ptr + 8; 2696 uint32_t buf[2]; 2697 2698 /* Mind the strict aliasing rules. */ 2699 memcpy (buf, &opd, sizeof buf); 2700 emit_insns(buf, 2); 2701 EMIT_ASM (/* Save return address. */ 2702 "mflr 0 \n" 2703 "std 0, 16(1) \n" 2704 /* Save r30 and incoming arguments. */ 2705 "std 31, -8(1) \n" 2706 "std 30, -16(1) \n" 2707 "std 4, -24(1) \n" 2708 "std 3, -32(1) \n" 2709 /* Point r31 to current r1 for access arguments. */ 2710 "mr 31, 1 \n" 2711 /* Adjust SP. 208 is the initial frame size. */ 2712 "stdu 1, -208(1) \n" 2713 /* Set r30 to pointing stack-top. */ 2714 "addi 30, 1, 168 \n" 2715 /* Initial r3/TOP to 0. */ 2716 "li 3, 0 \n"); 2717 } 2718 2719 /* Emit prologue in inferior memory. See above comments. */ 2720 2721 static void 2722 ppc64v2_emit_prologue (void) 2723 { 2724 EMIT_ASM (/* Save return address. */ 2725 "mflr 0 \n" 2726 "std 0, 16(1) \n" 2727 /* Save r30 and incoming arguments. */ 2728 "std 31, -8(1) \n" 2729 "std 30, -16(1) \n" 2730 "std 4, -24(1) \n" 2731 "std 3, -32(1) \n" 2732 /* Point r31 to current r1 for access arguments. */ 2733 "mr 31, 1 \n" 2734 /* Adjust SP. 208 is the initial frame size. */ 2735 "stdu 1, -208(1) \n" 2736 /* Set r30 to pointing stack-top. */ 2737 "addi 30, 1, 168 \n" 2738 /* Initial r3/TOP to 0. */ 2739 "li 3, 0 \n"); 2740 } 2741 2742 /* Emit epilogue in inferior memory. See above comments. */ 2743 2744 static void 2745 ppc64_emit_epilogue (void) 2746 { 2747 EMIT_ASM (/* Restore SP. */ 2748 "ld 1, 0(1) \n" 2749 /* *result = TOP */ 2750 "ld 4, -24(1) \n" 2751 "std 3, 0(4) \n" 2752 /* Restore registers. */ 2753 "ld 31, -8(1) \n" 2754 "ld 30, -16(1) \n" 2755 /* Restore LR. */ 2756 "ld 0, 16(1) \n" 2757 /* Return 0 for no-error. */ 2758 "li 3, 0 \n" 2759 "mtlr 0 \n" 2760 "blr \n"); 2761 } 2762 2763 /* TOP = stack[--sp] + TOP */ 2764 2765 static void 2766 ppc64_emit_add (void) 2767 { 2768 EMIT_ASM ("ldu 4, 8(30) \n" 2769 "add 3, 4, 3 \n"); 2770 } 2771 2772 /* TOP = stack[--sp] - TOP */ 2773 2774 static void 2775 ppc64_emit_sub (void) 2776 { 2777 EMIT_ASM ("ldu 4, 8(30) \n" 2778 "sub 3, 4, 3 \n"); 2779 } 2780 2781 /* TOP = stack[--sp] * TOP */ 2782 2783 static void 2784 ppc64_emit_mul (void) 2785 { 2786 EMIT_ASM ("ldu 4, 8(30) \n" 2787 "mulld 3, 4, 3 \n"); 2788 } 2789 2790 /* TOP = stack[--sp] << TOP */ 2791 2792 static void 2793 ppc64_emit_lsh (void) 2794 { 2795 EMIT_ASM ("ldu 4, 8(30) \n" 2796 "sld 3, 4, 3 \n"); 2797 } 2798 2799 /* Top = stack[--sp] >> TOP 2800 (Arithmetic shift right) */ 2801 2802 static void 2803 ppc64_emit_rsh_signed (void) 2804 { 2805 EMIT_ASM ("ldu 4, 8(30) \n" 2806 "srad 3, 4, 3 \n"); 2807 } 2808 2809 /* Top = stack[--sp] >> TOP 2810 (Logical shift right) */ 2811 2812 static void 2813 ppc64_emit_rsh_unsigned (void) 2814 { 2815 EMIT_ASM ("ldu 4, 8(30) \n" 2816 "srd 3, 4, 3 \n"); 2817 } 2818 2819 /* Emit code for signed-extension specified by ARG. */ 2820 2821 static void 2822 ppc64_emit_ext (int arg) 2823 { 2824 switch (arg) 2825 { 2826 case 8: 2827 EMIT_ASM ("extsb 3, 3"); 2828 break; 2829 case 16: 2830 EMIT_ASM ("extsh 3, 3"); 2831 break; 2832 case 32: 2833 EMIT_ASM ("extsw 3, 3"); 2834 break; 2835 default: 2836 emit_error = 1; 2837 } 2838 } 2839 2840 /* Emit code for zero-extension specified by ARG. */ 2841 2842 static void 2843 ppc64_emit_zero_ext (int arg) 2844 { 2845 switch (arg) 2846 { 2847 case 8: 2848 EMIT_ASM ("rldicl 3,3,0,56"); 2849 break; 2850 case 16: 2851 EMIT_ASM ("rldicl 3,3,0,48"); 2852 break; 2853 case 32: 2854 EMIT_ASM ("rldicl 3,3,0,32"); 2855 break; 2856 default: 2857 emit_error = 1; 2858 } 2859 } 2860 2861 /* TOP = !TOP 2862 i.e., TOP = (TOP == 0) ? 1 : 0; */ 2863 2864 static void 2865 ppc64_emit_log_not (void) 2866 { 2867 EMIT_ASM ("cntlzd 3, 3 \n" 2868 "srdi 3, 3, 6 \n"); 2869 } 2870 2871 /* TOP = stack[--sp] & TOP */ 2872 2873 static void 2874 ppc64_emit_bit_and (void) 2875 { 2876 EMIT_ASM ("ldu 4, 8(30) \n" 2877 "and 3, 4, 3 \n"); 2878 } 2879 2880 /* TOP = stack[--sp] | TOP */ 2881 2882 static void 2883 ppc64_emit_bit_or (void) 2884 { 2885 EMIT_ASM ("ldu 4, 8(30) \n" 2886 "or 3, 4, 3 \n"); 2887 } 2888 2889 /* TOP = stack[--sp] ^ TOP */ 2890 2891 static void 2892 ppc64_emit_bit_xor (void) 2893 { 2894 EMIT_ASM ("ldu 4, 8(30) \n" 2895 "xor 3, 4, 3 \n"); 2896 } 2897 2898 /* TOP = ~TOP 2899 i.e., TOP = ~(TOP | TOP) */ 2900 2901 static void 2902 ppc64_emit_bit_not (void) 2903 { 2904 EMIT_ASM ("nor 3, 3, 3 \n"); 2905 } 2906 2907 /* TOP = stack[--sp] == TOP */ 2908 2909 static void 2910 ppc64_emit_equal (void) 2911 { 2912 EMIT_ASM ("ldu 4, 8(30) \n" 2913 "xor 3, 3, 4 \n" 2914 "cntlzd 3, 3 \n" 2915 "srdi 3, 3, 6 \n"); 2916 } 2917 2918 /* TOP = stack[--sp] < TOP 2919 (Signed comparison) */ 2920 2921 static void 2922 ppc64_emit_less_signed (void) 2923 { 2924 EMIT_ASM ("ldu 4, 8(30) \n" 2925 "cmpd 7, 4, 3 \n" 2926 "mfcr 3 \n" 2927 "rlwinm 3, 3, 29, 31, 31 \n"); 2928 } 2929 2930 /* TOP = stack[--sp] < TOP 2931 (Unsigned comparison) */ 2932 2933 static void 2934 ppc64_emit_less_unsigned (void) 2935 { 2936 EMIT_ASM ("ldu 4, 8(30) \n" 2937 "cmpld 7, 4, 3 \n" 2938 "mfcr 3 \n" 2939 "rlwinm 3, 3, 29, 31, 31 \n"); 2940 } 2941 2942 /* Access the memory address in TOP in size of SIZE. 2943 Zero-extend the read value. */ 2944 2945 static void 2946 ppc64_emit_ref (int size) 2947 { 2948 switch (size) 2949 { 2950 case 1: 2951 EMIT_ASM ("lbz 3, 0(3)"); 2952 break; 2953 case 2: 2954 EMIT_ASM ("lhz 3, 0(3)"); 2955 break; 2956 case 4: 2957 EMIT_ASM ("lwz 3, 0(3)"); 2958 break; 2959 case 8: 2960 EMIT_ASM ("ld 3, 0(3)"); 2961 break; 2962 } 2963 } 2964 2965 /* TOP = NUM */ 2966 2967 static void 2968 ppc64_emit_const (LONGEST num) 2969 { 2970 uint32_t buf[5]; 2971 uint32_t *p = buf; 2972 2973 p += gen_limm (p, 3, num, 1); 2974 2975 emit_insns (buf, p - buf); 2976 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2977 } 2978 2979 /* Set TOP to the value of register REG by calling get_raw_reg function 2980 with two argument, collected buffer and register number. */ 2981 2982 static void 2983 ppc64v1_emit_reg (int reg) 2984 { 2985 uint32_t buf[15]; 2986 uint32_t *p = buf; 2987 2988 /* fctx->regs is passed in r3 and then saved in 176(1). */ 2989 p += GEN_LD (p, 3, 31, -32); 2990 p += GEN_LI (p, 4, reg); 2991 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ 2992 p += gen_call (p, get_raw_reg_func_addr (), 1, 1); 2993 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ 2994 2995 emit_insns (buf, p - buf); 2996 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 2997 } 2998 2999 /* Likewise, for ELFv2. */ 3000 3001 static void 3002 ppc64v2_emit_reg (int reg) 3003 { 3004 uint32_t buf[12]; 3005 uint32_t *p = buf; 3006 3007 /* fctx->regs is passed in r3 and then saved in 176(1). */ 3008 p += GEN_LD (p, 3, 31, -32); 3009 p += GEN_LI (p, 4, reg); 3010 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ 3011 p += gen_call (p, get_raw_reg_func_addr (), 1, 0); 3012 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ 3013 3014 emit_insns (buf, p - buf); 3015 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3016 } 3017 3018 /* TOP = stack[--sp] */ 3019 3020 static void 3021 ppc64_emit_pop (void) 3022 { 3023 EMIT_ASM ("ldu 3, 8(30)"); 3024 } 3025 3026 /* stack[sp++] = TOP 3027 3028 Because we may use up bytecode stack, expand 8 doublewords more 3029 if needed. */ 3030 3031 static void 3032 ppc64_emit_stack_flush (void) 3033 { 3034 /* Make sure bytecode stack is big enough before push. 3035 Otherwise, expand 64-byte more. */ 3036 3037 EMIT_ASM (" std 3, 0(30) \n" 3038 " addi 4, 30, -(112 + 8) \n" 3039 " cmpd 7, 4, 1 \n" 3040 " bgt 7, 1f \n" 3041 " stdu 31, -64(1) \n" 3042 "1:addi 30, 30, -8 \n"); 3043 } 3044 3045 /* Swap TOP and stack[sp-1] */ 3046 3047 static void 3048 ppc64_emit_swap (void) 3049 { 3050 EMIT_ASM ("ld 4, 8(30) \n" 3051 "std 3, 8(30) \n" 3052 "mr 3, 4 \n"); 3053 } 3054 3055 /* Call function FN - ELFv1. */ 3056 3057 static void 3058 ppc64v1_emit_call (CORE_ADDR fn) 3059 { 3060 uint32_t buf[13]; 3061 uint32_t *p = buf; 3062 3063 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ 3064 p += gen_call (p, fn, 1, 1); 3065 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ 3066 3067 emit_insns (buf, p - buf); 3068 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3069 } 3070 3071 /* Call function FN - ELFv2. */ 3072 3073 static void 3074 ppc64v2_emit_call (CORE_ADDR fn) 3075 { 3076 uint32_t buf[10]; 3077 uint32_t *p = buf; 3078 3079 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ 3080 p += gen_call (p, fn, 1, 0); 3081 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ 3082 3083 emit_insns (buf, p - buf); 3084 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3085 } 3086 3087 /* FN's prototype is `LONGEST(*fn)(int)'. 3088 TOP = fn (arg1) 3089 */ 3090 3091 static void 3092 ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1) 3093 { 3094 uint32_t buf[13]; 3095 uint32_t *p = buf; 3096 3097 /* Setup argument. arg1 is a 16-bit value. */ 3098 p += gen_limm (p, 3, arg1, 1); 3099 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ 3100 p += gen_call (p, fn, 1, 1); 3101 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ 3102 3103 emit_insns (buf, p - buf); 3104 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3105 } 3106 3107 /* Likewise for ELFv2. */ 3108 3109 static void 3110 ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1) 3111 { 3112 uint32_t buf[10]; 3113 uint32_t *p = buf; 3114 3115 /* Setup argument. arg1 is a 16-bit value. */ 3116 p += gen_limm (p, 3, arg1, 1); 3117 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ 3118 p += gen_call (p, fn, 1, 0); 3119 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ 3120 3121 emit_insns (buf, p - buf); 3122 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3123 } 3124 3125 /* FN's prototype is `void(*fn)(int,LONGEST)'. 3126 fn (arg1, TOP) 3127 3128 TOP should be preserved/restored before/after the call. */ 3129 3130 static void 3131 ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1) 3132 { 3133 uint32_t buf[17]; 3134 uint32_t *p = buf; 3135 3136 /* Save TOP. 0(30) is next-empty. */ 3137 p += GEN_STD (p, 3, 30, 0); 3138 3139 /* Setup argument. arg1 is a 16-bit value. */ 3140 p += GEN_MR (p, 4, 3); /* mr r4, r3 */ 3141 p += gen_limm (p, 3, arg1, 1); 3142 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */ 3143 p += gen_call (p, fn, 1, 1); 3144 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */ 3145 3146 /* Restore TOP */ 3147 p += GEN_LD (p, 3, 30, 0); 3148 3149 emit_insns (buf, p - buf); 3150 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3151 } 3152 3153 /* Likewise for ELFv2. */ 3154 3155 static void 3156 ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1) 3157 { 3158 uint32_t buf[14]; 3159 uint32_t *p = buf; 3160 3161 /* Save TOP. 0(30) is next-empty. */ 3162 p += GEN_STD (p, 3, 30, 0); 3163 3164 /* Setup argument. arg1 is a 16-bit value. */ 3165 p += GEN_MR (p, 4, 3); /* mr r4, r3 */ 3166 p += gen_limm (p, 3, arg1, 1); 3167 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */ 3168 p += gen_call (p, fn, 1, 0); 3169 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */ 3170 3171 /* Restore TOP */ 3172 p += GEN_LD (p, 3, 30, 0); 3173 3174 emit_insns (buf, p - buf); 3175 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf))); 3176 } 3177 3178 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */ 3179 3180 static void 3181 ppc64_emit_if_goto (int *offset_p, int *size_p) 3182 { 3183 EMIT_ASM ("cmpdi 7, 3, 0 \n" 3184 "ldu 3, 8(30) \n" 3185 "1:bne 7, 1b \n"); 3186 3187 if (offset_p) 3188 *offset_p = 8; 3189 if (size_p) 3190 *size_p = 14; 3191 } 3192 3193 /* Goto if stack[--sp] == TOP */ 3194 3195 static void 3196 ppc64_emit_eq_goto (int *offset_p, int *size_p) 3197 { 3198 EMIT_ASM ("ldu 4, 8(30) \n" 3199 "cmpd 7, 4, 3 \n" 3200 "ldu 3, 8(30) \n" 3201 "1:beq 7, 1b \n"); 3202 3203 if (offset_p) 3204 *offset_p = 12; 3205 if (size_p) 3206 *size_p = 14; 3207 } 3208 3209 /* Goto if stack[--sp] != TOP */ 3210 3211 static void 3212 ppc64_emit_ne_goto (int *offset_p, int *size_p) 3213 { 3214 EMIT_ASM ("ldu 4, 8(30) \n" 3215 "cmpd 7, 4, 3 \n" 3216 "ldu 3, 8(30) \n" 3217 "1:bne 7, 1b \n"); 3218 3219 if (offset_p) 3220 *offset_p = 12; 3221 if (size_p) 3222 *size_p = 14; 3223 } 3224 3225 /* Goto if stack[--sp] < TOP */ 3226 3227 static void 3228 ppc64_emit_lt_goto (int *offset_p, int *size_p) 3229 { 3230 EMIT_ASM ("ldu 4, 8(30) \n" 3231 "cmpd 7, 4, 3 \n" 3232 "ldu 3, 8(30) \n" 3233 "1:blt 7, 1b \n"); 3234 3235 if (offset_p) 3236 *offset_p = 12; 3237 if (size_p) 3238 *size_p = 14; 3239 } 3240 3241 /* Goto if stack[--sp] <= TOP */ 3242 3243 static void 3244 ppc64_emit_le_goto (int *offset_p, int *size_p) 3245 { 3246 EMIT_ASM ("ldu 4, 8(30) \n" 3247 "cmpd 7, 4, 3 \n" 3248 "ldu 3, 8(30) \n" 3249 "1:ble 7, 1b \n"); 3250 3251 if (offset_p) 3252 *offset_p = 12; 3253 if (size_p) 3254 *size_p = 14; 3255 } 3256 3257 /* Goto if stack[--sp] > TOP */ 3258 3259 static void 3260 ppc64_emit_gt_goto (int *offset_p, int *size_p) 3261 { 3262 EMIT_ASM ("ldu 4, 8(30) \n" 3263 "cmpd 7, 4, 3 \n" 3264 "ldu 3, 8(30) \n" 3265 "1:bgt 7, 1b \n"); 3266 3267 if (offset_p) 3268 *offset_p = 12; 3269 if (size_p) 3270 *size_p = 14; 3271 } 3272 3273 /* Goto if stack[--sp] >= TOP */ 3274 3275 static void 3276 ppc64_emit_ge_goto (int *offset_p, int *size_p) 3277 { 3278 EMIT_ASM ("ldu 4, 8(30) \n" 3279 "cmpd 7, 4, 3 \n" 3280 "ldu 3, 8(30) \n" 3281 "1:bge 7, 1b \n"); 3282 3283 if (offset_p) 3284 *offset_p = 12; 3285 if (size_p) 3286 *size_p = 14; 3287 } 3288 3289 /* Table of emit ops for 64-bit ELFv1. */ 3290 3291 static struct emit_ops ppc64v1_emit_ops_impl = 3292 { 3293 ppc64v1_emit_prologue, 3294 ppc64_emit_epilogue, 3295 ppc64_emit_add, 3296 ppc64_emit_sub, 3297 ppc64_emit_mul, 3298 ppc64_emit_lsh, 3299 ppc64_emit_rsh_signed, 3300 ppc64_emit_rsh_unsigned, 3301 ppc64_emit_ext, 3302 ppc64_emit_log_not, 3303 ppc64_emit_bit_and, 3304 ppc64_emit_bit_or, 3305 ppc64_emit_bit_xor, 3306 ppc64_emit_bit_not, 3307 ppc64_emit_equal, 3308 ppc64_emit_less_signed, 3309 ppc64_emit_less_unsigned, 3310 ppc64_emit_ref, 3311 ppc64_emit_if_goto, 3312 ppc_emit_goto, 3313 ppc_write_goto_address, 3314 ppc64_emit_const, 3315 ppc64v1_emit_call, 3316 ppc64v1_emit_reg, 3317 ppc64_emit_pop, 3318 ppc64_emit_stack_flush, 3319 ppc64_emit_zero_ext, 3320 ppc64_emit_swap, 3321 ppc_emit_stack_adjust, 3322 ppc64v1_emit_int_call_1, 3323 ppc64v1_emit_void_call_2, 3324 ppc64_emit_eq_goto, 3325 ppc64_emit_ne_goto, 3326 ppc64_emit_lt_goto, 3327 ppc64_emit_le_goto, 3328 ppc64_emit_gt_goto, 3329 ppc64_emit_ge_goto 3330 }; 3331 3332 /* Table of emit ops for 64-bit ELFv2. */ 3333 3334 static struct emit_ops ppc64v2_emit_ops_impl = 3335 { 3336 ppc64v2_emit_prologue, 3337 ppc64_emit_epilogue, 3338 ppc64_emit_add, 3339 ppc64_emit_sub, 3340 ppc64_emit_mul, 3341 ppc64_emit_lsh, 3342 ppc64_emit_rsh_signed, 3343 ppc64_emit_rsh_unsigned, 3344 ppc64_emit_ext, 3345 ppc64_emit_log_not, 3346 ppc64_emit_bit_and, 3347 ppc64_emit_bit_or, 3348 ppc64_emit_bit_xor, 3349 ppc64_emit_bit_not, 3350 ppc64_emit_equal, 3351 ppc64_emit_less_signed, 3352 ppc64_emit_less_unsigned, 3353 ppc64_emit_ref, 3354 ppc64_emit_if_goto, 3355 ppc_emit_goto, 3356 ppc_write_goto_address, 3357 ppc64_emit_const, 3358 ppc64v2_emit_call, 3359 ppc64v2_emit_reg, 3360 ppc64_emit_pop, 3361 ppc64_emit_stack_flush, 3362 ppc64_emit_zero_ext, 3363 ppc64_emit_swap, 3364 ppc_emit_stack_adjust, 3365 ppc64v2_emit_int_call_1, 3366 ppc64v2_emit_void_call_2, 3367 ppc64_emit_eq_goto, 3368 ppc64_emit_ne_goto, 3369 ppc64_emit_lt_goto, 3370 ppc64_emit_le_goto, 3371 ppc64_emit_gt_goto, 3372 ppc64_emit_ge_goto 3373 }; 3374 3375 #endif 3376 3377 /* Implementation of target ops method "emit_ops". */ 3378 3379 emit_ops * 3380 ppc_target::emit_ops () 3381 { 3382 #ifdef __powerpc64__ 3383 struct regcache *regcache = get_thread_regcache (current_thread, 0); 3384 3385 if (register_size (regcache->tdesc, 0) == 8) 3386 { 3387 if (is_elfv2_inferior ()) 3388 return &ppc64v2_emit_ops_impl; 3389 else 3390 return &ppc64v1_emit_ops_impl; 3391 } 3392 #endif 3393 return &ppc_emit_ops_impl; 3394 } 3395 3396 /* Implementation of target ops method "get_ipa_tdesc_idx". */ 3397 3398 int 3399 ppc_target::get_ipa_tdesc_idx () 3400 { 3401 struct regcache *regcache = get_thread_regcache (current_thread, 0); 3402 const struct target_desc *tdesc = regcache->tdesc; 3403 3404 #ifdef __powerpc64__ 3405 if (tdesc == tdesc_powerpc_64l) 3406 return PPC_TDESC_BASE; 3407 if (tdesc == tdesc_powerpc_altivec64l) 3408 return PPC_TDESC_ALTIVEC; 3409 if (tdesc == tdesc_powerpc_vsx64l) 3410 return PPC_TDESC_VSX; 3411 if (tdesc == tdesc_powerpc_isa205_64l) 3412 return PPC_TDESC_ISA205; 3413 if (tdesc == tdesc_powerpc_isa205_altivec64l) 3414 return PPC_TDESC_ISA205_ALTIVEC; 3415 if (tdesc == tdesc_powerpc_isa205_vsx64l) 3416 return PPC_TDESC_ISA205_VSX; 3417 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l) 3418 return PPC_TDESC_ISA205_PPR_DSCR_VSX; 3419 if (tdesc == tdesc_powerpc_isa207_vsx64l) 3420 return PPC_TDESC_ISA207_VSX; 3421 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l) 3422 return PPC_TDESC_ISA207_HTM_VSX; 3423 #endif 3424 3425 if (tdesc == tdesc_powerpc_32l) 3426 return PPC_TDESC_BASE; 3427 if (tdesc == tdesc_powerpc_altivec32l) 3428 return PPC_TDESC_ALTIVEC; 3429 if (tdesc == tdesc_powerpc_vsx32l) 3430 return PPC_TDESC_VSX; 3431 if (tdesc == tdesc_powerpc_isa205_32l) 3432 return PPC_TDESC_ISA205; 3433 if (tdesc == tdesc_powerpc_isa205_altivec32l) 3434 return PPC_TDESC_ISA205_ALTIVEC; 3435 if (tdesc == tdesc_powerpc_isa205_vsx32l) 3436 return PPC_TDESC_ISA205_VSX; 3437 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l) 3438 return PPC_TDESC_ISA205_PPR_DSCR_VSX; 3439 if (tdesc == tdesc_powerpc_isa207_vsx32l) 3440 return PPC_TDESC_ISA207_VSX; 3441 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l) 3442 return PPC_TDESC_ISA207_HTM_VSX; 3443 if (tdesc == tdesc_powerpc_e500l) 3444 return PPC_TDESC_E500; 3445 3446 return 0; 3447 } 3448 3449 /* The linux target ops object. */ 3450 3451 linux_process_target *the_linux_target = &the_ppc_target; 3452 3453 void 3454 initialize_low_arch (void) 3455 { 3456 /* Initialize the Linux target descriptions. */ 3457 3458 init_registers_powerpc_32l (); 3459 init_registers_powerpc_altivec32l (); 3460 init_registers_powerpc_vsx32l (); 3461 init_registers_powerpc_isa205_32l (); 3462 init_registers_powerpc_isa205_altivec32l (); 3463 init_registers_powerpc_isa205_vsx32l (); 3464 init_registers_powerpc_isa205_ppr_dscr_vsx32l (); 3465 init_registers_powerpc_isa207_vsx32l (); 3466 init_registers_powerpc_isa207_htm_vsx32l (); 3467 init_registers_powerpc_e500l (); 3468 #if __powerpc64__ 3469 init_registers_powerpc_64l (); 3470 init_registers_powerpc_altivec64l (); 3471 init_registers_powerpc_vsx64l (); 3472 init_registers_powerpc_isa205_64l (); 3473 init_registers_powerpc_isa205_altivec64l (); 3474 init_registers_powerpc_isa205_vsx64l (); 3475 init_registers_powerpc_isa205_ppr_dscr_vsx64l (); 3476 init_registers_powerpc_isa207_vsx64l (); 3477 init_registers_powerpc_isa207_htm_vsx64l (); 3478 #endif 3479 3480 initialize_regsets_info (&ppc_regsets_info); 3481 } 3482