1 /* riscv.h. RISC-V opcode list for GDB, the GNU debugger. 2 Copyright (C) 2011-2022 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 3, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; see the file COPYING3. If not, 19 see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _RISCV_H_ 22 #define _RISCV_H_ 23 24 #include "riscv-opc.h" 25 #include <stdlib.h> 26 #include <stdint.h> 27 28 typedef uint64_t insn_t; 29 30 static inline unsigned int riscv_insn_length (insn_t insn) 31 { 32 if ((insn & 0x3) != 0x3) /* RVC instructions. */ 33 return 2; 34 if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */ 35 return 4; 36 if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */ 37 return 6; 38 if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */ 39 return 8; 40 /* 80- ... 176-bit instructions. */ 41 if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000) 42 return 10 + ((insn >> 11) & 0xe); 43 /* Maximum value returned by this function. */ 44 #define RISCV_MAX_INSN_LEN 22 45 /* Longer instructions not supported at the moment. */ 46 return 2; 47 } 48 49 #define RVC_JUMP_BITS 11 50 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) 51 52 #define RVC_BRANCH_BITS 8 53 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) 54 55 #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) 56 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) 57 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) 58 59 #define EXTRACT_ITYPE_IMM(x) \ 60 (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) 61 #define EXTRACT_STYPE_IMM(x) \ 62 (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) 63 #define EXTRACT_BTYPE_IMM(x) \ 64 ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) 65 #define EXTRACT_UTYPE_IMM(x) \ 66 ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) 67 #define EXTRACT_JTYPE_IMM(x) \ 68 ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) 69 #define EXTRACT_CITYPE_IMM(x) \ 70 (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) 71 #define EXTRACT_CITYPE_LUI_IMM(x) \ 72 (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS) 73 #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \ 74 ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) 75 #define EXTRACT_CITYPE_LWSP_IMM(x) \ 76 ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) 77 #define EXTRACT_CITYPE_LDSP_IMM(x) \ 78 ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) 79 #define EXTRACT_CSSTYPE_IMM(x) \ 80 (RV_X(x, 7, 6) << 0) 81 #define EXTRACT_CSSTYPE_SWSP_IMM(x) \ 82 ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) 83 #define EXTRACT_CSSTYPE_SDSP_IMM(x) \ 84 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) 85 #define EXTRACT_CIWTYPE_IMM(x) \ 86 (RV_X(x, 5, 8)) 87 #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \ 88 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) 89 #define EXTRACT_CLTYPE_IMM(x) \ 90 ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2)) 91 #define EXTRACT_CLTYPE_LW_IMM(x) \ 92 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) 93 #define EXTRACT_CLTYPE_LD_IMM(x) \ 94 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) 95 #define EXTRACT_CBTYPE_IMM(x) \ 96 ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) 97 #define EXTRACT_CJTYPE_IMM(x) \ 98 ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) 99 #define EXTRACT_RVV_VI_IMM(x) \ 100 (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5)) 101 #define EXTRACT_RVV_VI_UIMM(x) \ 102 (RV_X(x, 15, 5)) 103 #define EXTRACT_RVV_OFFSET(x) \ 104 (RV_X(x, 29, 3)) 105 #define EXTRACT_RVV_VB_IMM(x) \ 106 (RV_X(x, 20, 10)) 107 #define EXTRACT_RVV_VC_IMM(x) \ 108 (RV_X(x, 20, 11)) 109 110 #define ENCODE_ITYPE_IMM(x) \ 111 (RV_X(x, 0, 12) << 20) 112 #define ENCODE_STYPE_IMM(x) \ 113 ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) 114 #define ENCODE_BTYPE_IMM(x) \ 115 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) 116 #define ENCODE_UTYPE_IMM(x) \ 117 (RV_X(x, 12, 20) << 12) 118 #define ENCODE_JTYPE_IMM(x) \ 119 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) 120 #define ENCODE_CITYPE_IMM(x) \ 121 ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) 122 #define ENCODE_CITYPE_LUI_IMM(x) \ 123 ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS) 124 #define ENCODE_CITYPE_ADDI16SP_IMM(x) \ 125 ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) 126 #define ENCODE_CITYPE_LWSP_IMM(x) \ 127 ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) 128 #define ENCODE_CITYPE_LDSP_IMM(x) \ 129 ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) 130 #define ENCODE_CSSTYPE_IMM(x) \ 131 (RV_X(x, 0, 6) << 7) 132 #define ENCODE_CSSTYPE_SWSP_IMM(x) \ 133 ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) 134 #define ENCODE_CSSTYPE_SDSP_IMM(x) \ 135 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) 136 #define ENCODE_CIWTYPE_IMM(x) \ 137 (RV_X(x, 0, 8) << 5) 138 #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \ 139 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) 140 #define ENCODE_CLTYPE_IMM(x) \ 141 ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10)) 142 #define ENCODE_CLTYPE_LW_IMM(x) \ 143 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) 144 #define ENCODE_CLTYPE_LD_IMM(x) \ 145 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) 146 #define ENCODE_CBTYPE_IMM(x) \ 147 ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) 148 #define ENCODE_CJTYPE_IMM(x) \ 149 ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) 150 #define ENCODE_RVV_VB_IMM(x) \ 151 (RV_X(x, 0, 10) << 20) 152 #define ENCODE_RVV_VC_IMM(x) \ 153 (RV_X(x, 0, 11) << 20) 154 155 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) 156 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) 157 #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x)) 158 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) 159 #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x)) 160 #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x)) 161 #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \ 162 && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x)) 163 #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \ 164 && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x)) 165 #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x)) 166 #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x)) 167 #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x)) 168 #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x)) 169 #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x)) 170 #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x)) 171 #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x)) 172 #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x)) 173 #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x)) 174 #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x)) 175 #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x)) 176 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x)) 177 #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x)) 178 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x)) 179 180 #define RISCV_RTYPE(insn, rd, rs1, rs2) \ 181 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) 182 #define RISCV_ITYPE(insn, rd, rs1, imm) \ 183 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) 184 #define RISCV_STYPE(insn, rs1, rs2, imm) \ 185 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) 186 #define RISCV_BTYPE(insn, rs1, rs2, target) \ 187 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target)) 188 #define RISCV_UTYPE(insn, rd, bigimm) \ 189 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) 190 #define RISCV_JTYPE(insn, rd, target) \ 191 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target)) 192 193 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) 194 #define RVC_NOP MATCH_C_ADDI 195 196 #define RISCV_CONST_HIGH_PART(VALUE) \ 197 (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) 198 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) 199 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) 200 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) 201 202 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS 203 #define RISCV_JUMP_ALIGN_BITS 1 204 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) 205 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) 206 207 #define RISCV_IMM_BITS 12 208 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) 209 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) 210 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) 211 #define RISCV_RVC_IMM_REACH (1LL << 6) 212 #define RISCV_BRANCH_BITS RISCV_IMM_BITS 213 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS 214 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) 215 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) 216 217 /* RV fields. */ 218 219 #define OP_MASK_OP 0x7f 220 #define OP_SH_OP 0 221 #define OP_MASK_RS2 0x1f 222 #define OP_SH_RS2 20 223 #define OP_MASK_RS1 0x1f 224 #define OP_SH_RS1 15 225 #define OP_MASK_RS3 0x1fU 226 #define OP_SH_RS3 27 227 #define OP_MASK_RD 0x1f 228 #define OP_SH_RD 7 229 #define OP_MASK_SHAMT 0x3f 230 #define OP_SH_SHAMT 20 231 #define OP_MASK_SHAMTW 0x1f 232 #define OP_SH_SHAMTW 20 233 #define OP_MASK_RM 0x7 234 #define OP_SH_RM 12 235 #define OP_MASK_PRED 0xf 236 #define OP_SH_PRED 24 237 #define OP_MASK_SUCC 0xf 238 #define OP_SH_SUCC 20 239 #define OP_MASK_AQ 0x1 240 #define OP_SH_AQ 26 241 #define OP_MASK_RL 0x1 242 #define OP_SH_RL 25 243 244 #define OP_MASK_CSR 0xfffU 245 #define OP_SH_CSR 20 246 247 #define OP_MASK_FUNCT3 0x7 248 #define OP_SH_FUNCT3 12 249 #define OP_MASK_FUNCT7 0x7fU 250 #define OP_SH_FUNCT7 25 251 #define OP_MASK_FUNCT2 0x3 252 #define OP_SH_FUNCT2 25 253 254 /* RVC fields. */ 255 256 #define OP_MASK_OP2 0x3 257 #define OP_SH_OP2 0 258 259 #define OP_MASK_CRS2 0x1f 260 #define OP_SH_CRS2 2 261 #define OP_MASK_CRS1S 0x7 262 #define OP_SH_CRS1S 7 263 #define OP_MASK_CRS2S 0x7 264 #define OP_SH_CRS2S 2 265 266 #define OP_MASK_CFUNCT6 0x3f 267 #define OP_SH_CFUNCT6 10 268 #define OP_MASK_CFUNCT4 0xf 269 #define OP_SH_CFUNCT4 12 270 #define OP_MASK_CFUNCT3 0x7 271 #define OP_SH_CFUNCT3 13 272 #define OP_MASK_CFUNCT2 0x3 273 #define OP_SH_CFUNCT2 5 274 275 /* Scalar crypto fields. */ 276 277 #define OP_SH_BS 30 278 #define OP_MASK_BS 3 279 #define OP_SH_RNUM 20 280 #define OP_MASK_RNUM 0xf 281 282 /* RVV fields. */ 283 284 #define OP_MASK_VD 0x1f 285 #define OP_SH_VD 7 286 #define OP_MASK_VS1 0x1f 287 #define OP_SH_VS1 15 288 #define OP_MASK_VS2 0x1f 289 #define OP_SH_VS2 20 290 #define OP_MASK_VIMM 0x1f 291 #define OP_SH_VIMM 15 292 #define OP_MASK_VMASK 0x1 293 #define OP_SH_VMASK 25 294 #define OP_MASK_VFUNCT6 0x3f 295 #define OP_SH_VFUNCT6 26 296 #define OP_MASK_VLMUL 0x7 297 #define OP_SH_VLMUL 0 298 #define OP_MASK_VSEW 0x7 299 #define OP_SH_VSEW 3 300 #define OP_MASK_VTA 0x1 301 #define OP_SH_VTA 6 302 #define OP_MASK_VMA 0x1 303 #define OP_SH_VMA 7 304 #define OP_MASK_VWD 0x1 305 #define OP_SH_VWD 26 306 307 #define NVECR 32 308 #define NVECM 1 309 310 /* ABI names for selected x-registers. */ 311 312 #define X_RA 1 313 #define X_SP 2 314 #define X_GP 3 315 #define X_TP 4 316 #define X_T0 5 317 #define X_T1 6 318 #define X_T2 7 319 #define X_T3 28 320 321 #define NGPR 32 322 #define NFPR 32 323 324 /* These fake label defines are use by both the assembler, and 325 libopcodes. The assembler uses this when it needs to generate a fake 326 label, and libopcodes uses it to hide the fake labels in its output. */ 327 #define RISCV_FAKE_LABEL_NAME ".L0 " 328 #define RISCV_FAKE_LABEL_CHAR ' ' 329 330 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in 331 VALUE << SHIFT. VALUE is evaluated exactly once. */ 332 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ 333 (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ 334 | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) 335 336 /* Extract bits MASK << SHIFT from STRUCT and shift them right 337 SHIFT places. */ 338 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 339 (((STRUCT) >> (SHIFT)) & (MASK)) 340 341 /* Extract the operand given by FIELD from integer INSN. */ 342 #define EXTRACT_OPERAND(FIELD, INSN) \ 343 EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) 344 345 /* Extract an unsigned immediate operand on position s with n bits. */ 346 #define EXTRACT_U_IMM(n, s, l) \ 347 RV_X (l, s, n) 348 349 /* Extract an signed immediate operand on position s with n bits. */ 350 #define EXTRACT_S_IMM(n, s, l) \ 351 RV_X_SIGNED (l, s, n) 352 353 /* Validate that unsigned n-bit immediate is within bounds. */ 354 #define VALIDATE_U_IMM(v, n) \ 355 ((unsigned long) v < (1UL << n)) 356 357 /* Validate that signed n-bit immediate is within bounds. */ 358 #define VALIDATE_S_IMM(v, n) \ 359 (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1))) 360 361 /* The maximal number of subset can be required. */ 362 #define MAX_SUBSET_NUM 4 363 364 /* All RISC-V instructions belong to at least one of these classes. */ 365 enum riscv_insn_class 366 { 367 INSN_CLASS_NONE, 368 369 INSN_CLASS_I, 370 INSN_CLASS_C, 371 INSN_CLASS_A, 372 INSN_CLASS_M, 373 INSN_CLASS_F, 374 INSN_CLASS_D, 375 INSN_CLASS_Q, 376 INSN_CLASS_F_AND_C, 377 INSN_CLASS_D_AND_C, 378 INSN_CLASS_ZICSR, 379 INSN_CLASS_ZIFENCEI, 380 INSN_CLASS_ZIHINTPAUSE, 381 INSN_CLASS_ZMMUL, 382 INSN_CLASS_ZAWRS, 383 INSN_CLASS_F_INX, 384 INSN_CLASS_D_INX, 385 INSN_CLASS_Q_INX, 386 INSN_CLASS_ZFH_INX, 387 INSN_CLASS_ZFHMIN, 388 INSN_CLASS_ZFHMIN_INX, 389 INSN_CLASS_ZFHMIN_AND_D_INX, 390 INSN_CLASS_ZFHMIN_AND_Q_INX, 391 INSN_CLASS_ZBA, 392 INSN_CLASS_ZBB, 393 INSN_CLASS_ZBC, 394 INSN_CLASS_ZBS, 395 INSN_CLASS_ZBKB, 396 INSN_CLASS_ZBKC, 397 INSN_CLASS_ZBKX, 398 INSN_CLASS_ZKND, 399 INSN_CLASS_ZKNE, 400 INSN_CLASS_ZKNH, 401 INSN_CLASS_ZKSED, 402 INSN_CLASS_ZKSH, 403 INSN_CLASS_ZBB_OR_ZBKB, 404 INSN_CLASS_ZBC_OR_ZBKC, 405 INSN_CLASS_ZKND_OR_ZKNE, 406 INSN_CLASS_V, 407 INSN_CLASS_ZVEF, 408 INSN_CLASS_SVINVAL, 409 INSN_CLASS_ZICBOM, 410 INSN_CLASS_ZICBOP, 411 INSN_CLASS_ZICBOZ, 412 INSN_CLASS_H, 413 INSN_CLASS_XTHEADBA, 414 INSN_CLASS_XTHEADBB, 415 INSN_CLASS_XTHEADBS, 416 INSN_CLASS_XTHEADCMO, 417 INSN_CLASS_XTHEADCONDMOV, 418 INSN_CLASS_XTHEADFMEMIDX, 419 INSN_CLASS_XTHEADFMV, 420 INSN_CLASS_XTHEADINT, 421 INSN_CLASS_XTHEADMAC, 422 INSN_CLASS_XTHEADMEMIDX, 423 INSN_CLASS_XTHEADMEMPAIR, 424 INSN_CLASS_XTHEADSYNC, 425 }; 426 427 /* This structure holds information for a particular instruction. */ 428 struct riscv_opcode 429 { 430 /* The name of the instruction. */ 431 const char *name; 432 433 /* The requirement of xlen for the instruction, 0 if no requirement. */ 434 unsigned xlen_requirement; 435 436 /* Class to which this instruction belongs. Used to decide whether or 437 not this instruction is legal in the current -march context. */ 438 enum riscv_insn_class insn_class; 439 440 /* A string describing the arguments for this instruction. */ 441 const char *args; 442 443 /* The basic opcode for the instruction. When assembling, this 444 opcode is modified by the arguments to produce the actual opcode 445 that is used. If pinfo is INSN_MACRO, then this is 0. */ 446 insn_t match; 447 448 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 449 relevant portions of the opcode when disassembling. If the 450 actual opcode anded with the match field equals the opcode field, 451 then we have found the correct instruction. If pinfo is 452 INSN_MACRO, then this field is the macro identifier. */ 453 insn_t mask; 454 455 /* A function to determine if a word corresponds to this instruction. 456 Usually, this computes ((word & mask) == match). */ 457 int (*match_func) (const struct riscv_opcode *op, insn_t word); 458 459 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 460 of bits describing the instruction, notably any relevant hazard 461 information. */ 462 unsigned long pinfo; 463 }; 464 465 /* Instruction is a simple alias (e.g. "mv" for "addi"). */ 466 #define INSN_ALIAS 0x00000001 467 468 /* These are for setting insn_info fields. 469 470 Nonbranch is the default. Noninsn is used only if there is no match. 471 There are no condjsr or dref2 instructions. So that leaves condbranch, 472 branch, jsr, and dref that we need to handle here, encoded in 3 bits. */ 473 #define INSN_TYPE 0x0000000e 474 475 /* Instruction is an unconditional branch. */ 476 #define INSN_BRANCH 0x00000002 477 /* Instruction is a conditional branch. */ 478 #define INSN_CONDBRANCH 0x00000004 479 /* Instruction is a jump to subroutine. */ 480 #define INSN_JSR 0x00000006 481 /* Instruction is a data reference. */ 482 #define INSN_DREF 0x00000008 483 /* Instruction is allowed when eew >= 64. */ 484 #define INSN_V_EEW64 0x10000000 485 486 /* We have 5 data reference sizes, which we can encode in 3 bits. */ 487 #define INSN_DATA_SIZE 0x00000070 488 #define INSN_DATA_SIZE_SHIFT 4 489 #define INSN_1_BYTE 0x00000010 490 #define INSN_2_BYTE 0x00000020 491 #define INSN_4_BYTE 0x00000030 492 #define INSN_8_BYTE 0x00000040 493 #define INSN_16_BYTE 0x00000050 494 495 /* Instruction is actually a macro. It should be ignored by the 496 disassembler, and requires special treatment by the assembler. */ 497 #define INSN_MACRO 0xffffffff 498 499 /* This is a list of macro expanded instructions. */ 500 enum 501 { 502 M_LA, 503 M_LLA, 504 M_LA_TLS_GD, 505 M_LA_TLS_IE, 506 M_LB, 507 M_LBU, 508 M_LH, 509 M_LHU, 510 M_LW, 511 M_LWU, 512 M_LD, 513 M_SB, 514 M_SH, 515 M_SW, 516 M_SD, 517 M_FLW, 518 M_FLD, 519 M_FLQ, 520 M_FSW, 521 M_FSD, 522 M_FSQ, 523 M_CALL, 524 M_J, 525 M_LI, 526 M_ZEXTH, 527 M_ZEXTW, 528 M_SEXTB, 529 M_SEXTH, 530 M_VMSGE, 531 M_VMSGEU, 532 M_FLH, 533 M_FSH, 534 M_NUM_MACROS 535 }; 536 537 /* The mapping symbol states. */ 538 enum riscv_seg_mstate 539 { 540 MAP_NONE = 0, /* Must be zero, for seginfo in new sections. */ 541 MAP_DATA, /* Data. */ 542 MAP_INSN, /* Instructions. */ 543 }; 544 545 extern const char * const riscv_gpr_names_numeric[NGPR]; 546 extern const char * const riscv_gpr_names_abi[NGPR]; 547 extern const char * const riscv_fpr_names_numeric[NFPR]; 548 extern const char * const riscv_fpr_names_abi[NFPR]; 549 extern const char * const riscv_rm[8]; 550 extern const char * const riscv_pred_succ[16]; 551 extern const char * const riscv_vecr_names_numeric[NVECR]; 552 extern const char * const riscv_vecm_names_numeric[NVECM]; 553 extern const char * const riscv_vsew[8]; 554 extern const char * const riscv_vlmul[8]; 555 extern const char * const riscv_vta[2]; 556 extern const char * const riscv_vma[2]; 557 558 extern const struct riscv_opcode riscv_opcodes[]; 559 extern const struct riscv_opcode riscv_insn_types[]; 560 561 #endif /* _RISCV_H_ */ 562