1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright (C) 1993-2022 Free Software Foundation, Inc. 3 Contributed by Ralph Campbell and OSF 4 Commented and modified by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #ifndef _MIPS_H_ 24 #define _MIPS_H_ 25 26 #include "bfd.h" 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* These are bit masks and shift counts to use to access the various 33 fields of an instruction. To retrieve the X field of an 34 instruction, use the expression 35 (i >> OP_SH_X) & OP_MASK_X 36 To set the same field (to j), use 37 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 38 39 Make sure you use fields that are appropriate for the instruction, 40 of course. 41 42 The 'i' format uses OP, RS, RT and IMMEDIATE. 43 44 The 'j' format uses OP and TARGET. 45 46 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 47 48 The 'b' format uses OP, RS, RT and DELTA. 49 50 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 51 52 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 53 54 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 55 breakpoint instruction are not defined; Kane says the breakpoint 56 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 57 only use ten bits). An optional two-operand form of break/sdbbp 58 allows the lower ten bits to be set too, and MIPS32 and later 59 architectures allow 20 bits to be set with a single operand for 60 the sdbbp instruction (using CODE20). 61 62 The syscall instruction uses CODE20. 63 64 The general coprocessor instructions use COPZ. */ 65 66 #define OP_MASK_OP 0x3f 67 #define OP_SH_OP 26 68 #define OP_MASK_RS 0x1f 69 #define OP_SH_RS 21 70 #define OP_MASK_FR 0x1f 71 #define OP_SH_FR 21 72 #define OP_MASK_FMT 0x1f 73 #define OP_SH_FMT 21 74 #define OP_MASK_BCC 0x7 75 #define OP_SH_BCC 18 76 #define OP_MASK_CODE 0x3ff 77 #define OP_SH_CODE 16 78 #define OP_MASK_CODE2 0x3ff 79 #define OP_SH_CODE2 6 80 #define OP_MASK_RT 0x1f 81 #define OP_SH_RT 16 82 #define OP_MASK_FT 0x1f 83 #define OP_SH_FT 16 84 #define OP_MASK_CACHE 0x1f 85 #define OP_SH_CACHE 16 86 #define OP_MASK_RD 0x1f 87 #define OP_SH_RD 11 88 #define OP_MASK_FS 0x1f 89 #define OP_SH_FS 11 90 #define OP_MASK_PREFX 0x1f 91 #define OP_SH_PREFX 11 92 #define OP_MASK_CCC 0x7 93 #define OP_SH_CCC 8 94 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 95 #define OP_SH_CODE20 6 96 #define OP_MASK_SHAMT 0x1f 97 #define OP_SH_SHAMT 6 98 #define OP_MASK_EXTLSB OP_MASK_SHAMT 99 #define OP_SH_EXTLSB OP_SH_SHAMT 100 #define OP_MASK_STYPE OP_MASK_SHAMT 101 #define OP_SH_STYPE OP_SH_SHAMT 102 #define OP_MASK_FD 0x1f 103 #define OP_SH_FD 6 104 #define OP_MASK_TARGET 0x3ffffff 105 #define OP_SH_TARGET 0 106 #define OP_MASK_COPZ 0x1ffffff 107 #define OP_SH_COPZ 0 108 #define OP_MASK_IMMEDIATE 0xffff 109 #define OP_SH_IMMEDIATE 0 110 #define OP_MASK_DELTA 0xffff 111 #define OP_SH_DELTA 0 112 #define OP_MASK_FUNCT 0x3f 113 #define OP_SH_FUNCT 0 114 #define OP_MASK_SPEC 0x3f 115 #define OP_SH_SPEC 0 116 #define OP_SH_LOCC 8 /* FP condition code. */ 117 #define OP_SH_HICC 18 /* FP condition code. */ 118 #define OP_MASK_CC 0x7 119 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 120 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 121 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 122 #define OP_MASK_COP1SPEC 0xf 123 #define OP_MASK_COP1SCLR 0x4 124 #define OP_MASK_COP1CMP 0x3 125 #define OP_SH_COP1CMP 4 126 #define OP_SH_FORMAT 21 /* FP short format field. */ 127 #define OP_MASK_FORMAT 0x7 128 #define OP_SH_TRUE 16 129 #define OP_MASK_TRUE 0x1 130 #define OP_SH_GE 17 131 #define OP_MASK_GE 0x01 132 #define OP_SH_UNSIGNED 16 133 #define OP_MASK_UNSIGNED 0x1 134 #define OP_SH_HINT 16 135 #define OP_MASK_HINT 0x1f 136 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 137 #define OP_MASK_MMI 0x3f 138 #define OP_SH_MMISUB 6 139 #define OP_MASK_MMISUB 0x1f 140 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 141 #define OP_SH_PERFREG 1 142 #define OP_SH_SEL 0 /* Coprocessor select field. */ 143 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 144 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 145 #define OP_MASK_CODE19 0x7ffff 146 #define OP_SH_ALN 21 147 #define OP_MASK_ALN 0x7 148 #define OP_SH_VSEL 21 149 #define OP_MASK_VSEL 0x1f 150 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 151 but 0x8-0xf don't select bytes. */ 152 #define OP_SH_VECBYTE 22 153 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 154 #define OP_SH_VECALIGN 21 155 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 156 #define OP_SH_INSMSB 11 157 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 158 #define OP_SH_EXTMSBD 11 159 160 /* MIPS DSP ASE */ 161 #define OP_SH_DSPACC 11 162 #define OP_MASK_DSPACC 0x3 163 #define OP_SH_DSPACC_S 21 164 #define OP_MASK_DSPACC_S 0x3 165 #define OP_SH_DSPSFT 20 166 #define OP_MASK_DSPSFT 0x3f 167 #define OP_SH_DSPSFT_7 19 168 #define OP_MASK_DSPSFT_7 0x7f 169 #define OP_SH_SA3 21 170 #define OP_MASK_SA3 0x7 171 #define OP_SH_SA4 21 172 #define OP_MASK_SA4 0xf 173 #define OP_SH_IMM8 16 174 #define OP_MASK_IMM8 0xff 175 #define OP_SH_IMM10 16 176 #define OP_MASK_IMM10 0x3ff 177 #define OP_SH_WRDSP 11 178 #define OP_MASK_WRDSP 0x3f 179 #define OP_SH_RDDSP 16 180 #define OP_MASK_RDDSP 0x3f 181 #define OP_SH_BP 11 182 #define OP_MASK_BP 0x3 183 184 /* MIPS MT ASE */ 185 #define OP_SH_MT_U 5 186 #define OP_MASK_MT_U 0x1 187 #define OP_SH_MT_H 4 188 #define OP_MASK_MT_H 0x1 189 #define OP_SH_MTACC_T 18 190 #define OP_MASK_MTACC_T 0x3 191 #define OP_SH_MTACC_D 13 192 #define OP_MASK_MTACC_D 0x3 193 194 /* MIPS MCU ASE */ 195 #define OP_MASK_3BITPOS 0x7 196 #define OP_SH_3BITPOS 12 197 #define OP_MASK_OFFSET12 0xfff 198 #define OP_SH_OFFSET12 0 199 200 #define OP_OP_COP0 0x10 201 #define OP_OP_COP1 0x11 202 #define OP_OP_COP2 0x12 203 #define OP_OP_COP3 0x13 204 #define OP_OP_LWC1 0x31 205 #define OP_OP_LWC2 0x32 206 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 207 #define OP_OP_LDC1 0x35 208 #define OP_OP_LDC2 0x36 209 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 210 #define OP_OP_SWC1 0x39 211 #define OP_OP_SWC2 0x3a 212 #define OP_OP_SWC3 0x3b 213 #define OP_OP_SDC1 0x3d 214 #define OP_OP_SDC2 0x3e 215 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 216 217 /* MIPS VIRT ASE */ 218 #define OP_MASK_CODE10 0x3ff 219 #define OP_SH_CODE10 11 220 221 /* Values in the 'VSEL' field. */ 222 #define MDMX_FMTSEL_IMM_QH 0x1d 223 #define MDMX_FMTSEL_IMM_OB 0x1e 224 #define MDMX_FMTSEL_VEC_QH 0x15 225 #define MDMX_FMTSEL_VEC_OB 0x16 226 227 /* UDI */ 228 #define OP_SH_UDI1 6 229 #define OP_MASK_UDI1 0x1f 230 #define OP_SH_UDI2 6 231 #define OP_MASK_UDI2 0x3ff 232 #define OP_SH_UDI3 6 233 #define OP_MASK_UDI3 0x7fff 234 #define OP_SH_UDI4 6 235 #define OP_MASK_UDI4 0xfffff 236 237 /* Octeon */ 238 #define OP_SH_BBITIND 16 239 #define OP_MASK_BBITIND 0x1f 240 #define OP_SH_CINSPOS 6 241 #define OP_MASK_CINSPOS 0x1f 242 #define OP_SH_CINSLM1 11 243 #define OP_MASK_CINSLM1 0x1f 244 #define OP_SH_SEQI 6 245 #define OP_MASK_SEQI 0x3ff 246 247 /* Loongson */ 248 #define OP_SH_OFFSET_A 6 249 #define OP_MASK_OFFSET_A 0xff 250 #define OP_SH_OFFSET_B 3 251 #define OP_MASK_OFFSET_B 0xff 252 #define OP_SH_OFFSET_C 6 253 #define OP_MASK_OFFSET_C 0x1ff 254 #define OP_SH_RZ 0 255 #define OP_MASK_RZ 0x1f 256 #define OP_SH_FZ 0 257 #define OP_MASK_FZ 0x1f 258 259 /* Every MICROMIPSOP_X definition requires a corresponding OP_X 260 definition, and vice versa. This simplifies various parts 261 of the operand handling in GAS. The fields below only exist 262 in the microMIPS encoding, so define each one to have an empty 263 range. */ 264 #define OP_MASK_TRAP 0 265 #define OP_SH_TRAP 0 266 #define OP_MASK_OFFSET10 0 267 #define OP_SH_OFFSET10 0 268 #define OP_MASK_RS3 0 269 #define OP_SH_RS3 0 270 #define OP_MASK_MB 0 271 #define OP_SH_MB 0 272 #define OP_MASK_MC 0 273 #define OP_SH_MC 0 274 #define OP_MASK_MD 0 275 #define OP_SH_MD 0 276 #define OP_MASK_ME 0 277 #define OP_SH_ME 0 278 #define OP_MASK_MF 0 279 #define OP_SH_MF 0 280 #define OP_MASK_MG 0 281 #define OP_SH_MG 0 282 #define OP_MASK_MH 0 283 #define OP_SH_MH 0 284 #define OP_MASK_MJ 0 285 #define OP_SH_MJ 0 286 #define OP_MASK_ML 0 287 #define OP_SH_ML 0 288 #define OP_MASK_MM 0 289 #define OP_SH_MM 0 290 #define OP_MASK_MN 0 291 #define OP_SH_MN 0 292 #define OP_MASK_MP 0 293 #define OP_SH_MP 0 294 #define OP_MASK_MQ 0 295 #define OP_SH_MQ 0 296 #define OP_MASK_IMMA 0 297 #define OP_SH_IMMA 0 298 #define OP_MASK_IMMB 0 299 #define OP_SH_IMMB 0 300 #define OP_MASK_IMMC 0 301 #define OP_SH_IMMC 0 302 #define OP_MASK_IMMF 0 303 #define OP_SH_IMMF 0 304 #define OP_MASK_IMMG 0 305 #define OP_SH_IMMG 0 306 #define OP_MASK_IMMH 0 307 #define OP_SH_IMMH 0 308 #define OP_MASK_IMMI 0 309 #define OP_SH_IMMI 0 310 #define OP_MASK_IMMJ 0 311 #define OP_SH_IMMJ 0 312 #define OP_MASK_IMML 0 313 #define OP_SH_IMML 0 314 #define OP_MASK_IMMM 0 315 #define OP_SH_IMMM 0 316 #define OP_MASK_IMMN 0 317 #define OP_SH_IMMN 0 318 #define OP_MASK_IMMO 0 319 #define OP_SH_IMMO 0 320 #define OP_MASK_IMMP 0 321 #define OP_SH_IMMP 0 322 #define OP_MASK_IMMQ 0 323 #define OP_SH_IMMQ 0 324 #define OP_MASK_IMMU 0 325 #define OP_SH_IMMU 0 326 #define OP_MASK_IMMW 0 327 #define OP_SH_IMMW 0 328 #define OP_MASK_IMMX 0 329 #define OP_SH_IMMX 0 330 #define OP_MASK_IMMY 0 331 #define OP_SH_IMMY 0 332 333 /* Enhanced VA Scheme */ 334 #define OP_SH_EVAOFFSET 7 335 #define OP_MASK_EVAOFFSET 0x1ff 336 337 /* Enumerates the various types of MIPS operand. */ 338 enum mips_operand_type { 339 /* Described by mips_int_operand. */ 340 OP_INT, 341 342 /* Described by mips_mapped_int_operand. */ 343 OP_MAPPED_INT, 344 345 /* Described by mips_msb_operand. */ 346 OP_MSB, 347 348 /* Described by mips_reg_operand. */ 349 OP_REG, 350 351 /* Like OP_REG, but can be omitted if the register is the same as the 352 previous operand. */ 353 OP_OPTIONAL_REG, 354 355 /* Described by mips_reg_pair_operand. */ 356 OP_REG_PAIR, 357 358 /* Described by mips_pcrel_operand. */ 359 OP_PCREL, 360 361 /* A performance register. The field is 5 bits in size, but the supported 362 values are much more restricted. */ 363 OP_PERF_REG, 364 365 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts 366 as a normal 9-bit signed offset that is multiplied by four, but there 367 are four special cases: 368 369 -2 * 4 => -258 * 4 370 -1 * 4 => -257 * 4 371 0 * 4 => 256 * 4 372 1 * 4 => 257 * 4. */ 373 OP_ADDIUSP_INT, 374 375 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two 376 5-bit register fields, both of which must be set to the destination 377 register. */ 378 OP_CLO_CLZ_DEST, 379 380 /* A register list for a microMIPS LWM or SWM instruction. The operand 381 size determines whether the 16-bit or 32-bit encoding is required. */ 382 OP_LWM_SWM_LIST, 383 384 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ 385 OP_ENTRY_EXIT_LIST, 386 387 /* The register list and frame size for a MIPS16 SAVE or RESTORE 388 instruction. */ 389 OP_SAVE_RESTORE_LIST, 390 391 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: 392 393 V Meaning 394 ----- ------- 395 0EEE0 8 copies of $vN[E], OB format 396 0EE01 4 copies of $vN[E], QH format 397 10110 all 8 elements of $vN, OB format 398 10101 all 4 elements of $vN, QH format 399 11110 8 copies of immediate N, OB format 400 11101 4 copies of immediate N, QH format. */ 401 OP_MDMX_IMM_REG, 402 403 /* A register operand that must match the destination register. */ 404 OP_REPEAT_DEST_REG, 405 406 /* A register operand that must match the previous register. */ 407 OP_REPEAT_PREV_REG, 408 409 /* $pc, which has no encoding in the architectural instruction. */ 410 OP_PC, 411 412 /* $28, which has no encoding in the MIPS16e architectural instruction. */ 413 OP_REG28, 414 415 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines 416 which. */ 417 OP_VU0_SUFFIX, 418 419 /* Like OP_VU0_SUFFIX, but used when the operand's value has already 420 been set. Any suffix used here must match the previous value. */ 421 OP_VU0_MATCH_SUFFIX, 422 423 /* An index selected by an integer, e.g. [1]. */ 424 OP_IMM_INDEX, 425 426 /* An index selected by a register, e.g. [$2]. */ 427 OP_REG_INDEX, 428 429 /* The operand spans two 5-bit register fields, both of which must be set to 430 the source register. */ 431 OP_SAME_RS_RT, 432 433 /* Described by mips_prev_operand. */ 434 OP_CHECK_PREV, 435 436 /* A register operand that must not be zero. */ 437 OP_NON_ZERO_REG 438 }; 439 440 /* Enumerates the types of MIPS register. */ 441 enum mips_reg_operand_type { 442 /* General registers $0-$31. Software names like $at can also be used. */ 443 OP_REG_GP, 444 445 /* Floating-point registers $f0-$f31. */ 446 OP_REG_FP, 447 448 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes 449 can also be written $fcc0-$fcc7. */ 450 OP_REG_CCC, 451 452 /* FPRs used in a vector capacity. They can be written $f0-$f31 453 or $v0-$v31, although the latter form is not used for the VR5400 454 vector instructions. */ 455 OP_REG_VEC, 456 457 /* DSP accumulator registers $ac0-$ac3. */ 458 OP_REG_ACC, 459 460 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can 461 also be used in some contexts. */ 462 OP_REG_COPRO, 463 464 /* Coprocessor control registers $0-$31. Mnemonic names like c1_fcsr can 465 also be used in some contexts. */ 466 OP_REG_CONTROL, 467 468 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can 469 also be used in some contexts. */ 470 OP_REG_HW, 471 472 /* Floating-point registers $vf0-$vf31. */ 473 OP_REG_VF, 474 475 /* Integer registers $vi0-$vi31. */ 476 OP_REG_VI, 477 478 /* R5900 VU0 registers $I, $Q, $R and $ACC. */ 479 OP_REG_R5900_I, 480 OP_REG_R5900_Q, 481 OP_REG_R5900_R, 482 OP_REG_R5900_ACC, 483 484 /* MSA registers $w0-$w31. */ 485 OP_REG_MSA, 486 487 /* MSA control registers $0-$31. */ 488 OP_REG_MSA_CTRL 489 }; 490 491 /* Base class for all operands. */ 492 struct mips_operand 493 { 494 /* The type of the operand. */ 495 enum mips_operand_type type; 496 497 /* The operand occupies SIZE bits of the instruction, starting at LSB. */ 498 unsigned short size; 499 unsigned short lsb; 500 }; 501 502 /* Describes an integer operand with a regular encoding pattern. */ 503 struct mips_int_operand 504 { 505 struct mips_operand root; 506 507 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. 508 The cyclically previous field value encodes 1 << SHIFT less than that, 509 and so on. E.g. 510 511 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, 512 but 15 encodes -1. 513 514 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is 515 shifted left two places. 516 517 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except 518 that 0 encodes 8. 519 520 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ 521 unsigned int max_val; 522 int bias; 523 unsigned int shift; 524 525 /* True if the operand should be printed as hex rather than decimal. */ 526 bool print_hex; 527 }; 528 529 /* Uses a lookup table to describe a small integer operand. */ 530 struct mips_mapped_int_operand 531 { 532 struct mips_operand root; 533 534 /* Maps each encoding value to the integer that it represents. */ 535 const int *int_map; 536 537 /* True if the operand should be printed as hex rather than decimal. */ 538 bool print_hex; 539 }; 540 541 /* An operand that encodes the most significant bit position of a bitfield. 542 Given a bitfield that spans bits [MSB, LSB], some operands of this type 543 encode MSB directly while others encode MSB - LSB. Each operand of this 544 type is preceded by an integer operand that specifies LSB. 545 546 The assembly form varies between instructions. For some instructions, 547 such as EXT, the operand is written as the bitfield size. For others, 548 such as EXTS, it is written in raw MSB - LSB form. */ 549 struct mips_msb_operand 550 { 551 struct mips_operand root; 552 553 /* The assembly-level operand encoded by a field value of 0. */ 554 int bias; 555 556 /* True if the operand encodes MSB directly, false if it encodes 557 MSB - LSB. */ 558 bool add_lsb; 559 560 /* The maximum value of MSB + 1. */ 561 unsigned int opsize; 562 }; 563 564 /* Describes a single register operand. */ 565 struct mips_reg_operand 566 { 567 struct mips_operand root; 568 569 /* The type of register. */ 570 enum mips_reg_operand_type reg_type; 571 572 /* If nonnull, REG_MAP[N] gives the register associated with encoding N, 573 otherwise the encoding is the same as the register number. */ 574 const unsigned char *reg_map; 575 }; 576 577 /* Describes an operand that which must match a condition based on the 578 previous operand. */ 579 struct mips_check_prev_operand 580 { 581 struct mips_operand root; 582 583 bool greater_than_ok; 584 bool less_than_ok; 585 bool equal_ok; 586 bool zero_ok; 587 }; 588 589 /* Describes an operand that encodes a pair of registers. */ 590 struct mips_reg_pair_operand 591 { 592 struct mips_operand root; 593 594 /* The type of register. */ 595 enum mips_reg_operand_type reg_type; 596 597 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ 598 unsigned char *reg1_map; 599 unsigned char *reg2_map; 600 }; 601 602 /* Describes an operand that is calculated relative to a base PC. 603 The base PC is usually the address of the following instruction, 604 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ 605 struct mips_pcrel_operand 606 { 607 /* Encodes the offset. */ 608 struct mips_int_operand root; 609 610 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', 611 which is then added to the offset encoded by ROOT. */ 612 unsigned int align_log2 : 8; 613 614 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then 615 reinstated. This is true for jumps and branches and false for 616 PC-relative data instructions. */ 617 unsigned int include_isa_bit : 1; 618 619 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. 620 This is true for JALX and false otherwise. */ 621 unsigned int flip_isa_bit : 1; 622 }; 623 624 /* Return true if the assembly syntax allows OPERAND to be omitted. */ 625 626 static inline bool 627 mips_optional_operand_p (const struct mips_operand *operand) 628 { 629 return (operand->type == OP_OPTIONAL_REG 630 || operand->type == OP_REPEAT_PREV_REG); 631 } 632 633 /* Return a version of INSN in which the field specified by OPERAND 634 has value UVAL. */ 635 636 static inline unsigned int 637 mips_insert_operand (const struct mips_operand *operand, unsigned int insn, 638 unsigned int uval) 639 { 640 unsigned int mask; 641 642 mask = (1 << operand->size) - 1; 643 insn &= ~(mask << operand->lsb); 644 insn |= (uval & mask) << operand->lsb; 645 return insn; 646 } 647 648 /* Extract OPERAND from instruction INSN. */ 649 650 static inline unsigned int 651 mips_extract_operand (const struct mips_operand *operand, unsigned int insn) 652 { 653 return (insn >> operand->lsb) & ((1 << operand->size) - 1); 654 } 655 656 /* UVAL is the value encoded by OPERAND. Return it in signed form. */ 657 658 static inline int 659 mips_signed_operand (const struct mips_operand *operand, unsigned int uval) 660 { 661 unsigned int sign_bit, mask; 662 663 mask = (1 << operand->size) - 1; 664 sign_bit = 1 << (operand->size - 1); 665 return ((uval + sign_bit) & mask) - sign_bit; 666 } 667 668 /* Return the integer that OPERAND encodes as UVAL. */ 669 670 static inline int 671 mips_decode_int_operand (const struct mips_int_operand *operand, 672 unsigned int uval) 673 { 674 uval |= (operand->max_val - uval) & -(1 << operand->root.size); 675 uval += operand->bias; 676 uval <<= operand->shift; 677 return uval; 678 } 679 680 /* Return the maximum value that can be encoded by OPERAND. */ 681 682 static inline int 683 mips_int_operand_max (const struct mips_int_operand *operand) 684 { 685 return (operand->max_val + operand->bias) << operand->shift; 686 } 687 688 /* Return the minimum value that can be encoded by OPERAND. */ 689 690 static inline int 691 mips_int_operand_min (const struct mips_int_operand *operand) 692 { 693 unsigned int mask; 694 695 mask = (1 << operand->root.size) - 1; 696 return mips_int_operand_max (operand) - (mask << operand->shift); 697 } 698 699 /* Return the register that OPERAND encodes as UVAL. */ 700 701 static inline int 702 mips_decode_reg_operand (const struct mips_reg_operand *operand, 703 unsigned int uval) 704 { 705 if (operand->reg_map) 706 uval = operand->reg_map[uval]; 707 return uval; 708 } 709 710 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. 711 Return the address that it encodes. */ 712 713 static inline bfd_vma 714 mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, 715 bfd_vma base_pc, unsigned int uval) 716 { 717 bfd_vma addr; 718 719 addr = base_pc & -(1 << operand->align_log2); 720 addr += mips_decode_int_operand (&operand->root, uval); 721 if (operand->include_isa_bit) 722 addr |= base_pc & 1; 723 if (operand->flip_isa_bit) 724 addr ^= 1; 725 return addr; 726 } 727 728 /* This structure holds information for a particular instruction. */ 729 730 struct mips_opcode 731 { 732 /* The name of the instruction. */ 733 const char *name; 734 /* A string describing the arguments for this instruction. */ 735 const char *args; 736 /* The basic opcode for the instruction. When assembling, this 737 opcode is modified by the arguments to produce the actual opcode 738 that is used. If pinfo is INSN_MACRO, then this is 0. */ 739 unsigned long match; 740 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 741 relevant portions of the opcode when disassembling. If the 742 actual opcode anded with the match field equals the opcode field, 743 then we have found the correct instruction. If pinfo is 744 INSN_MACRO, then this field is the macro identifier. */ 745 unsigned long mask; 746 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 747 of bits describing the instruction, notably any relevant hazard 748 information. */ 749 unsigned long pinfo; 750 /* A collection of additional bits describing the instruction. */ 751 unsigned long pinfo2; 752 /* A collection of bits describing the instruction sets of which this 753 instruction or macro is a member. */ 754 unsigned long membership; 755 /* A collection of bits describing the ASE of which this instruction 756 or macro is a member. */ 757 unsigned long ase; 758 /* A collection of bits describing the instruction sets of which this 759 instruction or macro is not a member. */ 760 unsigned long exclusions; 761 }; 762 763 /* Return true if MO is an instruction that requires 32-bit encoding. */ 764 765 static inline bool 766 mips_opcode_32bit_p (const struct mips_opcode *mo) 767 { 768 return mo->mask >> 16 != 0; 769 } 770 771 /* These are the characters which may appear in the args field of an 772 instruction. They appear in the order in which the fields appear 773 when the instruction is used. Commas and parentheses in the args 774 string are ignored when assembling, and written into the output 775 when disassembling. 776 777 Each of these characters corresponds to a mask field defined above. 778 779 "1" 5 bit sync type (OP_*_STYPE) 780 "<" 5 bit shift amount (OP_*_SHAMT) 781 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 782 "a" 26 bit target address (OP_*_TARGET) 783 "+i" likewise, but flips bit 0 784 "b" 5 bit base register (OP_*_RS) 785 "c" 10 bit breakpoint code (OP_*_CODE) 786 "d" 5 bit destination register specifier (OP_*_RD) 787 "h" 5 bit prefx hint (OP_*_PREFX) 788 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 789 "j" 16 bit signed immediate (OP_*_DELTA) 790 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 791 "o" 16 bit signed offset (OP_*_DELTA) 792 "p" 16 bit PC relative branch target address (OP_*_DELTA) 793 "q" 10 bit extra breakpoint code (OP_*_CODE2) 794 "r" 5 bit same register used as both source and target (OP_*_RS) 795 "s" 5 bit source register specifier (OP_*_RS) 796 "t" 5 bit target register (OP_*_RT) 797 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 798 "v" 5 bit same register used as both source and destination (OP_*_RS) 799 "w" 5 bit same register used as both target and destination (OP_*_RT) 800 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 801 (used by clo and clz) 802 "C" 25 bit coprocessor function code (OP_*_COPZ) 803 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 804 "J" 19 bit wait function code (OP_*_CODE19) 805 "x" accept and ignore register name 806 "z" must be zero register 807 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 808 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 809 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for 810 microMIPS compatibility). 811 Enforces: 0 <= pos < 32. 812 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 813 Requires that "+A" or "+E" occur first to set position. 814 Enforces: 0 < (pos+size) <= 32. 815 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 816 Requires that "+A" or "+E" occur first to set position. 817 Enforces: 0 < (pos+size) <= 32. 818 (Also used by "dext" w/ different limits, but limits for 819 that are checked by the M_DEXT macro.) 820 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 821 Enforces: 32 <= pos < 64. 822 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 823 Requires that "+A" or "+E" occur first to set position. 824 Enforces: 32 < (pos+size) <= 64. 825 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 826 Requires that "+A" or "+E" occur first to set position. 827 Enforces: 32 < (pos+size) <= 64. 828 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 829 Requires that "+A" or "+E" occur first to set position. 830 Enforces: 32 < (pos+size) <= 64. 831 832 Floating point instructions: 833 "D" 5 bit destination register (OP_*_FD) 834 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 835 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 836 "S" 5 bit fs source 1 register (OP_*_FS) 837 "T" 5 bit ft source 2 register (OP_*_FT) 838 "R" 5 bit fr source 3 register (OP_*_FR) 839 "V" 5 bit same register used as floating source and destination (OP_*_FS) 840 "W" 5 bit same register used as floating target and destination (OP_*_FT) 841 842 Coprocessor instructions: 843 "E" 5 bit target register (OP_*_RT) 844 "G" 5 bit destination register (OP_*_RD) 845 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 846 "P" 5 bit performance-monitor register (OP_*_PERFREG) 847 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 848 "g" 5 bit control destination register (OP_*_RD) 849 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 850 851 Macro instructions: 852 "A" General 32 bit expression 853 "I" 32 bit immediate (value placed in imm_expr). 854 "F" 64 bit floating point constant in .rdata 855 "L" 64 bit floating point constant in .lit8 856 "f" 32 bit floating point constant 857 "l" 32 bit floating point constant in .lit4 858 859 MDMX and VR5400 instruction operands (note that while these use the 860 FP register fields, the MDMX instructions accept both $fN and $vN names 861 for the registers): 862 "O" alignment offset (OP_*_ALN) 863 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 864 "X" destination register (OP_*_FD) 865 "Y" source register (OP_*_FS) 866 "Z" source register (OP_*_FT) 867 868 R5900 VU0 Macromode instructions: 869 "+5" 5 bit floating point register (FD) 870 "+6" 5 bit floating point register (FS) 871 "+7" 5 bit floating point register (FT) 872 "+8" 5 bit integer register (FD) 873 "+9" 5 bit integer register (FS) 874 "+0" 5 bit integer register (FT) 875 "+K" match an existing 4-bit channel mask starting at bit 21 876 "+L" 2-bit channel index starting at bit 21 877 "+M" 2-bit channel index starting at bit 23 878 "+N" match an existing 2-bit channel index starting at bit 0 879 "+f" 15 bit immediate for VCALLMS 880 "+g" 5 bit signed immediate for VIADDI 881 "+m" $ACC register (syntax only) 882 "+q" $Q register (syntax only) 883 "+r" $R register (syntax only) 884 "+y" $I register (syntax only) 885 "#+" "++" decorator in ($reg++) sequence 886 "#-" "--" decorator in (--$reg) sequence 887 888 DSP ASE usage: 889 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 890 "3" 3 bit unsigned immediate (OP_*_SA3) 891 "4" 4 bit unsigned immediate (OP_*_SA4) 892 "5" 8 bit unsigned immediate (OP_*_IMM8) 893 "6" 5 bit unsigned immediate (OP_*_RS) 894 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 895 "8" 6 bit unsigned immediate (OP_*_WRDSP) 896 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 897 "0" 6 bit signed immediate (OP_*_DSPSFT) 898 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 899 "'" 6 bit unsigned immediate (OP_*_RDDSP) 900 "@" 10 bit signed immediate (OP_*_IMM10) 901 902 MT ASE usage: 903 "!" 1 bit usermode flag (OP_*_MT_U) 904 "$" 1 bit load high flag (OP_*_MT_H) 905 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 906 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 907 "y" 5 bit control target register (OP_*_RT) 908 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 909 910 MCU ASE usage: 911 "~" 12 bit offset (OP_*_OFFSET12) 912 "\" 3 bit position for aset and aclr (OP_*_3BITPOS) 913 914 VIRT ASE usage: 915 "+J" 10-bit hypcall code (OP_*CODE10) 916 917 UDI immediates: 918 "+1" UDI immediate bits 6-10 919 "+2" UDI immediate bits 6-15 920 "+3" UDI immediate bits 6-20 921 "+4" UDI immediate bits 6-25 922 923 Octeon: 924 "+x" Bit index field of bbit. Enforces: 0 <= index < 32. 925 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, 926 otherwise skips to next candidate. 927 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. 928 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if 929 32 <= pos < 64, otherwise skips to next candidate. 930 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. 931 "+s" Length-minus-one field of cins32/exts32. Requires msb position 932 of the field to be <= 31. 933 "+S" Length-minus-one field of cins/exts. Requires msb position 934 of the field to be <= 63. 935 936 Loongson-ext ASE: 937 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) 938 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) 939 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) 940 "+z" 5-bit rz register (OP_*_RZ) 941 "+Z" 5-bit fz register (OP_*_FZ) 942 943 interAptiv MR2: 944 "-m" register list for SAVE/RESTORE instruction 945 946 Enhanced VA Scheme: 947 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) 948 949 MSA Extension: 950 "+d" 5-bit MSA register (FD) 951 "+e" 5-bit MSA register (FS) 952 "+h" 5-bit MSA register (FT) 953 "+k" 5-bit GPR at bit 6 954 "+l" 5-bit MSA control register at bit 6 955 "+n" 5-bit MSA control register at bit 11 956 "+o" 4-bit vector element index at bit 16 957 "+u" 3-bit vector element index at bit 16 958 "+v" 2-bit vector element index at bit 16 959 "+w" 1-bit vector element index at bit 16 960 "+T" (-512 .. 511) << 0 at bit 16 961 "+U" (-512 .. 511) << 1 at bit 16 962 "+V" (-512 .. 511) << 2 at bit 16 963 "+W" (-512 .. 511) << 3 at bit 16 964 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 965 "+!" 3 bit unsigned bit position at bit 16 966 "+@" 4 bit unsigned bit position at bit 16 967 "+#" 6 bit unsigned bit position at bit 16 968 "+$" 5 bit unsigned immediate at bit 16 969 "+%" 5 bit signed immediate at bit 16 970 "+^" 10 bit signed immediate at bit 11 971 "+&" 0 vector element index 972 "+*" 5-bit register vector element index at bit 16 973 "+|" 8-bit mask at bit 16 974 975 MIPS R6: 976 "+:" 11-bit mask at bit 0 977 "+'" 26 bit PC relative branch target address 978 "+"" 21 bit PC relative branch target address 979 "+;" 5 bit same register in both OP_*_RS and OP_*_RT 980 "+I" 2bit unsigned bit position at bit 6 981 "+O" 3bit unsigned bit position at bit 6 982 "+R" must be program counter 983 "-a" (-262144 .. 262143) << 2 at bit 0 984 "-b" (-131072 .. 131071) << 3 at bit 0 985 "-d" Same as destination register GP 986 "-s" 5 bit source register specifier (OP_*_RS) not $0 987 "-t" 5 bit source register specifier (OP_*_RT) not $0 988 "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS 989 "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS 990 "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS 991 "-x" 5 bit source register specifier (OP_*_RT) greater than or 992 equal to OP_*_RS 993 "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS 994 "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 995 "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 996 997 GINV ASE usage: 998 "+\" 2 bit Global TLB invalidate type at bit 8 999 1000 Other: 1001 "()" parens surrounding optional value 1002 "," separates operands 1003 "+" Start of extension sequence. 1004 1005 Characters used so far, for quick reference when adding more: 1006 "1234567890" 1007 "%[]<>(),+-:'@!#$*&\~" 1008 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 1009 "abcdef hijkl opqrstuvwxyz" 1010 1011 Extension character sequences used so far ("+" followed by the 1012 following), for quick reference when adding more: 1013 "1234567890" 1014 "~!@#$%^&*|:'";\" 1015 "ABCEFGHIJKLMNOPQRSTUVWXZ" 1016 "abcdefghijklmnopqrstuvwxyz" 1017 1018 Extension character sequences used so far ("-" followed by the 1019 following), for quick reference when adding more: 1020 "AB" 1021 "abdmstuvwxy" 1022 */ 1023 1024 /* These are the bits which may be set in the pinfo field of an 1025 instructions, if it is not equal to INSN_MACRO. */ 1026 1027 /* Writes to operand number N. */ 1028 #define INSN_WRITE_SHIFT 0 1029 #define INSN_WRITE_1 0x00000001 1030 #define INSN_WRITE_2 0x00000002 1031 #define INSN_WRITE_ALL 0x00000003 1032 /* Reads from operand number N. */ 1033 #define INSN_READ_SHIFT 2 1034 #define INSN_READ_1 0x00000004 1035 #define INSN_READ_2 0x00000008 1036 #define INSN_READ_3 0x00000010 1037 #define INSN_READ_4 0x00000020 1038 #define INSN_READ_ALL 0x0000003c 1039 /* Modifies general purpose register 31. */ 1040 #define INSN_WRITE_GPR_31 0x00000040 1041 /* Modifies coprocessor condition code. */ 1042 #define INSN_WRITE_COND_CODE 0x00000080 1043 /* Reads coprocessor condition code. */ 1044 #define INSN_READ_COND_CODE 0x00000100 1045 /* TLB operation. */ 1046 #define INSN_TLB 0x00000200 1047 /* Reads coprocessor register other than floating point register. */ 1048 #define INSN_COP 0x00000400 1049 /* Instruction loads value from memory. */ 1050 #define INSN_LOAD_MEMORY 0x00000800 1051 /* Instruction loads value from coprocessor, (may require delay). */ 1052 #define INSN_LOAD_COPROC 0x00001000 1053 /* Instruction has unconditional branch delay slot. */ 1054 #define INSN_UNCOND_BRANCH_DELAY 0x00002000 1055 /* Instruction has conditional branch delay slot. */ 1056 #define INSN_COND_BRANCH_DELAY 0x00004000 1057 /* Conditional branch likely: if branch not taken, insn nullified. */ 1058 #define INSN_COND_BRANCH_LIKELY 0x00008000 1059 /* Moves to coprocessor register, (may require delay). */ 1060 #define INSN_COPROC_MOVE 0x00010000 1061 /* Loads coprocessor register from memory, requiring delay. */ 1062 #define INSN_COPROC_MEMORY_DELAY 0x00020000 1063 /* Reads the HI register. */ 1064 #define INSN_READ_HI 0x00040000 1065 /* Reads the LO register. */ 1066 #define INSN_READ_LO 0x00080000 1067 /* Modifies the HI register. */ 1068 #define INSN_WRITE_HI 0x00100000 1069 /* Modifies the LO register. */ 1070 #define INSN_WRITE_LO 0x00200000 1071 /* Not to be placed in a branch delay slot, either architecturally 1072 or for ease of handling (such as with instructions that take a trap). */ 1073 #define INSN_NO_DELAY_SLOT 0x00400000 1074 /* Instruction stores value into memory. */ 1075 #define INSN_STORE_MEMORY 0x00800000 1076 /* Instruction uses single precision floating point. */ 1077 #define FP_S 0x01000000 1078 /* Instruction uses double precision floating point. */ 1079 #define FP_D 0x02000000 1080 /* Instruction is part of the tx39's integer multiply family. */ 1081 #define INSN_MULT 0x04000000 1082 /* Reads general purpose register 24. */ 1083 #define INSN_READ_GPR_24 0x08000000 1084 /* Writes to general purpose register 24. */ 1085 #define INSN_WRITE_GPR_24 0x10000000 1086 /* A user-defined instruction. */ 1087 #define INSN_UDI 0x20000000 1088 /* Instruction is actually a macro. It should be ignored by the 1089 disassembler, and requires special treatment by the assembler. */ 1090 #define INSN_MACRO 0xffffffff 1091 1092 /* These are the bits which may be set in the pinfo2 field of an 1093 instruction. */ 1094 1095 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 1096 #define INSN2_ALIAS 0x00000001 1097 /* Instruction reads MDMX accumulator. */ 1098 #define INSN2_READ_MDMX_ACC 0x00000002 1099 /* Instruction writes MDMX accumulator. */ 1100 #define INSN2_WRITE_MDMX_ACC 0x00000004 1101 /* Macro uses single-precision floating-point instructions. This should 1102 only be set for macros. For instructions, FP_S in pinfo carries the 1103 same information. */ 1104 #define INSN2_M_FP_S 0x00000008 1105 /* Macro uses double-precision floating-point instructions. This should 1106 only be set for macros. For instructions, FP_D in pinfo carries the 1107 same information. */ 1108 #define INSN2_M_FP_D 0x00000010 1109 /* Instruction has a branch delay slot that requires a 16-bit instruction. */ 1110 #define INSN2_BRANCH_DELAY_16BIT 0x00000020 1111 /* Instruction has a branch delay slot that requires a 32-bit instruction. */ 1112 #define INSN2_BRANCH_DELAY_32BIT 0x00000040 1113 /* Writes to the stack pointer ($29). */ 1114 #define INSN2_WRITE_SP 0x00000080 1115 /* Reads from the stack pointer ($29). */ 1116 #define INSN2_READ_SP 0x00000100 1117 /* Reads the RA ($31) register. */ 1118 #define INSN2_READ_GPR_31 0x00000200 1119 /* Reads the program counter ($pc). */ 1120 #define INSN2_READ_PC 0x00000400 1121 /* Is an unconditional branch insn. */ 1122 #define INSN2_UNCOND_BRANCH 0x00000800 1123 /* Is a conditional branch insn. */ 1124 #define INSN2_COND_BRANCH 0x00001000 1125 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */ 1126 #define INSN2_READ_GPR_16 0x00002000 1127 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ 1128 #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 1129 /* Instruction has a forbidden slot. */ 1130 #define INSN2_FORBIDDEN_SLOT 0x00008000 1131 /* Opcode table entry is for a short MIPS16 form only. An extended 1132 encoding may still exist, but with a separate opcode table entry 1133 required. In disassembly the presence of this flag in an otherwise 1134 successful match against an extended instruction encoding inhibits 1135 matching against any subsequent short table entry even if it does 1136 not have this flag set. A table entry matching the full extended 1137 encoding is needed or otherwise the final EXTEND entry will apply, 1138 for the disassembly of the prefix only. */ 1139 #define INSN2_SHORT_ONLY 0x00010000 1140 1141 /* Masks used to mark instructions to indicate which MIPS ISA level 1142 they were introduced in. INSN_ISA_MASK masks an enumeration that 1143 specifies the base ISA level(s). The remainder of a 32-bit 1144 word constructed using these macros is a bitmask of the remaining 1145 INSN_* values below. */ 1146 1147 #define INSN_ISA_MASK 0x0000001ful 1148 1149 /* We cannot start at zero due to ISA_UNKNOWN below. */ 1150 #define INSN_ISA1 1 1151 #define INSN_ISA2 2 1152 #define INSN_ISA3 3 1153 #define INSN_ISA4 4 1154 #define INSN_ISA5 5 1155 #define INSN_ISA32 6 1156 #define INSN_ISA32R2 7 1157 #define INSN_ISA32R3 8 1158 #define INSN_ISA32R5 9 1159 #define INSN_ISA32R6 10 1160 #define INSN_ISA64 11 1161 #define INSN_ISA64R2 12 1162 #define INSN_ISA64R3 13 1163 #define INSN_ISA64R5 14 1164 #define INSN_ISA64R6 15 1165 /* Below this point the INSN_* values correspond to combinations of ISAs. 1166 They are only for use in the opcodes table to indicate membership of 1167 a combination of ISAs that cannot be expressed using the usual inclusion 1168 ordering on the above INSN_* values. */ 1169 #define INSN_ISA3_32 16 1170 #define INSN_ISA3_32R2 17 1171 #define INSN_ISA4_32 18 1172 #define INSN_ISA4_32R2 19 1173 #define INSN_ISA5_32R2 20 1174 1175 /* The R6 definitions shown below state that they support all previous ISAs. 1176 This is not actually true as some instructions are removed in R6. 1177 The problem is that the removed instructions in R6 come from different 1178 ISAs. One approach to solve this would be to describe in the membership 1179 field of the opcode table the different ISAs an instruction belongs to. 1180 This would require us to create a large amount of different ISA 1181 combinations which is hard to manage. A cleaner approach (which is 1182 implemented here) is to say that R6 is an extension of R5 and then to 1183 deal with the removed instructions by adding instruction exclusions 1184 for R6 in the opcode table. */ 1185 1186 /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ 1187 1188 #define ISAF(X) (1 << (INSN_ISA##X - 1)) 1189 #define INSN_UPTO1 ISAF(1) 1190 #define INSN_UPTO2 INSN_UPTO1 | ISAF(2) 1191 #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) 1192 #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) 1193 #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) 1194 #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) 1195 #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ 1196 | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) 1197 #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) 1198 #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) 1199 #define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) 1200 #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) 1201 #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) 1202 #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) 1203 #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) 1204 #define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) 1205 1206 /* The same information in table form: bit INSN_ISA<X> - 1 of index 1207 INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ 1208 static const unsigned int mips_isa_table[] = { 1209 INSN_UPTO1, 1210 INSN_UPTO2, 1211 INSN_UPTO3, 1212 INSN_UPTO4, 1213 INSN_UPTO5, 1214 INSN_UPTO32, 1215 INSN_UPTO32R2, 1216 INSN_UPTO32R3, 1217 INSN_UPTO32R5, 1218 INSN_UPTO32R6, 1219 INSN_UPTO64, 1220 INSN_UPTO64R2, 1221 INSN_UPTO64R3, 1222 INSN_UPTO64R5, 1223 INSN_UPTO64R6 1224 }; 1225 #undef ISAF 1226 1227 /* Masks used for Chip specific instructions. */ 1228 #define INSN_CHIP_MASK 0xc7ff4f60 1229 1230 /* Cavium Networks Octeon instructions. */ 1231 #define INSN_OCTEON 0x00000800 1232 #define INSN_OCTEONP 0x00000200 1233 #define INSN_OCTEON2 0x00000100 1234 #define INSN_OCTEON3 0x00000040 1235 1236 /* MIPS R5900 instruction */ 1237 #define INSN_5900 0x00004000 1238 1239 /* MIPS R4650 instruction. */ 1240 #define INSN_4650 0x00010000 1241 /* LSI R4010 instruction. */ 1242 #define INSN_4010 0x00020000 1243 /* NEC VR4100 instruction. */ 1244 #define INSN_4100 0x00040000 1245 /* Toshiba R3900 instruction. */ 1246 #define INSN_3900 0x00080000 1247 /* MIPS R10000 instruction. */ 1248 #define INSN_10000 0x00100000 1249 /* Broadcom SB-1 instruction. */ 1250 #define INSN_SB1 0x00200000 1251 /* NEC VR4111/VR4181 instruction. */ 1252 #define INSN_4111 0x00400000 1253 /* NEC VR4120 instruction. */ 1254 #define INSN_4120 0x00800000 1255 /* NEC VR5400 instruction. */ 1256 #define INSN_5400 0x01000000 1257 /* NEC VR5500 instruction. */ 1258 #define INSN_5500 0x02000000 1259 1260 /* ST Microelectronics Loongson 2E. */ 1261 #define INSN_LOONGSON_2E 0x40000000 1262 /* ST Microelectronics Loongson 2F. */ 1263 #define INSN_LOONGSON_2F 0x80000000 1264 /* RMI Xlr instruction */ 1265 #define INSN_XLR 0x00000020 1266 /* Imagination interAptiv MR2. */ 1267 #define INSN_INTERAPTIV_MR2 0x04000000 1268 1269 /* DSP ASE */ 1270 #define ASE_DSP 0x00000001 1271 #define ASE_DSP64 0x00000002 1272 /* DSP R2 ASE */ 1273 #define ASE_DSPR2 0x00000004 1274 /* Enhanced VA Scheme */ 1275 #define ASE_EVA 0x00000008 1276 /* MCU (MicroController) ASE */ 1277 #define ASE_MCU 0x00000010 1278 /* MDMX ASE */ 1279 #define ASE_MDMX 0x00000020 1280 /* MIPS-3D ASE */ 1281 #define ASE_MIPS3D 0x00000040 1282 /* MT ASE */ 1283 #define ASE_MT 0x00000080 1284 /* SmartMIPS ASE */ 1285 #define ASE_SMARTMIPS 0x00000100 1286 /* Virtualization ASE */ 1287 #define ASE_VIRT 0x00000200 1288 #define ASE_VIRT64 0x00000400 1289 /* MSA Extension */ 1290 #define ASE_MSA 0x00000800 1291 #define ASE_MSA64 0x00001000 1292 /* eXtended Physical Address (XPA) Extension. */ 1293 #define ASE_XPA 0x00002000 1294 /* DSP R3 Module. */ 1295 #define ASE_DSPR3 0x00004000 1296 /* MIPS16e2 ASE. */ 1297 #define ASE_MIPS16E2 0x00008000 1298 /* MIPS16e2 MT ASE instructions. */ 1299 #define ASE_MIPS16E2_MT 0x00010000 1300 /* The Virtualization ASE has eXtended Physical Addressing (XPA) 1301 instructions which are only valid when both ASEs are enabled. */ 1302 #define ASE_XPA_VIRT 0x00020000 1303 /* Cyclic redundancy check (CRC) ASE. */ 1304 #define ASE_CRC 0x00040000 1305 #define ASE_CRC64 0x00080000 1306 /* Global INValidate Extension. */ 1307 #define ASE_GINV 0x00100000 1308 /* Loongson MultiMedia extensions Instructions (MMI). */ 1309 #define ASE_LOONGSON_MMI 0x00200000 1310 /* Loongson Content Address Memory (CAM). */ 1311 #define ASE_LOONGSON_CAM 0x00400000 1312 /* Loongson EXTensions (EXT) instructions. */ 1313 #define ASE_LOONGSON_EXT 0x00800000 1314 /* Loongson EXTensions R2 (EXT2) instructions. */ 1315 #define ASE_LOONGSON_EXT2 0x01000000 1316 /* The Enhanced VA Scheme (EVA) extension has instructions which are 1317 only valid for the R6 ISA. */ 1318 #define ASE_EVA_R6 0x02000000 1319 1320 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 1321 1322 #define ISA_UNKNOWN 0 /* Gas internal use. */ 1323 #define ISA_MIPS1 INSN_ISA1 1324 #define ISA_MIPS2 INSN_ISA2 1325 #define ISA_MIPS3 INSN_ISA3 1326 #define ISA_MIPS4 INSN_ISA4 1327 #define ISA_MIPS5 INSN_ISA5 1328 1329 #define ISA_MIPS32 INSN_ISA32 1330 #define ISA_MIPS64 INSN_ISA64 1331 1332 #define ISA_MIPS32R2 INSN_ISA32R2 1333 #define ISA_MIPS32R3 INSN_ISA32R3 1334 #define ISA_MIPS32R5 INSN_ISA32R5 1335 #define ISA_MIPS64R2 INSN_ISA64R2 1336 #define ISA_MIPS64R3 INSN_ISA64R3 1337 #define ISA_MIPS64R5 INSN_ISA64R5 1338 1339 #define ISA_MIPS32R6 INSN_ISA32R6 1340 #define ISA_MIPS64R6 INSN_ISA64R6 1341 1342 /* CPU defines, use instead of hardcoding processor number. Keep this 1343 in sync with bfd/archures.c in order for machine selection to work. */ 1344 #define CPU_UNKNOWN 0 /* Gas internal use. */ 1345 #define CPU_R3000 3000 1346 #define CPU_R3900 3900 1347 #define CPU_R4000 4000 1348 #define CPU_R4010 4010 1349 #define CPU_VR4100 4100 1350 #define CPU_R4111 4111 1351 #define CPU_VR4120 4120 1352 #define CPU_R4300 4300 1353 #define CPU_R4400 4400 1354 #define CPU_R4600 4600 1355 #define CPU_R4650 4650 1356 #define CPU_R5000 5000 1357 #define CPU_VR5400 5400 1358 #define CPU_VR5500 5500 1359 #define CPU_R5900 5900 1360 #define CPU_R6000 6000 1361 #define CPU_RM7000 7000 1362 #define CPU_R8000 8000 1363 #define CPU_RM9000 9000 1364 #define CPU_R10000 10000 1365 #define CPU_R12000 12000 1366 #define CPU_R14000 14000 1367 #define CPU_R16000 16000 1368 #define CPU_MIPS16 16 1369 #define CPU_MIPS32 32 1370 #define CPU_MIPS32R2 33 1371 #define CPU_MIPS32R3 34 1372 #define CPU_MIPS32R5 36 1373 #define CPU_MIPS32R6 37 1374 #define CPU_MIPS5 5 1375 #define CPU_MIPS64 64 1376 #define CPU_MIPS64R2 65 1377 #define CPU_MIPS64R3 66 1378 #define CPU_MIPS64R5 68 1379 #define CPU_MIPS64R6 69 1380 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 1381 #define CPU_LOONGSON_2E 3001 1382 #define CPU_LOONGSON_2F 3002 1383 #define CPU_GS464 3003 1384 #define CPU_GS464E 3004 1385 #define CPU_GS264E 3005 1386 #define CPU_OCTEON 6501 1387 #define CPU_OCTEONP 6601 1388 #define CPU_OCTEON2 6502 1389 #define CPU_OCTEON3 6503 1390 #define CPU_XLR 887682 /* decimal 'XLR' */ 1391 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ 1392 1393 /* Return true if the given CPU is included in INSN_* mask MASK. */ 1394 1395 static inline bool 1396 cpu_is_member (int cpu, unsigned int mask) 1397 { 1398 switch (cpu) 1399 { 1400 case CPU_R4650: 1401 case CPU_RM7000: 1402 case CPU_RM9000: 1403 return (mask & INSN_4650) != 0; 1404 1405 case CPU_R4010: 1406 return (mask & INSN_4010) != 0; 1407 1408 case CPU_VR4100: 1409 return (mask & INSN_4100) != 0; 1410 1411 case CPU_R3900: 1412 return (mask & INSN_3900) != 0; 1413 1414 case CPU_R10000: 1415 case CPU_R12000: 1416 case CPU_R14000: 1417 case CPU_R16000: 1418 return (mask & INSN_10000) != 0; 1419 1420 case CPU_SB1: 1421 return (mask & INSN_SB1) != 0; 1422 1423 case CPU_R4111: 1424 return (mask & INSN_4111) != 0; 1425 1426 case CPU_VR4120: 1427 return (mask & INSN_4120) != 0; 1428 1429 case CPU_VR5400: 1430 return (mask & INSN_5400) != 0; 1431 1432 case CPU_VR5500: 1433 return (mask & INSN_5500) != 0; 1434 1435 case CPU_R5900: 1436 return (mask & INSN_5900) != 0; 1437 1438 case CPU_LOONGSON_2E: 1439 return (mask & INSN_LOONGSON_2E) != 0; 1440 1441 case CPU_LOONGSON_2F: 1442 return (mask & INSN_LOONGSON_2F) != 0; 1443 1444 case CPU_OCTEON: 1445 return (mask & INSN_OCTEON) != 0; 1446 1447 case CPU_OCTEONP: 1448 return (mask & INSN_OCTEONP) != 0; 1449 1450 case CPU_OCTEON2: 1451 return (mask & INSN_OCTEON2) != 0; 1452 1453 case CPU_OCTEON3: 1454 return (mask & INSN_OCTEON3) != 0; 1455 1456 case CPU_XLR: 1457 return (mask & INSN_XLR) != 0; 1458 1459 case CPU_INTERAPTIV_MR2: 1460 return (mask & INSN_INTERAPTIV_MR2) != 0; 1461 1462 default: 1463 return false; 1464 } 1465 } 1466 1467 /* Return true if the given ISA is included in INSN_* mask MASK. */ 1468 1469 static inline bool 1470 isa_is_member (int isa, unsigned int mask) 1471 { 1472 isa &= INSN_ISA_MASK; 1473 mask &= INSN_ISA_MASK; 1474 1475 if (isa == 0) 1476 return false; 1477 1478 if (mask == 0) 1479 return false; 1480 1481 if (((mips_isa_table[isa - 1] >> (mask - 1)) & 1) == 0) 1482 return false; 1483 1484 return true; 1485 } 1486 1487 /* Test for membership in an ISA including chip specific ISAs. INSN 1488 is pointer to an element of the opcode table; ISA is the specified 1489 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 1490 test, or zero if no CPU specific ISA test is desired. Return true 1491 if instruction INSN is available to the given ISA and CPU. */ 1492 1493 static inline bool 1494 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) 1495 { 1496 /* Test for ISA level exclusion. */ 1497 if (isa_is_member (isa, insn->exclusions)) 1498 return false; 1499 1500 /* Test for processor-specific exclusion. */ 1501 if (cpu_is_member (cpu, insn->exclusions)) 1502 return false; 1503 1504 /* Test for ISA level compatibility. */ 1505 if (isa_is_member (isa, insn->membership)) 1506 return true; 1507 1508 /* Test for ASE compatibility. */ 1509 if ((ase & insn->ase) != 0) 1510 return true; 1511 1512 /* Test for processor-specific extensions. */ 1513 if (cpu_is_member (cpu, insn->membership)) 1514 return true; 1515 1516 return false; 1517 } 1518 1519 /* This is a list of macro expanded instructions. 1520 1521 _I appended means immediate 1522 _A appended means target address of a jump 1523 _AB appended means address with (possibly zero) base register 1524 _D appended means 64 bit floating point constant 1525 _S appended means 32 bit floating point constant. */ 1526 1527 enum 1528 { 1529 M_ABS, 1530 M_ACLR_AB, 1531 M_ADD_I, 1532 M_ADDU_I, 1533 M_AND_I, 1534 M_ASET_AB, 1535 M_BALIGN, 1536 M_BC1FL, 1537 M_BC1TL, 1538 M_BC2FL, 1539 M_BC2TL, 1540 M_BEQ, 1541 M_BEQ_I, 1542 M_BEQL, 1543 M_BEQL_I, 1544 M_BGE, 1545 M_BGEL, 1546 M_BGE_I, 1547 M_BGEL_I, 1548 M_BGEU, 1549 M_BGEUL, 1550 M_BGEU_I, 1551 M_BGEUL_I, 1552 M_BGEZ, 1553 M_BGEZL, 1554 M_BGEZALL, 1555 M_BGT, 1556 M_BGTL, 1557 M_BGT_I, 1558 M_BGTL_I, 1559 M_BGTU, 1560 M_BGTUL, 1561 M_BGTU_I, 1562 M_BGTUL_I, 1563 M_BGTZ, 1564 M_BGTZL, 1565 M_BLE, 1566 M_BLEL, 1567 M_BLE_I, 1568 M_BLEL_I, 1569 M_BLEU, 1570 M_BLEUL, 1571 M_BLEU_I, 1572 M_BLEUL_I, 1573 M_BLEZ, 1574 M_BLEZL, 1575 M_BLT, 1576 M_BLTL, 1577 M_BLT_I, 1578 M_BLTL_I, 1579 M_BLTU, 1580 M_BLTUL, 1581 M_BLTU_I, 1582 M_BLTUL_I, 1583 M_BLTZ, 1584 M_BLTZL, 1585 M_BLTZALL, 1586 M_BNE, 1587 M_BNEL, 1588 M_BNE_I, 1589 M_BNEL_I, 1590 M_CACHE_AB, 1591 M_CACHEE_AB, 1592 M_DABS, 1593 M_DADD_I, 1594 M_DADDU_I, 1595 M_DDIV_3, 1596 M_DDIV_3I, 1597 M_DDIVU_3, 1598 M_DDIVU_3I, 1599 M_DIV_3, 1600 M_DIV_3I, 1601 M_DIVU_3, 1602 M_DIVU_3I, 1603 M_DLA_AB, 1604 M_DLCA_AB, 1605 M_DLI, 1606 M_DMUL, 1607 M_DMUL_I, 1608 M_DMULO, 1609 M_DMULO_I, 1610 M_DMULOU, 1611 M_DMULOU_I, 1612 M_DREM_3, 1613 M_DREM_3I, 1614 M_DREMU_3, 1615 M_DREMU_3I, 1616 M_DSUB_I, 1617 M_DSUBU_I, 1618 M_DSUBU_I_2, 1619 M_J_A, 1620 M_JAL_1, 1621 M_JAL_2, 1622 M_JAL_A, 1623 M_JALS_1, 1624 M_JALS_2, 1625 M_JALS_A, 1626 M_JRADDIUSP, 1627 M_JRC, 1628 M_L_DAB, 1629 M_LA_AB, 1630 M_LB_AB, 1631 M_LBE_AB, 1632 M_LBU_AB, 1633 M_LBUE_AB, 1634 M_LCA_AB, 1635 M_LD_AB, 1636 M_LDC1_AB, 1637 M_LDC2_AB, 1638 M_LQC2_AB, 1639 M_LDC3_AB, 1640 M_LDL_AB, 1641 M_LDM_AB, 1642 M_LDP_AB, 1643 M_LDR_AB, 1644 M_LH_AB, 1645 M_LHE_AB, 1646 M_LHU_AB, 1647 M_LHUE_AB, 1648 M_LI, 1649 M_LI_D, 1650 M_LI_DD, 1651 M_LI_S, 1652 M_LI_SS, 1653 M_LL_AB, 1654 M_LLD_AB, 1655 M_LLDP_AB, 1656 M_LLE_AB, 1657 M_LLWP_AB, 1658 M_LLWPE_AB, 1659 M_LQ_AB, 1660 M_LW_AB, 1661 M_LWE_AB, 1662 M_LWC0_AB, 1663 M_LWC1_AB, 1664 M_LWC2_AB, 1665 M_LWC3_AB, 1666 M_LWL_AB, 1667 M_LWLE_AB, 1668 M_LWM_AB, 1669 M_LWP_AB, 1670 M_LWR_AB, 1671 M_LWRE_AB, 1672 M_LWU_AB, 1673 M_MSGSND, 1674 M_MSGLD, 1675 M_MSGLD_T, 1676 M_MSGWAIT, 1677 M_MSGWAIT_T, 1678 M_MOVE, 1679 M_MOVEP, 1680 M_MUL, 1681 M_MUL_I, 1682 M_MULO, 1683 M_MULO_I, 1684 M_MULOU, 1685 M_MULOU_I, 1686 M_NOR_I, 1687 M_OR_I, 1688 M_PREF_AB, 1689 M_PREFE_AB, 1690 M_REM_3, 1691 M_REM_3I, 1692 M_REMU_3, 1693 M_REMU_3I, 1694 M_DROL, 1695 M_ROL, 1696 M_DROL_I, 1697 M_ROL_I, 1698 M_DROR, 1699 M_ROR, 1700 M_DROR_I, 1701 M_ROR_I, 1702 M_S_DA, 1703 M_S_DAB, 1704 M_S_S, 1705 M_SAA_AB, 1706 M_SAAD_AB, 1707 M_SC_AB, 1708 M_SCD_AB, 1709 M_SCDP_AB, 1710 M_SCE_AB, 1711 M_SCWP_AB, 1712 M_SCWPE_AB, 1713 M_SD_AB, 1714 M_SDC1_AB, 1715 M_SDC2_AB, 1716 M_SQC2_AB, 1717 M_SDC3_AB, 1718 M_SDL_AB, 1719 M_SDM_AB, 1720 M_SDP_AB, 1721 M_SDR_AB, 1722 M_SEQ, 1723 M_SEQ_I, 1724 M_SGE, 1725 M_SGE_I, 1726 M_SGEU, 1727 M_SGEU_I, 1728 M_SGT, 1729 M_SGT_I, 1730 M_SGTU, 1731 M_SGTU_I, 1732 M_SLE, 1733 M_SLE_I, 1734 M_SLEU, 1735 M_SLEU_I, 1736 M_SLT_I, 1737 M_SLTU_I, 1738 M_SNE, 1739 M_SNE_I, 1740 M_SB_AB, 1741 M_SBE_AB, 1742 M_SH_AB, 1743 M_SHE_AB, 1744 M_SQ_AB, 1745 M_SW_AB, 1746 M_SWE_AB, 1747 M_SWC0_AB, 1748 M_SWC1_AB, 1749 M_SWC2_AB, 1750 M_SWC3_AB, 1751 M_SWL_AB, 1752 M_SWLE_AB, 1753 M_SWM_AB, 1754 M_SWP_AB, 1755 M_SWR_AB, 1756 M_SWRE_AB, 1757 M_SUB_I, 1758 M_SUBU_I, 1759 M_SUBU_I_2, 1760 M_TEQ_I, 1761 M_TGE_I, 1762 M_TGEU_I, 1763 M_TLT_I, 1764 M_TLTU_I, 1765 M_TNE_I, 1766 M_TRUNCWD, 1767 M_TRUNCWS, 1768 M_ULD_AB, 1769 M_ULH_AB, 1770 M_ULHU_AB, 1771 M_ULW_AB, 1772 M_USH_AB, 1773 M_USW_AB, 1774 M_USD_AB, 1775 M_XOR_I, 1776 M_COP0, 1777 M_COP1, 1778 M_COP2, 1779 M_COP3, 1780 M_NUM_MACROS 1781 }; 1782 1783 1784 /* The order of overloaded instructions matters. Label arguments and 1785 register arguments look the same. Instructions that can have either 1786 for arguments must apear in the correct order in this table for the 1787 assembler to pick the right one. In other words, entries with 1788 immediate operands must apear after the same instruction with 1789 registers. 1790 1791 Many instructions are short hand for other instructions (i.e., The 1792 jal <register> instruction is short for jalr <register>). */ 1793 1794 extern const struct mips_operand mips_vu0_channel_mask; 1795 extern const struct mips_operand *decode_mips_operand (const char *); 1796 extern const struct mips_opcode mips_builtin_opcodes[]; 1797 extern const int bfd_mips_num_builtin_opcodes; 1798 extern struct mips_opcode *mips_opcodes; 1799 extern int bfd_mips_num_opcodes; 1800 #define NUMOPCODES bfd_mips_num_opcodes 1801 1802 1803 /* The rest of this file adds definitions for the mips16 TinyRISC 1804 processor. */ 1805 1806 /* These are the bitmasks and shift counts used for the different 1807 fields in the instruction formats. Other than OP, no masks are 1808 provided for the fixed portions of an instruction, since they are 1809 not needed. 1810 1811 The I format uses IMM11. 1812 1813 The RI format uses RX and IMM8. 1814 1815 The RR format uses RX, and RY. 1816 1817 The RRI format uses RX, RY, and IMM5. 1818 1819 The RRR format uses RX, RY, and RZ. 1820 1821 The RRI_A format uses RX, RY, and IMM4. 1822 1823 The SHIFT format uses RX, RY, and SHAMT. 1824 1825 The I8 format uses IMM8. 1826 1827 The I8_MOVR32 format uses RY and REGR32. 1828 1829 The IR_MOV32R format uses REG32R and MOV32Z. 1830 1831 The I64 format uses IMM8. 1832 1833 The RI64 format uses RY and IMM5. 1834 */ 1835 1836 #define MIPS16OP_MASK_OP 0x1f 1837 #define MIPS16OP_SH_OP 11 1838 #define MIPS16OP_MASK_IMM11 0x7ff 1839 #define MIPS16OP_SH_IMM11 0 1840 #define MIPS16OP_MASK_RX 0x7 1841 #define MIPS16OP_SH_RX 8 1842 #define MIPS16OP_MASK_IMM8 0xff 1843 #define MIPS16OP_SH_IMM8 0 1844 #define MIPS16OP_MASK_RY 0x7 1845 #define MIPS16OP_SH_RY 5 1846 #define MIPS16OP_MASK_IMM5 0x1f 1847 #define MIPS16OP_SH_IMM5 0 1848 #define MIPS16OP_MASK_RZ 0x7 1849 #define MIPS16OP_SH_RZ 2 1850 #define MIPS16OP_MASK_IMM4 0xf 1851 #define MIPS16OP_SH_IMM4 0 1852 #define MIPS16OP_MASK_REGR32 0x1f 1853 #define MIPS16OP_SH_REGR32 0 1854 #define MIPS16OP_MASK_REG32R 0x1f 1855 #define MIPS16OP_SH_REG32R 3 1856 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 1857 #define MIPS16OP_MASK_MOVE32Z 0x7 1858 #define MIPS16OP_SH_MOVE32Z 0 1859 #define MIPS16OP_MASK_IMM6 0x3f 1860 #define MIPS16OP_SH_IMM6 5 1861 1862 /* These are the characters which may appears in the args field of a MIPS16 1863 instruction. They appear in the order in which the fields appear when the 1864 instruction is used. Commas and parentheses in the args string are ignored 1865 when assembling, and written into the output when disassembling. 1866 1867 "y" 3 bit register (MIPS16OP_*_RY) 1868 "x" 3 bit register (MIPS16OP_*_RX) 1869 "z" 3 bit register (MIPS16OP_*_RZ) 1870 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 1871 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 1872 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 1873 "." zero register ($0) 1874 "S" stack pointer ($sp or $29) 1875 "P" program counter 1876 "R" return address register ($ra or $31) 1877 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 1878 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 1879 "0" 5-bit ASMACRO p0 immediate 1880 "1" 3-bit ASMACRO p1 immediate 1881 "2" 3-bit ASMACRO p2 immediate 1882 "3" 5-bit ASMACRO p3 immediate 1883 "4" 3-bit ASMACRO p4 immediate 1884 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 1885 "a" 26 bit jump address 1886 "i" likewise, but flips bit 0 1887 "e" 11 bit extension value 1888 "l" register list for entry instruction 1889 "L" register list for exit instruction 1890 ">" 5-bit SYNC code 1891 "9" 9-bit signed immediate 1892 "G" global pointer ($gp or $28) 1893 "N" 5-bit coprocessor register 1894 "O" 3-bit sel field for MFC0/MTC0 1895 "Q" 5-bit hardware register 1896 "T" 5-bit CACHE opcode or PREF hint 1897 "b" 5-bit INS/EXT position, which becomes LSB 1898 Enforces: 0 <= pos < 32. 1899 "c" 5-bit INS size, which becomes MSB 1900 Requires that "b" occurs first to set position. 1901 Enforces: 0 < (pos+size) <= 32. 1902 "d" 5-bit EXT size, which becomes MSBD 1903 Requires that "b" occurs first to set position. 1904 Enforces: 0 < (pos+size) <= 32. 1905 "n" 2-bit immediate (1 .. 4) 1906 "o" 5-bit unsigned immediate * 16 1907 "r" 3-bit register 1908 "s" 3-bit ASMACRO select immediate 1909 "u" 16-bit unsigned immediate 1910 1911 "I" an immediate value used for macros 1912 1913 The remaining codes may be extended. Except as otherwise noted, 1914 the full extended operand is a 16 bit signed value. 1915 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 1916 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 1917 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 1918 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 1919 "F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 1920 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 1921 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 1922 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 1923 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 1924 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1925 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1926 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1927 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1928 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1929 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1930 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1931 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1932 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1933 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1934 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1935 "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended) 1936 1937 Characters used so far, for quick reference when adding more: 1938 "0123456 89" 1939 ".[]<>" 1940 "ABCDEFGHI KL NOPQRSTUVWXYZ" 1941 "abcde ijklmnopqrs uvwxyz" 1942 */ 1943 1944 /* Save/restore encoding for the args field when all 4 registers are 1945 either saved as arguments or saved/restored as statics. */ 1946 #define MIPS_SVRS_ALL_ARGS 0xe 1947 #define MIPS_SVRS_ALL_STATICS 0xb 1948 1949 /* The following flags have the same value for the mips16 opcode 1950 table: 1951 1952 INSN_ISA3 1953 1954 INSN_UNCOND_BRANCH_DELAY 1955 INSN_COND_BRANCH_DELAY 1956 INSN_COND_BRANCH_LIKELY (never used) 1957 INSN_READ_HI 1958 INSN_READ_LO 1959 INSN_WRITE_HI 1960 INSN_WRITE_LO 1961 INSN_TRAP 1962 FP_D (never used) 1963 */ 1964 1965 extern const struct mips_operand *decode_mips16_operand (char, bool); 1966 extern const struct mips_opcode mips16_opcodes[]; 1967 extern const int bfd_mips16_num_opcodes; 1968 1969 /* These are the bit masks and shift counts used for the different fields 1970 in the microMIPS instruction formats. No masks are provided for the 1971 fixed portions of an instruction, since they are not needed. */ 1972 1973 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff 1974 #define MICROMIPSOP_SH_IMMEDIATE 0 1975 #define MICROMIPSOP_MASK_DELTA 0xffff 1976 #define MICROMIPSOP_SH_DELTA 0 1977 #define MICROMIPSOP_MASK_CODE10 0x3ff 1978 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ 1979 #define MICROMIPSOP_MASK_TRAP 0xf 1980 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ 1981 #define MICROMIPSOP_MASK_SHAMT 0x1f 1982 #define MICROMIPSOP_SH_SHAMT 11 1983 #define MICROMIPSOP_MASK_TARGET 0x3ffffff 1984 #define MICROMIPSOP_SH_TARGET 0 1985 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ 1986 #define MICROMIPSOP_SH_EXTLSB 6 1987 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 1988 #define MICROMIPSOP_SH_EXTMSBD 11 1989 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ 1990 #define MICROMIPSOP_SH_INSMSB 11 1991 #define MICROMIPSOP_MASK_CODE 0x3ff 1992 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ 1993 #define MICROMIPSOP_MASK_CODE2 0x3ff 1994 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ 1995 #define MICROMIPSOP_MASK_CACHE 0x1f 1996 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ 1997 #define MICROMIPSOP_MASK_SEL 0x7 1998 #define MICROMIPSOP_SH_SEL 11 1999 #define MICROMIPSOP_MASK_OFFSET12 0xfff 2000 #define MICROMIPSOP_SH_OFFSET12 0 2001 #define MICROMIPSOP_MASK_3BITPOS 0x7 2002 #define MICROMIPSOP_SH_3BITPOS 21 2003 #define MICROMIPSOP_MASK_STYPE 0x1f 2004 #define MICROMIPSOP_SH_STYPE 16 2005 #define MICROMIPSOP_MASK_OFFSET10 0x3ff 2006 #define MICROMIPSOP_SH_OFFSET10 6 2007 #define MICROMIPSOP_MASK_RS 0x1f 2008 #define MICROMIPSOP_SH_RS 16 2009 #define MICROMIPSOP_MASK_RT 0x1f 2010 #define MICROMIPSOP_SH_RT 21 2011 #define MICROMIPSOP_MASK_RD 0x1f 2012 #define MICROMIPSOP_SH_RD 11 2013 #define MICROMIPSOP_MASK_FS 0x1f 2014 #define MICROMIPSOP_SH_FS 16 2015 #define MICROMIPSOP_MASK_FT 0x1f 2016 #define MICROMIPSOP_SH_FT 21 2017 #define MICROMIPSOP_MASK_FD 0x1f 2018 #define MICROMIPSOP_SH_FD 11 2019 #define MICROMIPSOP_MASK_FR 0x1f 2020 #define MICROMIPSOP_SH_FR 6 2021 #define MICROMIPSOP_MASK_RS3 0x1f 2022 #define MICROMIPSOP_SH_RS3 6 2023 #define MICROMIPSOP_MASK_PREFX 0x1f 2024 #define MICROMIPSOP_SH_PREFX 11 2025 #define MICROMIPSOP_MASK_BCC 0x7 2026 #define MICROMIPSOP_SH_BCC 18 2027 #define MICROMIPSOP_MASK_CCC 0x7 2028 #define MICROMIPSOP_SH_CCC 13 2029 #define MICROMIPSOP_MASK_COPZ 0x7fffff 2030 #define MICROMIPSOP_SH_COPZ 3 2031 2032 #define MICROMIPSOP_MASK_MB 0x7 2033 #define MICROMIPSOP_SH_MB 23 2034 #define MICROMIPSOP_MASK_MC 0x7 2035 #define MICROMIPSOP_SH_MC 4 2036 #define MICROMIPSOP_MASK_MD 0x7 2037 #define MICROMIPSOP_SH_MD 7 2038 #define MICROMIPSOP_MASK_ME 0x7 2039 #define MICROMIPSOP_SH_ME 1 2040 #define MICROMIPSOP_MASK_MF 0x7 2041 #define MICROMIPSOP_SH_MF 3 2042 #define MICROMIPSOP_MASK_MG 0x7 2043 #define MICROMIPSOP_SH_MG 0 2044 #define MICROMIPSOP_MASK_MH 0x7 2045 #define MICROMIPSOP_SH_MH 7 2046 #define MICROMIPSOP_MASK_MJ 0x1f 2047 #define MICROMIPSOP_SH_MJ 0 2048 #define MICROMIPSOP_MASK_ML 0x7 2049 #define MICROMIPSOP_SH_ML 4 2050 #define MICROMIPSOP_MASK_MM 0x7 2051 #define MICROMIPSOP_SH_MM 1 2052 #define MICROMIPSOP_MASK_MN 0x7 2053 #define MICROMIPSOP_SH_MN 4 2054 #define MICROMIPSOP_MASK_MP 0x1f 2055 #define MICROMIPSOP_SH_MP 5 2056 #define MICROMIPSOP_MASK_MQ 0x7 2057 #define MICROMIPSOP_SH_MQ 7 2058 2059 #define MICROMIPSOP_MASK_IMMA 0x7f 2060 #define MICROMIPSOP_SH_IMMA 0 2061 #define MICROMIPSOP_MASK_IMMB 0x7 2062 #define MICROMIPSOP_SH_IMMB 1 2063 #define MICROMIPSOP_MASK_IMMC 0xf 2064 #define MICROMIPSOP_SH_IMMC 0 2065 #define MICROMIPSOP_MASK_IMMD 0x3ff 2066 #define MICROMIPSOP_SH_IMMD 0 2067 #define MICROMIPSOP_MASK_IMME 0x7f 2068 #define MICROMIPSOP_SH_IMME 0 2069 #define MICROMIPSOP_MASK_IMMF 0xf 2070 #define MICROMIPSOP_SH_IMMF 0 2071 #define MICROMIPSOP_MASK_IMMG 0xf 2072 #define MICROMIPSOP_SH_IMMG 0 2073 #define MICROMIPSOP_MASK_IMMH 0xf 2074 #define MICROMIPSOP_SH_IMMH 0 2075 #define MICROMIPSOP_MASK_IMMI 0x7f 2076 #define MICROMIPSOP_SH_IMMI 0 2077 #define MICROMIPSOP_MASK_IMMJ 0xf 2078 #define MICROMIPSOP_SH_IMMJ 0 2079 #define MICROMIPSOP_MASK_IMML 0xf 2080 #define MICROMIPSOP_SH_IMML 0 2081 #define MICROMIPSOP_MASK_IMMM 0x7 2082 #define MICROMIPSOP_SH_IMMM 1 2083 #define MICROMIPSOP_MASK_IMMN 0x3 2084 #define MICROMIPSOP_SH_IMMN 4 2085 #define MICROMIPSOP_MASK_IMMO 0xf 2086 #define MICROMIPSOP_SH_IMMO 0 2087 #define MICROMIPSOP_MASK_IMMP 0x1f 2088 #define MICROMIPSOP_SH_IMMP 0 2089 #define MICROMIPSOP_MASK_IMMQ 0x7fffff 2090 #define MICROMIPSOP_SH_IMMQ 0 2091 #define MICROMIPSOP_MASK_IMMU 0x1f 2092 #define MICROMIPSOP_SH_IMMU 0 2093 #define MICROMIPSOP_MASK_IMMW 0x3f 2094 #define MICROMIPSOP_SH_IMMW 1 2095 #define MICROMIPSOP_MASK_IMMX 0xf 2096 #define MICROMIPSOP_SH_IMMX 1 2097 #define MICROMIPSOP_MASK_IMMY 0x1ff 2098 #define MICROMIPSOP_SH_IMMY 1 2099 2100 /* MIPS DSP ASE */ 2101 #define MICROMIPSOP_MASK_DSPACC 0x3 2102 #define MICROMIPSOP_SH_DSPACC 14 2103 #define MICROMIPSOP_MASK_DSPSFT 0x3f 2104 #define MICROMIPSOP_SH_DSPSFT 16 2105 #define MICROMIPSOP_MASK_SA3 0x7 2106 #define MICROMIPSOP_SH_SA3 13 2107 #define MICROMIPSOP_MASK_SA4 0xf 2108 #define MICROMIPSOP_SH_SA4 12 2109 #define MICROMIPSOP_MASK_IMM8 0xff 2110 #define MICROMIPSOP_SH_IMM8 13 2111 #define MICROMIPSOP_MASK_IMM10 0x3ff 2112 #define MICROMIPSOP_SH_IMM10 16 2113 #define MICROMIPSOP_MASK_WRDSP 0x3f 2114 #define MICROMIPSOP_SH_WRDSP 14 2115 #define MICROMIPSOP_MASK_BP 0x3 2116 #define MICROMIPSOP_SH_BP 14 2117 2118 /* Placeholders for fields that only exist in the traditional 32-bit 2119 instruction encoding; see the comment above for details. */ 2120 #define MICROMIPSOP_MASK_CODE20 0 2121 #define MICROMIPSOP_SH_CODE20 0 2122 #define MICROMIPSOP_MASK_PERFREG 0 2123 #define MICROMIPSOP_SH_PERFREG 0 2124 #define MICROMIPSOP_MASK_CODE19 0 2125 #define MICROMIPSOP_SH_CODE19 0 2126 #define MICROMIPSOP_MASK_ALN 0 2127 #define MICROMIPSOP_SH_ALN 0 2128 #define MICROMIPSOP_MASK_VECBYTE 0 2129 #define MICROMIPSOP_SH_VECBYTE 0 2130 #define MICROMIPSOP_MASK_VECALIGN 0 2131 #define MICROMIPSOP_SH_VECALIGN 0 2132 #define MICROMIPSOP_MASK_DSPACC_S 0 2133 #define MICROMIPSOP_SH_DSPACC_S 0 2134 #define MICROMIPSOP_MASK_DSPSFT_7 0 2135 #define MICROMIPSOP_SH_DSPSFT_7 0 2136 #define MICROMIPSOP_MASK_RDDSP 0 2137 #define MICROMIPSOP_SH_RDDSP 0 2138 #define MICROMIPSOP_MASK_MT_U 0 2139 #define MICROMIPSOP_SH_MT_U 0 2140 #define MICROMIPSOP_MASK_MT_H 0 2141 #define MICROMIPSOP_SH_MT_H 0 2142 #define MICROMIPSOP_MASK_MTACC_T 0 2143 #define MICROMIPSOP_SH_MTACC_T 0 2144 #define MICROMIPSOP_MASK_MTACC_D 0 2145 #define MICROMIPSOP_SH_MTACC_D 0 2146 #define MICROMIPSOP_MASK_BBITIND 0 2147 #define MICROMIPSOP_SH_BBITIND 0 2148 #define MICROMIPSOP_MASK_CINSPOS 0 2149 #define MICROMIPSOP_SH_CINSPOS 0 2150 #define MICROMIPSOP_MASK_CINSLM1 0 2151 #define MICROMIPSOP_SH_CINSLM1 0 2152 #define MICROMIPSOP_MASK_SEQI 0 2153 #define MICROMIPSOP_SH_SEQI 0 2154 #define MICROMIPSOP_SH_OFFSET_A 0 2155 #define MICROMIPSOP_MASK_OFFSET_A 0 2156 #define MICROMIPSOP_SH_OFFSET_B 0 2157 #define MICROMIPSOP_MASK_OFFSET_B 0 2158 #define MICROMIPSOP_SH_OFFSET_C 0 2159 #define MICROMIPSOP_MASK_OFFSET_C 0 2160 #define MICROMIPSOP_SH_RZ 0 2161 #define MICROMIPSOP_MASK_RZ 0 2162 #define MICROMIPSOP_SH_FZ 0 2163 #define MICROMIPSOP_MASK_FZ 0 2164 2165 /* microMIPS Enhanced VA Scheme */ 2166 #define MICROMIPSOP_SH_EVAOFFSET 0 2167 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff 2168 2169 /* These are the characters which may appears in the args field of a microMIPS 2170 instruction. They appear in the order in which the fields appear 2171 when the instruction is used. Commas and parentheses in the args 2172 string are ignored when assembling, and written into the output 2173 when disassembling. 2174 2175 The followings are for 16-bit microMIPS instructions. 2176 2177 "ma" must be $28 2178 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 2179 The same register used as both source and target. 2180 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 2181 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 2182 The same register used as both source and target. 2183 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 2184 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 2185 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 2186 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 2187 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 2188 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 2189 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 2190 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 2191 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 2192 "mr" must be program counter 2193 "ms" must be $29 2194 "mt" must be the same as the previous register 2195 "mx" must be the same as the destination register 2196 "my" must be $31 2197 "mz" must be $0 2198 2199 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) 2200 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) 2201 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, 2202 32768, 65535) (MICROMIPSOP_*_IMMC) 2203 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) 2204 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) 2205 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) 2206 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) 2207 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) 2208 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) 2209 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) 2210 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2211 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) 2212 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) 2213 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2214 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) 2215 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) 2216 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) 2217 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) 2218 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) 2219 "mZ" must be zero 2220 2221 In most cases 32-bit microMIPS instructions use the same characters 2222 as MIPS (with ADDIUPC being a notable exception, but there are some 2223 others too). 2224 2225 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) 2226 "1" 5-bit sync type (MICROMIPSOP_*_STYPE) 2227 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) 2228 ">" shift amount between 32 and 63, stored after subtracting 32 2229 (MICROMIPSOP_*_SHAMT) 2230 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) 2231 "|" 4-bit trap code (MICROMIPSOP_*_TRAP) 2232 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) 2233 "a" 26-bit target address (MICROMIPSOP_*_TARGET) 2234 "+i" likewise, but flips bit 0 2235 "b" 5-bit base register (MICROMIPSOP_*_RS) 2236 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) 2237 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) 2238 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) 2239 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) 2240 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) 2241 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) 2242 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) 2243 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) 2244 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) 2245 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) 2246 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) 2247 "s" 5-bit source register specifier (MICROMIPSOP_*_RS) 2248 "t" 5-bit target register (MICROMIPSOP_*_RT) 2249 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) 2250 "v" 5-bit same register used as both source and destination 2251 (MICROMIPSOP_*_RS) 2252 "w" 5-bit same register used as both target and destination 2253 (MICROMIPSOP_*_RT) 2254 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) 2255 "z" must be zero register 2256 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) 2257 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) 2258 2259 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes 2260 LSB (MICROMIPSOP_*_EXTLSB). 2261 Enforces: 0 <= pos < 32. 2262 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). 2263 Requires that "+A" or "+E" occur first to set position. 2264 Enforces: 0 < (pos+size) <= 32. 2265 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2266 Requires that "+A" or "+E" occur first to set position. 2267 Enforces: 0 < (pos+size) <= 32. 2268 (Also used by DEXT w/ different limits, but limits for 2269 that are checked by the M_DEXT macro.) 2270 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). 2271 Enforces: 32 <= pos < 64. 2272 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). 2273 Requires that "+A" or "+E" occur first to set position. 2274 Enforces: 32 < (pos+size) <= 64. 2275 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). 2276 Requires that "+A" or "+E" occur first to set position. 2277 Enforces: 32 < (pos+size) <= 64. 2278 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2279 Requires that "+A" or "+E" occur first to set position. 2280 Enforces: 32 < (pos+size) <= 64. 2281 "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code 2282 (MICROMIPSOP_*_CODE10) 2283 2284 PC-relative addition (ADDIUPC) instruction: 2285 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) 2286 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 2287 2288 Floating point instructions: 2289 "D" 5-bit destination register (MICROMIPSOP_*_FD) 2290 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) 2291 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) 2292 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) 2293 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) 2294 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) 2295 "V" 5-bit same register used as floating source and destination or target 2296 (MICROMIPSOP_*_FS) 2297 2298 Coprocessor instructions: 2299 "E" 5-bit target register (MICROMIPSOP_*_RT) 2300 "G" 5-bit source register (MICROMIPSOP_*_RS) 2301 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) 2302 "g" 5-bit control source register (MICROMIPSOP_*_RS) 2303 2304 Macro instructions: 2305 "A" general 32 bit expression 2306 "I" 32-bit immediate (value placed in imm_expr). 2307 "F" 64-bit floating point constant in .rdata 2308 "L" 64-bit floating point constant in .lit8 2309 "f" 32-bit floating point constant 2310 "l" 32-bit floating point constant in .lit4 2311 2312 DSP ASE usage: 2313 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) 2314 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) 2315 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) 2316 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) 2317 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) 2318 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) 2319 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) 2320 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) 2321 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) 2322 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) 2323 2324 microMIPS Enhanced VA Scheme: 2325 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) 2326 2327 MSA Extension: 2328 "+d" 5-bit MSA register (FD) 2329 "+e" 5-bit MSA register (FS) 2330 "+h" 5-bit MSA register (FT) 2331 "+k" 5-bit GPR at bit 6 2332 "+l" 5-bit MSA control register at bit 6 2333 "+n" 5-bit MSA control register at bit 11 2334 "+o" 4-bit vector element index at bit 16 2335 "+u" 3-bit vector element index at bit 16 2336 "+v" 2-bit vector element index at bit 16 2337 "+w" 1-bit vector element index at bit 16 2338 "+x" 5-bit shift amount at bit 16 2339 "+T" (-512 .. 511) << 0 at bit 16 2340 "+U" (-512 .. 511) << 1 at bit 16 2341 "+V" (-512 .. 511) << 2 at bit 16 2342 "+W" (-512 .. 511) << 3 at bit 16 2343 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 2344 "+!" 3 bit unsigned bit position at bit 16 2345 "+@" 4 bit unsigned bit position at bit 16 2346 "+#" 6 bit unsigned bit position at bit 16 2347 "+$" 5 bit unsigned immediate at bit 16 2348 "+%" 5 bit signed immediate at bit 16 2349 "+^" 10 bit signed immediate at bit 11 2350 "+&" 0 vector element index 2351 "+*" 5-bit register vector element index at bit 16 2352 "+|" 8-bit mask at bit 16 2353 2354 Other: 2355 "()" parens surrounding optional value 2356 "," separates operands 2357 "+" start of extension sequence 2358 "m" start of microMIPS extension sequence 2359 2360 Characters used so far, for quick reference when adding more: 2361 "12345678 0" 2362 "<>(),+-.@\^|~" 2363 "ABCDEFGHI KLMN RST V " 2364 "abcd fghijklmnopqrstuvw yz" 2365 2366 Extension character sequences used so far ("+" followed by the 2367 following), for quick reference when adding more: 2368 "" 2369 "~!@#$%^&*|" 2370 "ABCEFGHJTUVW" 2371 "dehijklnouvwx" 2372 2373 Extension character sequences used so far ("m" followed by the 2374 following), for quick reference when adding more: 2375 "" 2376 "" 2377 " BCDEFGHIJ LMNOPQ U WXYZ" 2378 " bcdefghij lmn pq st xyz" 2379 2380 Extension character sequences used so far ("-" followed by the 2381 following), for quick reference when adding more: 2382 "" 2383 "" 2384 <none so far> 2385 */ 2386 2387 extern const struct mips_operand *decode_micromips_operand (const char *); 2388 extern const struct mips_opcode micromips_opcodes[]; 2389 extern const int bfd_micromips_num_opcodes; 2390 2391 /* A NOP insn impemented as "or at,at,zero". 2392 Used to implement -mfix-loongson2f. */ 2393 #define LOONGSON2F_NOP_INSN 0x00200825 2394 2395 #ifdef __cplusplus 2396 } 2397 #endif 2398 2399 #endif /* _MIPS_H_ */ 2400