1 /* Target-dependent code for SPARC. 2 3 Copyright (C) 2003-2023 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "arch-utils.h" 22 #include "dis-asm.h" 23 #include "dwarf2.h" 24 #include "dwarf2/frame.h" 25 #include "frame.h" 26 #include "frame-base.h" 27 #include "frame-unwind.h" 28 #include "gdbcore.h" 29 #include "gdbtypes.h" 30 #include "inferior.h" 31 #include "symtab.h" 32 #include "objfiles.h" 33 #include "osabi.h" 34 #include "regcache.h" 35 #include "target.h" 36 #include "target-descriptions.h" 37 #include "value.h" 38 39 #include "sparc-tdep.h" 40 #include "sparc-ravenscar-thread.h" 41 #include <algorithm> 42 43 struct regset; 44 45 /* This file implements the SPARC 32-bit ABI as defined by the section 46 "Low-Level System Information" of the SPARC Compliance Definition 47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD 48 lists changes with respect to the original 32-bit psABI as defined 49 in the "System V ABI, SPARC Processor Supplement". 50 51 Note that if we talk about SunOS, we mean SunOS 4.x, which was 52 BSD-based, which is sometimes (retroactively?) referred to as 53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and 54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 55 suffering from severe version number inflation). Solaris 2.x is 56 also known as SunOS 5.x, since that's what uname(1) says. Solaris 57 2.x is SVR4-based. */ 58 59 /* Please use the sparc32_-prefix for 32-bit specific code, the 60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for 61 code that can handle both. The 64-bit specific code lives in 62 sparc64-tdep.c; don't add any here. */ 63 64 /* The stack pointer is offset from the stack frame by a BIAS of 2047 65 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC 66 hosts, so undefine it first. */ 67 #undef BIAS 68 #define BIAS 2047 69 70 /* Macros to extract fields from SPARC instructions. */ 71 #define X_OP(i) (((i) >> 30) & 0x3) 72 #define X_RD(i) (((i) >> 25) & 0x1f) 73 #define X_A(i) (((i) >> 29) & 1) 74 #define X_COND(i) (((i) >> 25) & 0xf) 75 #define X_OP2(i) (((i) >> 22) & 0x7) 76 #define X_IMM22(i) ((i) & 0x3fffff) 77 #define X_OP3(i) (((i) >> 19) & 0x3f) 78 #define X_RS1(i) (((i) >> 14) & 0x1f) 79 #define X_RS2(i) ((i) & 0x1f) 80 #define X_I(i) (((i) >> 13) & 1) 81 /* Sign extension macros. */ 82 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) 83 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) 84 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) 85 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) 86 /* Macros to identify some instructions. */ 87 /* RETURN (RETT in V8) */ 88 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) 89 90 /* Fetch the instruction at PC. Instructions are always big-endian 91 even if the processor operates in little-endian mode. */ 92 93 unsigned long 94 sparc_fetch_instruction (CORE_ADDR pc) 95 { 96 gdb_byte buf[4]; 97 unsigned long insn; 98 int i; 99 100 /* If we can't read the instruction at PC, return zero. */ 101 if (target_read_memory (pc, buf, sizeof (buf))) 102 return 0; 103 104 insn = 0; 105 for (i = 0; i < sizeof (buf); i++) 106 insn = (insn << 8) | buf[i]; 107 return insn; 108 } 109 110 111 /* Return non-zero if the instruction corresponding to PC is an "unimp" 112 instruction. */ 113 114 static int 115 sparc_is_unimp_insn (CORE_ADDR pc) 116 { 117 const unsigned long insn = sparc_fetch_instruction (pc); 118 119 return ((insn & 0xc1c00000) == 0); 120 } 121 122 /* Return non-zero if the instruction corresponding to PC is an 123 "annulled" branch, i.e. the annul bit is set. */ 124 125 int 126 sparc_is_annulled_branch_insn (CORE_ADDR pc) 127 { 128 /* The branch instructions featuring an annul bit can be identified 129 by the following bit patterns: 130 131 OP=0 132 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). 133 OP2=2: Branch on Integer Condition Codes (Bcc). 134 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). 135 OP2=6: Branch on FP Condition Codes (FBcc). 136 OP2=3 && Bit28=0: 137 Branch on Integer Register with Prediction (BPr). 138 139 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 140 coprocessor branch instructions (Op2=7). */ 141 142 const unsigned long insn = sparc_fetch_instruction (pc); 143 const unsigned op2 = X_OP2 (insn); 144 145 if ((X_OP (insn) == 0) 146 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) 147 || ((op2 == 3) && ((insn & 0x10000000) == 0)))) 148 return X_A (insn); 149 else 150 return 0; 151 } 152 153 /* OpenBSD/sparc includes StackGhost, which according to the author's 154 website http://stackghost.cerias.purdue.edu "... transparently and 155 automatically protects applications' stack frames; more 156 specifically, it guards the return pointers. The protection 157 mechanisms require no application source or binary modification and 158 imposes only a negligible performance penalty." 159 160 The same website provides the following description of how 161 StackGhost works: 162 163 "StackGhost interfaces with the kernel trap handler that would 164 normally write out registers to the stack and the handler that 165 would read them back in. By XORing a cookie into the 166 return-address saved in the user stack when it is actually written 167 to the stack, and then XOR it out when the return-address is pulled 168 from the stack, StackGhost can cause attacker corrupted return 169 pointers to behave in a manner the attacker cannot predict. 170 StackGhost can also use several unused bits in the return pointer 171 to detect a smashed return pointer and abort the process." 172 173 For GDB this means that whenever we're reading %i7 from a stack 174 frame's window save area, we'll have to XOR the cookie. 175 176 More information on StackGuard can be found on in: 177 178 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated 179 Stack Protection." 2001. Published in USENIX Security Symposium 180 '01. */ 181 182 /* Fetch StackGhost Per-Process XOR cookie. */ 183 184 ULONGEST 185 sparc_fetch_wcookie (struct gdbarch *gdbarch) 186 { 187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 188 struct target_ops *ops = current_inferior ()->top_target (); 189 gdb_byte buf[8]; 190 int len; 191 192 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); 193 if (len == -1) 194 return 0; 195 196 /* We should have either an 32-bit or an 64-bit cookie. */ 197 gdb_assert (len == 4 || len == 8); 198 199 return extract_unsigned_integer (buf, len, byte_order); 200 } 201 202 203 /* The functions on this page are intended to be used to classify 204 function arguments. */ 205 206 /* Check whether TYPE is "Integral or Pointer". */ 207 208 static int 209 sparc_integral_or_pointer_p (const struct type *type) 210 { 211 int len = type->length (); 212 213 switch (type->code ()) 214 { 215 case TYPE_CODE_INT: 216 case TYPE_CODE_BOOL: 217 case TYPE_CODE_CHAR: 218 case TYPE_CODE_ENUM: 219 case TYPE_CODE_RANGE: 220 /* We have byte, half-word, word and extended-word/doubleword 221 integral types. The doubleword is an extension to the 222 original 32-bit ABI by the SCD 2.4.x. */ 223 return (len == 1 || len == 2 || len == 4 || len == 8); 224 case TYPE_CODE_PTR: 225 case TYPE_CODE_REF: 226 case TYPE_CODE_RVALUE_REF: 227 /* Allow either 32-bit or 64-bit pointers. */ 228 return (len == 4 || len == 8); 229 default: 230 break; 231 } 232 233 return 0; 234 } 235 236 /* Check whether TYPE is "Floating". */ 237 238 static int 239 sparc_floating_p (const struct type *type) 240 { 241 switch (type->code ()) 242 { 243 case TYPE_CODE_FLT: 244 { 245 int len = type->length (); 246 return (len == 4 || len == 8 || len == 16); 247 } 248 default: 249 break; 250 } 251 252 return 0; 253 } 254 255 /* Check whether TYPE is "Complex Floating". */ 256 257 static int 258 sparc_complex_floating_p (const struct type *type) 259 { 260 switch (type->code ()) 261 { 262 case TYPE_CODE_COMPLEX: 263 { 264 int len = type->length (); 265 return (len == 8 || len == 16 || len == 32); 266 } 267 default: 268 break; 269 } 270 271 return 0; 272 } 273 274 /* Check whether TYPE is "Structure or Union". 275 276 In terms of Ada subprogram calls, arrays are treated the same as 277 struct and union types. So this function also returns non-zero 278 for array types. */ 279 280 static int 281 sparc_structure_or_union_p (const struct type *type) 282 { 283 switch (type->code ()) 284 { 285 case TYPE_CODE_STRUCT: 286 case TYPE_CODE_UNION: 287 case TYPE_CODE_ARRAY: 288 return 1; 289 default: 290 break; 291 } 292 293 return 0; 294 } 295 296 /* Return true if TYPE is returned by memory, false if returned by 297 register. */ 298 299 static bool 300 sparc_structure_return_p (const struct type *type) 301 { 302 if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) 303 { 304 /* Float vectors are always returned by memory. */ 305 if (sparc_floating_p (check_typedef (type->target_type ()))) 306 return true; 307 /* Integer vectors are returned by memory if the vector size 308 is greater than 8 bytes long. */ 309 return (type->length () > 8); 310 } 311 312 if (sparc_floating_p (type)) 313 { 314 /* Floating point types are passed by register for size 4 and 315 8 bytes, and by memory for size 16 bytes. */ 316 return (type->length () == 16); 317 } 318 319 /* Other than that, only aggregates of all sizes get returned by 320 memory. */ 321 return sparc_structure_or_union_p (type); 322 } 323 324 /* Return true if arguments of the given TYPE are passed by 325 memory; false if returned by register. */ 326 327 static bool 328 sparc_arg_by_memory_p (const struct type *type) 329 { 330 if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) 331 { 332 /* Float vectors are always passed by memory. */ 333 if (sparc_floating_p (check_typedef (type->target_type ()))) 334 return true; 335 /* Integer vectors are passed by memory if the vector size 336 is greater than 8 bytes long. */ 337 return (type->length () > 8); 338 } 339 340 /* Floats are passed by register for size 4 and 8 bytes, and by memory 341 for size 16 bytes. */ 342 if (sparc_floating_p (type)) 343 return (type->length () == 16); 344 345 /* Complex floats and aggregates of all sizes are passed by memory. */ 346 if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type)) 347 return true; 348 349 /* Everything else gets passed by register. */ 350 return false; 351 } 352 353 /* Register information. */ 354 #define SPARC32_FPU_REGISTERS \ 355 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 356 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 357 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ 358 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 359 #define SPARC32_CP0_REGISTERS \ 360 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" 361 362 static const char * const sparc_core_register_names[] = { 363 SPARC_CORE_REGISTERS 364 }; 365 static const char * const sparc32_fpu_register_names[] = { 366 SPARC32_FPU_REGISTERS 367 }; 368 static const char * const sparc32_cp0_register_names[] = { 369 SPARC32_CP0_REGISTERS 370 }; 371 372 static const char * const sparc32_register_names[] = 373 { 374 SPARC_CORE_REGISTERS, 375 SPARC32_FPU_REGISTERS, 376 SPARC32_CP0_REGISTERS 377 }; 378 379 /* Total number of registers. */ 380 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) 381 382 /* We provide the aliases %d0..%d30 for the floating registers as 383 "psuedo" registers. */ 384 385 static const char * const sparc32_pseudo_register_names[] = 386 { 387 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", 388 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" 389 }; 390 391 /* Total number of pseudo registers. */ 392 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) 393 394 /* Return the name of pseudo register REGNUM. */ 395 396 static const char * 397 sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 398 { 399 regnum -= gdbarch_num_regs (gdbarch); 400 401 gdb_assert (regnum < SPARC32_NUM_PSEUDO_REGS); 402 return sparc32_pseudo_register_names[regnum]; 403 } 404 405 /* Return the name of register REGNUM. */ 406 407 static const char * 408 sparc32_register_name (struct gdbarch *gdbarch, int regnum) 409 { 410 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 411 return tdesc_register_name (gdbarch, regnum); 412 413 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) 414 return sparc32_register_names[regnum]; 415 416 return sparc32_pseudo_register_name (gdbarch, regnum); 417 } 418 419 /* Construct types for ISA-specific registers. */ 420 421 static struct type * 422 sparc_psr_type (struct gdbarch *gdbarch) 423 { 424 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); 425 426 if (!tdep->sparc_psr_type) 427 { 428 struct type *type; 429 430 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32); 431 append_flags_type_flag (type, 5, "ET"); 432 append_flags_type_flag (type, 6, "PS"); 433 append_flags_type_flag (type, 7, "S"); 434 append_flags_type_flag (type, 12, "EF"); 435 append_flags_type_flag (type, 13, "EC"); 436 437 tdep->sparc_psr_type = type; 438 } 439 440 return tdep->sparc_psr_type; 441 } 442 443 static struct type * 444 sparc_fsr_type (struct gdbarch *gdbarch) 445 { 446 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); 447 448 if (!tdep->sparc_fsr_type) 449 { 450 struct type *type; 451 452 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32); 453 append_flags_type_flag (type, 0, "NXA"); 454 append_flags_type_flag (type, 1, "DZA"); 455 append_flags_type_flag (type, 2, "UFA"); 456 append_flags_type_flag (type, 3, "OFA"); 457 append_flags_type_flag (type, 4, "NVA"); 458 append_flags_type_flag (type, 5, "NXC"); 459 append_flags_type_flag (type, 6, "DZC"); 460 append_flags_type_flag (type, 7, "UFC"); 461 append_flags_type_flag (type, 8, "OFC"); 462 append_flags_type_flag (type, 9, "NVC"); 463 append_flags_type_flag (type, 22, "NS"); 464 append_flags_type_flag (type, 23, "NXM"); 465 append_flags_type_flag (type, 24, "DZM"); 466 append_flags_type_flag (type, 25, "UFM"); 467 append_flags_type_flag (type, 26, "OFM"); 468 append_flags_type_flag (type, 27, "NVM"); 469 470 tdep->sparc_fsr_type = type; 471 } 472 473 return tdep->sparc_fsr_type; 474 } 475 476 /* Return the GDB type object for the "standard" data type of data in 477 pseudo register REGNUM. */ 478 479 static struct type * 480 sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 481 { 482 regnum -= gdbarch_num_regs (gdbarch); 483 484 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) 485 return builtin_type (gdbarch)->builtin_double; 486 487 internal_error (_("sparc32_pseudo_register_type: bad register number %d"), 488 regnum); 489 } 490 491 /* Return the GDB type object for the "standard" data type of data in 492 register REGNUM. */ 493 494 static struct type * 495 sparc32_register_type (struct gdbarch *gdbarch, int regnum) 496 { 497 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 498 return tdesc_register_type (gdbarch, regnum); 499 500 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) 501 return builtin_type (gdbarch)->builtin_float; 502 503 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) 504 return builtin_type (gdbarch)->builtin_data_ptr; 505 506 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 507 return builtin_type (gdbarch)->builtin_func_ptr; 508 509 if (regnum == SPARC32_PSR_REGNUM) 510 return sparc_psr_type (gdbarch); 511 512 if (regnum == SPARC32_FSR_REGNUM) 513 return sparc_fsr_type (gdbarch); 514 515 if (regnum >= gdbarch_num_regs (gdbarch)) 516 return sparc32_pseudo_register_type (gdbarch, regnum); 517 518 return builtin_type (gdbarch)->builtin_int32; 519 } 520 521 static enum register_status 522 sparc32_pseudo_register_read (struct gdbarch *gdbarch, 523 readable_regcache *regcache, 524 int regnum, gdb_byte *buf) 525 { 526 enum register_status status; 527 528 regnum -= gdbarch_num_regs (gdbarch); 529 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 530 531 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 532 status = regcache->raw_read (regnum, buf); 533 if (status == REG_VALID) 534 status = regcache->raw_read (regnum + 1, buf + 4); 535 return status; 536 } 537 538 static void 539 sparc32_pseudo_register_write (struct gdbarch *gdbarch, 540 struct regcache *regcache, 541 int regnum, const gdb_byte *buf) 542 { 543 regnum -= gdbarch_num_regs (gdbarch); 544 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 545 546 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 547 regcache->raw_write (regnum, buf); 548 regcache->raw_write (regnum + 1, buf + 4); 549 } 550 551 /* Implement the stack_frame_destroyed_p gdbarch method. */ 552 553 int 554 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 555 { 556 /* This function must return true if we are one instruction after an 557 instruction that destroyed the stack frame of the current 558 function. The SPARC instructions used to restore the callers 559 stack frame are RESTORE and RETURN/RETT. 560 561 Of these RETURN/RETT is a branch instruction and thus we return 562 true if we are in its delay slot. 563 564 RESTORE is almost always found in the delay slot of a branch 565 instruction that transfers control to the caller, such as JMPL. 566 Thus the next instruction is in the caller frame and we don't 567 need to do anything about it. */ 568 569 unsigned int insn = sparc_fetch_instruction (pc - 4); 570 571 return X_RETTURN (insn); 572 } 573 574 575 static CORE_ADDR 576 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) 577 { 578 /* The ABI requires double-word alignment. */ 579 return address & ~0x7; 580 } 581 582 static CORE_ADDR 583 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 584 CORE_ADDR funcaddr, 585 struct value **args, int nargs, 586 struct type *value_type, 587 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 588 struct regcache *regcache) 589 { 590 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 591 592 *bp_addr = sp - 4; 593 *real_pc = funcaddr; 594 595 if (using_struct_return (gdbarch, NULL, value_type)) 596 { 597 gdb_byte buf[4]; 598 599 /* This is an UNIMP instruction. */ 600 store_unsigned_integer (buf, 4, byte_order, 601 value_type->length () & 0x1fff); 602 write_memory (sp - 8, buf, 4); 603 return sp - 8; 604 } 605 606 return sp - 4; 607 } 608 609 static CORE_ADDR 610 sparc32_store_arguments (struct regcache *regcache, int nargs, 611 struct value **args, CORE_ADDR sp, 612 function_call_return_method return_method, 613 CORE_ADDR struct_addr) 614 { 615 struct gdbarch *gdbarch = regcache->arch (); 616 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 617 /* Number of words in the "parameter array". */ 618 int num_elements = 0; 619 int element = 0; 620 int i; 621 622 for (i = 0; i < nargs; i++) 623 { 624 struct type *type = value_type (args[i]); 625 int len = type->length (); 626 627 if (sparc_arg_by_memory_p (type)) 628 { 629 /* Structure, Union and Quad-Precision Arguments. */ 630 sp -= len; 631 632 /* Use doubleword alignment for these values. That's always 633 correct, and wasting a few bytes shouldn't be a problem. */ 634 sp &= ~0x7; 635 636 write_memory (sp, value_contents (args[i]).data (), len); 637 args[i] = value_from_pointer (lookup_pointer_type (type), sp); 638 num_elements++; 639 } 640 else if (sparc_floating_p (type)) 641 { 642 /* Floating arguments. */ 643 gdb_assert (len == 4 || len == 8); 644 num_elements += (len / 4); 645 } 646 else 647 { 648 /* Arguments passed via the General Purpose Registers. */ 649 num_elements += ((len + 3) / 4); 650 } 651 } 652 653 /* Always allocate at least six words. */ 654 sp -= std::max (6, num_elements) * 4; 655 656 /* The psABI says that "Software convention requires space for the 657 struct/union return value pointer, even if the word is unused." */ 658 sp -= 4; 659 660 /* The psABI says that "Although software convention and the 661 operating system require every stack frame to be doubleword 662 aligned." */ 663 sp &= ~0x7; 664 665 for (i = 0; i < nargs; i++) 666 { 667 const bfd_byte *valbuf = value_contents (args[i]).data (); 668 struct type *type = value_type (args[i]); 669 int len = type->length (); 670 gdb_byte buf[4]; 671 672 if (len < 4) 673 { 674 memset (buf, 0, 4 - len); 675 memcpy (buf + 4 - len, valbuf, len); 676 valbuf = buf; 677 len = 4; 678 } 679 680 gdb_assert (len == 4 || len == 8); 681 682 if (element < 6) 683 { 684 int regnum = SPARC_O0_REGNUM + element; 685 686 regcache->cooked_write (regnum, valbuf); 687 if (len > 4 && element < 5) 688 regcache->cooked_write (regnum + 1, valbuf + 4); 689 } 690 691 /* Always store the argument in memory. */ 692 write_memory (sp + 4 + element * 4, valbuf, len); 693 element += len / 4; 694 } 695 696 gdb_assert (element == num_elements); 697 698 if (return_method == return_method_struct) 699 { 700 gdb_byte buf[4]; 701 702 store_unsigned_integer (buf, 4, byte_order, struct_addr); 703 write_memory (sp, buf, 4); 704 } 705 706 return sp; 707 } 708 709 static CORE_ADDR 710 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 711 struct regcache *regcache, CORE_ADDR bp_addr, 712 int nargs, struct value **args, CORE_ADDR sp, 713 function_call_return_method return_method, 714 CORE_ADDR struct_addr) 715 { 716 CORE_ADDR call_pc = (return_method == return_method_struct 717 ? (bp_addr - 12) : (bp_addr - 8)); 718 719 /* Set return address. */ 720 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); 721 722 /* Set up function arguments. */ 723 sp = sparc32_store_arguments (regcache, nargs, args, sp, return_method, 724 struct_addr); 725 726 /* Allocate the 16-word window save area. */ 727 sp -= 16 * 4; 728 729 /* Stack should be doubleword aligned at this point. */ 730 gdb_assert (sp % 8 == 0); 731 732 /* Finally, update the stack pointer. */ 733 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); 734 735 return sp; 736 } 737 738 739 /* Use the program counter to determine the contents and size of a 740 breakpoint instruction. Return a pointer to a string of bytes that 741 encode a breakpoint instruction, store the length of the string in 742 *LEN and optionally adjust *PC to point to the correct memory 743 location for inserting the breakpoint. */ 744 constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; 745 746 typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; 747 748 749 /* Allocate and initialize a frame cache. */ 750 751 static struct sparc_frame_cache * 752 sparc_alloc_frame_cache (void) 753 { 754 struct sparc_frame_cache *cache; 755 756 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); 757 758 /* Base address. */ 759 cache->base = 0; 760 cache->pc = 0; 761 762 /* Frameless until proven otherwise. */ 763 cache->frameless_p = 1; 764 cache->frame_offset = 0; 765 cache->saved_regs_mask = 0; 766 cache->copied_regs_mask = 0; 767 cache->struct_return_p = 0; 768 769 return cache; 770 } 771 772 /* GCC generates several well-known sequences of instructions at the begining 773 of each function prologue when compiling with -fstack-check. If one of 774 such sequences starts at START_PC, then return the address of the 775 instruction immediately past this sequence. Otherwise, return START_PC. */ 776 777 static CORE_ADDR 778 sparc_skip_stack_check (const CORE_ADDR start_pc) 779 { 780 CORE_ADDR pc = start_pc; 781 unsigned long insn; 782 int probing_loop = 0; 783 784 /* With GCC, all stack checking sequences begin with the same two 785 instructions, plus an optional one in the case of a probing loop: 786 787 sethi <some immediate>, %g1 788 sub %sp, %g1, %g1 789 790 or: 791 792 sethi <some immediate>, %g1 793 sethi <some immediate>, %g4 794 sub %sp, %g1, %g1 795 796 or: 797 798 sethi <some immediate>, %g1 799 sub %sp, %g1, %g1 800 sethi <some immediate>, %g4 801 802 If the optional instruction is found (setting g4), assume that a 803 probing loop will follow. */ 804 805 /* sethi <some immediate>, %g1 */ 806 insn = sparc_fetch_instruction (pc); 807 pc = pc + 4; 808 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) 809 return start_pc; 810 811 /* optional: sethi <some immediate>, %g4 */ 812 insn = sparc_fetch_instruction (pc); 813 pc = pc + 4; 814 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 815 { 816 probing_loop = 1; 817 insn = sparc_fetch_instruction (pc); 818 pc = pc + 4; 819 } 820 821 /* sub %sp, %g1, %g1 */ 822 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 823 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) 824 return start_pc; 825 826 insn = sparc_fetch_instruction (pc); 827 pc = pc + 4; 828 829 /* optional: sethi <some immediate>, %g4 */ 830 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 831 { 832 probing_loop = 1; 833 insn = sparc_fetch_instruction (pc); 834 pc = pc + 4; 835 } 836 837 /* First possible sequence: 838 [first two instructions above] 839 clr [%g1 - some immediate] */ 840 841 /* clr [%g1 - some immediate] */ 842 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 843 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 844 { 845 /* Valid stack-check sequence, return the new PC. */ 846 return pc; 847 } 848 849 /* Second possible sequence: A small number of probes. 850 [first two instructions above] 851 clr [%g1] 852 add %g1, -<some immediate>, %g1 853 clr [%g1] 854 [repeat the two instructions above any (small) number of times] 855 clr [%g1 - some immediate] */ 856 857 /* clr [%g1] */ 858 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 859 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 860 { 861 while (1) 862 { 863 /* add %g1, -<some immediate>, %g1 */ 864 insn = sparc_fetch_instruction (pc); 865 pc = pc + 4; 866 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 867 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 868 break; 869 870 /* clr [%g1] */ 871 insn = sparc_fetch_instruction (pc); 872 pc = pc + 4; 873 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 874 && X_RD (insn) == 0 && X_RS1 (insn) == 1)) 875 return start_pc; 876 } 877 878 /* clr [%g1 - some immediate] */ 879 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 880 && X_RS1 (insn) == 1 && X_RD (insn) == 0)) 881 return start_pc; 882 883 /* We found a valid stack-check sequence, return the new PC. */ 884 return pc; 885 } 886 887 /* Third sequence: A probing loop. 888 [first three instructions above] 889 sub %g1, %g4, %g4 890 cmp %g1, %g4 891 be <disp> 892 add %g1, -<some immediate>, %g1 893 ba <disp> 894 clr [%g1] 895 896 And an optional last probe for the remainder: 897 898 clr [%g4 - some immediate] */ 899 900 if (probing_loop) 901 { 902 /* sub %g1, %g4, %g4 */ 903 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 904 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 905 return start_pc; 906 907 /* cmp %g1, %g4 */ 908 insn = sparc_fetch_instruction (pc); 909 pc = pc + 4; 910 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) 911 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 912 return start_pc; 913 914 /* be <disp> */ 915 insn = sparc_fetch_instruction (pc); 916 pc = pc + 4; 917 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) 918 return start_pc; 919 920 /* add %g1, -<some immediate>, %g1 */ 921 insn = sparc_fetch_instruction (pc); 922 pc = pc + 4; 923 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 924 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 925 return start_pc; 926 927 /* ba <disp> */ 928 insn = sparc_fetch_instruction (pc); 929 pc = pc + 4; 930 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) 931 return start_pc; 932 933 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ 934 insn = sparc_fetch_instruction (pc); 935 pc = pc + 4; 936 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 937 && X_RD (insn) == 0 && X_RS1 (insn) == 1 938 && (!X_I(insn) || X_SIMM13 (insn) == 0))) 939 return start_pc; 940 941 /* We found a valid stack-check sequence, return the new PC. */ 942 943 /* optional: clr [%g4 - some immediate] */ 944 insn = sparc_fetch_instruction (pc); 945 pc = pc + 4; 946 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 947 && X_RS1 (insn) == 4 && X_RD (insn) == 0)) 948 return pc - 4; 949 else 950 return pc; 951 } 952 953 /* No stack check code in our prologue, return the start_pc. */ 954 return start_pc; 955 } 956 957 /* Record the effect of a SAVE instruction on CACHE. */ 958 959 void 960 sparc_record_save_insn (struct sparc_frame_cache *cache) 961 { 962 /* The frame is set up. */ 963 cache->frameless_p = 0; 964 965 /* The frame pointer contains the CFA. */ 966 cache->frame_offset = 0; 967 968 /* The `local' and `in' registers are all saved. */ 969 cache->saved_regs_mask = 0xffff; 970 971 /* The `out' registers are all renamed. */ 972 cache->copied_regs_mask = 0xff; 973 } 974 975 /* Do a full analysis of the prologue at PC and update CACHE accordingly. 976 Bail out early if CURRENT_PC is reached. Return the address where 977 the analysis stopped. 978 979 We handle both the traditional register window model and the single 980 register window (aka flat) model. */ 981 982 CORE_ADDR 983 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, 984 CORE_ADDR current_pc, struct sparc_frame_cache *cache) 985 { 986 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); 987 unsigned long insn; 988 int offset = 0; 989 int dest = -1; 990 991 pc = sparc_skip_stack_check (pc); 992 993 if (current_pc <= pc) 994 return current_pc; 995 996 /* We have to handle to "Procedure Linkage Table" (PLT) special. On 997 SPARC the linker usually defines a symbol (typically 998 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. 999 This symbol makes us end up here with PC pointing at the start of 1000 the PLT and CURRENT_PC probably pointing at a PLT entry. If we 1001 would do our normal prologue analysis, we would probably conclude 1002 that we've got a frame when in reality we don't, since the 1003 dynamic linker patches up the first PLT with some code that 1004 starts with a SAVE instruction. Patch up PC such that it points 1005 at the start of our PLT entry. */ 1006 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) 1007 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); 1008 1009 insn = sparc_fetch_instruction (pc); 1010 1011 /* Recognize store insns and record their sources. */ 1012 while (X_OP (insn) == 3 1013 && (X_OP3 (insn) == 0x4 /* stw */ 1014 || X_OP3 (insn) == 0x7 /* std */ 1015 || X_OP3 (insn) == 0xe) /* stx */ 1016 && X_RS1 (insn) == SPARC_SP_REGNUM) 1017 { 1018 int regnum = X_RD (insn); 1019 1020 /* Recognize stores into the corresponding stack slots. */ 1021 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1022 && ((X_I (insn) 1023 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe 1024 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS 1025 : (regnum - SPARC_L0_REGNUM) * 4)) 1026 || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) 1027 { 1028 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); 1029 if (X_OP3 (insn) == 0x7) 1030 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); 1031 } 1032 1033 offset += 4; 1034 1035 insn = sparc_fetch_instruction (pc + offset); 1036 } 1037 1038 /* Recognize a SETHI insn and record its destination. */ 1039 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) 1040 { 1041 dest = X_RD (insn); 1042 offset += 4; 1043 1044 insn = sparc_fetch_instruction (pc + offset); 1045 } 1046 1047 /* Allow for an arithmetic operation on DEST or %g1. */ 1048 if (X_OP (insn) == 2 && X_I (insn) 1049 && (X_RD (insn) == 1 || X_RD (insn) == dest)) 1050 { 1051 offset += 4; 1052 1053 insn = sparc_fetch_instruction (pc + offset); 1054 } 1055 1056 /* Check for the SAVE instruction that sets up the frame. */ 1057 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) 1058 { 1059 sparc_record_save_insn (cache); 1060 offset += 4; 1061 return pc + offset; 1062 } 1063 1064 /* Check for an arithmetic operation on %sp. */ 1065 if (X_OP (insn) == 2 1066 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1067 && X_RS1 (insn) == SPARC_SP_REGNUM 1068 && X_RD (insn) == SPARC_SP_REGNUM) 1069 { 1070 if (X_I (insn)) 1071 { 1072 cache->frame_offset = X_SIMM13 (insn); 1073 if (X_OP3 (insn) == 0) 1074 cache->frame_offset = -cache->frame_offset; 1075 } 1076 offset += 4; 1077 1078 insn = sparc_fetch_instruction (pc + offset); 1079 1080 /* Check for an arithmetic operation that sets up the frame. */ 1081 if (X_OP (insn) == 2 1082 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1083 && X_RS1 (insn) == SPARC_SP_REGNUM 1084 && X_RD (insn) == SPARC_FP_REGNUM) 1085 { 1086 cache->frameless_p = 0; 1087 cache->frame_offset = 0; 1088 /* We could check that the amount subtracted to %sp above is the 1089 same as the one added here, but this seems superfluous. */ 1090 cache->copied_regs_mask |= 0x40; 1091 offset += 4; 1092 1093 insn = sparc_fetch_instruction (pc + offset); 1094 } 1095 1096 /* Check for a move (or) operation that copies the return register. */ 1097 if (X_OP (insn) == 2 1098 && X_OP3 (insn) == 0x2 1099 && !X_I (insn) 1100 && X_RS1 (insn) == SPARC_G0_REGNUM 1101 && X_RS2 (insn) == SPARC_O7_REGNUM 1102 && X_RD (insn) == SPARC_I7_REGNUM) 1103 { 1104 cache->copied_regs_mask |= 0x80; 1105 offset += 4; 1106 } 1107 1108 return pc + offset; 1109 } 1110 1111 return pc; 1112 } 1113 1114 /* Return PC of first real instruction of the function starting at 1115 START_PC. */ 1116 1117 static CORE_ADDR 1118 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1119 { 1120 CORE_ADDR func_addr; 1121 struct sparc_frame_cache cache; 1122 1123 /* This is the preferred method, find the end of the prologue by 1124 using the debugging information. */ 1125 1126 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 1127 { 1128 CORE_ADDR post_prologue_pc 1129 = skip_prologue_using_sal (gdbarch, func_addr); 1130 1131 if (post_prologue_pc != 0) 1132 return std::max (start_pc, post_prologue_pc); 1133 } 1134 1135 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); 1136 1137 /* The psABI says that "Although the first 6 words of arguments 1138 reside in registers, the standard stack frame reserves space for 1139 them.". It also suggests that a function may use that space to 1140 "write incoming arguments 0 to 5" into that space, and that's 1141 indeed what GCC seems to be doing. In that case GCC will 1142 generate debug information that points to the stack slots instead 1143 of the registers, so we should consider the instructions that 1144 write out these incoming arguments onto the stack. */ 1145 1146 while (1) 1147 { 1148 unsigned long insn = sparc_fetch_instruction (start_pc); 1149 1150 /* Recognize instructions that store incoming arguments into the 1151 corresponding stack slots. */ 1152 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 1153 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) 1154 { 1155 int regnum = X_RD (insn); 1156 1157 /* Case of arguments still in %o[0..5]. */ 1158 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM 1159 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) 1160 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) 1161 { 1162 start_pc += 4; 1163 continue; 1164 } 1165 1166 /* Case of arguments copied into %i[0..5]. */ 1167 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM 1168 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) 1169 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) 1170 { 1171 start_pc += 4; 1172 continue; 1173 } 1174 } 1175 1176 break; 1177 } 1178 1179 return start_pc; 1180 } 1181 1182 /* Normal frames. */ 1183 1184 struct sparc_frame_cache * 1185 sparc_frame_cache (frame_info_ptr this_frame, void **this_cache) 1186 { 1187 struct sparc_frame_cache *cache; 1188 1189 if (*this_cache) 1190 return (struct sparc_frame_cache *) *this_cache; 1191 1192 cache = sparc_alloc_frame_cache (); 1193 *this_cache = cache; 1194 1195 cache->pc = get_frame_func (this_frame); 1196 if (cache->pc != 0) 1197 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, 1198 get_frame_pc (this_frame), cache); 1199 1200 if (cache->frameless_p) 1201 { 1202 /* This function is frameless, so %fp (%i6) holds the frame 1203 pointer for our calling frame. Use %sp (%o6) as this frame's 1204 base address. */ 1205 cache->base = 1206 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1207 } 1208 else 1209 { 1210 /* For normal frames, %fp (%i6) holds the frame pointer, the 1211 base address for the current stack frame. */ 1212 cache->base = 1213 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); 1214 } 1215 1216 cache->base += cache->frame_offset; 1217 1218 if (cache->base & 1) 1219 cache->base += BIAS; 1220 1221 return cache; 1222 } 1223 1224 static int 1225 sparc32_struct_return_from_sym (struct symbol *sym) 1226 { 1227 struct type *type = check_typedef (sym->type ()); 1228 enum type_code code = type->code (); 1229 1230 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) 1231 { 1232 type = check_typedef (type->target_type ()); 1233 if (sparc_structure_or_union_p (type) 1234 || (sparc_floating_p (type) && type->length () == 16)) 1235 return 1; 1236 } 1237 1238 return 0; 1239 } 1240 1241 struct sparc_frame_cache * 1242 sparc32_frame_cache (frame_info_ptr this_frame, void **this_cache) 1243 { 1244 struct sparc_frame_cache *cache; 1245 struct symbol *sym; 1246 1247 if (*this_cache) 1248 return (struct sparc_frame_cache *) *this_cache; 1249 1250 cache = sparc_frame_cache (this_frame, this_cache); 1251 1252 sym = find_pc_function (cache->pc); 1253 if (sym) 1254 { 1255 cache->struct_return_p = sparc32_struct_return_from_sym (sym); 1256 } 1257 else 1258 { 1259 /* There is no debugging information for this function to 1260 help us determine whether this function returns a struct 1261 or not. So we rely on another heuristic which is to check 1262 the instruction at the return address and see if this is 1263 an "unimp" instruction. If it is, then it is a struct-return 1264 function. */ 1265 CORE_ADDR pc; 1266 int regnum = 1267 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1268 1269 pc = get_frame_register_unsigned (this_frame, regnum) + 8; 1270 if (sparc_is_unimp_insn (pc)) 1271 cache->struct_return_p = 1; 1272 } 1273 1274 return cache; 1275 } 1276 1277 static void 1278 sparc32_frame_this_id (frame_info_ptr this_frame, void **this_cache, 1279 struct frame_id *this_id) 1280 { 1281 struct sparc_frame_cache *cache = 1282 sparc32_frame_cache (this_frame, this_cache); 1283 1284 /* This marks the outermost frame. */ 1285 if (cache->base == 0) 1286 return; 1287 1288 (*this_id) = frame_id_build (cache->base, cache->pc); 1289 } 1290 1291 static struct value * 1292 sparc32_frame_prev_register (frame_info_ptr this_frame, 1293 void **this_cache, int regnum) 1294 { 1295 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1296 struct sparc_frame_cache *cache = 1297 sparc32_frame_cache (this_frame, this_cache); 1298 1299 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 1300 { 1301 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; 1302 1303 /* If this functions has a Structure, Union or Quad-Precision 1304 return value, we have to skip the UNIMP instruction that encodes 1305 the size of the structure. */ 1306 if (cache->struct_return_p) 1307 pc += 4; 1308 1309 regnum = 1310 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1311 pc += get_frame_register_unsigned (this_frame, regnum) + 8; 1312 return frame_unwind_got_constant (this_frame, regnum, pc); 1313 } 1314 1315 /* Handle StackGhost. */ 1316 { 1317 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1318 1319 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) 1320 { 1321 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1322 ULONGEST i7; 1323 1324 /* Read the value in from memory. */ 1325 i7 = get_frame_memory_unsigned (this_frame, addr, 4); 1326 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); 1327 } 1328 } 1329 1330 /* The previous frame's `local' and `in' registers may have been saved 1331 in the register save area. */ 1332 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1333 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) 1334 { 1335 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1336 1337 return frame_unwind_got_memory (this_frame, regnum, addr); 1338 } 1339 1340 /* The previous frame's `out' registers may be accessible as the current 1341 frame's `in' registers. */ 1342 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM 1343 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) 1344 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); 1345 1346 return frame_unwind_got_register (this_frame, regnum, regnum); 1347 } 1348 1349 static const struct frame_unwind sparc32_frame_unwind = 1350 { 1351 "sparc32 prologue", 1352 NORMAL_FRAME, 1353 default_frame_unwind_stop_reason, 1354 sparc32_frame_this_id, 1355 sparc32_frame_prev_register, 1356 NULL, 1357 default_frame_sniffer 1358 }; 1359 1360 1361 static CORE_ADDR 1362 sparc32_frame_base_address (frame_info_ptr this_frame, void **this_cache) 1363 { 1364 struct sparc_frame_cache *cache = 1365 sparc32_frame_cache (this_frame, this_cache); 1366 1367 return cache->base; 1368 } 1369 1370 static const struct frame_base sparc32_frame_base = 1371 { 1372 &sparc32_frame_unwind, 1373 sparc32_frame_base_address, 1374 sparc32_frame_base_address, 1375 sparc32_frame_base_address 1376 }; 1377 1378 static struct frame_id 1379 sparc_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) 1380 { 1381 CORE_ADDR sp; 1382 1383 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1384 if (sp & 1) 1385 sp += BIAS; 1386 return frame_id_build (sp, get_frame_pc (this_frame)); 1387 } 1388 1389 1390 /* Extract a function return value of TYPE from REGCACHE, and copy 1391 that into VALBUF. */ 1392 1393 static void 1394 sparc32_extract_return_value (struct type *type, struct regcache *regcache, 1395 gdb_byte *valbuf) 1396 { 1397 int len = type->length (); 1398 gdb_byte buf[32]; 1399 1400 gdb_assert (!sparc_structure_return_p (type)); 1401 1402 if (sparc_floating_p (type) || sparc_complex_floating_p (type) 1403 || type->code () == TYPE_CODE_ARRAY) 1404 { 1405 /* Floating return values. */ 1406 regcache->cooked_read (SPARC_F0_REGNUM, buf); 1407 if (len > 4) 1408 regcache->cooked_read (SPARC_F1_REGNUM, buf + 4); 1409 if (len > 8) 1410 { 1411 regcache->cooked_read (SPARC_F2_REGNUM, buf + 8); 1412 regcache->cooked_read (SPARC_F3_REGNUM, buf + 12); 1413 } 1414 if (len > 16) 1415 { 1416 regcache->cooked_read (SPARC_F4_REGNUM, buf + 16); 1417 regcache->cooked_read (SPARC_F5_REGNUM, buf + 20); 1418 regcache->cooked_read (SPARC_F6_REGNUM, buf + 24); 1419 regcache->cooked_read (SPARC_F7_REGNUM, buf + 28); 1420 } 1421 memcpy (valbuf, buf, len); 1422 } 1423 else 1424 { 1425 /* Integral and pointer return values. */ 1426 gdb_assert (sparc_integral_or_pointer_p (type)); 1427 1428 regcache->cooked_read (SPARC_O0_REGNUM, buf); 1429 if (len > 4) 1430 { 1431 regcache->cooked_read (SPARC_O1_REGNUM, buf + 4); 1432 gdb_assert (len == 8); 1433 memcpy (valbuf, buf, 8); 1434 } 1435 else 1436 { 1437 /* Just stripping off any unused bytes should preserve the 1438 signed-ness just fine. */ 1439 memcpy (valbuf, buf + 4 - len, len); 1440 } 1441 } 1442 } 1443 1444 /* Store the function return value of type TYPE from VALBUF into 1445 REGCACHE. */ 1446 1447 static void 1448 sparc32_store_return_value (struct type *type, struct regcache *regcache, 1449 const gdb_byte *valbuf) 1450 { 1451 int len = type->length (); 1452 gdb_byte buf[32]; 1453 1454 gdb_assert (!sparc_structure_return_p (type)); 1455 1456 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1457 { 1458 /* Floating return values. */ 1459 memcpy (buf, valbuf, len); 1460 regcache->cooked_write (SPARC_F0_REGNUM, buf); 1461 if (len > 4) 1462 regcache->cooked_write (SPARC_F1_REGNUM, buf + 4); 1463 if (len > 8) 1464 { 1465 regcache->cooked_write (SPARC_F2_REGNUM, buf + 8); 1466 regcache->cooked_write (SPARC_F3_REGNUM, buf + 12); 1467 } 1468 if (len > 16) 1469 { 1470 regcache->cooked_write (SPARC_F4_REGNUM, buf + 16); 1471 regcache->cooked_write (SPARC_F5_REGNUM, buf + 20); 1472 regcache->cooked_write (SPARC_F6_REGNUM, buf + 24); 1473 regcache->cooked_write (SPARC_F7_REGNUM, buf + 28); 1474 } 1475 } 1476 else 1477 { 1478 /* Integral and pointer return values. */ 1479 gdb_assert (sparc_integral_or_pointer_p (type)); 1480 1481 if (len > 4) 1482 { 1483 gdb_assert (len == 8); 1484 memcpy (buf, valbuf, 8); 1485 regcache->cooked_write (SPARC_O1_REGNUM, buf + 4); 1486 } 1487 else 1488 { 1489 /* ??? Do we need to do any sign-extension here? */ 1490 memcpy (buf + 4 - len, valbuf, len); 1491 } 1492 regcache->cooked_write (SPARC_O0_REGNUM, buf); 1493 } 1494 } 1495 1496 static enum return_value_convention 1497 sparc32_return_value (struct gdbarch *gdbarch, struct value *function, 1498 struct type *type, struct regcache *regcache, 1499 gdb_byte *readbuf, const gdb_byte *writebuf) 1500 { 1501 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1502 1503 /* The psABI says that "...every stack frame reserves the word at 1504 %fp+64. If a function returns a structure, union, or 1505 quad-precision value, this word should hold the address of the 1506 object into which the return value should be copied." This 1507 guarantees that we can always find the return value, not just 1508 before the function returns. */ 1509 1510 if (sparc_structure_return_p (type)) 1511 { 1512 ULONGEST sp; 1513 CORE_ADDR addr; 1514 1515 if (readbuf) 1516 { 1517 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1518 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1519 read_memory (addr, readbuf, type->length ()); 1520 } 1521 if (writebuf) 1522 { 1523 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1524 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1525 write_memory (addr, writebuf, type->length ()); 1526 } 1527 1528 return RETURN_VALUE_ABI_PRESERVES_ADDRESS; 1529 } 1530 1531 if (readbuf) 1532 sparc32_extract_return_value (type, regcache, readbuf); 1533 if (writebuf) 1534 sparc32_store_return_value (type, regcache, writebuf); 1535 1536 return RETURN_VALUE_REGISTER_CONVENTION; 1537 } 1538 1539 static int 1540 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) 1541 { 1542 return (sparc_structure_or_union_p (type) 1543 || (sparc_floating_p (type) && type->length () == 16) 1544 || sparc_complex_floating_p (type)); 1545 } 1546 1547 static int 1548 sparc32_dwarf2_struct_return_p (frame_info_ptr this_frame) 1549 { 1550 CORE_ADDR pc = get_frame_address_in_block (this_frame); 1551 struct symbol *sym = find_pc_function (pc); 1552 1553 if (sym) 1554 return sparc32_struct_return_from_sym (sym); 1555 return 0; 1556 } 1557 1558 static void 1559 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1560 struct dwarf2_frame_state_reg *reg, 1561 frame_info_ptr this_frame) 1562 { 1563 int off; 1564 1565 switch (regnum) 1566 { 1567 case SPARC_G0_REGNUM: 1568 /* Since %g0 is always zero, there is no point in saving it, and 1569 people will be inclined omit it from the CFI. Make sure we 1570 don't warn about that. */ 1571 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1572 break; 1573 case SPARC_SP_REGNUM: 1574 reg->how = DWARF2_FRAME_REG_CFA; 1575 break; 1576 case SPARC32_PC_REGNUM: 1577 case SPARC32_NPC_REGNUM: 1578 reg->how = DWARF2_FRAME_REG_RA_OFFSET; 1579 off = 8; 1580 if (sparc32_dwarf2_struct_return_p (this_frame)) 1581 off += 4; 1582 if (regnum == SPARC32_NPC_REGNUM) 1583 off += 4; 1584 reg->loc.offset = off; 1585 break; 1586 } 1587 } 1588 1589 /* Implement the execute_dwarf_cfa_vendor_op method. */ 1590 1591 static bool 1592 sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, 1593 struct dwarf2_frame_state *fs) 1594 { 1595 /* Only DW_CFA_GNU_window_save is expected on SPARC. */ 1596 if (op != DW_CFA_GNU_window_save) 1597 return false; 1598 1599 uint64_t reg; 1600 int size = register_size (gdbarch, 0); 1601 1602 fs->regs.alloc_regs (32); 1603 for (reg = 8; reg < 16; reg++) 1604 { 1605 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; 1606 fs->regs.reg[reg].loc.reg = reg + 16; 1607 } 1608 for (reg = 16; reg < 32; reg++) 1609 { 1610 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; 1611 fs->regs.reg[reg].loc.offset = (reg - 16) * size; 1612 } 1613 1614 return true; 1615 } 1616 1617 1618 /* The SPARC Architecture doesn't have hardware single-step support, 1619 and most operating systems don't implement it either, so we provide 1620 software single-step mechanism. */ 1621 1622 static CORE_ADDR 1623 sparc_analyze_control_transfer (struct regcache *regcache, 1624 CORE_ADDR pc, CORE_ADDR *npc) 1625 { 1626 unsigned long insn = sparc_fetch_instruction (pc); 1627 int conditional_p = X_COND (insn) & 0x7; 1628 int branch_p = 0, fused_p = 0; 1629 long offset = 0; /* Must be signed for sign-extend. */ 1630 1631 if (X_OP (insn) == 0 && X_OP2 (insn) == 3) 1632 { 1633 if ((insn & 0x10000000) == 0) 1634 { 1635 /* Branch on Integer Register with Prediction (BPr). */ 1636 branch_p = 1; 1637 conditional_p = 1; 1638 } 1639 else 1640 { 1641 /* Compare and Branch */ 1642 branch_p = 1; 1643 fused_p = 1; 1644 offset = 4 * X_DISP10 (insn); 1645 } 1646 } 1647 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) 1648 { 1649 /* Branch on Floating-Point Condition Codes (FBfcc). */ 1650 branch_p = 1; 1651 offset = 4 * X_DISP22 (insn); 1652 } 1653 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) 1654 { 1655 /* Branch on Floating-Point Condition Codes with Prediction 1656 (FBPfcc). */ 1657 branch_p = 1; 1658 offset = 4 * X_DISP19 (insn); 1659 } 1660 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) 1661 { 1662 /* Branch on Integer Condition Codes (Bicc). */ 1663 branch_p = 1; 1664 offset = 4 * X_DISP22 (insn); 1665 } 1666 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) 1667 { 1668 /* Branch on Integer Condition Codes with Prediction (BPcc). */ 1669 branch_p = 1; 1670 offset = 4 * X_DISP19 (insn); 1671 } 1672 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) 1673 { 1674 frame_info_ptr frame = get_current_frame (); 1675 1676 /* Trap instruction (TRAP). */ 1677 gdbarch *arch = regcache->arch (); 1678 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (arch); 1679 return tdep->step_trap (frame, insn); 1680 } 1681 1682 /* FIXME: Handle DONE and RETRY instructions. */ 1683 1684 if (branch_p) 1685 { 1686 if (fused_p) 1687 { 1688 /* Fused compare-and-branch instructions are non-delayed, 1689 and do not have an annulling capability. So we need to 1690 always set a breakpoint on both the NPC and the branch 1691 target address. */ 1692 gdb_assert (offset != 0); 1693 return pc + offset; 1694 } 1695 else if (conditional_p) 1696 { 1697 /* For conditional branches, return nPC + 4 iff the annul 1698 bit is 1. */ 1699 return (X_A (insn) ? *npc + 4 : 0); 1700 } 1701 else 1702 { 1703 /* For unconditional branches, return the target if its 1704 specified condition is "always" and return nPC + 4 if the 1705 condition is "never". If the annul bit is 1, set *NPC to 1706 zero. */ 1707 if (X_COND (insn) == 0x0) 1708 pc = *npc, offset = 4; 1709 if (X_A (insn)) 1710 *npc = 0; 1711 1712 return pc + offset; 1713 } 1714 } 1715 1716 return 0; 1717 } 1718 1719 static CORE_ADDR 1720 sparc_step_trap (frame_info_ptr frame, unsigned long insn) 1721 { 1722 return 0; 1723 } 1724 1725 static std::vector<CORE_ADDR> 1726 sparc_software_single_step (struct regcache *regcache) 1727 { 1728 struct gdbarch *arch = regcache->arch (); 1729 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (arch); 1730 CORE_ADDR npc, nnpc; 1731 1732 CORE_ADDR pc, orig_npc; 1733 std::vector<CORE_ADDR> next_pcs; 1734 1735 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); 1736 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); 1737 1738 /* Analyze the instruction at PC. */ 1739 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); 1740 if (npc != 0) 1741 next_pcs.push_back (npc); 1742 1743 if (nnpc != 0) 1744 next_pcs.push_back (nnpc); 1745 1746 /* Assert that we have set at least one breakpoint, and that 1747 they're not set at the same spot - unless we're going 1748 from here straight to NULL, i.e. a call or jump to 0. */ 1749 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); 1750 gdb_assert (nnpc != npc || orig_npc == 0); 1751 1752 return next_pcs; 1753 } 1754 1755 static void 1756 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) 1757 { 1758 gdbarch *arch = regcache->arch (); 1759 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (arch); 1760 1761 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); 1762 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); 1763 } 1764 1765 1766 /* Iterate over core file register note sections. */ 1767 1768 static void 1769 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, 1770 iterate_over_regset_sections_cb *cb, 1771 void *cb_data, 1772 const struct regcache *regcache) 1773 { 1774 sparc_gdbarch_tdep *tdep = gdbarch_tdep<sparc_gdbarch_tdep> (gdbarch); 1775 1776 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, 1777 cb_data); 1778 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, 1779 NULL, cb_data); 1780 } 1781 1782 1783 static int 1784 validate_tdesc_registers (const struct target_desc *tdesc, 1785 struct tdesc_arch_data *tdesc_data, 1786 const char *feature_name, 1787 const char * const register_names[], 1788 unsigned int registers_num, 1789 unsigned int reg_start) 1790 { 1791 int valid_p = 1; 1792 const struct tdesc_feature *feature; 1793 1794 feature = tdesc_find_feature (tdesc, feature_name); 1795 if (feature == NULL) 1796 return 0; 1797 1798 for (unsigned int i = 0; i < registers_num; i++) 1799 valid_p &= tdesc_numbered_register (feature, tdesc_data, 1800 reg_start + i, 1801 register_names[i]); 1802 1803 return valid_p; 1804 } 1805 1806 static struct gdbarch * 1807 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1808 { 1809 const struct target_desc *tdesc = info.target_desc; 1810 struct gdbarch *gdbarch; 1811 int valid_p = 1; 1812 1813 /* If there is already a candidate, use it. */ 1814 arches = gdbarch_list_lookup_by_info (arches, &info); 1815 if (arches != NULL) 1816 return arches->gdbarch; 1817 1818 /* Allocate space for the new architecture. */ 1819 sparc_gdbarch_tdep *tdep = new sparc_gdbarch_tdep; 1820 gdbarch = gdbarch_alloc (&info, tdep); 1821 1822 tdep->pc_regnum = SPARC32_PC_REGNUM; 1823 tdep->npc_regnum = SPARC32_NPC_REGNUM; 1824 tdep->step_trap = sparc_step_trap; 1825 tdep->fpu_register_names = sparc32_fpu_register_names; 1826 tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); 1827 tdep->cp0_register_names = sparc32_cp0_register_names; 1828 tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); 1829 1830 set_gdbarch_long_double_bit (gdbarch, 128); 1831 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); 1832 1833 set_gdbarch_wchar_bit (gdbarch, 16); 1834 set_gdbarch_wchar_signed (gdbarch, 1); 1835 1836 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); 1837 set_gdbarch_register_name (gdbarch, sparc32_register_name); 1838 set_gdbarch_register_type (gdbarch, sparc32_register_type); 1839 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); 1840 set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); 1841 set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); 1842 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); 1843 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); 1844 1845 /* Register numbers of various important registers. */ 1846 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ 1847 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ 1848 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ 1849 1850 /* Call dummy code. */ 1851 set_gdbarch_frame_align (gdbarch, sparc32_frame_align); 1852 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 1853 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); 1854 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); 1855 1856 set_gdbarch_return_value (gdbarch, sparc32_return_value); 1857 set_gdbarch_stabs_argument_has_addr 1858 (gdbarch, sparc32_stabs_argument_has_addr); 1859 1860 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); 1861 1862 /* Stack grows downward. */ 1863 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1864 1865 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 1866 sparc_breakpoint::kind_from_pc); 1867 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 1868 sparc_breakpoint::bp_from_kind); 1869 1870 set_gdbarch_frame_args_skip (gdbarch, 8); 1871 1872 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); 1873 set_gdbarch_write_pc (gdbarch, sparc_write_pc); 1874 1875 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); 1876 1877 frame_base_set_default (gdbarch, &sparc32_frame_base); 1878 1879 /* Hook in the DWARF CFI frame unwinder. */ 1880 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); 1881 /* Register DWARF vendor CFI handler. */ 1882 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, 1883 sparc_execute_dwarf_cfa_vendor_op); 1884 /* FIXME: kettenis/20050423: Don't enable the unwinder until the 1885 StackGhost issues have been resolved. */ 1886 1887 /* Hook in ABI-specific overrides, if they have been registered. */ 1888 gdbarch_init_osabi (info, gdbarch); 1889 1890 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); 1891 1892 if (tdesc_has_registers (tdesc)) 1893 { 1894 tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); 1895 1896 /* Validate that the descriptor provides the mandatory registers 1897 and allocate their numbers. */ 1898 valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), 1899 "org.gnu.gdb.sparc.cpu", 1900 sparc_core_register_names, 1901 ARRAY_SIZE (sparc_core_register_names), 1902 SPARC_G0_REGNUM); 1903 valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), 1904 "org.gnu.gdb.sparc.fpu", 1905 tdep->fpu_register_names, 1906 tdep->fpu_registers_num, 1907 SPARC_F0_REGNUM); 1908 valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), 1909 "org.gnu.gdb.sparc.cp0", 1910 tdep->cp0_register_names, 1911 tdep->cp0_registers_num, 1912 SPARC_F0_REGNUM 1913 + tdep->fpu_registers_num); 1914 if (!valid_p) 1915 return NULL; 1916 1917 /* Target description may have changed. */ 1918 info.tdesc_data = tdesc_data.get (); 1919 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); 1920 } 1921 1922 /* If we have register sets, enable the generic core file support. */ 1923 if (tdep->gregset) 1924 set_gdbarch_iterate_over_regset_sections 1925 (gdbarch, sparc_iterate_over_regset_sections); 1926 1927 register_sparc_ravenscar_ops (gdbarch); 1928 1929 return gdbarch; 1930 } 1931 1932 /* Helper functions for dealing with register windows. */ 1933 1934 void 1935 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) 1936 { 1937 struct gdbarch *gdbarch = regcache->arch (); 1938 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1939 int offset = 0; 1940 gdb_byte buf[8]; 1941 int i; 1942 1943 /* This function calls functions that depend on the global current thread. */ 1944 gdb_assert (regcache->ptid () == inferior_ptid); 1945 1946 if (sp & 1) 1947 { 1948 /* Registers are 64-bit. */ 1949 sp += BIAS; 1950 1951 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1952 { 1953 if (regnum == i || regnum == -1) 1954 { 1955 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1956 1957 /* Handle StackGhost. */ 1958 if (i == SPARC_I7_REGNUM) 1959 { 1960 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1961 ULONGEST i7; 1962 1963 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1964 store_unsigned_integer (buf + offset, 8, byte_order, 1965 i7 ^ wcookie); 1966 } 1967 1968 regcache->raw_supply (i, buf); 1969 } 1970 } 1971 } 1972 else 1973 { 1974 /* Registers are 32-bit. Toss any sign-extension of the stack 1975 pointer. */ 1976 sp &= 0xffffffffUL; 1977 1978 /* Clear out the top half of the temporary buffer, and put the 1979 register value in the bottom half if we're in 64-bit mode. */ 1980 if (gdbarch_ptr_bit (regcache->arch ()) == 64) 1981 { 1982 memset (buf, 0, 4); 1983 offset = 4; 1984 } 1985 1986 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1987 { 1988 if (regnum == i || regnum == -1) 1989 { 1990 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 1991 buf + offset, 4); 1992 1993 /* Handle StackGhost. */ 1994 if (i == SPARC_I7_REGNUM) 1995 { 1996 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1997 ULONGEST i7; 1998 1999 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 2000 store_unsigned_integer (buf + offset, 4, byte_order, 2001 i7 ^ wcookie); 2002 } 2003 2004 regcache->raw_supply (i, buf); 2005 } 2006 } 2007 } 2008 } 2009 2010 void 2011 sparc_collect_rwindow (const struct regcache *regcache, 2012 CORE_ADDR sp, int regnum) 2013 { 2014 struct gdbarch *gdbarch = regcache->arch (); 2015 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2016 int offset = 0; 2017 gdb_byte buf[8]; 2018 int i; 2019 2020 /* This function calls functions that depend on the global current thread. */ 2021 gdb_assert (regcache->ptid () == inferior_ptid); 2022 2023 if (sp & 1) 2024 { 2025 /* Registers are 64-bit. */ 2026 sp += BIAS; 2027 2028 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2029 { 2030 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 2031 { 2032 regcache->raw_collect (i, buf); 2033 2034 /* Handle StackGhost. */ 2035 if (i == SPARC_I7_REGNUM) 2036 { 2037 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2038 ULONGEST i7; 2039 2040 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 2041 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); 2042 } 2043 2044 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 2045 } 2046 } 2047 } 2048 else 2049 { 2050 /* Registers are 32-bit. Toss any sign-extension of the stack 2051 pointer. */ 2052 sp &= 0xffffffffUL; 2053 2054 /* Only use the bottom half if we're in 64-bit mode. */ 2055 if (gdbarch_ptr_bit (regcache->arch ()) == 64) 2056 offset = 4; 2057 2058 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2059 { 2060 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 2061 { 2062 regcache->raw_collect (i, buf); 2063 2064 /* Handle StackGhost. */ 2065 if (i == SPARC_I7_REGNUM) 2066 { 2067 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2068 ULONGEST i7; 2069 2070 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 2071 store_unsigned_integer (buf + offset, 4, byte_order, 2072 i7 ^ wcookie); 2073 } 2074 2075 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 2076 buf + offset, 4); 2077 } 2078 } 2079 } 2080 } 2081 2082 /* Helper functions for dealing with register sets. */ 2083 2084 void 2085 sparc32_supply_gregset (const struct sparc_gregmap *gregmap, 2086 struct regcache *regcache, 2087 int regnum, const void *gregs) 2088 { 2089 const gdb_byte *regs = (const gdb_byte *) gregs; 2090 gdb_byte zero[4] = { 0 }; 2091 int i; 2092 2093 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2094 regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); 2095 2096 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2097 regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); 2098 2099 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2100 regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); 2101 2102 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2103 regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); 2104 2105 if (regnum == SPARC_G0_REGNUM || regnum == -1) 2106 regcache->raw_supply (SPARC_G0_REGNUM, &zero); 2107 2108 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2109 { 2110 int offset = gregmap->r_g1_offset; 2111 2112 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2113 { 2114 if (regnum == i || regnum == -1) 2115 regcache->raw_supply (i, regs + offset); 2116 offset += 4; 2117 } 2118 } 2119 2120 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2121 { 2122 /* Not all of the register set variants include Locals and 2123 Inputs. For those that don't, we read them off the stack. */ 2124 if (gregmap->r_l0_offset == -1) 2125 { 2126 ULONGEST sp; 2127 2128 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 2129 sparc_supply_rwindow (regcache, sp, regnum); 2130 } 2131 else 2132 { 2133 int offset = gregmap->r_l0_offset; 2134 2135 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2136 { 2137 if (regnum == i || regnum == -1) 2138 regcache->raw_supply (i, regs + offset); 2139 offset += 4; 2140 } 2141 } 2142 } 2143 } 2144 2145 void 2146 sparc32_collect_gregset (const struct sparc_gregmap *gregmap, 2147 const struct regcache *regcache, 2148 int regnum, void *gregs) 2149 { 2150 gdb_byte *regs = (gdb_byte *) gregs; 2151 int i; 2152 2153 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2154 regcache->raw_collect (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); 2155 2156 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2157 regcache->raw_collect (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); 2158 2159 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2160 regcache->raw_collect (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); 2161 2162 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2163 regcache->raw_collect (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); 2164 2165 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2166 { 2167 int offset = gregmap->r_g1_offset; 2168 2169 /* %g0 is always zero. */ 2170 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2171 { 2172 if (regnum == i || regnum == -1) 2173 regcache->raw_collect (i, regs + offset); 2174 offset += 4; 2175 } 2176 } 2177 2178 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2179 { 2180 /* Not all of the register set variants include Locals and 2181 Inputs. For those that don't, we read them off the stack. */ 2182 if (gregmap->r_l0_offset != -1) 2183 { 2184 int offset = gregmap->r_l0_offset; 2185 2186 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2187 { 2188 if (regnum == i || regnum == -1) 2189 regcache->raw_collect (i, regs + offset); 2190 offset += 4; 2191 } 2192 } 2193 } 2194 } 2195 2196 void 2197 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, 2198 struct regcache *regcache, 2199 int regnum, const void *fpregs) 2200 { 2201 const gdb_byte *regs = (const gdb_byte *) fpregs; 2202 int i; 2203 2204 for (i = 0; i < 32; i++) 2205 { 2206 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2207 regcache->raw_supply (SPARC_F0_REGNUM + i, 2208 regs + fpregmap->r_f0_offset + (i * 4)); 2209 } 2210 2211 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2212 regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); 2213 } 2214 2215 void 2216 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, 2217 const struct regcache *regcache, 2218 int regnum, void *fpregs) 2219 { 2220 gdb_byte *regs = (gdb_byte *) fpregs; 2221 int i; 2222 2223 for (i = 0; i < 32; i++) 2224 { 2225 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2226 regcache->raw_collect (SPARC_F0_REGNUM + i, 2227 regs + fpregmap->r_f0_offset + (i * 4)); 2228 } 2229 2230 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2231 regcache->raw_collect (SPARC32_FSR_REGNUM, 2232 regs + fpregmap->r_fsr_offset); 2233 } 2234 2235 2236 /* SunOS 4. */ 2237 2238 /* From <machine/reg.h>. */ 2239 const struct sparc_gregmap sparc32_sunos4_gregmap = 2240 { 2241 0 * 4, /* %psr */ 2242 1 * 4, /* %pc */ 2243 2 * 4, /* %npc */ 2244 3 * 4, /* %y */ 2245 -1, /* %wim */ 2246 -1, /* %tbr */ 2247 4 * 4, /* %g1 */ 2248 -1 /* %l0 */ 2249 }; 2250 2251 const struct sparc_fpregmap sparc32_sunos4_fpregmap = 2252 { 2253 0 * 4, /* %f0 */ 2254 33 * 4, /* %fsr */ 2255 }; 2256 2257 const struct sparc_fpregmap sparc32_bsd_fpregmap = 2258 { 2259 0 * 4, /* %f0 */ 2260 32 * 4, /* %fsr */ 2261 }; 2262 2263 void _initialize_sparc_tdep (); 2264 void 2265 _initialize_sparc_tdep () 2266 { 2267 gdbarch_register (bfd_arch_sparc, sparc32_gdbarch_init); 2268 } 2269