1 /* Target-dependent code for Renesas Super-H, for GDB. 2 3 Copyright (C) 1993-2023 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* Contributed by Steve Chamberlain 21 sac@cygnus.com. */ 22 23 #include "defs.h" 24 #include "frame.h" 25 #include "frame-base.h" 26 #include "frame-unwind.h" 27 #include "dwarf2/frame.h" 28 #include "symtab.h" 29 #include "gdbtypes.h" 30 #include "gdbcmd.h" 31 #include "gdbcore.h" 32 #include "value.h" 33 #include "dis-asm.h" 34 #include "inferior.h" 35 #include "arch-utils.h" 36 #include "regcache.h" 37 #include "target-float.h" 38 #include "osabi.h" 39 #include "reggroups.h" 40 #include "regset.h" 41 #include "objfiles.h" 42 43 #include "sh-tdep.h" 44 45 #include "elf-bfd.h" 46 #include "solib-svr4.h" 47 48 /* sh flags */ 49 #include "elf/sh.h" 50 #include "dwarf2.h" 51 /* registers numbers shared with the simulator. */ 52 #include "gdb/sim-sh.h" 53 #include <algorithm> 54 55 /* List of "set sh ..." and "show sh ..." commands. */ 56 static struct cmd_list_element *setshcmdlist = NULL; 57 static struct cmd_list_element *showshcmdlist = NULL; 58 59 static const char sh_cc_gcc[] = "gcc"; 60 static const char sh_cc_renesas[] = "renesas"; 61 static const char *const sh_cc_enum[] = { 62 sh_cc_gcc, 63 sh_cc_renesas, 64 NULL 65 }; 66 67 static const char *sh_active_calling_convention = sh_cc_gcc; 68 69 #define SH_NUM_REGS 67 70 71 struct sh_frame_cache 72 { 73 /* Base address. */ 74 CORE_ADDR base; 75 LONGEST sp_offset; 76 CORE_ADDR pc; 77 78 /* Flag showing that a frame has been created in the prologue code. */ 79 int uses_fp; 80 81 /* Saved registers. */ 82 CORE_ADDR saved_regs[SH_NUM_REGS]; 83 CORE_ADDR saved_sp; 84 }; 85 86 static int 87 sh_is_renesas_calling_convention (struct type *func_type) 88 { 89 int val = 0; 90 91 if (func_type) 92 { 93 func_type = check_typedef (func_type); 94 95 if (func_type->code () == TYPE_CODE_PTR) 96 func_type = check_typedef (func_type->target_type ()); 97 98 if (func_type->code () == TYPE_CODE_FUNC 99 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) 100 val = 1; 101 } 102 103 if (sh_active_calling_convention == sh_cc_renesas) 104 val = 1; 105 106 return val; 107 } 108 109 static const char * 110 sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) 111 { 112 static const char *register_names[] = { 113 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 114 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 115 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr" 116 }; 117 118 if (reg_nr >= ARRAY_SIZE (register_names)) 119 return ""; 120 return register_names[reg_nr]; 121 } 122 123 static const char * 124 sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) 125 { 126 static const char *register_names[] = { 127 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 128 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 129 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 130 "", "", 131 "", "", "", "", "", "", "", "", 132 "", "", "", "", "", "", "", "", 133 "ssr", "spc", 134 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 135 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 136 }; 137 138 if (reg_nr >= ARRAY_SIZE (register_names)) 139 return ""; 140 return register_names[reg_nr]; 141 } 142 143 static const char * 144 sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) 145 { 146 static const char *register_names[] = { 147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 149 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 150 "fpul", "fpscr", 151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 153 "ssr", "spc", 154 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 155 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 156 }; 157 if (reg_nr >= ARRAY_SIZE (register_names)) 158 return ""; 159 return register_names[reg_nr]; 160 } 161 162 static const char * 163 sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) 164 { 165 static const char *register_names[] = { 166 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 167 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 168 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 169 "fpul", "fpscr", 170 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 171 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 172 }; 173 if (reg_nr >= ARRAY_SIZE (register_names)) 174 return ""; 175 return register_names[reg_nr]; 176 } 177 178 static const char * 179 sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) 180 { 181 static const char *register_names[] = { 182 /* general registers 0-15 */ 183 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 184 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 185 /* 16 - 22 */ 186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 187 /* 23, 24 */ 188 "fpul", "fpscr", 189 /* floating point registers 25 - 40 */ 190 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 191 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 192 /* 41, 42 */ 193 "", "", 194 /* 43 - 62. Banked registers. The bank number used is determined by 195 the bank register (63). */ 196 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 197 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 198 "machb", "ivnb", "prb", "gbrb", "maclb", 199 /* 63: register bank number, not a real register but used to 200 communicate the register bank currently get/set. This register 201 is hidden to the user, who manipulates it using the pseudo 202 register called "bank" (67). See below. */ 203 "", 204 /* 64 - 66 */ 205 "ibcr", "ibnr", "tbr", 206 /* 67: register bank number, the user visible pseudo register. */ 207 "bank", 208 /* double precision (pseudo) 68 - 75 */ 209 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 210 }; 211 if (reg_nr >= ARRAY_SIZE (register_names)) 212 return ""; 213 return register_names[reg_nr]; 214 } 215 216 static const char * 217 sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) 218 { 219 static const char *register_names[] = { 220 /* general registers 0-15 */ 221 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 222 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 223 /* 16 - 22 */ 224 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 225 /* 23, 24 */ 226 "", "", 227 /* floating point registers 25 - 40 */ 228 "", "", "", "", "", "", "", "", 229 "", "", "", "", "", "", "", "", 230 /* 41, 42 */ 231 "", "", 232 /* 43 - 62. Banked registers. The bank number used is determined by 233 the bank register (63). */ 234 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 235 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 236 "machb", "ivnb", "prb", "gbrb", "maclb", 237 /* 63: register bank number, not a real register but used to 238 communicate the register bank currently get/set. This register 239 is hidden to the user, who manipulates it using the pseudo 240 register called "bank" (67). See below. */ 241 "", 242 /* 64 - 66 */ 243 "ibcr", "ibnr", "tbr", 244 /* 67: register bank number, the user visible pseudo register. */ 245 "bank", 246 /* double precision (pseudo) 68 - 75: report blank, see below. */ 247 }; 248 if (reg_nr >= ARRAY_SIZE (register_names)) 249 return ""; 250 return register_names[reg_nr]; 251 } 252 253 static const char * 254 sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 255 { 256 static const char *register_names[] = { 257 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 258 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 259 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 260 "", "dsr", 261 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 262 "y0", "y1", "", "", "", "", "", "mod", 263 "", "", 264 "rs", "re", 265 }; 266 if (reg_nr >= ARRAY_SIZE (register_names)) 267 return ""; 268 return register_names[reg_nr]; 269 } 270 271 static const char * 272 sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 273 { 274 static const char *register_names[] = { 275 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 276 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 277 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 278 "", "dsr", 279 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 280 "y0", "y1", "", "", "", "", "", "mod", 281 "ssr", "spc", 282 "rs", "re", "", "", "", "", "", "", 283 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 284 }; 285 if (reg_nr >= ARRAY_SIZE (register_names)) 286 return ""; 287 return register_names[reg_nr]; 288 } 289 290 static const char * 291 sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) 292 { 293 static const char *register_names[] = { 294 /* general registers 0-15 */ 295 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 296 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 297 /* 16 - 22 */ 298 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 299 /* 23, 24 */ 300 "fpul", "fpscr", 301 /* floating point registers 25 - 40 */ 302 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 303 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 304 /* 41, 42 */ 305 "ssr", "spc", 306 /* bank 0 43 - 50 */ 307 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 308 /* bank 1 51 - 58 */ 309 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 310 /* 59 - 66 */ 311 "", "", "", "", "", "", "", "", 312 /* pseudo bank register. */ 313 "", 314 /* double precision (pseudo) 68 - 75 */ 315 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 316 /* vectors (pseudo) 76 - 79 */ 317 "fv0", "fv4", "fv8", "fv12", 318 /* FIXME: missing XF */ 319 /* FIXME: missing XD */ 320 }; 321 if (reg_nr >= ARRAY_SIZE (register_names)) 322 return ""; 323 return register_names[reg_nr]; 324 } 325 326 static const char * 327 sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) 328 { 329 static const char *register_names[] = { 330 /* general registers 0-15 */ 331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 333 /* 16 - 22 */ 334 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 335 /* 23, 24 */ 336 "", "", 337 /* floating point registers 25 - 40 -- not for nofpu target */ 338 "", "", "", "", "", "", "", "", 339 "", "", "", "", "", "", "", "", 340 /* 41, 42 */ 341 "ssr", "spc", 342 /* bank 0 43 - 50 */ 343 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 344 /* bank 1 51 - 58 */ 345 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 346 /* 59 - 66 */ 347 "", "", "", "", "", "", "", "", 348 /* pseudo bank register. */ 349 "", 350 /* double precision (pseudo) 68 - 75 -- not for nofpu target */ 351 "", "", "", "", "", "", "", "", 352 /* vectors (pseudo) 76 - 79 -- not for nofpu target: report blank 353 below. */ 354 }; 355 if (reg_nr >= ARRAY_SIZE (register_names)) 356 return ""; 357 return register_names[reg_nr]; 358 } 359 360 static const char * 361 sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) 362 { 363 static const char *register_names[] = { 364 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 365 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 366 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 367 "", "dsr", 368 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 369 "y0", "y1", "", "", "", "", "", "mod", 370 "ssr", "spc", 371 "rs", "re", "", "", "", "", "", "", 372 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 373 }; 374 if (reg_nr >= ARRAY_SIZE (register_names)) 375 return ""; 376 return register_names[reg_nr]; 377 } 378 379 /* Implement the breakpoint_kind_from_pc gdbarch method. */ 380 381 static int 382 sh_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 383 { 384 return 2; 385 } 386 387 /* Implement the sw_breakpoint_from_kind gdbarch method. */ 388 389 static const gdb_byte * 390 sh_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 391 { 392 *size = kind; 393 394 /* For remote stub targets, trapa #20 is used. */ 395 if (strcmp (target_shortname (), "remote") == 0) 396 { 397 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; 398 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; 399 400 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 401 return big_remote_breakpoint; 402 else 403 return little_remote_breakpoint; 404 } 405 else 406 { 407 /* 0xc3c3 is trapa #c3, and it works in big and little endian 408 modes. */ 409 static unsigned char breakpoint[] = { 0xc3, 0xc3 }; 410 411 return breakpoint; 412 } 413 } 414 415 /* Prologue looks like 416 mov.l r14,@-r15 417 sts.l pr,@-r15 418 mov.l <regs>,@-r15 419 sub <room_for_loca_vars>,r15 420 mov r15,r14 421 422 Actually it can be more complicated than this but that's it, basically. */ 423 424 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) 425 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) 426 427 /* JSR @Rm 0100mmmm00001011 */ 428 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) 429 430 /* STS.L PR,@-r15 0100111100100010 431 r15-4-->r15, PR-->(r15) */ 432 #define IS_STS(x) ((x) == 0x4f22) 433 434 /* STS.L MACL,@-r15 0100111100010010 435 r15-4-->r15, MACL-->(r15) */ 436 #define IS_MACL_STS(x) ((x) == 0x4f12) 437 438 /* MOV.L Rm,@-r15 00101111mmmm0110 439 r15-4-->r15, Rm-->(R15) */ 440 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) 441 442 /* MOV r15,r14 0110111011110011 443 r15-->r14 */ 444 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) 445 446 /* ADD #imm,r15 01111111iiiiiiii 447 r15+imm-->r15 */ 448 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) 449 450 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) 451 #define IS_SHLL_R3(x) ((x) == 0x4300) 452 453 /* ADD r3,r15 0011111100111100 454 r15+r3-->r15 */ 455 #define IS_ADD_R3SP(x) ((x) == 0x3f3c) 456 457 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 458 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 459 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ 460 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to 461 make this entirely clear. */ 462 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ 463 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) 464 465 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ 466 #define IS_MOV_ARG_TO_REG(x) \ 467 (((x) & 0xf00f) == 0x6003 && \ 468 ((x) & 0x00f0) >= 0x0040 && \ 469 ((x) & 0x00f0) <= 0x0070) 470 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ 471 #define IS_MOV_ARG_TO_IND_R14(x) \ 472 (((x) & 0xff0f) == 0x2e02 && \ 473 ((x) & 0x00f0) >= 0x0040 && \ 474 ((x) & 0x00f0) <= 0x0070) 475 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ 476 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ 477 (((x) & 0xff00) == 0x1e00 && \ 478 ((x) & 0x00f0) >= 0x0040 && \ 479 ((x) & 0x00f0) <= 0x0070) 480 481 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ 482 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) 483 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ 484 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) 485 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ 486 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) 487 /* SUB Rn,R15 00111111nnnn1000 */ 488 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) 489 490 #define FPSCR_SZ (1 << 20) 491 492 /* The following instructions are used for epilogue testing. */ 493 #define IS_RESTORE_FP(x) ((x) == 0x6ef6) 494 #define IS_RTS(x) ((x) == 0x000b) 495 #define IS_LDS(x) ((x) == 0x4f26) 496 #define IS_MACL_LDS(x) ((x) == 0x4f16) 497 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) 498 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) 499 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) 500 501 static CORE_ADDR 502 sh_analyze_prologue (struct gdbarch *gdbarch, 503 CORE_ADDR pc, CORE_ADDR limit_pc, 504 struct sh_frame_cache *cache, ULONGEST fpscr) 505 { 506 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 507 ULONGEST inst; 508 int offset; 509 int sav_offset = 0; 510 int r3_val = 0; 511 int reg, sav_reg = -1; 512 513 cache->uses_fp = 0; 514 for (; pc < limit_pc; pc += 2) 515 { 516 inst = read_memory_unsigned_integer (pc, 2, byte_order); 517 /* See where the registers will be saved to. */ 518 if (IS_PUSH (inst)) 519 { 520 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; 521 cache->sp_offset += 4; 522 } 523 else if (IS_STS (inst)) 524 { 525 cache->saved_regs[PR_REGNUM] = cache->sp_offset; 526 cache->sp_offset += 4; 527 } 528 else if (IS_MACL_STS (inst)) 529 { 530 cache->saved_regs[MACL_REGNUM] = cache->sp_offset; 531 cache->sp_offset += 4; 532 } 533 else if (IS_MOV_R3 (inst)) 534 { 535 r3_val = ((inst & 0xff) ^ 0x80) - 0x80; 536 } 537 else if (IS_SHLL_R3 (inst)) 538 { 539 r3_val <<= 1; 540 } 541 else if (IS_ADD_R3SP (inst)) 542 { 543 cache->sp_offset += -r3_val; 544 } 545 else if (IS_ADD_IMM_SP (inst)) 546 { 547 offset = ((inst & 0xff) ^ 0x80) - 0x80; 548 cache->sp_offset -= offset; 549 } 550 else if (IS_MOVW_PCREL_TO_REG (inst)) 551 { 552 if (sav_reg < 0) 553 { 554 reg = GET_TARGET_REG (inst); 555 if (reg < 14) 556 { 557 sav_reg = reg; 558 offset = (inst & 0xff) << 1; 559 sav_offset = 560 read_memory_integer ((pc + 4) + offset, 2, byte_order); 561 } 562 } 563 } 564 else if (IS_MOVL_PCREL_TO_REG (inst)) 565 { 566 if (sav_reg < 0) 567 { 568 reg = GET_TARGET_REG (inst); 569 if (reg < 14) 570 { 571 sav_reg = reg; 572 offset = (inst & 0xff) << 2; 573 sav_offset = 574 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 575 4, byte_order); 576 } 577 } 578 } 579 else if (IS_MOVI20 (inst) 580 && (pc + 2 < limit_pc)) 581 { 582 if (sav_reg < 0) 583 { 584 reg = GET_TARGET_REG (inst); 585 if (reg < 14) 586 { 587 sav_reg = reg; 588 sav_offset = GET_SOURCE_REG (inst) << 16; 589 /* MOVI20 is a 32 bit instruction! */ 590 pc += 2; 591 sav_offset 592 |= read_memory_unsigned_integer (pc, 2, byte_order); 593 /* Now sav_offset contains an unsigned 20 bit value. 594 It must still get sign extended. */ 595 if (sav_offset & 0x00080000) 596 sav_offset |= 0xfff00000; 597 } 598 } 599 } 600 else if (IS_SUB_REG_FROM_SP (inst)) 601 { 602 reg = GET_SOURCE_REG (inst); 603 if (sav_reg > 0 && reg == sav_reg) 604 { 605 sav_reg = -1; 606 } 607 cache->sp_offset += sav_offset; 608 } 609 else if (IS_FPUSH (inst)) 610 { 611 if (fpscr & FPSCR_SZ) 612 { 613 cache->sp_offset += 8; 614 } 615 else 616 { 617 cache->sp_offset += 4; 618 } 619 } 620 else if (IS_MOV_SP_FP (inst)) 621 { 622 pc += 2; 623 /* Don't go any further than six more instructions. */ 624 limit_pc = std::min (limit_pc, pc + (2 * 6)); 625 626 cache->uses_fp = 1; 627 /* At this point, only allow argument register moves to other 628 registers or argument register moves to @(X,fp) which are 629 moving the register arguments onto the stack area allocated 630 by a former add somenumber to SP call. Don't allow moving 631 to an fp indirect address above fp + cache->sp_offset. */ 632 for (; pc < limit_pc; pc += 2) 633 { 634 inst = read_memory_integer (pc, 2, byte_order); 635 if (IS_MOV_ARG_TO_IND_R14 (inst)) 636 { 637 reg = GET_SOURCE_REG (inst); 638 if (cache->sp_offset > 0) 639 cache->saved_regs[reg] = cache->sp_offset; 640 } 641 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) 642 { 643 reg = GET_SOURCE_REG (inst); 644 offset = (inst & 0xf) * 4; 645 if (cache->sp_offset > offset) 646 cache->saved_regs[reg] = cache->sp_offset - offset; 647 } 648 else if (IS_MOV_ARG_TO_REG (inst)) 649 continue; 650 else 651 break; 652 } 653 break; 654 } 655 else if (IS_JSR (inst)) 656 { 657 /* We have found a jsr that has been scheduled into the prologue. 658 If we continue the scan and return a pc someplace after this, 659 then setting a breakpoint on this function will cause it to 660 appear to be called after the function it is calling via the 661 jsr, which will be very confusing. Most likely the next 662 instruction is going to be IS_MOV_SP_FP in the delay slot. If 663 so, note that before returning the current pc. */ 664 if (pc + 2 < limit_pc) 665 { 666 inst = read_memory_integer (pc + 2, 2, byte_order); 667 if (IS_MOV_SP_FP (inst)) 668 cache->uses_fp = 1; 669 } 670 break; 671 } 672 #if 0 /* This used to just stop when it found an instruction 673 that was not considered part of the prologue. Now, 674 we just keep going looking for likely 675 instructions. */ 676 else 677 break; 678 #endif 679 } 680 681 return pc; 682 } 683 684 /* Skip any prologue before the guts of a function. */ 685 static CORE_ADDR 686 sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 687 { 688 CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; 689 struct sh_frame_cache cache; 690 691 /* See if we can determine the end of the prologue via the symbol table. 692 If so, then return either PC, or the PC after the prologue, whichever 693 is greater. */ 694 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) 695 { 696 post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); 697 if (post_prologue_pc != 0) 698 return std::max (pc, post_prologue_pc); 699 } 700 701 /* Can't determine prologue from the symbol table, need to examine 702 instructions. */ 703 704 /* Find an upper limit on the function prologue using the debug 705 information. If the debug information could not be used to provide 706 that bound, then use an arbitrary large number as the upper bound. */ 707 limit_pc = skip_prologue_using_sal (gdbarch, pc); 708 if (limit_pc == 0) 709 /* Don't go any further than 28 instructions. */ 710 limit_pc = pc + (2 * 28); 711 712 /* Do not allow limit_pc to be past the function end, if we know 713 where that end is... */ 714 if (func_end_addr != 0) 715 limit_pc = std::min (limit_pc, func_end_addr); 716 717 cache.sp_offset = -4; 718 post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); 719 if (cache.uses_fp) 720 pc = post_prologue_pc; 721 722 return pc; 723 } 724 725 /* The ABI says: 726 727 Aggregate types not bigger than 8 bytes that have the same size and 728 alignment as one of the integer scalar types are returned in the 729 same registers as the integer type they match. 730 731 For example, a 2-byte aligned structure with size 2 bytes has the 732 same size and alignment as a short int, and will be returned in R0. 733 A 4-byte aligned structure with size 8 bytes has the same size and 734 alignment as a long long int, and will be returned in R0 and R1. 735 736 When an aggregate type is returned in R0 and R1, R0 contains the 737 first four bytes of the aggregate, and R1 contains the 738 remainder. If the size of the aggregate type is not a multiple of 4 739 bytes, the aggregate is tail-padded up to a multiple of 4 740 bytes. The value of the padding is undefined. For little-endian 741 targets the padding will appear at the most significant end of the 742 last element, for big-endian targets the padding appears at the 743 least significant end of the last element. 744 745 All other aggregate types are returned by address. The caller 746 function passes the address of an area large enough to hold the 747 aggregate value in R2. The called function stores the result in 748 this location. 749 750 To reiterate, structs smaller than 8 bytes could also be returned 751 in memory, if they don't pass the "same size and alignment as an 752 integer type" rule. 753 754 For example, in 755 756 struct s { char c[3]; } wibble; 757 struct s foo(void) { return wibble; } 758 759 the return value from foo() will be in memory, not 760 in R0, because there is no 3-byte integer type. 761 762 Similarly, in 763 764 struct s { char c[2]; } wibble; 765 struct s foo(void) { return wibble; } 766 767 because a struct containing two chars has alignment 1, that matches 768 type char, but size 2, that matches type short. There's no integer 769 type that has alignment 1 and size 2, so the struct is returned in 770 memory. */ 771 772 static int 773 sh_use_struct_convention (int renesas_abi, struct type *type) 774 { 775 int len = type->length (); 776 int nelem = type->num_fields (); 777 778 /* The Renesas ABI returns aggregate types always on stack. */ 779 if (renesas_abi && (type->code () == TYPE_CODE_STRUCT 780 || type->code () == TYPE_CODE_UNION)) 781 return 1; 782 783 /* Non-power of 2 length types and types bigger than 8 bytes (which don't 784 fit in two registers anyway) use struct convention. */ 785 if (len != 1 && len != 2 && len != 4 && len != 8) 786 return 1; 787 788 /* Scalar types and aggregate types with exactly one field are aligned 789 by definition. They are returned in registers. */ 790 if (nelem <= 1) 791 return 0; 792 793 /* If the first field in the aggregate has the same length as the entire 794 aggregate type, the type is returned in registers. */ 795 if (type->field (0).type ()->length () == len) 796 return 0; 797 798 /* If the size of the aggregate is 8 bytes and the first field is 799 of size 4 bytes its alignment is equal to long long's alignment, 800 so it's returned in registers. */ 801 if (len == 8 && type->field (0).type ()->length () == 4) 802 return 0; 803 804 /* Otherwise use struct convention. */ 805 return 1; 806 } 807 808 static int 809 sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) 810 { 811 /* The Renesas ABI returns long longs/doubles etc. always on stack. */ 812 if (renesas_abi && type->num_fields () == 0 && type->length () >= 8) 813 return 1; 814 return sh_use_struct_convention (renesas_abi, type); 815 } 816 817 static CORE_ADDR 818 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) 819 { 820 return sp & ~3; 821 } 822 823 /* Function: push_dummy_call (formerly push_arguments) 824 Setup the function arguments for calling a function in the inferior. 825 826 On the Renesas SH architecture, there are four registers (R4 to R7) 827 which are dedicated for passing function arguments. Up to the first 828 four arguments (depending on size) may go into these registers. 829 The rest go on the stack. 830 831 MVS: Except on SH variants that have floating point registers. 832 In that case, float and double arguments are passed in the same 833 manner, but using FP registers instead of GP registers. 834 835 Arguments that are smaller than 4 bytes will still take up a whole 836 register or a whole 32-bit word on the stack, and will be 837 right-justified in the register or the stack word. This includes 838 chars, shorts, and small aggregate types. 839 840 Arguments that are larger than 4 bytes may be split between two or 841 more registers. If there are not enough registers free, an argument 842 may be passed partly in a register (or registers), and partly on the 843 stack. This includes doubles, long longs, and larger aggregates. 844 As far as I know, there is no upper limit to the size of aggregates 845 that will be passed in this way; in other words, the convention of 846 passing a pointer to a large aggregate instead of a copy is not used. 847 848 MVS: The above appears to be true for the SH variants that do not 849 have an FPU, however those that have an FPU appear to copy the 850 aggregate argument onto the stack (and not place it in registers) 851 if it is larger than 16 bytes (four GP registers). 852 853 An exceptional case exists for struct arguments (and possibly other 854 aggregates such as arrays) if the size is larger than 4 bytes but 855 not a multiple of 4 bytes. In this case the argument is never split 856 between the registers and the stack, but instead is copied in its 857 entirety onto the stack, AND also copied into as many registers as 858 there is room for. In other words, space in registers permitting, 859 two copies of the same argument are passed in. As far as I can tell, 860 only the one on the stack is used, although that may be a function 861 of the level of compiler optimization. I suspect this is a compiler 862 bug. Arguments of these odd sizes are left-justified within the 863 word (as opposed to arguments smaller than 4 bytes, which are 864 right-justified). 865 866 If the function is to return an aggregate type such as a struct, it 867 is either returned in the normal return value register R0 (if its 868 size is no greater than one byte), or else the caller must allocate 869 space into which the callee will copy the return value (if the size 870 is greater than one byte). In this case, a pointer to the return 871 value location is passed into the callee in register R2, which does 872 not displace any of the other arguments passed in via registers R4 873 to R7. */ 874 875 /* Helper function to justify value in register according to endianness. */ 876 static const gdb_byte * 877 sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) 878 { 879 static gdb_byte valbuf[4]; 880 881 memset (valbuf, 0, sizeof (valbuf)); 882 if (len < 4) 883 { 884 /* value gets right-justified in the register or stack word. */ 885 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 886 memcpy (valbuf + (4 - len), value_contents (val).data (), len); 887 else 888 memcpy (valbuf, value_contents (val).data (), len); 889 return valbuf; 890 } 891 return value_contents (val).data (); 892 } 893 894 /* Helper function to eval number of bytes to allocate on stack. */ 895 static CORE_ADDR 896 sh_stack_allocsize (int nargs, struct value **args) 897 { 898 int stack_alloc = 0; 899 while (nargs-- > 0) 900 stack_alloc += ((value_type (args[nargs])->length () + 3) & ~3); 901 return stack_alloc; 902 } 903 904 /* Helper functions for getting the float arguments right. Registers usage 905 depends on the ABI and the endianness. The comments should enlighten how 906 it's intended to work. */ 907 908 /* This array stores which of the float arg registers are already in use. */ 909 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; 910 911 /* This function just resets the above array to "no reg used so far". */ 912 static void 913 sh_init_flt_argreg (void) 914 { 915 memset (flt_argreg_array, 0, sizeof flt_argreg_array); 916 } 917 918 /* This function returns the next register to use for float arg passing. 919 It returns either a valid value between FLOAT_ARG0_REGNUM and 920 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns 921 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. 922 923 Note that register number 0 in flt_argreg_array corresponds with the 924 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is 925 29) the parity of the register number is preserved, which is important 926 for the double register passing test (see the "argreg & 1" test below). */ 927 static int 928 sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) 929 { 930 int argreg; 931 932 /* First search for the next free register. */ 933 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; 934 ++argreg) 935 if (!flt_argreg_array[argreg]) 936 break; 937 938 /* No register left? */ 939 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 940 return FLOAT_ARGLAST_REGNUM + 1; 941 942 if (len == 8) 943 { 944 /* Doubles are always starting in a even register number. */ 945 if (argreg & 1) 946 { 947 /* In gcc ABI, the skipped register is lost for further argument 948 passing now. Not so in Renesas ABI. */ 949 if (!sh_is_renesas_calling_convention (func_type)) 950 flt_argreg_array[argreg] = 1; 951 952 ++argreg; 953 954 /* No register left? */ 955 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 956 return FLOAT_ARGLAST_REGNUM + 1; 957 } 958 /* Also mark the next register as used. */ 959 flt_argreg_array[argreg + 1] = 1; 960 } 961 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 962 && !sh_is_renesas_calling_convention (func_type)) 963 { 964 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ 965 if (!flt_argreg_array[argreg + 1]) 966 ++argreg; 967 } 968 flt_argreg_array[argreg] = 1; 969 return FLOAT_ARG0_REGNUM + argreg; 970 } 971 972 /* Helper function which figures out, if a type is treated like a float type. 973 974 The FPU ABIs have a special way how to treat types as float types. 975 Structures with exactly one member, which is of type float or double, are 976 treated exactly as the base types float or double: 977 978 struct sf { 979 float f; 980 }; 981 982 struct sd { 983 double d; 984 }; 985 986 are handled the same way as just 987 988 float f; 989 990 double d; 991 992 As a result, arguments of these struct types are pushed into floating point 993 registers exactly as floats or doubles, using the same decision algorithm. 994 995 The same is valid if these types are used as function return types. The 996 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 997 or even using struct convention as it is for other structs. */ 998 999 static int 1000 sh_treat_as_flt_p (struct type *type) 1001 { 1002 /* Ordinary float types are obviously treated as float. */ 1003 if (type->code () == TYPE_CODE_FLT) 1004 return 1; 1005 /* Otherwise non-struct types are not treated as float. */ 1006 if (type->code () != TYPE_CODE_STRUCT) 1007 return 0; 1008 /* Otherwise structs with more than one member are not treated as float. */ 1009 if (type->num_fields () != 1) 1010 return 0; 1011 /* Otherwise if the type of that member is float, the whole type is 1012 treated as float. */ 1013 if (type->field (0).type ()->code () == TYPE_CODE_FLT) 1014 return 1; 1015 /* Otherwise it's not treated as float. */ 1016 return 0; 1017 } 1018 1019 static CORE_ADDR 1020 sh_push_dummy_call_fpu (struct gdbarch *gdbarch, 1021 struct value *function, 1022 struct regcache *regcache, 1023 CORE_ADDR bp_addr, int nargs, 1024 struct value **args, 1025 CORE_ADDR sp, function_call_return_method return_method, 1026 CORE_ADDR struct_addr) 1027 { 1028 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1029 int stack_offset = 0; 1030 int argreg = ARG0_REGNUM; 1031 int flt_argreg = 0; 1032 int argnum; 1033 struct type *func_type = value_type (function); 1034 struct type *type; 1035 CORE_ADDR regval; 1036 const gdb_byte *val; 1037 int len, reg_size = 0; 1038 int pass_on_stack = 0; 1039 int treat_as_flt; 1040 int last_reg_arg = INT_MAX; 1041 1042 /* The Renesas ABI expects all varargs arguments, plus the last 1043 non-vararg argument to be on the stack, no matter how many 1044 registers have been used so far. */ 1045 if (sh_is_renesas_calling_convention (func_type) 1046 && func_type->has_varargs ()) 1047 last_reg_arg = func_type->num_fields () - 2; 1048 1049 /* First force sp to a 4-byte alignment. */ 1050 sp = sh_frame_align (gdbarch, sp); 1051 1052 /* Make room on stack for args. */ 1053 sp -= sh_stack_allocsize (nargs, args); 1054 1055 /* Initialize float argument mechanism. */ 1056 sh_init_flt_argreg (); 1057 1058 /* Now load as many as possible of the first arguments into 1059 registers, and push the rest onto the stack. There are 16 bytes 1060 in four registers available. Loop thru args from first to last. */ 1061 for (argnum = 0; argnum < nargs; argnum++) 1062 { 1063 type = value_type (args[argnum]); 1064 len = type->length (); 1065 val = sh_justify_value_in_reg (gdbarch, args[argnum], len); 1066 1067 /* Some decisions have to be made how various types are handled. 1068 This also differs in different ABIs. */ 1069 pass_on_stack = 0; 1070 1071 /* Find out the next register to use for a floating point value. */ 1072 treat_as_flt = sh_treat_as_flt_p (type); 1073 if (treat_as_flt) 1074 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); 1075 /* In Renesas ABI, long longs and aggregate types are always passed 1076 on stack. */ 1077 else if (sh_is_renesas_calling_convention (func_type) 1078 && ((type->code () == TYPE_CODE_INT && len == 8) 1079 || type->code () == TYPE_CODE_STRUCT 1080 || type->code () == TYPE_CODE_UNION)) 1081 pass_on_stack = 1; 1082 /* In contrast to non-FPU CPUs, arguments are never split between 1083 registers and stack. If an argument doesn't fit in the remaining 1084 registers it's always pushed entirely on the stack. */ 1085 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) 1086 pass_on_stack = 1; 1087 1088 while (len > 0) 1089 { 1090 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) 1091 || (!treat_as_flt && (argreg > ARGLAST_REGNUM 1092 || pass_on_stack)) 1093 || argnum > last_reg_arg) 1094 { 1095 /* The data goes entirely on the stack, 4-byte aligned. */ 1096 reg_size = (len + 3) & ~3; 1097 write_memory (sp + stack_offset, val, reg_size); 1098 stack_offset += reg_size; 1099 } 1100 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) 1101 { 1102 /* Argument goes in a float argument register. */ 1103 reg_size = register_size (gdbarch, flt_argreg); 1104 regval = extract_unsigned_integer (val, reg_size, byte_order); 1105 /* In little endian mode, float types taking two registers 1106 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must 1107 be stored swapped in the argument registers. The below 1108 code first writes the first 32 bits in the next but one 1109 register, increments the val and len values accordingly 1110 and then proceeds as normal by writing the second 32 bits 1111 into the next register. */ 1112 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE 1113 && type->length () == 2 * reg_size) 1114 { 1115 regcache_cooked_write_unsigned (regcache, flt_argreg + 1, 1116 regval); 1117 val += reg_size; 1118 len -= reg_size; 1119 regval = extract_unsigned_integer (val, reg_size, 1120 byte_order); 1121 } 1122 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); 1123 } 1124 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) 1125 { 1126 /* there's room in a register */ 1127 reg_size = register_size (gdbarch, argreg); 1128 regval = extract_unsigned_integer (val, reg_size, byte_order); 1129 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1130 } 1131 /* Store the value one register at a time or in one step on 1132 stack. */ 1133 len -= reg_size; 1134 val += reg_size; 1135 } 1136 } 1137 1138 if (return_method == return_method_struct) 1139 { 1140 if (sh_is_renesas_calling_convention (func_type)) 1141 /* If the function uses the Renesas ABI, subtract another 4 bytes from 1142 the stack and store the struct return address there. */ 1143 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); 1144 else 1145 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has 1146 its own dedicated register. */ 1147 regcache_cooked_write_unsigned (regcache, 1148 STRUCT_RETURN_REGNUM, struct_addr); 1149 } 1150 1151 /* Store return address. */ 1152 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1153 1154 /* Update stack pointer. */ 1155 regcache_cooked_write_unsigned (regcache, 1156 gdbarch_sp_regnum (gdbarch), sp); 1157 1158 return sp; 1159 } 1160 1161 static CORE_ADDR 1162 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, 1163 struct value *function, 1164 struct regcache *regcache, 1165 CORE_ADDR bp_addr, 1166 int nargs, struct value **args, 1167 CORE_ADDR sp, 1168 function_call_return_method return_method, 1169 CORE_ADDR struct_addr) 1170 { 1171 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1172 int stack_offset = 0; 1173 int argreg = ARG0_REGNUM; 1174 int argnum; 1175 struct type *func_type = value_type (function); 1176 struct type *type; 1177 CORE_ADDR regval; 1178 const gdb_byte *val; 1179 int len, reg_size = 0; 1180 int pass_on_stack = 0; 1181 int last_reg_arg = INT_MAX; 1182 1183 /* The Renesas ABI expects all varargs arguments, plus the last 1184 non-vararg argument to be on the stack, no matter how many 1185 registers have been used so far. */ 1186 if (sh_is_renesas_calling_convention (func_type) 1187 && func_type->has_varargs ()) 1188 last_reg_arg = func_type->num_fields () - 2; 1189 1190 /* First force sp to a 4-byte alignment. */ 1191 sp = sh_frame_align (gdbarch, sp); 1192 1193 /* Make room on stack for args. */ 1194 sp -= sh_stack_allocsize (nargs, args); 1195 1196 /* Now load as many as possible of the first arguments into 1197 registers, and push the rest onto the stack. There are 16 bytes 1198 in four registers available. Loop thru args from first to last. */ 1199 for (argnum = 0; argnum < nargs; argnum++) 1200 { 1201 type = value_type (args[argnum]); 1202 len = type->length (); 1203 val = sh_justify_value_in_reg (gdbarch, args[argnum], len); 1204 1205 /* Some decisions have to be made how various types are handled. 1206 This also differs in different ABIs. */ 1207 pass_on_stack = 0; 1208 /* Renesas ABI pushes doubles and long longs entirely on stack. 1209 Same goes for aggregate types. */ 1210 if (sh_is_renesas_calling_convention (func_type) 1211 && ((type->code () == TYPE_CODE_INT && len >= 8) 1212 || (type->code () == TYPE_CODE_FLT && len >= 8) 1213 || type->code () == TYPE_CODE_STRUCT 1214 || type->code () == TYPE_CODE_UNION)) 1215 pass_on_stack = 1; 1216 while (len > 0) 1217 { 1218 if (argreg > ARGLAST_REGNUM || pass_on_stack 1219 || argnum > last_reg_arg) 1220 { 1221 /* The remainder of the data goes entirely on the stack, 1222 4-byte aligned. */ 1223 reg_size = (len + 3) & ~3; 1224 write_memory (sp + stack_offset, val, reg_size); 1225 stack_offset += reg_size; 1226 } 1227 else if (argreg <= ARGLAST_REGNUM) 1228 { 1229 /* There's room in a register. */ 1230 reg_size = register_size (gdbarch, argreg); 1231 regval = extract_unsigned_integer (val, reg_size, byte_order); 1232 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1233 } 1234 /* Store the value reg_size bytes at a time. This means that things 1235 larger than reg_size bytes may go partly in registers and partly 1236 on the stack. */ 1237 len -= reg_size; 1238 val += reg_size; 1239 } 1240 } 1241 1242 if (return_method == return_method_struct) 1243 { 1244 if (sh_is_renesas_calling_convention (func_type)) 1245 /* If the function uses the Renesas ABI, subtract another 4 bytes from 1246 the stack and store the struct return address there. */ 1247 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); 1248 else 1249 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has 1250 its own dedicated register. */ 1251 regcache_cooked_write_unsigned (regcache, 1252 STRUCT_RETURN_REGNUM, struct_addr); 1253 } 1254 1255 /* Store return address. */ 1256 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1257 1258 /* Update stack pointer. */ 1259 regcache_cooked_write_unsigned (regcache, 1260 gdbarch_sp_regnum (gdbarch), sp); 1261 1262 return sp; 1263 } 1264 1265 /* Find a function's return value in the appropriate registers (in 1266 regbuf), and copy it into valbuf. Extract from an array REGBUF 1267 containing the (raw) register state a function return value of type 1268 TYPE, and copy that, in virtual format, into VALBUF. */ 1269 static void 1270 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, 1271 gdb_byte *valbuf) 1272 { 1273 struct gdbarch *gdbarch = regcache->arch (); 1274 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1275 int len = type->length (); 1276 1277 if (len <= 4) 1278 { 1279 ULONGEST c; 1280 1281 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); 1282 store_unsigned_integer (valbuf, len, byte_order, c); 1283 } 1284 else if (len == 8) 1285 { 1286 int i, regnum = R0_REGNUM; 1287 for (i = 0; i < len; i += 4) 1288 regcache->raw_read (regnum++, valbuf + i); 1289 } 1290 else 1291 error (_("bad size for return value")); 1292 } 1293 1294 static void 1295 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, 1296 gdb_byte *valbuf) 1297 { 1298 struct gdbarch *gdbarch = regcache->arch (); 1299 if (sh_treat_as_flt_p (type)) 1300 { 1301 int len = type->length (); 1302 int i, regnum = gdbarch_fp0_regnum (gdbarch); 1303 for (i = 0; i < len; i += 4) 1304 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) 1305 regcache->raw_read (regnum++, 1306 valbuf + len - 4 - i); 1307 else 1308 regcache->raw_read (regnum++, valbuf + i); 1309 } 1310 else 1311 sh_extract_return_value_nofpu (type, regcache, valbuf); 1312 } 1313 1314 /* Write into appropriate registers a function return value 1315 of type TYPE, given in virtual format. 1316 If the architecture is sh4 or sh3e, store a function's return value 1317 in the R0 general register or in the FP0 floating point register, 1318 depending on the type of the return value. In all the other cases 1319 the result is stored in r0, left-justified. */ 1320 static void 1321 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, 1322 const gdb_byte *valbuf) 1323 { 1324 struct gdbarch *gdbarch = regcache->arch (); 1325 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1326 ULONGEST val; 1327 int len = type->length (); 1328 1329 if (len <= 4) 1330 { 1331 val = extract_unsigned_integer (valbuf, len, byte_order); 1332 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); 1333 } 1334 else 1335 { 1336 int i, regnum = R0_REGNUM; 1337 for (i = 0; i < len; i += 4) 1338 regcache->raw_write (regnum++, valbuf + i); 1339 } 1340 } 1341 1342 static void 1343 sh_store_return_value_fpu (struct type *type, struct regcache *regcache, 1344 const gdb_byte *valbuf) 1345 { 1346 struct gdbarch *gdbarch = regcache->arch (); 1347 if (sh_treat_as_flt_p (type)) 1348 { 1349 int len = type->length (); 1350 int i, regnum = gdbarch_fp0_regnum (gdbarch); 1351 for (i = 0; i < len; i += 4) 1352 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) 1353 regcache->raw_write (regnum++, 1354 valbuf + len - 4 - i); 1355 else 1356 regcache->raw_write (regnum++, valbuf + i); 1357 } 1358 else 1359 sh_store_return_value_nofpu (type, regcache, valbuf); 1360 } 1361 1362 static enum return_value_convention 1363 sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, 1364 struct type *type, struct regcache *regcache, 1365 gdb_byte *readbuf, const gdb_byte *writebuf) 1366 { 1367 struct type *func_type = function ? value_type (function) : NULL; 1368 1369 if (sh_use_struct_convention_nofpu 1370 (sh_is_renesas_calling_convention (func_type), type)) 1371 return RETURN_VALUE_STRUCT_CONVENTION; 1372 if (writebuf) 1373 sh_store_return_value_nofpu (type, regcache, writebuf); 1374 else if (readbuf) 1375 sh_extract_return_value_nofpu (type, regcache, readbuf); 1376 return RETURN_VALUE_REGISTER_CONVENTION; 1377 } 1378 1379 static enum return_value_convention 1380 sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, 1381 struct type *type, struct regcache *regcache, 1382 gdb_byte *readbuf, const gdb_byte *writebuf) 1383 { 1384 struct type *func_type = function ? value_type (function) : NULL; 1385 1386 if (sh_use_struct_convention ( 1387 sh_is_renesas_calling_convention (func_type), type)) 1388 return RETURN_VALUE_STRUCT_CONVENTION; 1389 if (writebuf) 1390 sh_store_return_value_fpu (type, regcache, writebuf); 1391 else if (readbuf) 1392 sh_extract_return_value_fpu (type, regcache, readbuf); 1393 return RETURN_VALUE_REGISTER_CONVENTION; 1394 } 1395 1396 static struct type * 1397 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) 1398 { 1399 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 1400 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1401 return builtin_type (gdbarch)->builtin_float; 1402 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1403 return builtin_type (gdbarch)->builtin_double; 1404 else 1405 return builtin_type (gdbarch)->builtin_int; 1406 } 1407 1408 /* Return the GDB type object for the "standard" data type 1409 of data in register N. */ 1410 static struct type * 1411 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) 1412 { 1413 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 1414 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1415 return builtin_type (gdbarch)->builtin_float; 1416 else 1417 return builtin_type (gdbarch)->builtin_int; 1418 } 1419 1420 static struct type * 1421 sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) 1422 { 1423 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, 1424 0, high); 1425 } 1426 1427 static struct type * 1428 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) 1429 { 1430 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) 1431 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1432 return builtin_type (gdbarch)->builtin_float; 1433 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1434 return builtin_type (gdbarch)->builtin_double; 1435 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1436 return sh_sh4_build_float_register_type (gdbarch, 3); 1437 else 1438 return builtin_type (gdbarch)->builtin_int; 1439 } 1440 1441 static struct type * 1442 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) 1443 { 1444 return builtin_type (gdbarch)->builtin_int; 1445 } 1446 1447 /* Is a register in a reggroup? 1448 The default code in reggroup.c doesn't identify system registers, some 1449 float registers or any of the vector registers. 1450 TODO: sh2a and dsp registers. */ 1451 static int 1452 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 1453 const struct reggroup *reggroup) 1454 { 1455 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 1456 return 0; 1457 1458 if (reggroup == float_reggroup 1459 && (regnum == FPUL_REGNUM 1460 || regnum == FPSCR_REGNUM)) 1461 return 1; 1462 1463 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) 1464 { 1465 if (reggroup == vector_reggroup || reggroup == float_reggroup) 1466 return 1; 1467 if (reggroup == general_reggroup) 1468 return 0; 1469 } 1470 1471 if (regnum == VBR_REGNUM 1472 || regnum == SR_REGNUM 1473 || regnum == FPSCR_REGNUM 1474 || regnum == SSR_REGNUM 1475 || regnum == SPC_REGNUM) 1476 { 1477 if (reggroup == system_reggroup) 1478 return 1; 1479 if (reggroup == general_reggroup) 1480 return 0; 1481 } 1482 1483 /* The default code can cope with any other registers. */ 1484 return default_register_reggroup_p (gdbarch, regnum, reggroup); 1485 } 1486 1487 /* On the sh4, the DRi pseudo registers are problematic if the target 1488 is little endian. When the user writes one of those registers, for 1489 instance with 'set var $dr0=1', we want the double to be stored 1490 like this: 1491 fr0 = 0x00 0x00 0xf0 0x3f 1492 fr1 = 0x00 0x00 0x00 0x00 1493 1494 This corresponds to little endian byte order & big endian word 1495 order. However if we let gdb write the register w/o conversion, it 1496 will write fr0 and fr1 this way: 1497 fr0 = 0x00 0x00 0x00 0x00 1498 fr1 = 0x00 0x00 0xf0 0x3f 1499 because it will consider fr0 and fr1 as a single LE stretch of memory. 1500 1501 To achieve what we want we must force gdb to store things in 1502 floatformat_ieee_double_littlebyte_bigword (which is defined in 1503 include/floatformat.h and libiberty/floatformat.c. 1504 1505 In case the target is big endian, there is no problem, the 1506 raw bytes will look like: 1507 fr0 = 0x3f 0xf0 0x00 0x00 1508 fr1 = 0x00 0x00 0x00 0x00 1509 1510 The other pseudo registers (the FVs) also don't pose a problem 1511 because they are stored as 4 individual FP elements. */ 1512 1513 static struct type * 1514 sh_littlebyte_bigword_type (struct gdbarch *gdbarch) 1515 { 1516 sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); 1517 1518 if (tdep->sh_littlebyte_bigword_type == NULL) 1519 tdep->sh_littlebyte_bigword_type 1520 = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword", 1521 floatformats_ieee_double_littlebyte_bigword); 1522 1523 return tdep->sh_littlebyte_bigword_type; 1524 } 1525 1526 static void 1527 sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, 1528 struct type *type, gdb_byte *from, gdb_byte *to) 1529 { 1530 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) 1531 { 1532 /* It is a no-op. */ 1533 memcpy (to, from, register_size (gdbarch, regnum)); 1534 return; 1535 } 1536 1537 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 1538 target_float_convert (from, sh_littlebyte_bigword_type (gdbarch), 1539 to, type); 1540 else 1541 error 1542 ("sh_register_convert_to_virtual called with non DR register number"); 1543 } 1544 1545 static void 1546 sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, 1547 int regnum, const gdb_byte *from, gdb_byte *to) 1548 { 1549 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) 1550 { 1551 /* It is a no-op. */ 1552 memcpy (to, from, register_size (gdbarch, regnum)); 1553 return; 1554 } 1555 1556 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 1557 target_float_convert (from, type, 1558 to, sh_littlebyte_bigword_type (gdbarch)); 1559 else 1560 error (_("sh_register_convert_to_raw called with non DR register number")); 1561 } 1562 1563 /* For vectors of 4 floating point registers. */ 1564 static int 1565 fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) 1566 { 1567 int fp_regnum; 1568 1569 fp_regnum = gdbarch_fp0_regnum (gdbarch) 1570 + (fv_regnum - FV0_REGNUM) * 4; 1571 return fp_regnum; 1572 } 1573 1574 /* For double precision floating point registers, i.e 2 fp regs. */ 1575 static int 1576 dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) 1577 { 1578 int fp_regnum; 1579 1580 fp_regnum = gdbarch_fp0_regnum (gdbarch) 1581 + (dr_regnum - DR0_REGNUM) * 2; 1582 return fp_regnum; 1583 } 1584 1585 /* Concatenate PORTIONS contiguous raw registers starting at 1586 BASE_REGNUM into BUFFER. */ 1587 1588 static enum register_status 1589 pseudo_register_read_portions (struct gdbarch *gdbarch, 1590 readable_regcache *regcache, 1591 int portions, 1592 int base_regnum, gdb_byte *buffer) 1593 { 1594 int portion; 1595 1596 for (portion = 0; portion < portions; portion++) 1597 { 1598 enum register_status status; 1599 gdb_byte *b; 1600 1601 b = buffer + register_size (gdbarch, base_regnum) * portion; 1602 status = regcache->raw_read (base_regnum + portion, b); 1603 if (status != REG_VALID) 1604 return status; 1605 } 1606 1607 return REG_VALID; 1608 } 1609 1610 static enum register_status 1611 sh_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 1612 int reg_nr, gdb_byte *buffer) 1613 { 1614 int base_regnum; 1615 enum register_status status; 1616 1617 if (reg_nr == PSEUDO_BANK_REGNUM) 1618 return regcache->raw_read (BANK_REGNUM, buffer); 1619 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1620 { 1621 /* Enough space for two float registers. */ 1622 gdb_byte temp_buffer[4 * 2]; 1623 base_regnum = dr_reg_base_num (gdbarch, reg_nr); 1624 1625 /* Build the value in the provided buffer. */ 1626 /* Read the real regs for which this one is an alias. */ 1627 status = pseudo_register_read_portions (gdbarch, regcache, 1628 2, base_regnum, temp_buffer); 1629 if (status == REG_VALID) 1630 { 1631 /* We must pay attention to the endianness. */ 1632 sh_register_convert_to_virtual (gdbarch, reg_nr, 1633 register_type (gdbarch, reg_nr), 1634 temp_buffer, buffer); 1635 } 1636 return status; 1637 } 1638 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1639 { 1640 base_regnum = fv_reg_base_num (gdbarch, reg_nr); 1641 1642 /* Read the real regs for which this one is an alias. */ 1643 return pseudo_register_read_portions (gdbarch, regcache, 1644 4, base_regnum, buffer); 1645 } 1646 else 1647 gdb_assert_not_reached ("invalid pseudo register number"); 1648 } 1649 1650 static void 1651 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 1652 int reg_nr, const gdb_byte *buffer) 1653 { 1654 int base_regnum, portion; 1655 1656 if (reg_nr == PSEUDO_BANK_REGNUM) 1657 { 1658 /* When the bank register is written to, the whole register bank 1659 is switched and all values in the bank registers must be read 1660 from the target/sim again. We're just invalidating the regcache 1661 so that a re-read happens next time it's necessary. */ 1662 int bregnum; 1663 1664 regcache->raw_write (BANK_REGNUM, buffer); 1665 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) 1666 regcache->invalidate (bregnum); 1667 } 1668 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1669 { 1670 /* Enough space for two float registers. */ 1671 gdb_byte temp_buffer[4 * 2]; 1672 base_regnum = dr_reg_base_num (gdbarch, reg_nr); 1673 1674 /* We must pay attention to the endianness. */ 1675 sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), 1676 reg_nr, buffer, temp_buffer); 1677 1678 /* Write the real regs for which this one is an alias. */ 1679 for (portion = 0; portion < 2; portion++) 1680 regcache->raw_write (base_regnum + portion, 1681 (temp_buffer 1682 + register_size (gdbarch, 1683 base_regnum) * portion)); 1684 } 1685 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1686 { 1687 base_regnum = fv_reg_base_num (gdbarch, reg_nr); 1688 1689 /* Write the real regs for which this one is an alias. */ 1690 for (portion = 0; portion < 4; portion++) 1691 regcache->raw_write (base_regnum + portion, 1692 (buffer 1693 + register_size (gdbarch, 1694 base_regnum) * portion)); 1695 } 1696 } 1697 1698 static int 1699 sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) 1700 { 1701 if (legacy_register_sim_regno (gdbarch, nr) < 0) 1702 return legacy_register_sim_regno (gdbarch, nr); 1703 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) 1704 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; 1705 if (nr == MOD_REGNUM) 1706 return SIM_SH_MOD_REGNUM; 1707 if (nr == RS_REGNUM) 1708 return SIM_SH_RS_REGNUM; 1709 if (nr == RE_REGNUM) 1710 return SIM_SH_RE_REGNUM; 1711 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) 1712 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; 1713 return nr; 1714 } 1715 1716 static int 1717 sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) 1718 { 1719 switch (nr) 1720 { 1721 case TBR_REGNUM: 1722 return SIM_SH_TBR_REGNUM; 1723 case IBNR_REGNUM: 1724 return SIM_SH_IBNR_REGNUM; 1725 case IBCR_REGNUM: 1726 return SIM_SH_IBCR_REGNUM; 1727 case BANK_REGNUM: 1728 return SIM_SH_BANK_REGNUM; 1729 case MACLB_REGNUM: 1730 return SIM_SH_BANK_MACL_REGNUM; 1731 case GBRB_REGNUM: 1732 return SIM_SH_BANK_GBR_REGNUM; 1733 case PRB_REGNUM: 1734 return SIM_SH_BANK_PR_REGNUM; 1735 case IVNB_REGNUM: 1736 return SIM_SH_BANK_IVN_REGNUM; 1737 case MACHB_REGNUM: 1738 return SIM_SH_BANK_MACH_REGNUM; 1739 default: 1740 break; 1741 } 1742 return legacy_register_sim_regno (gdbarch, nr); 1743 } 1744 1745 /* Set up the register unwinding such that call-clobbered registers are 1746 not displayed in frames >0 because the true value is not certain. 1747 The 'undefined' registers will show up as 'not available' unless the 1748 CFI says otherwise. 1749 1750 This function is currently set up for SH4 and compatible only. */ 1751 1752 static void 1753 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1754 struct dwarf2_frame_state_reg *reg, 1755 frame_info_ptr this_frame) 1756 { 1757 /* Mark the PC as the destination for the return address. */ 1758 if (regnum == gdbarch_pc_regnum (gdbarch)) 1759 reg->how = DWARF2_FRAME_REG_RA; 1760 1761 /* Mark the stack pointer as the call frame address. */ 1762 else if (regnum == gdbarch_sp_regnum (gdbarch)) 1763 reg->how = DWARF2_FRAME_REG_CFA; 1764 1765 /* The above was taken from the default init_reg in dwarf2-frame.c 1766 while the below is SH specific. */ 1767 1768 /* Caller save registers. */ 1769 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) 1770 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) 1771 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) 1772 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) 1773 || (regnum == MACH_REGNUM) 1774 || (regnum == MACL_REGNUM) 1775 || (regnum == FPUL_REGNUM) 1776 || (regnum == SR_REGNUM)) 1777 reg->how = DWARF2_FRAME_REG_UNDEFINED; 1778 1779 /* Callee save registers. */ 1780 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) 1781 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) 1782 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) 1783 || (regnum == FV0_REGNUM+3)) 1784 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1785 1786 /* Other registers. These are not in the ABI and may or may not 1787 mean anything in frames >0 so don't show them. */ 1788 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) 1789 || (regnum == GBR_REGNUM) 1790 || (regnum == VBR_REGNUM) 1791 || (regnum == FPSCR_REGNUM) 1792 || (regnum == SSR_REGNUM) 1793 || (regnum == SPC_REGNUM)) 1794 reg->how = DWARF2_FRAME_REG_UNDEFINED; 1795 } 1796 1797 static struct sh_frame_cache * 1798 sh_alloc_frame_cache (void) 1799 { 1800 struct sh_frame_cache *cache; 1801 int i; 1802 1803 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); 1804 1805 /* Base address. */ 1806 cache->base = 0; 1807 cache->saved_sp = 0; 1808 cache->sp_offset = 0; 1809 cache->pc = 0; 1810 1811 /* Frameless until proven otherwise. */ 1812 cache->uses_fp = 0; 1813 1814 /* Saved registers. We initialize these to -1 since zero is a valid 1815 offset (that's where fp is supposed to be stored). */ 1816 for (i = 0; i < SH_NUM_REGS; i++) 1817 { 1818 cache->saved_regs[i] = -1; 1819 } 1820 1821 return cache; 1822 } 1823 1824 static struct sh_frame_cache * 1825 sh_frame_cache (frame_info_ptr this_frame, void **this_cache) 1826 { 1827 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1828 struct sh_frame_cache *cache; 1829 CORE_ADDR current_pc; 1830 int i; 1831 1832 if (*this_cache) 1833 return (struct sh_frame_cache *) *this_cache; 1834 1835 cache = sh_alloc_frame_cache (); 1836 *this_cache = cache; 1837 1838 /* In principle, for normal frames, fp holds the frame pointer, 1839 which holds the base address for the current stack frame. 1840 However, for functions that don't need it, the frame pointer is 1841 optional. For these "frameless" functions the frame pointer is 1842 actually the frame pointer of the calling frame. */ 1843 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); 1844 if (cache->base == 0) 1845 return cache; 1846 1847 cache->pc = get_frame_func (this_frame); 1848 current_pc = get_frame_pc (this_frame); 1849 if (cache->pc != 0) 1850 { 1851 ULONGEST fpscr; 1852 1853 /* Check for the existence of the FPSCR register. If it exists, 1854 fetch its value for use in prologue analysis. Passing a zero 1855 value is the best choice for architecture variants upon which 1856 there's no FPSCR register. */ 1857 if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) 1858 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); 1859 else 1860 fpscr = 0; 1861 1862 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); 1863 } 1864 1865 if (!cache->uses_fp) 1866 { 1867 /* We didn't find a valid frame, which means that CACHE->base 1868 currently holds the frame pointer for our calling frame. If 1869 we're at the start of a function, or somewhere half-way its 1870 prologue, the function's frame probably hasn't been fully 1871 setup yet. Try to reconstruct the base address for the stack 1872 frame by looking at the stack pointer. For truly "frameless" 1873 functions this might work too. */ 1874 cache->base = get_frame_register_unsigned 1875 (this_frame, gdbarch_sp_regnum (gdbarch)); 1876 } 1877 1878 /* Now that we have the base address for the stack frame we can 1879 calculate the value of sp in the calling frame. */ 1880 cache->saved_sp = cache->base + cache->sp_offset; 1881 1882 /* Adjust all the saved registers such that they contain addresses 1883 instead of offsets. */ 1884 for (i = 0; i < SH_NUM_REGS; i++) 1885 if (cache->saved_regs[i] != -1) 1886 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; 1887 1888 return cache; 1889 } 1890 1891 static struct value * 1892 sh_frame_prev_register (frame_info_ptr this_frame, 1893 void **this_cache, int regnum) 1894 { 1895 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1896 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 1897 1898 gdb_assert (regnum >= 0); 1899 1900 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 1901 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 1902 1903 /* The PC of the previous frame is stored in the PR register of 1904 the current frame. Frob regnum so that we pull the value from 1905 the correct place. */ 1906 if (regnum == gdbarch_pc_regnum (gdbarch)) 1907 regnum = PR_REGNUM; 1908 1909 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) 1910 return frame_unwind_got_memory (this_frame, regnum, 1911 cache->saved_regs[regnum]); 1912 1913 return frame_unwind_got_register (this_frame, regnum, regnum); 1914 } 1915 1916 static void 1917 sh_frame_this_id (frame_info_ptr this_frame, void **this_cache, 1918 struct frame_id *this_id) 1919 { 1920 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 1921 1922 /* This marks the outermost frame. */ 1923 if (cache->base == 0) 1924 return; 1925 1926 *this_id = frame_id_build (cache->saved_sp, cache->pc); 1927 } 1928 1929 static const struct frame_unwind sh_frame_unwind = { 1930 "sh prologue", 1931 NORMAL_FRAME, 1932 default_frame_unwind_stop_reason, 1933 sh_frame_this_id, 1934 sh_frame_prev_register, 1935 NULL, 1936 default_frame_sniffer 1937 }; 1938 1939 static CORE_ADDR 1940 sh_frame_base_address (frame_info_ptr this_frame, void **this_cache) 1941 { 1942 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); 1943 1944 return cache->base; 1945 } 1946 1947 static const struct frame_base sh_frame_base = { 1948 &sh_frame_unwind, 1949 sh_frame_base_address, 1950 sh_frame_base_address, 1951 sh_frame_base_address 1952 }; 1953 1954 static struct sh_frame_cache * 1955 sh_make_stub_cache (frame_info_ptr this_frame) 1956 { 1957 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1958 struct sh_frame_cache *cache; 1959 1960 cache = sh_alloc_frame_cache (); 1961 1962 cache->saved_sp 1963 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); 1964 1965 return cache; 1966 } 1967 1968 static void 1969 sh_stub_this_id (frame_info_ptr this_frame, void **this_cache, 1970 struct frame_id *this_id) 1971 { 1972 struct sh_frame_cache *cache; 1973 1974 if (*this_cache == NULL) 1975 *this_cache = sh_make_stub_cache (this_frame); 1976 cache = (struct sh_frame_cache *) *this_cache; 1977 1978 *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); 1979 } 1980 1981 static int 1982 sh_stub_unwind_sniffer (const struct frame_unwind *self, 1983 frame_info_ptr this_frame, 1984 void **this_prologue_cache) 1985 { 1986 CORE_ADDR addr_in_block; 1987 1988 addr_in_block = get_frame_address_in_block (this_frame); 1989 if (in_plt_section (addr_in_block)) 1990 return 1; 1991 1992 return 0; 1993 } 1994 1995 static const struct frame_unwind sh_stub_unwind = 1996 { 1997 "sh stub", 1998 NORMAL_FRAME, 1999 default_frame_unwind_stop_reason, 2000 sh_stub_this_id, 2001 sh_frame_prev_register, 2002 NULL, 2003 sh_stub_unwind_sniffer 2004 }; 2005 2006 /* Implement the stack_frame_destroyed_p gdbarch method. 2007 2008 The epilogue is defined here as the area at the end of a function, 2009 either on the `ret' instruction itself or after an instruction which 2010 destroys the function's stack frame. */ 2011 2012 static int 2013 sh_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2014 { 2015 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2016 CORE_ADDR func_addr = 0, func_end = 0; 2017 2018 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 2019 { 2020 ULONGEST inst; 2021 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes 2022 for a nop and some fixed data (e.g. big offsets) which are 2023 unfortunately also treated as part of the function (which 2024 means, they are below func_end. */ 2025 CORE_ADDR addr = func_end - 28; 2026 if (addr < func_addr + 4) 2027 addr = func_addr + 4; 2028 if (pc < addr) 2029 return 0; 2030 2031 /* First search forward until hitting an rts. */ 2032 while (addr < func_end 2033 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) 2034 addr += 2; 2035 if (addr >= func_end) 2036 return 0; 2037 2038 /* At this point we should find a mov.l @r15+,r14 instruction, 2039 either before or after the rts. If not, then the function has 2040 probably no "normal" epilogue and we bail out here. */ 2041 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2042 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, 2043 byte_order))) 2044 addr -= 2; 2045 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, 2046 byte_order))) 2047 return 0; 2048 2049 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2050 2051 /* Step over possible lds.l @r15+,macl. */ 2052 if (IS_MACL_LDS (inst)) 2053 { 2054 addr -= 2; 2055 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2056 } 2057 2058 /* Step over possible lds.l @r15+,pr. */ 2059 if (IS_LDS (inst)) 2060 { 2061 addr -= 2; 2062 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2063 } 2064 2065 /* Step over possible mov r14,r15. */ 2066 if (IS_MOV_FP_SP (inst)) 2067 { 2068 addr -= 2; 2069 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2070 } 2071 2072 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 2073 instructions. */ 2074 while (addr > func_addr + 4 2075 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) 2076 { 2077 addr -= 2; 2078 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); 2079 } 2080 2081 /* On SH2a check if the previous instruction was perhaps a MOVI20. 2082 That's allowed for the epilogue. */ 2083 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a 2084 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) 2085 && addr > func_addr + 6 2086 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, 2087 byte_order))) 2088 addr -= 4; 2089 2090 if (pc >= addr) 2091 return 1; 2092 } 2093 return 0; 2094 } 2095 2096 2097 /* Supply register REGNUM from the buffer specified by REGS and LEN 2098 in the register set REGSET to register cache REGCACHE. 2099 REGTABLE specifies where each register can be found in REGS. 2100 If REGNUM is -1, do this for all registers in REGSET. */ 2101 2102 void 2103 sh_corefile_supply_regset (const struct regset *regset, 2104 struct regcache *regcache, 2105 int regnum, const void *regs, size_t len) 2106 { 2107 struct gdbarch *gdbarch = regcache->arch (); 2108 sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); 2109 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset 2110 ? tdep->core_gregmap 2111 : tdep->core_fpregmap); 2112 int i; 2113 2114 for (i = 0; regmap[i].regnum != -1; i++) 2115 { 2116 if ((regnum == -1 || regnum == regmap[i].regnum) 2117 && regmap[i].offset + 4 <= len) 2118 regcache->raw_supply 2119 (regmap[i].regnum, (char *) regs + regmap[i].offset); 2120 } 2121 } 2122 2123 /* Collect register REGNUM in the register set REGSET from register cache 2124 REGCACHE into the buffer specified by REGS and LEN. 2125 REGTABLE specifies where each register can be found in REGS. 2126 If REGNUM is -1, do this for all registers in REGSET. */ 2127 2128 void 2129 sh_corefile_collect_regset (const struct regset *regset, 2130 const struct regcache *regcache, 2131 int regnum, void *regs, size_t len) 2132 { 2133 struct gdbarch *gdbarch = regcache->arch (); 2134 sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); 2135 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset 2136 ? tdep->core_gregmap 2137 : tdep->core_fpregmap); 2138 int i; 2139 2140 for (i = 0; regmap[i].regnum != -1; i++) 2141 { 2142 if ((regnum == -1 || regnum == regmap[i].regnum) 2143 && regmap[i].offset + 4 <= len) 2144 regcache->raw_collect (regmap[i].regnum, 2145 (char *)regs + regmap[i].offset); 2146 } 2147 } 2148 2149 /* The following two regsets have the same contents, so it is tempting to 2150 unify them, but they are distiguished by their address, so don't. */ 2151 2152 const struct regset sh_corefile_gregset = 2153 { 2154 NULL, 2155 sh_corefile_supply_regset, 2156 sh_corefile_collect_regset 2157 }; 2158 2159 static const struct regset sh_corefile_fpregset = 2160 { 2161 NULL, 2162 sh_corefile_supply_regset, 2163 sh_corefile_collect_regset 2164 }; 2165 2166 static void 2167 sh_iterate_over_regset_sections (struct gdbarch *gdbarch, 2168 iterate_over_regset_sections_cb *cb, 2169 void *cb_data, 2170 const struct regcache *regcache) 2171 { 2172 sh_gdbarch_tdep *tdep = gdbarch_tdep<sh_gdbarch_tdep> (gdbarch); 2173 2174 if (tdep->core_gregmap != NULL) 2175 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, 2176 &sh_corefile_gregset, NULL, cb_data); 2177 2178 if (tdep->core_fpregmap != NULL) 2179 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, 2180 &sh_corefile_fpregset, NULL, cb_data); 2181 } 2182 2183 /* This is the implementation of gdbarch method 2184 return_in_first_hidden_param_p. */ 2185 2186 static int 2187 sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, 2188 struct type *type) 2189 { 2190 return 0; 2191 } 2192 2193 2194 2195 static struct gdbarch * 2196 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2197 { 2198 struct gdbarch *gdbarch; 2199 2200 /* If there is already a candidate, use it. */ 2201 arches = gdbarch_list_lookup_by_info (arches, &info); 2202 if (arches != NULL) 2203 return arches->gdbarch; 2204 2205 /* None found, create a new architecture from the information 2206 provided. */ 2207 sh_gdbarch_tdep *tdep = new sh_gdbarch_tdep; 2208 gdbarch = gdbarch_alloc (&info, tdep); 2209 2210 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2211 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2212 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2213 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2214 2215 set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2216 set_gdbarch_wchar_signed (gdbarch, 0); 2217 2218 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2219 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2220 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2221 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2222 2223 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); 2224 set_gdbarch_sp_regnum (gdbarch, 15); 2225 set_gdbarch_pc_regnum (gdbarch, 16); 2226 set_gdbarch_fp0_regnum (gdbarch, -1); 2227 set_gdbarch_num_pseudo_regs (gdbarch, 0); 2228 2229 set_gdbarch_register_type (gdbarch, sh_default_register_type); 2230 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); 2231 2232 set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh_breakpoint_kind_from_pc); 2233 set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh_sw_breakpoint_from_kind); 2234 2235 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); 2236 2237 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); 2238 2239 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); 2240 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2241 2242 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); 2243 set_gdbarch_return_in_first_hidden_param_p (gdbarch, 2244 sh_return_in_first_hidden_param_p); 2245 2246 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2247 2248 set_gdbarch_frame_align (gdbarch, sh_frame_align); 2249 frame_base_set_default (gdbarch, &sh_frame_base); 2250 2251 set_gdbarch_stack_frame_destroyed_p (gdbarch, sh_stack_frame_destroyed_p); 2252 2253 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); 2254 2255 set_gdbarch_iterate_over_regset_sections 2256 (gdbarch, sh_iterate_over_regset_sections); 2257 2258 switch (info.bfd_arch_info->mach) 2259 { 2260 case bfd_mach_sh: 2261 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2262 break; 2263 2264 case bfd_mach_sh2: 2265 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2266 break; 2267 2268 case bfd_mach_sh2e: 2269 /* doubles on sh2e and sh3e are actually 4 byte. */ 2270 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2271 set_gdbarch_double_format (gdbarch, floatformats_ieee_single); 2272 2273 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); 2274 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2275 set_gdbarch_fp0_regnum (gdbarch, 25); 2276 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2277 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2278 break; 2279 2280 case bfd_mach_sh2a: 2281 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); 2282 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); 2283 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2284 2285 set_gdbarch_fp0_regnum (gdbarch, 25); 2286 set_gdbarch_num_pseudo_regs (gdbarch, 9); 2287 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2288 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2289 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2290 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2291 break; 2292 2293 case bfd_mach_sh2a_nofpu: 2294 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); 2295 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2296 2297 set_gdbarch_num_pseudo_regs (gdbarch, 1); 2298 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2299 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2300 break; 2301 2302 case bfd_mach_sh_dsp: 2303 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); 2304 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2305 break; 2306 2307 case bfd_mach_sh3: 2308 case bfd_mach_sh3_nommu: 2309 case bfd_mach_sh2a_nofpu_or_sh3_nommu: 2310 set_gdbarch_register_name (gdbarch, sh_sh3_register_name); 2311 break; 2312 2313 case bfd_mach_sh3e: 2314 case bfd_mach_sh2a_or_sh3e: 2315 /* doubles on sh2e and sh3e are actually 4 byte. */ 2316 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2317 set_gdbarch_double_format (gdbarch, floatformats_ieee_single); 2318 2319 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); 2320 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2321 set_gdbarch_fp0_regnum (gdbarch, 25); 2322 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2323 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2324 break; 2325 2326 case bfd_mach_sh3_dsp: 2327 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); 2328 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2329 break; 2330 2331 case bfd_mach_sh4: 2332 case bfd_mach_sh4a: 2333 case bfd_mach_sh2a_or_sh4: 2334 set_gdbarch_register_name (gdbarch, sh_sh4_register_name); 2335 set_gdbarch_register_type (gdbarch, sh_sh4_register_type); 2336 set_gdbarch_fp0_regnum (gdbarch, 25); 2337 set_gdbarch_num_pseudo_regs (gdbarch, 13); 2338 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2339 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2340 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2341 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2342 break; 2343 2344 case bfd_mach_sh4_nofpu: 2345 case bfd_mach_sh4a_nofpu: 2346 case bfd_mach_sh4_nommu_nofpu: 2347 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: 2348 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); 2349 break; 2350 2351 case bfd_mach_sh4al_dsp: 2352 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); 2353 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2354 break; 2355 2356 default: 2357 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2358 break; 2359 } 2360 2361 /* Hook in ABI-specific overrides, if they have been registered. */ 2362 gdbarch_init_osabi (info, gdbarch); 2363 2364 dwarf2_append_unwinders (gdbarch); 2365 frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); 2366 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); 2367 2368 return gdbarch; 2369 } 2370 2371 void _initialize_sh_tdep (); 2372 void 2373 _initialize_sh_tdep () 2374 { 2375 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); 2376 2377 add_setshow_prefix_cmd ("sh", no_class, 2378 _("SH specific commands."), 2379 _("SH specific commands."), 2380 &setshcmdlist, &showshcmdlist, 2381 &setlist, &showlist); 2382 2383 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, 2384 &sh_active_calling_convention, 2385 _("Set calling convention used when calling target " 2386 "functions from GDB."), 2387 _("Show calling convention used when calling target " 2388 "functions from GDB."), 2389 _("gcc - Use GCC calling convention (default).\n" 2390 "renesas - Enforce Renesas calling convention."), 2391 NULL, NULL, 2392 &setshcmdlist, &showshcmdlist); 2393 } 2394