1This is as.info, produced by makeinfo version 7.0.2 from as.texi. 2 3This file documents the GNU Assembler "as". 4 5 Copyright © 1991-2024 Free Software Foundation, Inc. 6 7 Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 or 9any later version published by the Free Software Foundation; with no 10Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 11Texts. A copy of the license is included in the section entitled “GNU 12Free Documentation License”. 13 14INFO-DIR-SECTION Software development 15START-INFO-DIR-ENTRY 16* As: (as). The GNU assembler. 17* Gas: (as). The GNU assembler. 18END-INFO-DIR-ENTRY 19 20 21File: as.info, Node: Top, Next: Overview, Up: (dir) 22 23Using as 24******** 25 26This file is a user guide to the GNU assembler ‘as’ (GNU Binutils) 27version 2.42. 28 29 This document is distributed under the terms of the GNU Free 30Documentation License. A copy of the license is included in the section 31entitled “GNU Free Documentation License”. 32 33* Menu: 34 35* Overview:: Overview 36* Invoking:: Command-Line Options 37* Syntax:: Syntax 38* Sections:: Sections and Relocation 39* Symbols:: Symbols 40* Expressions:: Expressions 41* Pseudo Ops:: Assembler Directives 42* Object Attributes:: Object Attributes 43* Machine Dependencies:: Machine Dependent Features 44* Reporting Bugs:: Reporting Bugs 45* Acknowledgements:: Who Did What 46* GNU Free Documentation License:: GNU Free Documentation License 47* AS Index:: AS Index 48 49 50File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 51 521 Overview 53********** 54 55Here is a brief summary of how to invoke ‘as’. For details, see *note 56Command-Line Options: Invoking. 57 58 as [-a[cdghilns][=FILE]] 59 [--alternate] 60 [--compress-debug-sections] [--nocompress-debug-sections] 61 [-D] 62 [--dump-config] 63 [--debug-prefix-map OLD=NEW] 64 [--defsym SYM=VAL] 65 [--elf-stt-common=[no|yes]] 66 [--emulation=NAME] 67 [-f] 68 [-g] [--gstabs] [--gstabs+] 69 [--gdwarf-<N>] [--gdwarf-sections] 70 [--gdwarf-cie-version=VERSION] 71 [--generate-missing-build-notes=[no|yes]] 72 [--gsframe] 73 [--hash-size=N] 74 [--help] [--target-help] 75 [-I DIR] 76 [-J] 77 [-K] 78 [--keep-locals] 79 [-L] 80 [--listing-lhs-width=NUM] 81 [--listing-lhs-width2=NUM] 82 [--listing-rhs-width=NUM] 83 [--listing-cont-lines=NUM] 84 [--multibyte-handling=[allow|warn|warn-sym-only]] 85 [--no-pad-sections] 86 [-o OBJFILE] [-R] 87 [--scfi=experimental] 88 [--sectname-subst] 89 [--size-check=[error|warning]] 90 [--statistics] 91 [-v] [-version] [--version] 92 [-W] [--warn] [--fatal-warnings] [-w] [-x] 93 [-Z] [@FILE] 94 [TARGET-OPTIONS] 95 [--|FILES ...] 96 97 _Target AArch64 options:_ 98 [-EB|-EL] 99 [-mabi=ABI] 100 101 _Target Alpha options:_ 102 [-mCPU] 103 [-mdebug | -no-mdebug] 104 [-replace | -noreplace] 105 [-relax] [-g] [-GSIZE] 106 [-F] [-32addr] 107 108 _Target ARC options:_ 109 [-mcpu=CPU] 110 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] 111 [-mcode-density] 112 [-mrelax] 113 [-EB|-EL] 114 115 _Target ARM options:_ 116 [-mcpu=PROCESSOR[+EXTENSION...]] 117 [-march=ARCHITECTURE[+EXTENSION...]] 118 [-mfpu=FLOATING-POINT-FORMAT] 119 [-mfloat-abi=ABI] 120 [-meabi=VER] 121 [-mthumb] 122 [-EB|-EL] 123 [-mapcs-32|-mapcs-26|-mapcs-float| 124 -mapcs-reentrant] 125 [-mthumb-interwork] [-k] 126 127 _Target Blackfin options:_ 128 [-mcpu=PROCESSOR[-SIREVISION]] 129 [-mfdpic] 130 [-mno-fdpic] 131 [-mnopic] 132 133 _Target BPF options:_ 134 [-EL] [-EB] 135 136 _Target CRIS options:_ 137 [--underscore | --no-underscore] 138 [--pic] [-N] 139 [--emulation=criself | --emulation=crisaout] 140 [--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32] 141 142 _Target C-SKY options:_ 143 [-march=ARCH] [-mcpu=CPU] 144 [-EL] [-mlittle-endian] [-EB] [-mbig-endian] 145 [-fpic] [-pic] 146 [-mljump] [-mno-ljump] 147 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr] 148 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr] 149 [-mnolrw ] [-mno-lrw] 150 [-melrw] [-mno-elrw] 151 [-mlaf ] [-mliterals-after-func] 152 [-mno-laf] [-mno-literals-after-func] 153 [-mlabr] [-mliterals-after-br] 154 [-mno-labr] [-mnoliterals-after-br] 155 [-mistack] [-mno-istack] 156 [-mhard-float] [-mmp] [-mcp] [-mcache] 157 [-msecurity] [-mtrust] 158 [-mdsp] [-medsp] [-mvdsp] 159 160 _Target D10V options:_ 161 [-O] 162 163 _Target D30V options:_ 164 [-O|-n|-N] 165 166 _Target EPIPHANY options:_ 167 [-mepiphany|-mepiphany16] 168 169 _Target H8/300 options:_ 170 [-h-tick-hex] 171 172 _Target i386 options:_ 173 [--32|--x32|--64] [-n] 174 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 175 176 _Target IA-64 options:_ 177 [-mconstant-gp|-mauto-pic] 178 [-milp32|-milp64|-mlp64|-mp64] 179 [-mle|mbe] 180 [-mtune=itanium1|-mtune=itanium2] 181 [-munwind-check=warning|-munwind-check=error] 182 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 183 [-x|-xexplicit] [-xauto] [-xdebug] 184 185 _Target IP2K options:_ 186 [-mip2022|-mip2022ext] 187 188 _Target M32C options:_ 189 [-m32c|-m16c] [-relax] [-h-tick-hex] 190 191 _Target M32R options:_ 192 [--m32rx|--[no-]warn-explicit-parallel-conflicts| 193 --W[n]p] 194 195 _Target M680X0 options:_ 196 [-l] [-m68000|-m68010|-m68020|...] 197 198 _Target M68HC11 options:_ 199 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] 200 [-mshort|-mlong] 201 [-mshort-double|-mlong-double] 202 [--force-long-branches] [--short-branches] 203 [--strict-direct-mode] [--print-insn-syntax] 204 [--print-opcodes] [--generate-example] 205 206 _Target MCORE options:_ 207 [-jsri2bsr] [-sifilter] [-relax] 208 [-mcpu=[210|340]] 209 210 _Target Meta options:_ 211 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU] 212 _Target MICROBLAZE options:_ 213 [-mlittle-endian] [-mbig-endian] 214 215 _Target MIPS options:_ 216 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 217 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 218 [-non_shared] [-xgot [-mvxworks-pic] 219 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 220 [-mfp64] [-mgp64] [-mfpxx] 221 [-modd-spreg] [-mno-odd-spreg] 222 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 223 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 224 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] 225 [-mips64r3] [-mips64r5] [-mips64r6] 226 [-construct-floats] [-no-construct-floats] 227 [-mignore-branch-isa] [-mno-ignore-branch-isa] 228 [-mnan=ENCODING] 229 [-trap] [-no-break] [-break] [-no-trap] 230 [-mips16] [-no-mips16] 231 [-mmips16e2] [-mno-mips16e2] 232 [-mmicromips] [-mno-micromips] 233 [-msmartmips] [-mno-smartmips] 234 [-mips3d] [-no-mips3d] 235 [-mdmx] [-no-mdmx] 236 [-mdsp] [-mno-dsp] 237 [-mdspr2] [-mno-dspr2] 238 [-mdspr3] [-mno-dspr3] 239 [-mmsa] [-mno-msa] 240 [-mxpa] [-mno-xpa] 241 [-mmt] [-mno-mt] 242 [-mmcu] [-mno-mcu] 243 [-mcrc] [-mno-crc] 244 [-mginv] [-mno-ginv] 245 [-mloongson-mmi] [-mno-loongson-mmi] 246 [-mloongson-cam] [-mno-loongson-cam] 247 [-mloongson-ext] [-mno-loongson-ext] 248 [-mloongson-ext2] [-mno-loongson-ext2] 249 [-minsn32] [-mno-insn32] 250 [-mfix7000] [-mno-fix7000] 251 [-mfix-rm7000] [-mno-fix-rm7000] 252 [-mfix-vr4120] [-mno-fix-vr4120] 253 [-mfix-vr4130] [-mno-fix-vr4130] 254 [-mfix-r5900] [-mno-fix-r5900] 255 [-mdebug] [-no-mdebug] 256 [-mpdr] [-mno-pdr] 257 258 _Target MMIX options:_ 259 [--fixed-special-register-names] [--globalize-symbols] 260 [--gnu-syntax] [--relax] [--no-predefined-symbols] 261 [--no-expand] [--no-merge-gregs] [-x] 262 [--linker-allocated-gregs] 263 264 _Target Nios II options:_ 265 [-relax-all] [-relax-section] [-no-relax] 266 [-EB] [-EL] 267 268 _Target NDS32 options:_ 269 [-EL] [-EB] [-O] [-Os] [-mcpu=CPU] 270 [-misa=ISA] [-mabi=ABI] [-mall-ext] 271 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext] 272 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div] 273 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext] 274 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs] 275 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax] 276 [-mb2bb] 277 278 _Target PDP11 options:_ 279 [-mpic|-mno-pic] [-mall] [-mno-extensions] 280 [-mEXTENSION|-mno-EXTENSION] 281 [-mCPU] [-mMACHINE] 282 283 _Target picoJava options:_ 284 [-mb|-me] 285 286 _Target PowerPC options:_ 287 [-a32|-a64] 288 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 289 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko| 290 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500| 291 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x| 292 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| 293 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom] 294 [-many] [-maltivec|-mvsx|-mhtm|-mvle] 295 [-mregnames|-mno-regnames] 296 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 297 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 298 [-msolaris|-mno-solaris] 299 [-nops=COUNT] 300 301 _Target PRU options:_ 302 [-link-relax] 303 [-mnolink-relax] 304 [-mno-warn-regname-label] 305 306 _Target RISC-V options:_ 307 [-fpic|-fPIC|-fno-pic] 308 [-march=ISA] 309 [-mabi=ABI] 310 [-mlittle-endian|-mbig-endian] 311 312 _Target RL78 options:_ 313 [-mg10] 314 [-m32bit-doubles|-m64bit-doubles] 315 316 _Target RX options:_ 317 [-mlittle-endian|-mbig-endian] 318 [-m32bit-doubles|-m64bit-doubles] 319 [-muse-conventional-section-names] 320 [-msmall-data-limit] 321 [-mpid] 322 [-mrelax] 323 [-mint-register=NUMBER] 324 [-mgcc-abi|-mrx-abi] 325 326 _Target s390 options:_ 327 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 328 [-mregnames|-mno-regnames] 329 [-mwarn-areg-zero] 330 331 _Target SCORE options:_ 332 [-EB][-EL][-FIXDD][-NWARN] 333 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 334 [-march=score7][-march=score3] 335 [-USE_R1][-KPIC][-O0][-G NUM][-V] 336 337 _Target SPARC options:_ 338 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite 339 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd 340 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c 341 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis 342 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 343 -Asparcvisr|-Asparc5] 344 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc 345 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 346 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e 347 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis 348 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima 349 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 350 -bump] 351 [-32|-64] 352 [--enforce-aligned-data][--dcti-couples-detect] 353 354 _Target TIC54X options:_ 355 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 356 [-merrors-to-file <FILENAME>|-me <FILENAME>] 357 358 _Target TIC6X options:_ 359 [-march=ARCH] [-mbig-endian|-mlittle-endian] 360 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] 361 [-mpic|-mno-pic] 362 363 _Target TILE-Gx options:_ 364 [-m32|-m64][-EB][-EL] 365 366 _Target Visium options:_ 367 [-mtune=ARCH] 368 369 _Target Xtensa options:_ 370 [--[no-]text-section-literals] [--[no-]auto-litpools] 371 [--[no-]absolute-literals] 372 [--[no-]target-align] [--[no-]longcalls] 373 [--[no-]transform] 374 [--rename-section OLDNAME=NEWNAME] 375 [--[no-]trampolines] 376 [--abi-windowed|--abi-call0] 377 378 _Target Z80 options:_ 379 [-march=CPU[-EXT][+EXT]] 380 [-local-prefix=PREFIX] 381 [-colonless] 382 [-sdcc] 383 [-fp-s=FORMAT] 384 [-fp-d=FORMAT] 385 386 387 388‘@FILE’ 389 Read command-line options from FILE. The options read are inserted 390 in place of the original @FILE option. If FILE does not exist, or 391 cannot be read, then the option will be treated literally, and not 392 removed. 393 394 Options in FILE are separated by whitespace. A whitespace 395 character may be included in an option by surrounding the entire 396 option in either single or double quotes. Any character (including 397 a backslash) may be included by prefixing the character to be 398 included with a backslash. The FILE may itself contain additional 399 @FILE options; any such options will be processed recursively. 400 401‘-a[cdghilmns]’ 402 Turn on listings, in any of a variety of ways: 403 404 ‘-ac’ 405 omit false conditionals 406 407 ‘-ad’ 408 omit debugging directives 409 410 ‘-ag’ 411 include general information, like as version and options 412 passed 413 414 ‘-ah’ 415 include high-level source 416 417 ‘-al’ 418 include assembly 419 420 ‘-ali’ 421 include assembly with ginsn 422 423 ‘-am’ 424 include macro expansions 425 426 ‘-an’ 427 omit forms processing 428 429 ‘-as’ 430 include symbols 431 432 ‘=file’ 433 set the name of the listing file 434 435 You may combine these options; for example, use ‘-aln’ for assembly 436 listing without forms processing. The ‘=file’ option, if used, 437 must be the last one. By itself, ‘-a’ defaults to ‘-ahls’. 438 439‘--alternate’ 440 Begin in alternate macro mode. *Note ‘.altmacro’: Altmacro. 441 442‘--compress-debug-sections’ 443 Compress DWARF debug sections using zlib with SHF_COMPRESSED from 444 the ELF ABI. The resulting object file may not be compatible with 445 older linkers and object file utilities. Note if compression would 446 make a given section _larger_ then it is not compressed. 447 448‘--compress-debug-sections=none’ 449‘--compress-debug-sections=zlib’ 450‘--compress-debug-sections=zlib-gnu’ 451‘--compress-debug-sections=zlib-gabi’ 452‘--compress-debug-sections=zstd’ 453 These options control how DWARF debug sections are compressed. 454 ‘--compress-debug-sections=none’ is equivalent to 455 ‘--nocompress-debug-sections’. ‘--compress-debug-sections=zlib’ 456 and ‘--compress-debug-sections=zlib-gabi’ are equivalent to 457 ‘--compress-debug-sections’. ‘--compress-debug-sections=zlib-gnu’ 458 compresses DWARF debug sections using the obsoleted zlib-gnu 459 format. The debug sections are renamed to begin with ‘.zdebug’. 460 ‘--compress-debug-sections=zstd’ compresses DWARF debug sections 461 using zstd. Note - if compression would actually make a section 462 _larger_, then it is not compressed nor renamed. 463 464‘--nocompress-debug-sections’ 465 Do not compress DWARF debug sections. This is usually the default 466 for all targets except the x86/x86_64, but a configure time option 467 can be used to override this. 468 469‘-D’ 470 Enable debugging in target specific backends, if supported. 471 Otherwise ignored. Even if ignored, this option is accepted for 472 script compatibility with calls to other assemblers. 473 474‘--debug-prefix-map OLD=NEW’ 475 When assembling files in directory ‘OLD’, record debugging 476 information describing them as in ‘NEW’ instead. 477 478‘--defsym SYM=VALUE’ 479 Define the symbol SYM to be VALUE before assembling the input file. 480 VALUE must be an integer constant. As in C, a leading ‘0x’ 481 indicates a hexadecimal value, and a leading ‘0’ indicates an octal 482 value. The value of the symbol can be overridden inside a source 483 file via the use of a ‘.set’ pseudo-op. 484 485‘--dump-config’ 486 Displays how the assembler is configured and then exits. 487 488‘--elf-stt-common=no’ 489‘--elf-stt-common=yes’ 490 These options control whether the ELF assembler should generate 491 common symbols with the ‘STT_COMMON’ type. The default can be 492 controlled by a configure option ‘--enable-elf-stt-common’. 493 494‘--emulation=NAME’ 495 If the assembler is configured to support multiple different target 496 configurations then this option can be used to select the desired 497 form. 498 499‘-f’ 500 “fast”—skip whitespace and comment preprocessing (assume source is 501 compiler output). 502 503‘-g’ 504‘--gen-debug’ 505 Generate debugging information for each assembler source line using 506 whichever debug format is preferred by the target. This currently 507 means either STABS, ECOFF or DWARF2. When the debug format is 508 DWARF then a ‘.debug_info’ and ‘.debug_line’ section is only 509 emitted when the assembly file doesn’t generate one itself. 510 511‘--gstabs’ 512 Generate stabs debugging information for each assembler line. This 513 may help debugging assembler code, if the debugger can handle it. 514 515‘--gstabs+’ 516 Generate stabs debugging information for each assembler line, with 517 GNU extensions that probably only gdb can handle, and that could 518 make other debuggers crash or refuse to read your program. This 519 may help debugging assembler code. Currently the only GNU 520 extension is the location of the current working directory at 521 assembling time. 522 523‘--gdwarf-2’ 524 Generate DWARF2 debugging information for each assembler line. 525 This may help debugging assembler code, if the debugger can handle 526 it. Note—this option is only supported by some targets, not all of 527 them. 528 529‘--gdwarf-3’ 530 This option is the same as the ‘--gdwarf-2’ option, except that it 531 allows for the possibility of the generation of extra debug 532 information as per version 3 of the DWARF specification. Note - 533 enabling this option does not guarantee the generation of any extra 534 information, the choice to do so is on a per target basis. 535 536‘--gdwarf-4’ 537 This option is the same as the ‘--gdwarf-2’ option, except that it 538 allows for the possibility of the generation of extra debug 539 information as per version 4 of the DWARF specification. Note - 540 enabling this option does not guarantee the generation of any extra 541 information, the choice to do so is on a per target basis. 542 543‘--gdwarf-5’ 544 This option is the same as the ‘--gdwarf-2’ option, except that it 545 allows for the possibility of the generation of extra debug 546 information as per version 5 of the DWARF specification. Note - 547 enabling this option does not guarantee the generation of any extra 548 information, the choice to do so is on a per target basis. 549 550‘--gdwarf-sections’ 551 Instead of creating a .debug_line section, create a series of 552 .debug_line.FOO sections where FOO is the name of the corresponding 553 code section. For example a code section called .TEXT.FUNC will 554 have its dwarf line number information placed into a section called 555 .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT 556 then debug line section will still be called just .DEBUG_LINE 557 without any suffix. 558 559‘--gdwarf-cie-version=VERSION’ 560 Control which version of DWARF Common Information Entries (CIEs) 561 are produced. When this flag is not specified the default is 562 version 1, though some targets can modify this default. Other 563 possible values for VERSION are 3 or 4. 564 565‘--generate-missing-build-notes=yes’ 566‘--generate-missing-build-notes=no’ 567 These options control whether the ELF assembler should generate GNU 568 Build attribute notes if none are present in the input sources. 569 The default can be controlled by the 570 ‘--enable-generate-build-notes’ configure option. 571 572‘--gsframe’ 573‘--gsframe’ 574 Create .SFRAME section from CFI directives. 575 576‘--hash-size N’ 577 Ignored. Supported for command line compatibility with other 578 assemblers. 579 580‘--help’ 581 Print a summary of the command-line options and exit. 582 583‘--target-help’ 584 Print a summary of all target specific options and exit. 585 586‘-I DIR’ 587 Add directory DIR to the search list for ‘.include’ directives. 588 589‘-J’ 590 Don’t warn about signed overflow. 591 592‘-K’ 593 Issue warnings when difference tables altered for long 594 displacements. 595 596‘-L’ 597‘--keep-locals’ 598 Keep (in the symbol table) local symbols. These symbols start with 599 system-specific local label prefixes, typically ‘.L’ for ELF 600 systems or ‘L’ for traditional a.out systems. *Note Symbol 601 Names::. 602 603‘--listing-lhs-width=NUMBER’ 604 Set the maximum width, in words, of the output data column for an 605 assembler listing to NUMBER. 606 607‘--listing-lhs-width2=NUMBER’ 608 Set the maximum width, in words, of the output data column for 609 continuation lines in an assembler listing to NUMBER. 610 611‘--listing-rhs-width=NUMBER’ 612 Set the maximum width of an input source line, as displayed in a 613 listing, to NUMBER bytes. 614 615‘--listing-cont-lines=NUMBER’ 616 Set the maximum number of lines printed in a listing for a single 617 line of input to NUMBER + 1. 618 619‘--multibyte-handling=allow’ 620‘--multibyte-handling=warn’ 621‘--multibyte-handling=warn-sym-only’ 622‘--multibyte-handling=warn_sym_only’ 623 Controls how the assembler handles multibyte characters in the 624 input. The default (which can be restored by using the ‘allow’ 625 argument) is to allow such characters without complaint. Using the 626 ‘warn’ argument will make the assembler generate a warning message 627 whenever any multibyte character is encountered. Using the 628 ‘warn-sym-only’ argument will only cause a warning to be generated 629 when a symbol is defined with a name that contains multibyte 630 characters. (References to undefined symbols will not generate a 631 warning). 632 633‘--no-pad-sections’ 634 Stop the assembler for padding the ends of output sections to the 635 alignment of that section. The default is to pad the sections, but 636 this can waste space which might be needed on targets which have 637 tight memory constraints. 638 639‘-o OBJFILE’ 640 Name the object-file output from ‘as’ OBJFILE. 641 642‘-R’ 643 Fold the data section into the text section. 644 645‘--reduce-memory-overheads’ 646 Ignored. Supported for compatibility with tools that apss the same 647 option to both the assembler and the linker. 648 649‘--scfi=experimental’ 650 This option controls whether the assembler should synthesize CFI 651 for hand-written input. If the input already contains some 652 synthesizable CFI directives, the assembler ignores them and emits 653 a warning. Note that ‘--scfi=experimental’ is not intended to be 654 used for compiler-generated code, including inline assembly. This 655 experimental support is work in progress. Only System V AMD64 ABI 656 is supported. 657 658 Each input function in assembly must begin with the ‘.type’ 659 directive, and should ideally be closed off using a ‘.size’ 660 directive. When using SCFI, each ‘.type’ directive prompts GAS to 661 start a new FDE (a.k.a., Function Descriptor Entry). This implies 662 that with each ‘.type’ directive, a previous block of instructions, 663 if any, is finalised as a distinct FDE. 664 665‘--sectname-subst’ 666 Honor substitution sequences in section names. *Note ‘.section 667 NAME’: Section Name Substitutions. 668 669‘--size-check=error’ 670‘--size-check=warning’ 671 Issue an error or warning for invalid ELF .size directive. 672 673‘--statistics’ 674 Print the maximum space (in bytes) and total time (in seconds) used 675 by assembly. 676 677‘--strip-local-absolute’ 678 Remove local absolute symbols from the outgoing symbol table. 679 680‘-v’ 681‘-version’ 682 Print the ‘as’ version. 683 684‘--version’ 685 Print the ‘as’ version and exit. 686 687‘-W’ 688‘--no-warn’ 689 Suppress warning messages. 690 691‘--fatal-warnings’ 692 Treat warnings as errors. 693 694‘--warn’ 695 Don’t suppress warning messages or treat them as errors. 696 697‘-w’ 698 Ignored. 699 700‘-x’ 701 Ignored. 702 703‘-Z’ 704 Generate an object file even after errors. 705 706‘-- | FILES ...’ 707 Standard input, or source files to assemble. 708 709 *Note AArch64 Options::, for the options available when as is 710configured for the 64-bit mode of the ARM Architecture (AArch64). 711 712 *Note Alpha Options::, for the options available when as is 713configured for an Alpha processor. 714 715 The following options are available when as is configured for an ARC 716processor. 717 718‘-mcpu=CPU’ 719 This option selects the core processor variant. 720‘-EB | -EL’ 721 Select either big-endian (-EB) or little-endian (-EL) output. 722‘-mcode-density’ 723 Enable Code Density extension instructions. 724 725 The following options are available when as is configured for the ARM 726processor family. 727 728‘-mcpu=PROCESSOR[+EXTENSION...]’ 729 Specify which ARM processor variant is the target. 730‘-march=ARCHITECTURE[+EXTENSION...]’ 731 Specify which ARM architecture variant is used by the target. 732‘-mfpu=FLOATING-POINT-FORMAT’ 733 Select which Floating Point architecture is the target. 734‘-mfloat-abi=ABI’ 735 Select which floating point ABI is in use. 736‘-mthumb’ 737 Enable Thumb only instruction decoding. 738‘-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant’ 739 Select which procedure calling convention is in use. 740‘-EB | -EL’ 741 Select either big-endian (-EB) or little-endian (-EL) output. 742‘-mthumb-interwork’ 743 Specify that the code has been generated with interworking between 744 Thumb and ARM code in mind. 745‘-mccs’ 746 Turns on CodeComposer Studio assembly syntax compatibility mode. 747‘-k’ 748 Specify that PIC code has been generated. 749 750 *Note Blackfin Options::, for the options available when as is 751configured for the Blackfin processor family. 752 753 *Note BPF Options::, for the options available when as is configured 754for the Linux kernel BPF processor family. 755 756 See the info pages for documentation of the CRIS-specific options. 757 758 *Note C-SKY Options::, for the options available when as is 759configured for the C-SKY processor family. 760 761 The following options are available when as is configured for a D10V 762processor. 763‘-O’ 764 Optimize output by parallelizing instructions. 765 766 The following options are available when as is configured for a D30V 767processor. 768‘-O’ 769 Optimize output by parallelizing instructions. 770 771‘-n’ 772 Warn when nops are generated. 773 774‘-N’ 775 Warn when a nop after a 32-bit multiply instruction is generated. 776 777 The following options are available when as is configured for the 778Adapteva EPIPHANY series. 779 780 *Note Epiphany Options::, for the options available when as is 781configured for an Epiphany processor. 782 783 *Note i386-Options::, for the options available when as is configured 784for an i386 processor. 785 786 The following options are available when as is configured for the 787Ubicom IP2K series. 788 789‘-mip2022ext’ 790 Specifies that the extended IP2022 instructions are allowed. 791 792‘-mip2022’ 793 Restores the default behaviour, which restricts the permitted 794 instructions to just the basic IP2022 ones. 795 796 The following options are available when as is configured for the 797Renesas M32C and M16C processors. 798 799‘-m32c’ 800 Assemble M32C instructions. 801 802‘-m16c’ 803 Assemble M16C instructions (the default). 804 805‘-relax’ 806 Enable support for link-time relaxations. 807 808‘-h-tick-hex’ 809 Support H’00 style hex constants in addition to 0x00 style. 810 811 The following options are available when as is configured for the 812Renesas M32R (formerly Mitsubishi M32R) series. 813 814‘--m32rx’ 815 Specify which processor in the M32R family is the target. The 816 default is normally the M32R, but this option changes it to the 817 M32RX. 818 819‘--warn-explicit-parallel-conflicts or --Wp’ 820 Produce warning messages when questionable parallel constructs are 821 encountered. 822 823‘--no-warn-explicit-parallel-conflicts or --Wnp’ 824 Do not produce warning messages when questionable parallel 825 constructs are encountered. 826 827 The following options are available when as is configured for the 828Motorola 68000 series. 829 830‘-l’ 831 Shorten references to undefined symbols, to one word instead of 832 two. 833 834‘-m68000 | -m68008 | -m68010 | -m68020 | -m68030’ 835‘| -m68040 | -m68060 | -m68302 | -m68331 | -m68332’ 836‘| -m68333 | -m68340 | -mcpu32 | -m5200’ 837 Specify what processor in the 68000 family is the target. The 838 default is normally the 68020, but this can be changed at 839 configuration time. 840 841‘-m68881 | -m68882 | -mno-68881 | -mno-68882’ 842 The target machine does (or does not) have a floating-point 843 coprocessor. The default is to assume a coprocessor for 68020, 844 68030, and cpu32. Although the basic 68000 is not compatible with 845 the 68881, a combination of the two can be specified, since it’s 846 possible to do emulation of the coprocessor instructions with the 847 main processor. 848 849‘-m68851 | -mno-68851’ 850 The target machine does (or does not) have a memory-management unit 851 coprocessor. The default is to assume an MMU for 68020 and up. 852 853 *Note Nios II Options::, for the options available when as is 854configured for an Altera Nios II processor. 855 856 For details about the PDP-11 machine dependent features options, see 857*note PDP-11-Options::. 858 859‘-mpic | -mno-pic’ 860 Generate position-independent (or position-dependent) code. The 861 default is ‘-mpic’. 862 863‘-mall’ 864‘-mall-extensions’ 865 Enable all instruction set extensions. This is the default. 866 867‘-mno-extensions’ 868 Disable all instruction set extensions. 869 870‘-mEXTENSION | -mno-EXTENSION’ 871 Enable (or disable) a particular instruction set extension. 872 873‘-mCPU’ 874 Enable the instruction set extensions supported by a particular 875 CPU, and disable all other extensions. 876 877‘-mMACHINE’ 878 Enable the instruction set extensions supported by a particular 879 machine model, and disable all other extensions. 880 881 The following options are available when as is configured for a 882picoJava processor. 883 884‘-mb’ 885 Generate “big endian” format output. 886 887‘-ml’ 888 Generate “little endian” format output. 889 890 *Note PRU Options::, for the options available when as is configured 891for a PRU processor. 892 893 The following options are available when as is configured for the 894Motorola 68HC11 or 68HC12 series. 895 896‘-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg’ 897 Specify what processor is the target. The default is defined by 898 the configuration option when building the assembler. 899 900‘--xgate-ramoffset’ 901 Instruct the linker to offset RAM addresses from S12X address space 902 into XGATE address space. 903 904‘-mshort’ 905 Specify to use the 16-bit integer ABI. 906 907‘-mlong’ 908 Specify to use the 32-bit integer ABI. 909 910‘-mshort-double’ 911 Specify to use the 32-bit double ABI. 912 913‘-mlong-double’ 914 Specify to use the 64-bit double ABI. 915 916‘--force-long-branches’ 917 Relative branches are turned into absolute ones. This concerns 918 conditional branches, unconditional branches and branches to a sub 919 routine. 920 921‘-S | --short-branches’ 922 Do not turn relative branches into absolute ones when the offset is 923 out of range. 924 925‘--strict-direct-mode’ 926 Do not turn the direct addressing mode into extended addressing 927 mode when the instruction does not support direct addressing mode. 928 929‘--print-insn-syntax’ 930 Print the syntax of instruction in case of error. 931 932‘--print-opcodes’ 933 Print the list of instructions with syntax and then exit. 934 935‘--generate-example’ 936 Print an example of instruction for each possible instruction and 937 then exit. This option is only useful for testing ‘as’. 938 939 The following options are available when ‘as’ is configured for the 940SPARC architecture: 941 942‘-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite’ 943‘-Av8plus | -Av8plusa | -Av9 | -Av9a’ 944 Explicitly select a variant of the SPARC architecture. 945 946 ‘-Av8plus’ and ‘-Av8plusa’ select a 32 bit environment. ‘-Av9’ and 947 ‘-Av9a’ select a 64 bit environment. 948 949 ‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with 950 UltraSPARC extensions. 951 952‘-xarch=v8plus | -xarch=v8plusa’ 953 For compatibility with the Solaris v9 assembler. These options are 954 equivalent to -Av8plus and -Av8plusa, respectively. 955 956‘-bump’ 957 Warn when the assembler switches to another architecture. 958 959 The following options are available when as is configured for the 960’c54x architecture. 961 962‘-mfar-mode’ 963 Enable extended addressing mode. All addresses and relocations 964 will assume extended addressing (usually 23 bits). 965‘-mcpu=CPU_VERSION’ 966 Sets the CPU version being compiled for. 967‘-merrors-to-file FILENAME’ 968 Redirect error output to a file, for broken systems which don’t 969 support such behaviour in the shell. 970 971 The following options are available when as is configured for a MIPS 972processor. 973 974‘-G NUM’ 975 This option sets the largest size of an object that can be 976 referenced implicitly with the ‘gp’ register. It is only accepted 977 for targets that use ECOFF format, such as a DECstation running 978 Ultrix. The default value is 8. 979 980‘-EB’ 981 Generate “big endian” format output. 982 983‘-EL’ 984 Generate “little endian” format output. 985 986‘-mips1’ 987‘-mips2’ 988‘-mips3’ 989‘-mips4’ 990‘-mips5’ 991‘-mips32’ 992‘-mips32r2’ 993‘-mips32r3’ 994‘-mips32r5’ 995‘-mips32r6’ 996‘-mips64’ 997‘-mips64r2’ 998‘-mips64r3’ 999‘-mips64r5’ 1000‘-mips64r6’ 1001 Generate code for a particular MIPS Instruction Set Architecture 1002 level. ‘-mips1’ is an alias for ‘-march=r3000’, ‘-mips2’ is an 1003 alias for ‘-march=r6000’, ‘-mips3’ is an alias for ‘-march=r4000’ 1004 and ‘-mips4’ is an alias for ‘-march=r8000’. ‘-mips5’, ‘-mips32’, 1005 ‘-mips32r2’, ‘-mips32r3’, ‘-mips32r5’, ‘-mips32r6’, ‘-mips64’, 1006 ‘-mips64r2’, ‘-mips64r3’, ‘-mips64r5’, and ‘-mips64r6’ correspond 1007 to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, 1008 MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, 1009 MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA 1010 processors, respectively. 1011 1012‘-march=CPU’ 1013 Generate code for a particular MIPS CPU. 1014 1015‘-mtune=CPU’ 1016 Schedule and tune for a particular MIPS CPU. 1017 1018‘-mfix7000’ 1019‘-mno-fix7000’ 1020 Cause nops to be inserted if the read of the destination register 1021 of an mfhi or mflo instruction occurs in the following two 1022 instructions. 1023 1024‘-mfix-rm7000’ 1025‘-mno-fix-rm7000’ 1026 Cause nops to be inserted if a dmult or dmultu instruction is 1027 followed by a load instruction. 1028 1029‘-mfix-r5900’ 1030‘-mno-fix-r5900’ 1031 Do not attempt to schedule the preceding instruction into the delay 1032 slot of a branch instruction placed at the end of a short loop of 1033 six instructions or fewer and always schedule a ‘nop’ instruction 1034 there instead. The short loop bug under certain conditions causes 1035 loops to execute only once or twice, due to a hardware bug in the 1036 R5900 chip. 1037 1038‘-mdebug’ 1039‘-no-mdebug’ 1040 Cause stabs-style debugging output to go into an ECOFF-style 1041 .mdebug section instead of the standard ELF .stabs sections. 1042 1043‘-mpdr’ 1044‘-mno-pdr’ 1045 Control generation of ‘.pdr’ sections. 1046 1047‘-mgp32’ 1048‘-mfp32’ 1049 The register sizes are normally inferred from the ISA and ABI, but 1050 these flags force a certain group of registers to be treated as 32 1051 bits wide at all times. ‘-mgp32’ controls the size of 1052 general-purpose registers and ‘-mfp32’ controls the size of 1053 floating-point registers. 1054 1055‘-mgp64’ 1056‘-mfp64’ 1057 The register sizes are normally inferred from the ISA and ABI, but 1058 these flags force a certain group of registers to be treated as 64 1059 bits wide at all times. ‘-mgp64’ controls the size of 1060 general-purpose registers and ‘-mfp64’ controls the size of 1061 floating-point registers. 1062 1063‘-mfpxx’ 1064 The register sizes are normally inferred from the ISA and ABI, but 1065 using this flag in combination with ‘-mabi=32’ enables an ABI 1066 variant which will operate correctly with floating-point registers 1067 which are 32 or 64 bits wide. 1068 1069‘-modd-spreg’ 1070‘-mno-odd-spreg’ 1071 Enable use of floating-point operations on odd-numbered 1072 single-precision registers when supported by the ISA. ‘-mfpxx’ 1073 implies ‘-mno-odd-spreg’, otherwise the default is ‘-modd-spreg’. 1074 1075‘-mips16’ 1076‘-no-mips16’ 1077 Generate code for the MIPS 16 processor. This is equivalent to 1078 putting ‘.module mips16’ at the start of the assembly file. 1079 ‘-no-mips16’ turns off this option. 1080 1081‘-mmips16e2’ 1082‘-mno-mips16e2’ 1083 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is 1084 equivalent to putting ‘.module mips16e2’ at the start of the 1085 assembly file. ‘-mno-mips16e2’ turns off this option. 1086 1087‘-mmicromips’ 1088‘-mno-micromips’ 1089 Generate code for the microMIPS processor. This is equivalent to 1090 putting ‘.module micromips’ at the start of the assembly file. 1091 ‘-mno-micromips’ turns off this option. This is equivalent to 1092 putting ‘.module nomicromips’ at the start of the assembly file. 1093 1094‘-msmartmips’ 1095‘-mno-smartmips’ 1096 Enables the SmartMIPS extension to the MIPS32 instruction set. 1097 This is equivalent to putting ‘.module smartmips’ at the start of 1098 the assembly file. ‘-mno-smartmips’ turns off this option. 1099 1100‘-mips3d’ 1101‘-no-mips3d’ 1102 Generate code for the MIPS-3D Application Specific Extension. This 1103 tells the assembler to accept MIPS-3D instructions. ‘-no-mips3d’ 1104 turns off this option. 1105 1106‘-mdmx’ 1107‘-no-mdmx’ 1108 Generate code for the MDMX Application Specific Extension. This 1109 tells the assembler to accept MDMX instructions. ‘-no-mdmx’ turns 1110 off this option. 1111 1112‘-mdsp’ 1113‘-mno-dsp’ 1114 Generate code for the DSP Release 1 Application Specific Extension. 1115 This tells the assembler to accept DSP Release 1 instructions. 1116 ‘-mno-dsp’ turns off this option. 1117 1118‘-mdspr2’ 1119‘-mno-dspr2’ 1120 Generate code for the DSP Release 2 Application Specific Extension. 1121 This option implies ‘-mdsp’. This tells the assembler to accept 1122 DSP Release 2 instructions. ‘-mno-dspr2’ turns off this option. 1123 1124‘-mdspr3’ 1125‘-mno-dspr3’ 1126 Generate code for the DSP Release 3 Application Specific Extension. 1127 This option implies ‘-mdsp’ and ‘-mdspr2’. This tells the 1128 assembler to accept DSP Release 3 instructions. ‘-mno-dspr3’ turns 1129 off this option. 1130 1131‘-mmsa’ 1132‘-mno-msa’ 1133 Generate code for the MIPS SIMD Architecture Extension. This tells 1134 the assembler to accept MSA instructions. ‘-mno-msa’ turns off 1135 this option. 1136 1137‘-mxpa’ 1138‘-mno-xpa’ 1139 Generate code for the MIPS eXtended Physical Address (XPA) 1140 Extension. This tells the assembler to accept XPA instructions. 1141 ‘-mno-xpa’ turns off this option. 1142 1143‘-mmt’ 1144‘-mno-mt’ 1145 Generate code for the MT Application Specific Extension. This 1146 tells the assembler to accept MT instructions. ‘-mno-mt’ turns off 1147 this option. 1148 1149‘-mmcu’ 1150‘-mno-mcu’ 1151 Generate code for the MCU Application Specific Extension. This 1152 tells the assembler to accept MCU instructions. ‘-mno-mcu’ turns 1153 off this option. 1154 1155‘-mcrc’ 1156‘-mno-crc’ 1157 Generate code for the MIPS cyclic redundancy check (CRC) 1158 Application Specific Extension. This tells the assembler to accept 1159 CRC instructions. ‘-mno-crc’ turns off this option. 1160 1161‘-mginv’ 1162‘-mno-ginv’ 1163 Generate code for the Global INValidate (GINV) Application Specific 1164 Extension. This tells the assembler to accept GINV instructions. 1165 ‘-mno-ginv’ turns off this option. 1166 1167‘-mloongson-mmi’ 1168‘-mno-loongson-mmi’ 1169 Generate code for the Loongson MultiMedia extensions Instructions 1170 (MMI) Application Specific Extension. This tells the assembler to 1171 accept MMI instructions. ‘-mno-loongson-mmi’ turns off this 1172 option. 1173 1174‘-mloongson-cam’ 1175‘-mno-loongson-cam’ 1176 Generate code for the Loongson Content Address Memory (CAM) 1177 instructions. This tells the assembler to accept Loongson CAM 1178 instructions. ‘-mno-loongson-cam’ turns off this option. 1179 1180‘-mloongson-ext’ 1181‘-mno-loongson-ext’ 1182 Generate code for the Loongson EXTensions (EXT) instructions. This 1183 tells the assembler to accept Loongson EXT instructions. 1184 ‘-mno-loongson-ext’ turns off this option. 1185 1186‘-mloongson-ext2’ 1187‘-mno-loongson-ext2’ 1188 Generate code for the Loongson EXTensions R2 (EXT2) instructions. 1189 This option implies ‘-mloongson-ext’. This tells the assembler to 1190 accept Loongson EXT2 instructions. ‘-mno-loongson-ext2’ turns off 1191 this option. 1192 1193‘-minsn32’ 1194‘-mno-insn32’ 1195 Only use 32-bit instruction encodings when generating code for the 1196 microMIPS processor. This option inhibits the use of any 16-bit 1197 instructions. This is equivalent to putting ‘.set insn32’ at the 1198 start of the assembly file. ‘-mno-insn32’ turns off this option. 1199 This is equivalent to putting ‘.set noinsn32’ at the start of the 1200 assembly file. By default ‘-mno-insn32’ is selected, allowing all 1201 instructions to be used. 1202 1203‘--construct-floats’ 1204‘--no-construct-floats’ 1205 The ‘--no-construct-floats’ option disables the construction of 1206 double width floating point constants by loading the two halves of 1207 the value into the two single width floating point registers that 1208 make up the double width register. By default ‘--construct-floats’ 1209 is selected, allowing construction of these floating point 1210 constants. 1211 1212‘--relax-branch’ 1213‘--no-relax-branch’ 1214 The ‘--relax-branch’ option enables the relaxation of out-of-range 1215 branches. By default ‘--no-relax-branch’ is selected, causing any 1216 out-of-range branches to produce an error. 1217 1218‘-mignore-branch-isa’ 1219‘-mno-ignore-branch-isa’ 1220 Ignore branch checks for invalid transitions between ISA modes. 1221 The semantics of branches does not provide for an ISA mode switch, 1222 so in most cases the ISA mode a branch has been encoded for has to 1223 be the same as the ISA mode of the branch’s target label. 1224 Therefore GAS has checks implemented that verify in branch assembly 1225 that the two ISA modes match. ‘-mignore-branch-isa’ disables these 1226 checks. By default ‘-mno-ignore-branch-isa’ is selected, causing 1227 any invalid branch requiring a transition between ISA modes to 1228 produce an error. 1229 1230‘-mnan=ENCODING’ 1231 Select between the IEEE 754-2008 (‘-mnan=2008’) or the legacy 1232 (‘-mnan=legacy’) NaN encoding format. The latter is the default. 1233 1234‘--emulation=NAME’ 1235 This option was formerly used to switch between ELF and ECOFF 1236 output on targets like IRIX 5 that supported both. MIPS ECOFF 1237 support was removed in GAS 2.24, so the option now serves little 1238 purpose. It is retained for backwards compatibility. 1239 1240 The available configuration names are: ‘mipself’, ‘mipslelf’ and 1241 ‘mipsbelf’. Choosing ‘mipself’ now has no effect, since the output 1242 is always ELF. ‘mipslelf’ and ‘mipsbelf’ select little- and 1243 big-endian output respectively, but ‘-EL’ and ‘-EB’ are now the 1244 preferred options instead. 1245 1246‘-nocpp’ 1247 ‘as’ ignores this option. It is accepted for compatibility with 1248 the native tools. 1249 1250‘--trap’ 1251‘--no-trap’ 1252‘--break’ 1253‘--no-break’ 1254 Control how to deal with multiplication overflow and division by 1255 zero. ‘--trap’ or ‘--no-break’ (which are synonyms) take a trap 1256 exception (and only work for Instruction Set Architecture level 2 1257 and higher); ‘--break’ or ‘--no-trap’ (also synonyms, and the 1258 default) take a break exception. 1259 1260‘-n’ 1261 When this option is used, ‘as’ will issue a warning every time it 1262 generates a nop instruction from a macro. 1263 1264 The following options are available when as is configured for an 1265MCore processor. 1266 1267‘-jsri2bsr’ 1268‘-nojsri2bsr’ 1269 Enable or disable the JSRI to BSR transformation. By default this 1270 is enabled. The command-line option ‘-nojsri2bsr’ can be used to 1271 disable it. 1272 1273‘-sifilter’ 1274‘-nosifilter’ 1275 Enable or disable the silicon filter behaviour. By default this is 1276 disabled. The default can be overridden by the ‘-sifilter’ 1277 command-line option. 1278 1279‘-relax’ 1280 Alter jump instructions for long displacements. 1281 1282‘-mcpu=[210|340]’ 1283 Select the cpu type on the target hardware. This controls which 1284 instructions can be assembled. 1285 1286‘-EB’ 1287 Assemble for a big endian target. 1288 1289‘-EL’ 1290 Assemble for a little endian target. 1291 1292 *Note Meta Options::, for the options available when as is configured 1293for a Meta processor. 1294 1295 See the info pages for documentation of the MMIX-specific options. 1296 1297 *Note NDS32 Options::, for the options available when as is 1298configured for a NDS32 processor. 1299 1300 *Note PowerPC-Opts::, for the options available when as is configured 1301for a PowerPC processor. 1302 1303 *Note RISC-V-Options::, for the options available when as is 1304configured for a RISC-V processor. 1305 1306 See the info pages for documentation of the RX-specific options. 1307 1308 The following options are available when as is configured for the 1309s390 processor family. 1310 1311‘-m31’ 1312‘-m64’ 1313 Select the word size, either 31/32 bits or 64 bits. 1314‘-mesa’ 1315‘-mzarch’ 1316 Select the architecture mode, either the Enterprise System 1317 Architecture (esa) or the z/Architecture mode (zarch). 1318‘-march=PROCESSOR’ 1319 Specify which s390 processor variant is the target, ‘g5’ (or 1320 ‘arch3’), ‘g6’, ‘z900’ (or ‘arch5’), ‘z990’ (or ‘arch6’), ‘z9-109’, 1321 ‘z9-ec’ (or ‘arch7’), ‘z10’ (or ‘arch8’), ‘z196’ (or ‘arch9’), 1322 ‘zEC12’ (or ‘arch10’), ‘z13’ (or ‘arch11’), ‘z14’ (or ‘arch12’), 1323 ‘z15’ (or ‘arch13’), or ‘z16’ (or ‘arch14’). 1324‘-mregnames’ 1325‘-mno-regnames’ 1326 Allow or disallow symbolic names for registers. 1327‘-mwarn-areg-zero’ 1328 Warn whenever the operand for a base or index register has been 1329 specified but evaluates to zero. 1330 1331 *Note TIC6X Options::, for the options available when as is 1332configured for a TMS320C6000 processor. 1333 1334 *Note TILE-Gx Options::, for the options available when as is 1335configured for a TILE-Gx processor. 1336 1337 *Note Visium Options::, for the options available when as is 1338configured for a Visium processor. 1339 1340 *Note Xtensa Options::, for the options available when as is 1341configured for an Xtensa processor. 1342 1343 *Note Z80 Options::, for the options available when as is configured 1344for an Z80 processor. 1345 1346* Menu: 1347 1348* Manual:: Structure of this Manual 1349* GNU Assembler:: The GNU Assembler 1350* Object Formats:: Object File Formats 1351* Command Line:: Command Line 1352* Input Files:: Input Files 1353* Object:: Output (Object) File 1354* Errors:: Error and Warning Messages 1355 1356 1357File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1358 13591.1 Structure of this Manual 1360============================ 1361 1362This manual is intended to describe what you need to know to use GNU 1363‘as’. We cover the syntax expected in source files, including notation 1364for symbols, constants, and expressions; the directives that ‘as’ 1365understands; and of course how to invoke ‘as’. 1366 1367 This manual also describes some of the machine-dependent features of 1368various flavors of the assembler. 1369 1370 On the other hand, this manual is _not_ intended as an introduction 1371to programming in assembly language—let alone programming in general! 1372In a similar vein, we make no attempt to introduce the machine 1373architecture; we do _not_ describe the instruction set, standard 1374mnemonics, registers or addressing modes that are standard to a 1375particular architecture. You may want to consult the manufacturer’s 1376machine architecture manual for this information. 1377 1378 1379File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1380 13811.2 The GNU Assembler 1382===================== 1383 1384GNU ‘as’ is really a family of assemblers. If you use (or have used) 1385the GNU assembler on one architecture, you should find a fairly similar 1386environment when you use it on another architecture. Each version has 1387much in common with the others, including object file formats, most 1388assembler directives (often called “pseudo-ops”) and assembler syntax. 1389 1390 ‘as’ is primarily intended to assemble the output of the GNU C 1391compiler ‘gcc’ for use by the linker ‘ld’. Nevertheless, we’ve tried to 1392make ‘as’ assemble correctly everything that other assemblers for the 1393same machine would assemble. Any exceptions are documented explicitly 1394(*note Machine Dependencies::). This doesn’t mean ‘as’ always uses the 1395same syntax as another assembler for the same architecture; for example, 1396we know of several incompatible versions of 680x0 assembly language 1397syntax. 1398 1399 Unlike older assemblers, ‘as’ is designed to assemble a source 1400program in one pass of the source file. This has a subtle impact on the 1401‘.org’ directive (*note ‘.org’: Org.). 1402 1403 1404File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1405 14061.3 Object File Formats 1407======================= 1408 1409The GNU assembler can be configured to produce several alternative 1410object file formats. For the most part, this does not affect how you 1411write assembly language programs; but directives for debugging symbols 1412are typically different in different file formats. *Note Symbol 1413Attributes: Symbol Attributes. 1414 1415 1416File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1417 14181.4 Command Line 1419================ 1420 1421After the program name ‘as’, the command line may contain options and 1422file names. Options may appear in any order, and may be before, after, 1423or between file names. The order of file names is significant. 1424 1425 ‘--’ (two hyphens) by itself names the standard input file 1426explicitly, as one of the files for ‘as’ to assemble. 1427 1428 Except for ‘--’ any command-line argument that begins with a hyphen 1429(‘-’) is an option. Each option changes the behavior of ‘as’. No 1430option changes the way another option works. An option is a ‘-’ 1431followed by one or more letters; the case of the letter is important. 1432All options are optional. 1433 1434 Some options expect exactly one file name to follow them. The file 1435name may either immediately follow the option’s letter (compatible with 1436older assemblers) or it may be the next command argument (GNU standard). 1437These two command lines are equivalent: 1438 1439 as -o my-object-file.o mumble.s 1440 as -omy-object-file.o mumble.s 1441 1442 1443File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1444 14451.5 Input Files 1446=============== 1447 1448We use the phrase “source program”, abbreviated “source”, to describe 1449the program input to one run of ‘as’. The program may be in one or more 1450files; how the source is partitioned into files doesn’t change the 1451meaning of the source. 1452 1453 The source program is a concatenation of the text in all the files, 1454in the order specified. 1455 1456 Each time you run ‘as’ it assembles exactly one source program. The 1457source program is made up of one or more files. (The standard input is 1458also a file.) 1459 1460 You give ‘as’ a command line that has zero or more input file names. 1461The input files are read (from left file name to right). A command-line 1462argument (in any position) that has no special meaning is taken to be an 1463input file name. 1464 1465 If you give ‘as’ no file names it attempts to read one input file 1466from the ‘as’ standard input, which is normally your terminal. You may 1467have to type <ctl-D> to tell ‘as’ there is no more program to assemble. 1468 1469 Use ‘--’ if you need to explicitly name the standard input file in 1470your command line. 1471 1472 If the source is empty, ‘as’ produces a small, empty object file. 1473 1474Filenames and Line-numbers 1475-------------------------- 1476 1477There are two ways of locating a line in the input file (or files) and 1478either may be used in reporting error messages. One way refers to a 1479line number in a physical file; the other refers to a line number in a 1480“logical” file. *Note Error and Warning Messages: Errors. 1481 1482 “Physical files” are those files named in the command line given to 1483‘as’. 1484 1485 “Logical files” are simply names declared explicitly by assembler 1486directives; they bear no relation to physical files. Logical file names 1487help error messages reflect the original source file, when ‘as’ source 1488is itself synthesized from other files. ‘as’ understands the ‘#’ 1489directives emitted by the ‘gcc’ preprocessor. See also *note ‘.file’: 1490File. 1491 1492 1493File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1494 14951.6 Output (Object) File 1496======================== 1497 1498Every time you run ‘as’ it produces an output file, which is your 1499assembly language program translated into numbers. This file is the 1500object file. Its default name is ‘a.out’. You can give it another name 1501by using the ‘-o’ option. Conventionally, object file names end with 1502‘.o’. The default name is used for historical reasons: older assemblers 1503were capable of assembling self-contained programs directly into a 1504runnable program. (For some formats, this isn’t currently possible, but 1505it can be done for the ‘a.out’ format.) 1506 1507 The object file is meant for input to the linker ‘ld’. It contains 1508assembled program code, information to help ‘ld’ integrate the assembled 1509program into a runnable file, and (optionally) symbolic information for 1510the debugger. 1511 1512 1513File: as.info, Node: Errors, Prev: Object, Up: Overview 1514 15151.7 Error and Warning Messages 1516============================== 1517 1518‘as’ may write warnings and error messages to the standard error file 1519(usually your terminal). This should not happen when a compiler runs 1520‘as’ automatically. Warnings report an assumption made so that ‘as’ 1521could keep assembling a flawed program; errors report a grave problem 1522that stops the assembly. 1523 1524 Warning messages have the format 1525 1526 file_name:NNN:Warning Message Text 1527 1528(where NNN is a line number). If both a logical file name (*note 1529‘.file’: File.) and a logical line number (*note ‘.line’: Line.) have 1530been given then they will be used, otherwise the file name and line 1531number in the current assembler source file will be used. The message 1532text is intended to be self explanatory (in the grand Unix tradition). 1533 1534 Note the file name must be set via the logical version of the ‘.file’ 1535directive, not the DWARF2 version of the ‘.file’ directive. For 1536example: 1537 1538 .file 2 "bar.c" 1539 error_assembler_source 1540 .file "foo.c" 1541 .line 30 1542 error_c_source 1543 1544 produces this output: 1545 1546 Assembler messages: 1547 asm.s:2: Error: no such instruction: `error_assembler_source' 1548 foo.c:31: Error: no such instruction: `error_c_source' 1549 1550 Error messages have the format 1551 1552 file_name:NNN:FATAL:Error Message Text 1553 1554 The file name and line number are derived as for warning messages. 1555The actual message text may be rather less explanatory because many of 1556them aren’t supposed to happen. 1557 1558 1559File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1560 15612 Command-Line Options 1562********************** 1563 1564This chapter describes command-line options available in _all_ versions 1565of the GNU assembler; see *note Machine Dependencies::, for options 1566specific to particular machine architectures. 1567 1568 If you are invoking ‘as’ via the GNU C compiler, you can use the 1569‘-Wa’ option to pass arguments through to the assembler. The assembler 1570arguments must be separated from each other (and the ‘-Wa’) by commas. 1571For example: 1572 1573 gcc -c -g -O -Wa,-alh,-L file.c 1574 1575This passes two options to the assembler: ‘-alh’ (emit a listing to 1576standard output with high-level and assembly source) and ‘-L’ (retain 1577local symbols in the symbol table). 1578 1579 Usually you do not need to use this ‘-Wa’ mechanism, since many 1580compiler command-line options are automatically passed to the assembler 1581by the compiler. (You can call the GNU compiler driver with the ‘-v’ 1582option to see precisely what options it passes to each compilation pass, 1583including the assembler.) 1584 1585* Menu: 1586 1587* a:: -a[cdghilns] enable listings 1588* alternate:: –alternate enable alternate macro syntax 1589* D:: -D for compatibility and debugging 1590* f:: -f to work faster 1591* I:: -I for .include search path 1592* K:: -K for difference tables 1593 1594* L:: -L to retain local symbols 1595* listing:: –listing-XXX to configure listing output 1596* M:: -M or –mri to assemble in MRI compatibility mode 1597* MD:: –MD for dependency tracking 1598* no-pad-sections:: –no-pad-sections to stop section padding 1599* o:: -o to name the object file 1600* R:: -R to join data and text sections 1601* statistics:: –statistics to see statistics about assembly 1602* traditional-format:: –traditional-format for compatible output 1603* v:: -v to announce version 1604* W:: -W, –no-warn, –warn, –fatal-warnings to control warnings 1605* Z:: -Z to make object file even after errors 1606 1607 1608File: as.info, Node: a, Next: alternate, Up: Invoking 1609 16102.1 Enable Listings: ‘-a[cdghilns]’ 1611=================================== 1612 1613These options enable listing output from the assembler. By itself, ‘-a’ 1614requests high-level, assembly, and symbols listing. You can use other 1615letters to select specific options for the list: ‘-ah’ requests a 1616high-level language listing, ‘-al’ requests an output-program assembly 1617listing, ‘-ali’ requests an output-program assembly listing along with 1618the associated ginsn, and ‘-as’ requests a symbol table listing. 1619High-level listings require that a compiler debugging option like ‘-g’ 1620be used, and that assembly listings (‘-al’) be requested also. 1621 1622 Use the ‘-ag’ option to print a first section with general assembly 1623information, like as version, switches passed, or time stamp. 1624 1625 Use the ‘-ac’ option to omit false conditionals from a listing. Any 1626lines which are not assembled because of a false ‘.if’ (or ‘.ifdef’, or 1627any other conditional), or a true ‘.if’ followed by an ‘.else’, will be 1628omitted from the listing. 1629 1630 Use the ‘-ad’ option to omit debugging directives from the listing. 1631 1632 Once you have specified one of these options, you can further control 1633listing output and its appearance using the directives ‘.list’, 1634‘.nolist’, ‘.psize’, ‘.eject’, ‘.title’, and ‘.sbttl’. The ‘-an’ option 1635turns off all forms processing. If you do not request listing output 1636with one of the ‘-a’ options, the listing-control directives have no 1637effect. 1638 1639 The letters after ‘-a’ may be combined into one option, _e.g._, 1640‘-aln’. 1641 1642 Note if the assembler source is coming from the standard input (e.g., 1643because it is being created by ‘gcc’ and the ‘-pipe’ command-line switch 1644is being used) then the listing will not contain any comments or 1645preprocessor directives. This is because the listing code buffers input 1646source lines from stdin only after they have been preprocessed by the 1647assembler. This reduces memory usage and makes the code more efficient. 1648 1649 1650File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1651 16522.2 ‘--alternate’ 1653================= 1654 1655Begin in alternate macro mode, see *note ‘.altmacro’: Altmacro. 1656 1657 1658File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1659 16602.3 ‘-D’ 1661======== 1662 1663This option enables debugging, if it is supported by the assembler’s 1664configuration. Otherwise it does nothing as is ignored. This allows 1665scripts designed to work with other assemblers to also work with GAS. 1666‘as’. 1667 1668 1669File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1670 16712.4 Work Faster: ‘-f’ 1672===================== 1673 1674‘-f’ should only be used when assembling programs written by a (trusted) 1675compiler. ‘-f’ stops the assembler from doing whitespace and comment 1676preprocessing on the input file(s) before assembling them. *Note 1677Preprocessing: Preprocessing. 1678 1679 _Warning:_ if you use ‘-f’ when the files actually need to be 1680 preprocessed (if they contain comments, for example), ‘as’ does not 1681 work correctly. 1682 1683 1684File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1685 16862.5 ‘.include’ Search Path: ‘-I’ PATH 1687===================================== 1688 1689Use this option to add a PATH to the list of directories ‘as’ searches 1690for files specified in ‘.include’ directives (*note ‘.include’: 1691Include.). You may use ‘-I’ as many times as necessary to include a 1692variety of paths. The current working directory is always searched 1693first; after that, ‘as’ searches any ‘-I’ directories in the same order 1694as they were specified (left to right) on the command line. 1695 1696 1697File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1698 16992.6 Difference Tables: ‘-K’ 1700=========================== 1701 1702‘as’ sometimes alters the code emitted for directives of the form ‘.word 1703SYM1-SYM2’. *Note ‘.word’: Word. You can use the ‘-K’ option if you 1704want a warning issued when this is done. 1705 1706 1707File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1708 17092.7 Include Local Symbols: ‘-L’ 1710=============================== 1711 1712Symbols beginning with system-specific local label prefixes, typically 1713‘.L’ for ELF systems or ‘L’ for traditional a.out systems, are called 1714“local symbols”. *Note Symbol Names::. Normally you do not see such 1715symbols when debugging, because they are intended for the use of 1716programs (like compilers) that compose assembler programs, not for your 1717notice. Normally both ‘as’ and ‘ld’ discard such symbols, so you do not 1718normally debug with them. 1719 1720 This option tells ‘as’ to retain those local symbols in the object 1721file. Usually if you do this you also tell the linker ‘ld’ to preserve 1722those symbols. 1723 1724 1725File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1726 17272.8 Configuring listing output: ‘--listing’ 1728=========================================== 1729 1730The listing feature of the assembler can be enabled via the command-line 1731switch ‘-a’ (*note a::). This feature combines the input source file(s) 1732with a hex dump of the corresponding locations in the output object 1733file, and displays them as a listing file. The format of this listing 1734can be controlled by directives inside the assembler source (i.e., 1735‘.list’ (*note List::), ‘.title’ (*note Title::), ‘.sbttl’ (*note 1736Sbttl::), ‘.psize’ (*note Psize::), and ‘.eject’ (*note Eject::) and 1737also by the following switches: 1738 1739‘--listing-lhs-width=‘number’’ 1740 Sets the maximum width, in words, of the first line of the hex byte 1741 dump. This dump appears on the left hand side of the listing 1742 output. 1743 1744‘--listing-lhs-width2=‘number’’ 1745 Sets the maximum width, in words, of any further lines of the hex 1746 byte dump for a given input source line. If this value is not 1747 specified, it defaults to being the same as the value specified for 1748 ‘--listing-lhs-width’. If neither switch is used the default is to 1749 one. 1750 1751‘--listing-rhs-width=‘number’’ 1752 Sets the maximum width, in characters, of the source line that is 1753 displayed alongside the hex dump. The default value for this 1754 parameter is 100. The source line is displayed on the right hand 1755 side of the listing output. 1756 1757‘--listing-cont-lines=‘number’’ 1758 Sets the maximum number of continuation lines of hex dump that will 1759 be displayed for a given single line of source input. The default 1760 value is 4. 1761 1762 1763File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1764 17652.9 Assemble in MRI Compatibility Mode: ‘-M’ 1766============================================ 1767 1768The ‘-M’ or ‘--mri’ option selects MRI compatibility mode. This changes 1769the syntax and pseudo-op handling of ‘as’ to make it compatible with the 1770‘ASM68K’ assembler from Microtec Research. The exact nature of the MRI 1771syntax will not be documented here; see the MRI manuals for more 1772information. Note in particular that the handling of macros and macro 1773arguments is somewhat different. The purpose of this option is to 1774permit assembling existing MRI assembler code using ‘as’. 1775 1776 The MRI compatibility is not complete. Certain operations of the MRI 1777assembler depend upon its object file format, and can not be supported 1778using other object file formats. Supporting these would require 1779enhancing each object file format individually. These are: 1780 1781 • global symbols in common section 1782 1783 The m68k MRI assembler supports common sections which are merged by 1784 the linker. Other object file formats do not support this. ‘as’ 1785 handles common sections by treating them as a single common symbol. 1786 It permits local symbols to be defined within a common section, but 1787 it can not support global symbols, since it has no way to describe 1788 them. 1789 1790 • complex relocations 1791 1792 The MRI assemblers support relocations against a negated section 1793 address, and relocations which combine the start addresses of two 1794 or more sections. These are not support by other object file 1795 formats. 1796 1797 • ‘END’ pseudo-op specifying start address 1798 1799 The MRI ‘END’ pseudo-op permits the specification of a start 1800 address. This is not supported by other object file formats. The 1801 start address may instead be specified using the ‘-e’ option to the 1802 linker, or in a linker script. 1803 1804 • ‘IDNT’, ‘.ident’ and ‘NAME’ pseudo-ops 1805 1806 The MRI ‘IDNT’, ‘.ident’ and ‘NAME’ pseudo-ops assign a module name 1807 to the output file. This is not supported by other object file 1808 formats. 1809 1810 • ‘ORG’ pseudo-op 1811 1812 The m68k MRI ‘ORG’ pseudo-op begins an absolute section at a given 1813 address. This differs from the usual ‘as’ ‘.org’ pseudo-op, which 1814 changes the location within the current section. Absolute sections 1815 are not supported by other object file formats. The address of a 1816 section may be assigned within a linker script. 1817 1818 There are some other features of the MRI assembler which are not 1819supported by ‘as’, typically either because they are difficult or 1820because they seem of little consequence. Some of these may be supported 1821in future releases. 1822 1823 • EBCDIC strings 1824 1825 EBCDIC strings are not supported. 1826 1827 • packed binary coded decimal 1828 1829 Packed binary coded decimal is not supported. This means that the 1830 ‘DC.P’ and ‘DCB.P’ pseudo-ops are not supported. 1831 1832 • ‘FEQU’ pseudo-op 1833 1834 The m68k ‘FEQU’ pseudo-op is not supported. 1835 1836 • ‘NOOBJ’ pseudo-op 1837 1838 The m68k ‘NOOBJ’ pseudo-op is not supported. 1839 1840 • ‘OPT’ branch control options 1841 1842 The m68k ‘OPT’ branch control options—‘B’, ‘BRS’, ‘BRB’, ‘BRL’, and 1843 ‘BRW’—are ignored. ‘as’ automatically relaxes all branches, 1844 whether forward or backward, to an appropriate size, so these 1845 options serve no purpose. 1846 1847 • ‘OPT’ list control options 1848 1849 The following m68k ‘OPT’ list control options are ignored: ‘C’, 1850 ‘CEX’, ‘CL’, ‘CRE’, ‘E’, ‘G’, ‘I’, ‘M’, ‘MEX’, ‘MC’, ‘MD’, ‘X’. 1851 1852 • other ‘OPT’ options 1853 1854 The following m68k ‘OPT’ options are ignored: ‘NEST’, ‘O’, ‘OLD’, 1855 ‘OP’, ‘P’, ‘PCO’, ‘PCR’, ‘PCS’, ‘R’. 1856 1857 • ‘OPT’ ‘D’ option is default 1858 1859 The m68k ‘OPT’ ‘D’ option is the default, unlike the MRI assembler. 1860 ‘OPT NOD’ may be used to turn it off. 1861 1862 • ‘XREF’ pseudo-op. 1863 1864 The m68k ‘XREF’ pseudo-op is ignored. 1865 1866 1867File: as.info, Node: MD, Next: no-pad-sections, Prev: M, Up: Invoking 1868 18692.10 Dependency Tracking: ‘--MD’ 1870================================ 1871 1872‘as’ can generate a dependency file for the file it creates. This file 1873consists of a single rule suitable for ‘make’ describing the 1874dependencies of the main source file. 1875 1876 The rule is written to the file named in its argument. 1877 1878 This feature is used in the automatic updating of makefiles. 1879 1880 1881File: as.info, Node: no-pad-sections, Next: o, Prev: MD, Up: Invoking 1882 18832.11 Output Section Padding 1884=========================== 1885 1886Normally the assembler will pad the end of each output section up to its 1887alignment boundary. But this can waste space, which can be significant 1888on memory constrained targets. So the ‘--no-pad-sections’ option will 1889disable this behaviour. 1890 1891 1892File: as.info, Node: o, Next: R, Prev: no-pad-sections, Up: Invoking 1893 18942.12 Name the Object File: ‘-o’ 1895=============================== 1896 1897There is always one object file output when you run ‘as’. By default it 1898has the name ‘a.out’. You use this option (which takes exactly one 1899filename) to give the object file a different name. 1900 1901 Whatever the object file is called, ‘as’ overwrites any existing file 1902of the same name. 1903 1904 1905File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1906 19072.13 Join Data and Text Sections: ‘-R’ 1908====================================== 1909 1910‘-R’ tells ‘as’ to write the object file as if all data-section data 1911lives in the text section. This is only done at the very last moment: 1912your binary data are the same, but data section parts are relocated 1913differently. The data section part of your object file is zero bytes 1914long because all its bytes are appended to the text section. (*Note 1915Sections and Relocation: Sections.) 1916 1917 When you specify ‘-R’ it would be possible to generate shorter 1918address displacements (because we do not have to cross between text and 1919data section). We refrain from doing this simply for compatibility with 1920older versions of ‘as’. In future, ‘-R’ may work this way. 1921 1922 When ‘as’ is configured for COFF or ELF output, this option is only 1923useful if you use sections named ‘.text’ and ‘.data’. 1924 1925 ‘-R’ is not supported for any of the HPPA targets. Using ‘-R’ 1926generates a warning from ‘as’. 1927 1928 1929File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1930 19312.14 Display Assembly Statistics: ‘--statistics’ 1932================================================ 1933 1934Use ‘--statistics’ to display two statistics about the resources used by 1935‘as’: the maximum amount of space allocated during the assembly (in 1936bytes), and the total execution time taken for the assembly (in CPU 1937seconds). 1938 1939 1940File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1941 19422.15 Compatible Output: ‘--traditional-format’ 1943============================================== 1944 1945For some targets, the output of ‘as’ is different in some ways from the 1946output of some existing assembler. This switch requests ‘as’ to use the 1947traditional format instead. 1948 1949 For example, it disables the exception frame optimizations which ‘as’ 1950normally does by default on ‘gcc’ output. 1951 1952 1953File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1954 19552.16 Announce Version: ‘-v’ 1956=========================== 1957 1958You can find out what version of as is running by including the option 1959‘-v’ (which you can also spell as ‘-version’) on the command line. 1960 1961 1962File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1963 19642.17 Control Warnings: ‘-W’, ‘--warn’, ‘--no-warn’, ‘--fatal-warnings’ 1965====================================================================== 1966 1967‘as’ should never give a warning or error message when assembling 1968compiler output. But programs written by people often cause ‘as’ to 1969give a warning that a particular assumption was made. All such warnings 1970are directed to the standard error file. 1971 1972 If you use the ‘-W’ and ‘--no-warn’ options, no warnings are issued. 1973This only affects the warning messages: it does not change any 1974particular of how ‘as’ assembles your file. Errors, which stop the 1975assembly, are still reported. 1976 1977 If you use the ‘--fatal-warnings’ option, ‘as’ considers files that 1978generate warnings to be in error. 1979 1980 You can switch these options off again by specifying ‘--warn’, which 1981causes warnings to be output as usual. 1982 1983 1984File: as.info, Node: Z, Prev: W, Up: Invoking 1985 19862.18 Generate Object File in Spite of Errors: ‘-Z’ 1987================================================== 1988 1989After an error message, ‘as’ normally produces no output. If for some 1990reason you are interested in object file output even after ‘as’ gives an 1991error message on your program, use the ‘-Z’ option. If there are any 1992errors, ‘as’ continues anyways, and writes an object file after a final 1993warning message of the form ‘N errors, M warnings, generating bad object 1994file.’ 1995 1996 1997File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1998 19993 Syntax 2000******** 2001 2002This chapter describes the machine-independent syntax allowed in a 2003source file. ‘as’ syntax is similar to what many other assemblers use; 2004it is inspired by the BSD 4.2 assembler, except that ‘as’ does not 2005assemble Vax bit-fields. 2006 2007* Menu: 2008 2009* Preprocessing:: Preprocessing 2010* Whitespace:: Whitespace 2011* Comments:: Comments 2012* Symbol Intro:: Symbols 2013* Statements:: Statements 2014* Constants:: Constants 2015 2016 2017File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 2018 20193.1 Preprocessing 2020================= 2021 2022The ‘as’ internal preprocessor: 2023 • adjusts and removes extra whitespace. It leaves one space or tab 2024 before the keywords on a line, and turns any other whitespace on 2025 the line into a single space. 2026 2027 • removes all comments, replacing them with a single space, or an 2028 appropriate number of newlines. 2029 2030 • converts character constants into the appropriate numeric values. 2031 2032 It does not do macro processing, include file handling, or anything 2033else you may get from your C compiler’s preprocessor. You can do 2034include file processing with the ‘.include’ directive (*note ‘.include’: 2035Include.). You can use the GNU C compiler driver to get other “CPP” 2036style preprocessing by giving the input file a ‘.S’ suffix. See the 2037’Options Controlling the Kind of Output’ section of the GCC manual for 2038more details 2039(https://gcc.gnu.org/onlinedocs/gcc/Overall-Options.html#Overall-Options) 2040 2041 Excess whitespace, comments, and character constants cannot be used 2042in the portions of the input text that are not preprocessed. 2043 2044 If the first line of an input file is ‘#NO_APP’ or if you use the 2045‘-f’ option, whitespace and comments are not removed from the input 2046file. Within an input file, you can ask for whitespace and comment 2047removal in specific portions of the file by putting a line that says 2048‘#APP’ before the text that may contain whitespace or comments, and 2049putting a line that says ‘#NO_APP’ after this text. This feature is 2050mainly intended to support ‘asm’ statements in compilers whose output is 2051otherwise free of comments and whitespace. 2052 2053 2054File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 2055 20563.2 Whitespace 2057============== 2058 2059“Whitespace” is one or more blanks or tabs, in any order. Whitespace is 2060used to separate symbols, and to make programs neater for people to 2061read. Unless within character constants (*note Character Constants: 2062Characters.), any whitespace means the same as exactly one space. 2063 2064 2065File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 2066 20673.3 Comments 2068============ 2069 2070There are two ways of rendering comments to ‘as’. In both cases the 2071comment is equivalent to one space. 2072 2073 Anything from ‘/*’ through the next ‘*/’ is a comment. This means 2074you may not nest these comments. 2075 2076 /* 2077 The only way to include a newline ('\n') in a comment 2078 is to use this sort of comment. 2079 */ 2080 2081 /* This sort of comment does not nest. */ 2082 2083 Anything from a “line comment” character up to the next newline is 2084considered a comment and is ignored. The line comment character is 2085target specific, and some targets support multiple comment characters. 2086Some targets also have line comment characters that only work if they 2087are the first character on a line. Some targets use a sequence of two 2088characters to introduce a line comment. Some targets can also change 2089their line comment characters depending upon command-line options that 2090have been used. For more details see the _Syntax_ section in the 2091documentation for individual targets. 2092 2093 If the line comment character is the hash sign (‘#’) then it still 2094has the special ability to enable and disable preprocessing (*note 2095Preprocessing::) and to specify logical line numbers: 2096 2097 To be compatible with past assemblers, lines that begin with ‘#’ have 2098a special interpretation. Following the ‘#’ should be an absolute 2099expression (*note Expressions::): the logical line number of the _next_ 2100line. Then a string (*note Strings: Strings.) is allowed: if present it 2101is a new logical file name. The rest of the line, if any, should be 2102whitespace. 2103 2104 If the first non-whitespace characters on the line are not numeric, 2105the line is ignored. (Just like a comment.) 2106 2107 # This is an ordinary comment. 2108 # 42-6 "new_file_name" # New logical file name 2109 # This is logical line # 36. 2110 This feature is deprecated, and may disappear from future versions of 2111‘as’. 2112 2113 2114File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 2115 21163.4 Symbols 2117=========== 2118 2119A “symbol” is one or more characters chosen from the set of all letters 2120(both upper and lower case), digits and the three characters ‘_.$’. On 2121most machines, you can also use ‘$’ in symbol names; exceptions are 2122noted in *note Machine Dependencies::. No symbol may begin with a 2123digit. Case is significant. There is no length limit; all characters 2124are significant. Multibyte characters are supported, but note that the 2125setting of the ‘--multibyte-handling’ option might prevent their use. 2126Symbols are delimited by characters not in that set, or by the beginning 2127of a file (since the source program must end with a newline, the end of 2128a file is not a possible symbol delimiter). *Note Symbols::. 2129 2130 Symbol names may also be enclosed in double quote ‘"’ characters. In 2131such cases any characters are allowed, except for the NUL character. If 2132a double quote character is to be included in the symbol name it must be 2133preceded by a backslash ‘\’ character. 2134 2135 2136File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 2137 21383.5 Statements 2139============== 2140 2141A “statement” ends at a newline character (‘\n’) or a “line separator 2142character”. The line separator character is target specific and 2143described in the _Syntax_ section of each target’s documentation. Not 2144all targets support a line separator character. The newline or line 2145separator character is considered to be part of the preceding statement. 2146Newlines and separators within character constants are an exception: 2147they do not end statements. 2148 2149 It is an error to end any statement with end-of-file: the last 2150character of any input file should be a newline. 2151 2152 An empty statement is allowed, and may include whitespace. It is 2153ignored. 2154 2155 A statement begins with zero or more labels, optionally followed by a 2156key symbol which determines what kind of statement it is. The key 2157symbol determines the syntax of the rest of the statement. If the 2158symbol begins with a dot ‘.’ then the statement is an assembler 2159directive: typically valid for any computer. If the symbol begins with 2160a letter the statement is an assembly language “instruction”: it 2161assembles into a machine language instruction. Different versions of 2162‘as’ for different computers recognize different instructions. In fact, 2163the same symbol may represent a different instruction in a different 2164computer’s assembly language. 2165 2166 A label is a symbol immediately followed by a colon (‘:’). 2167Whitespace before a label or after a colon is permitted, but you may not 2168have whitespace between a label’s symbol and its colon. *Note Labels::. 2169 2170 For HPPA targets, labels need not be immediately followed by a colon, 2171but the definition of a label must begin in column zero. This also 2172implies that only one label may be defined on each line. 2173 2174 label: .directive followed by something 2175 another_label: # This is an empty statement. 2176 instruction operand_1, operand_2, ... 2177 2178 2179File: as.info, Node: Constants, Prev: Statements, Up: Syntax 2180 21813.6 Constants 2182============= 2183 2184A constant is a number, written so that its value is known by 2185inspection, without knowing any context. Like this: 2186 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 2187 .ascii "Ring the bell\7" # A string constant. 2188 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 2189 .float 0f-314159265358979323846264338327\ 2190 95028841971.693993751E-40 # - pi, a flonum. 2191 2192* Menu: 2193 2194* Characters:: Character Constants 2195* Numbers:: Number Constants 2196 2197 2198File: as.info, Node: Characters, Next: Numbers, Up: Constants 2199 22003.6.1 Character Constants 2201------------------------- 2202 2203There are two kinds of character constants. A “character” stands for 2204one character in one byte and its value may be used in numeric 2205expressions. String constants (properly called string _literals_) are 2206potentially many bytes and their values may not be used in arithmetic 2207expressions. 2208 2209* Menu: 2210 2211* Strings:: Strings 2212* Chars:: Characters 2213 2214 2215File: as.info, Node: Strings, Next: Chars, Up: Characters 2216 22173.6.1.1 Strings 2218............... 2219 2220A “string” is written between double-quotes. It may contain 2221double-quotes or null characters. The way to get special characters 2222into a string is to “escape” these characters: precede them with a 2223backslash ‘\’ character. For example ‘\\’ represents one backslash: the 2224first ‘\’ is an escape which tells ‘as’ to interpret the second 2225character literally as a backslash (which prevents ‘as’ from recognizing 2226the second ‘\’ as an escape character). The complete list of escapes 2227follows. 2228 2229‘\b’ 2230 Mnemonic for backspace; for ASCII this is octal code 010. 2231 2232‘backslash-f’ 2233 Mnemonic for FormFeed; for ASCII this is octal code 014. 2234 2235‘\n’ 2236 Mnemonic for newline; for ASCII this is octal code 012. 2237 2238‘\r’ 2239 Mnemonic for carriage-Return; for ASCII this is octal code 015. 2240 2241‘\t’ 2242 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 2243 2244‘\ DIGIT DIGIT DIGIT’ 2245 An octal character code. The numeric code is 3 octal digits. For 2246 compatibility with other Unix systems, 8 and 9 are accepted as 2247 digits: for example, ‘\008’ has the value 010, and ‘\009’ the value 2248 011. 2249 2250‘\x HEX-DIGITS...’ 2251 A hex character code. All trailing hex digits are combined. 2252 Either upper or lower case ‘x’ works. 2253 2254‘\\’ 2255 Represents one ‘\’ character. 2256 2257‘\"’ 2258 Represents one ‘"’ character. Needed in strings to represent this 2259 character, because an unescaped ‘"’ would end the string. 2260 2261‘\ ANYTHING-ELSE’ 2262 Any other character when escaped by ‘\’ gives a warning, but 2263 assembles as if the ‘\’ was not present. The idea is that if you 2264 used an escape sequence you clearly didn’t want the literal 2265 interpretation of the following character. However ‘as’ has no 2266 other interpretation, so ‘as’ knows it is giving you the wrong code 2267 and warns you of the fact. 2268 2269 Which characters are escapable, and what those escapes represent, 2270varies widely among assemblers. The current set is what we think the 2271BSD 4.2 assembler recognizes, and is a subset of what most C compilers 2272recognize. If you are in doubt, do not use an escape sequence. 2273 2274 2275File: as.info, Node: Chars, Prev: Strings, Up: Characters 2276 22773.6.1.2 Characters 2278.................. 2279 2280A single character may be written as a single quote immediately followed 2281by that character. Some backslash escapes apply to characters, ‘\b’, 2282‘\f’, ‘\n’, ‘\r’, ‘\t’, and ‘\"’ with the same meaning as for strings, 2283plus ‘\'’ for a single quote. So if you want to write the character 2284backslash, you must write ‘'\\’ where the first ‘\’ escapes the second 2285‘\’. As you can see, the quote is an acute accent, not a grave accent. 2286A newline immediately following an acute accent is taken as a literal 2287character and does not count as the end of a statement. The value of a 2288character constant in a numeric expression is the machine’s byte-wide 2289code for that character. ‘as’ assumes your character code is ASCII: 2290‘'A’ means 65, ‘'B’ means 66, and so on. 2291 2292 2293File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2294 22953.6.2 Number Constants 2296---------------------- 2297 2298‘as’ distinguishes three kinds of numbers according to how they are 2299stored in the target machine. _Integers_ are numbers that would fit 2300into an ‘int’ in the C language. _Bignums_ are integers, but they are 2301stored in more than 32 bits. _Flonums_ are floating point numbers, 2302described below. 2303 2304* Menu: 2305 2306* Integers:: Integers 2307* Bignums:: Bignums 2308* Flonums:: Flonums 2309 2310 2311File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2312 23133.6.2.1 Integers 2314................ 2315 2316A binary integer is ‘0b’ or ‘0B’ followed by zero or more of the binary 2317digits ‘01’. 2318 2319 An octal integer is ‘0’ followed by zero or more of the octal digits 2320(‘01234567’). 2321 2322 A decimal integer starts with a non-zero digit followed by zero or 2323more digits (‘0123456789’). 2324 2325 A hexadecimal integer is ‘0x’ or ‘0X’ followed by one or more 2326hexadecimal digits chosen from ‘0123456789abcdefABCDEF’. 2327 2328 Integers have the usual values. To denote a negative integer, use 2329the prefix operator ‘-’ discussed under expressions (*note Prefix 2330Operators: Prefix Ops.). 2331 2332 2333File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2334 23353.6.2.2 Bignums 2336............... 2337 2338A “bignum” has the same syntax and semantics as an integer except that 2339the number (or its negative) takes more than 32 bits to represent in 2340binary. The distinction is made because in some places integers are 2341permitted while bignums are not. 2342 2343 2344File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2345 23463.6.2.3 Flonums 2347............... 2348 2349A “flonum” represents a floating point number. The translation is 2350indirect: a decimal floating point number from the text is converted by 2351‘as’ to a generic binary floating point number of more than sufficient 2352precision. This generic floating point number is converted to a 2353particular computer’s floating point format (or formats) by a portion of 2354‘as’ specialized to that computer. 2355 2356 A flonum is written by writing (in order) 2357 • The digit ‘0’. (‘0’ is optional on the HPPA.) 2358 2359 • A letter, to tell ‘as’ the rest of the number is a flonum. ‘e’ is 2360 recommended. Case is not important. 2361 2362 On the H8/300 and Renesas / SuperH SH architectures, the letter 2363 must be one of the letters ‘DFPRSX’ (in upper or lower case). 2364 2365 On the ARC, the letter must be one of the letters ‘DFRS’ (in upper 2366 or lower case). 2367 2368 On the HPPA architecture, the letter must be ‘E’ (upper case only). 2369 2370 • An optional sign: either ‘+’ or ‘-’. 2371 2372 • An optional “integer part”: zero or more decimal digits. 2373 2374 • An optional “fractional part”: ‘.’ followed by zero or more decimal 2375 digits. 2376 2377 • An optional exponent, consisting of: 2378 2379 • An ‘E’ or ‘e’. 2380 • Optional sign: either ‘+’ or ‘-’. 2381 • One or more decimal digits. 2382 2383 At least one of the integer part or the fractional part must be 2384present. The floating point number has the usual base-10 value. 2385 2386 ‘as’ does all processing using integers. Flonums are computed 2387independently of any floating point hardware in the computer running 2388‘as’. 2389 2390 2391File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2392 23934 Sections and Relocation 2394************************* 2395 2396* Menu: 2397 2398* Secs Background:: Background 2399* Ld Sections:: Linker Sections 2400* As Sections:: Assembler Internal Sections 2401* Sub-Sections:: Sub-Sections 2402* bss:: bss Section 2403 2404 2405File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2406 24074.1 Background 2408============== 2409 2410Roughly, a section is a range of addresses, with no gaps; all data “in” 2411those addresses is treated the same for some particular purpose. For 2412example there may be a “read only” section. 2413 2414 The linker ‘ld’ reads many object files (partial programs) and 2415combines their contents to form a runnable program. When ‘as’ emits an 2416object file, the partial program is assumed to start at address 0. ‘ld’ 2417assigns the final addresses for the partial program, so that different 2418partial programs do not overlap. This is actually an 2419oversimplification, but it suffices to explain how ‘as’ uses sections. 2420 2421 ‘ld’ moves blocks of bytes of your program to their run-time 2422addresses. These blocks slide to their run-time addresses as rigid 2423units; their length does not change and neither does the order of bytes 2424within them. Such a rigid unit is called a _section_. Assigning 2425run-time addresses to sections is called “relocation”. It includes the 2426task of adjusting mentions of object-file addresses so they refer to the 2427proper run-time addresses. For the H8/300, and for the Renesas / SuperH 2428SH, ‘as’ pads sections if needed to ensure they end on a word (sixteen 2429bit) boundary. 2430 2431 An object file written by ‘as’ has at least three sections, any of 2432which may be empty. These are named “text”, “data” and “bss” sections. 2433 2434 When it generates COFF or ELF output, ‘as’ can also generate whatever 2435other named sections you specify using the ‘.section’ directive (*note 2436‘.section’: Section.). If you do not use any directives that place 2437output in the ‘.text’ or ‘.data’ sections, these sections still exist, 2438but are empty. 2439 2440 When ‘as’ generates SOM or ELF output for the HPPA, ‘as’ can also 2441generate whatever other named sections you specify using the ‘.space’ 2442and ‘.subspace’ directives. See ‘HP9000 Series 800 Assembly Language 2443Reference Manual’ (HP 92432-90001) for details on the ‘.space’ and 2444‘.subspace’ assembler directives. 2445 2446 Additionally, ‘as’ uses different names for the standard text, data, 2447and bss sections when generating SOM output. Program text is placed 2448into the ‘$CODE$’ section, data into ‘$DATA$’, and BSS into ‘$BSS$’. 2449 2450 Within the object file, the text section starts at address ‘0’, the 2451data section follows, and the bss section follows the data section. 2452 2453 When generating either SOM or ELF output files on the HPPA, the text 2454section starts at address ‘0’, the data section at address ‘0x4000000’, 2455and the bss section follows the data section. 2456 2457 To let ‘ld’ know which data changes when the sections are relocated, 2458and how to change that data, ‘as’ also writes to the object file details 2459of the relocation needed. To perform relocation ‘ld’ must know, each 2460time an address in the object file is mentioned: 2461 • Where in the object file is the beginning of this reference to an 2462 address? 2463 • How long (in bytes) is this reference? 2464 • Which section does the address refer to? What is the numeric value 2465 of 2466 (ADDRESS) − (START-ADDRESS OF SECTION)? 2467 • Is the reference to an address “Program-Counter relative”? 2468 2469 In fact, every address ‘as’ ever uses is expressed as 2470 (SECTION) + (OFFSET INTO SECTION) 2471Further, most expressions ‘as’ computes have this section-relative 2472nature. (For some object formats, such as SOM for the HPPA, some 2473expressions are symbol-relative instead.) 2474 2475 In this manual we use the notation {SECNAME N} to mean “offset N into 2476section SECNAME.” 2477 2478 Apart from text, data and bss sections you need to know about the 2479“absolute” section. When ‘ld’ mixes partial programs, addresses in the 2480absolute section remain unchanged. For example, address ‘{absolute 0}’ 2481is “relocated” to run-time address 0 by ‘ld’. Although the linker never 2482arranges two partial programs’ data sections with overlapping addresses 2483after linking, _by definition_ their absolute sections must overlap. 2484Address ‘{absolute 239}’ in one part of a program is always the same 2485address when the program is running as address ‘{absolute 239}’ in any 2486other part of the program. 2487 2488 The idea of sections is extended to the “undefined” section. Any 2489address whose section is unknown at assembly time is by definition 2490rendered {undefined U}—where U is filled in later. Since numbers are 2491always defined, the only way to generate an undefined address is to 2492mention an undefined symbol. A reference to a named common block would 2493be such a symbol: its value is unknown at assembly time so it has 2494section _undefined_. 2495 2496 By analogy the word _section_ is used to describe groups of sections 2497in the linked program. ‘ld’ puts all partial programs’ text sections in 2498contiguous addresses in the linked program. It is customary to refer to 2499the _text section_ of a program, meaning all the addresses of all 2500partial programs’ text sections. Likewise for data and bss sections. 2501 2502 Some sections are manipulated by ‘ld’; others are invented for use of 2503‘as’ and have no meaning except during assembly. 2504 2505 2506File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2507 25084.2 Linker Sections 2509=================== 2510 2511‘ld’ deals with just four kinds of sections, summarized below. 2512 2513*named sections* 2514*text section* 2515*data section* 2516 These sections hold your program. ‘as’ and ‘ld’ treat them as 2517 separate but equal sections. Anything you can say of one section 2518 is true of another. When the program is running, however, it is 2519 customary for the text section to be unalterable. The text section 2520 is often shared among processes: it contains instructions, 2521 constants and the like. The data section of a running program is 2522 usually alterable: for example, C variables would be stored in the 2523 data section. 2524 2525*bss section* 2526 This section contains zeroed bytes when your program begins 2527 running. It is used to hold uninitialized variables or common 2528 storage. The length of each partial program’s bss section is 2529 important, but because it starts out containing zeroed bytes there 2530 is no need to store explicit zero bytes in the object file. The 2531 bss section was invented to eliminate those explicit zeros from 2532 object files. 2533 2534*absolute section* 2535 Address 0 of this section is always “relocated” to runtime address 2536 0. This is useful if you want to refer to an address that ‘ld’ 2537 must not change when relocating. In this sense we speak of 2538 absolute addresses being “unrelocatable”: they do not change during 2539 relocation. 2540 2541*undefined section* 2542 This “section” is a catch-all for address references to objects not 2543 in the preceding sections. 2544 2545 An idealized example of three relocatable sections follows. The 2546example uses the traditional section names ‘.text’ and ‘.data’. Memory 2547addresses are on the horizontal axis. 2548 2549 +-----+----+--+ 2550 partial program # 1: |ttttt|dddd|00| 2551 +-----+----+--+ 2552 2553 text data bss 2554 seg. seg. seg. 2555 2556 +---+---+---+ 2557 partial program # 2: |TTT|DDD|000| 2558 +---+---+---+ 2559 2560 +--+---+-----+--+----+---+-----+~~ 2561 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2562 +--+---+-----+--+----+---+-----+~~ 2563 2564 addresses: 0 ... 2565 2566 2567File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2568 25694.3 Assembler Internal Sections 2570=============================== 2571 2572These sections are meant only for the internal use of ‘as’. They have 2573no meaning at run-time. You do not really need to know about these 2574sections for most purposes; but they can be mentioned in ‘as’ warning 2575messages, so it might be helpful to have an idea of their meanings to 2576‘as’. These sections are used to permit the value of every expression 2577in your assembly language program to be a section-relative address. 2578 2579ASSEMBLER-INTERNAL-LOGIC-ERROR! 2580 An internal assembler logic error has been found. This means there 2581 is a bug in the assembler. 2582 2583expr section 2584 The assembler stores complex expressions internally as combinations 2585 of symbols. When it needs to represent an expression as a symbol, 2586 it puts it in the expr section. 2587 2588 2589File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2590 25914.4 Sub-Sections 2592================ 2593 2594Assembled bytes conventionally fall into two sections: text and data. 2595You may have separate groups of data in named sections that you want to 2596end up near to each other in the object file, even though they are not 2597contiguous in the assembler source. ‘as’ allows you to use 2598“subsections” for this purpose. Within each section, there can be 2599numbered subsections with values from 0 to 8192. Objects assembled into 2600the same subsection go into the object file together with other objects 2601in the same subsection. For example, a compiler might want to store 2602constants in the text section, but might not want to have them 2603interspersed with the program being assembled. In this case, the 2604compiler could issue a ‘.text 0’ before each section of code being 2605output, and a ‘.text 1’ before each group of constants being output. 2606 2607 Subsections are optional. If you do not use subsections, everything 2608goes in subsection number zero. 2609 2610 Each subsection is zero-padded up to a multiple of four bytes. 2611(Subsections may be padded a different amount on different flavors of 2612‘as’.) 2613 2614 Subsections appear in your object file in numeric order, lowest 2615numbered to highest. (All this to be compatible with other people’s 2616assemblers.) The object file contains no representation of subsections; 2617‘ld’ and other programs that manipulate object files see no trace of 2618them. They just see all your text subsections as a text section, and 2619all your data subsections as a data section. 2620 2621 To specify which subsection you want subsequent statements assembled 2622into, use a numeric argument to specify it, in a ‘.text EXPRESSION’ or a 2623‘.data EXPRESSION’ statement. When generating COFF output, you can also 2624use an extra subsection argument with arbitrary named sections: 2625‘.section NAME, EXPRESSION’. When generating ELF output, you can also 2626use the ‘.subsection’ directive (*note SubSection::) to specify a 2627subsection: ‘.subsection EXPRESSION’. EXPRESSION should be an absolute 2628expression (*note Expressions::). If you just say ‘.text’ then ‘.text 26290’ is assumed. Likewise ‘.data’ means ‘.data 0’. Assembly begins in 2630‘text 0’. For instance: 2631 .text 0 # The default subsection is text 0 anyway. 2632 .ascii "This lives in the first text subsection. *" 2633 .text 1 2634 .ascii "But this lives in the second text subsection." 2635 .data 0 2636 .ascii "This lives in the data section," 2637 .ascii "in the first data subsection." 2638 .text 0 2639 .ascii "This lives in the first text section," 2640 .ascii "immediately following the asterisk (*)." 2641 2642 Each section has a “location counter” incremented by one for every 2643byte assembled into that section. Because subsections are merely a 2644convenience restricted to ‘as’ there is no concept of a subsection 2645location counter. There is no way to directly manipulate a location 2646counter—but the ‘.align’ directive changes it, and any label definition 2647captures its current value. The location counter of the section where 2648statements are being assembled is said to be the “active” location 2649counter. 2650 2651 2652File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2653 26544.5 bss Section 2655=============== 2656 2657The bss section is used for local common variable storage. You may 2658allocate address space in the bss section, but you may not dictate data 2659to load into it before your program executes. When your program starts 2660running, all the contents of the bss section are zeroed bytes. 2661 2662 The ‘.lcomm’ pseudo-op defines a symbol in the bss section; see *note 2663‘.lcomm’: Lcomm. 2664 2665 The ‘.comm’ pseudo-op may be used to declare a common symbol, which 2666is another form of uninitialized symbol; see *note ‘.comm’: Comm. 2667 2668 When assembling for a target which supports multiple sections, such 2669as ELF or COFF, you may switch into the ‘.bss’ section and define 2670symbols as usual; see *note ‘.section’: Section. You may only assemble 2671zero values into the section. Typically the section will only contain 2672symbol definitions and ‘.skip’ directives (*note ‘.skip’: Skip.). 2673 2674 2675File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2676 26775 Symbols 2678********* 2679 2680Symbols are a central concept: the programmer uses symbols to name 2681things, the linker uses symbols to link, and the debugger uses symbols 2682to debug. 2683 2684 _Warning:_ ‘as’ does not place symbols in the object file in the 2685 same order they were declared. This may break some debuggers. 2686 2687* Menu: 2688 2689* Labels:: Labels 2690* Setting Symbols:: Giving Symbols Other Values 2691* Symbol Names:: Symbol Names 2692* Dot:: The Special Dot Symbol 2693* Symbol Attributes:: Symbol Attributes 2694 2695 2696File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2697 26985.1 Labels 2699========== 2700 2701A “label” is written as a symbol immediately followed by a colon ‘:’. 2702The symbol then represents the current value of the active location 2703counter, and is, for example, a suitable instruction operand. You are 2704warned if you use the same symbol to represent two different locations: 2705the first definition overrides any other definitions. 2706 2707 On the HPPA, the usual form for a label need not be immediately 2708followed by a colon, but instead must start in column zero. Only one 2709label may be defined on a single line. To work around this, the HPPA 2710version of ‘as’ also provides a special directive ‘.label’ for defining 2711labels more flexibly. 2712 2713 2714File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2715 27165.2 Giving Symbols Other Values 2717=============================== 2718 2719A symbol can be given an arbitrary value by writing a symbol, followed 2720by an equals sign ‘=’, followed by an expression (*note Expressions::). 2721This is equivalent to using the ‘.set’ directive. *Note ‘.set’: Set. 2722In the same way, using a double equals sign ‘=’‘=’ here represents an 2723equivalent of the ‘.eqv’ directive. *Note ‘.eqv’: Eqv. 2724 2725 Blackfin does not support symbol assignment with ‘=’. 2726 2727 2728File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2729 27305.3 Symbol Names 2731================ 2732 2733Symbol names begin with a letter or with one of ‘._’. On most machines, 2734you can also use ‘$’ in symbol names; exceptions are noted in *note 2735Machine Dependencies::. That character may be followed by any string of 2736digits, letters, dollar signs (unless otherwise noted for a particular 2737target machine), and underscores. These restrictions do not apply when 2738quoting symbol names by ‘"’, which is permitted for most targets. 2739Escaping characters in quoted symbol names with ‘\’ generally extends 2740only to ‘\’ itself and ‘"’, at the time of writing. 2741 2742 Case of letters is significant: ‘foo’ is a different symbol name than 2743‘Foo’. 2744 2745 Symbol names do not start with a digit. An exception to this rule is 2746made for Local Labels. See below. 2747 2748 Multibyte characters are supported, but note that the setting of the 2749‘multibyte-handling’ option might prevent their use. To generate a 2750symbol name containing multibyte characters enclose it within double 2751quotes and use escape codes. cf *Note Strings::. Generating a 2752multibyte symbol name from a label is not currently supported. 2753 2754 Since multibyte symbol names are unusual, and could possibly be used 2755maliciously, ‘as’ provides a command line option 2756(‘--multibyte-handling=warn-sym-only’) which can be used to generate a 2757warning message whenever a symbol name containing multibyte characters 2758is defined. 2759 2760 Each symbol has exactly one name. Each name in an assembly language 2761program refers to exactly one symbol. You may use that symbol name any 2762number of times in a program. 2763 2764Local Symbol Names 2765------------------ 2766 2767A local symbol is any symbol beginning with certain local label 2768prefixes. By default, the local label prefix is ‘.L’ for ELF systems or 2769‘L’ for traditional a.out systems, but each target may have its own set 2770of local label prefixes. On the HPPA local symbols begin with ‘L$’. 2771 2772 Local symbols are defined and used within the assembler, but they are 2773normally not saved in object files. Thus, they are not visible when 2774debugging. You may use the ‘-L’ option (*note Include Local Symbols: 2775L.) to retain the local symbols in the object files. 2776 2777Local Labels 2778------------ 2779 2780Local labels are different from local symbols. Local labels help 2781compilers and programmers use names temporarily. They create symbols 2782which are guaranteed to be unique over the entire scope of the input 2783source code and which can be referred to by a simple notation. To 2784define a local label, write a label of the form ‘N:’ (where N represents 2785any non-negative integer). To refer to the most recent previous 2786definition of that label write ‘Nb’, using the same number as when you 2787defined the label. To refer to the next definition of a local label, 2788write ‘Nf’. The ‘b’ stands for “backwards” and the ‘f’ stands for 2789“forwards”. 2790 2791 There is no restriction on how you can use these labels, and you can 2792reuse them too. So that it is possible to repeatedly define the same 2793local label (using the same number ‘N’), although you can only refer to 2794the most recently defined local label of that number (for a backwards 2795reference) or the next definition of a specific local label for a 2796forward reference. It is also worth noting that the first 10 local 2797labels (‘0:’...‘9:’) are implemented in a slightly more efficient manner 2798than the others. 2799 2800 Here is an example: 2801 2802 1: branch 1f 2803 2: branch 1b 2804 1: branch 2f 2805 2: branch 1b 2806 2807 Which is the equivalent of: 2808 2809 label_1: branch label_3 2810 label_2: branch label_1 2811 label_3: branch label_4 2812 label_4: branch label_3 2813 2814 Local label names are only a notational device. They are immediately 2815transformed into more conventional symbol names before the assembler 2816uses them. The symbol names are stored in the symbol table, appear in 2817error messages, and are optionally emitted to the object file. The 2818names are constructed using these parts: 2819 2820‘_local label prefix_’ 2821 All local symbols begin with the system-specific local label 2822 prefix. Normally both ‘as’ and ‘ld’ forget symbols that start with 2823 the local label prefix. These labels are used for symbols you are 2824 never intended to see. If you use the ‘-L’ option then ‘as’ 2825 retains these symbols in the object file. If you also instruct 2826 ‘ld’ to retain these symbols, you may use them in debugging. 2827 2828‘NUMBER’ 2829 This is the number that was used in the local label definition. So 2830 if the label is written ‘55:’ then the number is ‘55’. 2831 2832‘C-B’ 2833 This unusual character is included so you do not accidentally 2834 invent a symbol of the same name. The character has ASCII value of 2835 ‘\002’ (control-B). 2836 2837‘_ordinal number_’ 2838 This is a serial number to keep the labels distinct. The first 2839 definition of ‘0:’ gets the number ‘1’. The 15th definition of 2840 ‘0:’ gets the number ‘15’, and so on. Likewise the first 2841 definition of ‘1:’ gets the number ‘1’ and its 15th definition gets 2842 ‘15’ as well. 2843 2844 So for example, the first ‘1:’ may be named ‘.L1C-B1’, and the 44th 2845‘3:’ may be named ‘.L3C-B44’. 2846 2847Dollar Local Labels 2848------------------- 2849 2850On some targets ‘as’ also supports an even more local form of local 2851labels called dollar labels. These labels go out of scope (i.e., they 2852become undefined) as soon as a non-local label is defined. Thus they 2853remain valid for only a small region of the input source code. Normal 2854local labels, by contrast, remain in scope for the entire file, or until 2855they are redefined by another occurrence of the same local label. 2856 2857 Dollar labels are defined in exactly the same way as ordinary local 2858labels, except that they have a dollar sign suffix to their numeric 2859value, e.g., ‘55$:’. 2860 2861 They can also be distinguished from ordinary local labels by their 2862transformed names which use ASCII character ‘\001’ (control-A) as the 2863magic character to distinguish them from ordinary labels. For example, 2864the fifth definition of ‘6$’ may be named ‘.L6‘C-A’5’. 2865 2866 2867File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2868 28695.4 The Special Dot Symbol 2870========================== 2871 2872The special symbol ‘.’ refers to the current address that ‘as’ is 2873assembling into. Thus, the expression ‘melvin: .long .’ defines 2874‘melvin’ to contain its own address. Assigning a value to ‘.’ is 2875treated the same as a ‘.org’ directive. Thus, the expression ‘.=.+4’ is 2876the same as saying ‘.space 4’. 2877 2878 2879File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2880 28815.5 Symbol Attributes 2882===================== 2883 2884Every symbol has, as well as its name, the attributes “Value” and 2885“Type”. Depending on output format, symbols can also have auxiliary 2886attributes. 2887 2888 If you use a symbol without defining it, ‘as’ assumes zero for all 2889these attributes, and probably won’t warn you. This makes the symbol an 2890externally defined symbol, which is generally what you would want. 2891 2892* Menu: 2893 2894* Symbol Value:: Value 2895* Symbol Type:: Type 2896* a.out Symbols:: Symbol Attributes: ‘a.out’ 2897* COFF Symbols:: Symbol Attributes for COFF 2898* SOM Symbols:: Symbol Attributes for SOM 2899 2900 2901File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2902 29035.5.1 Value 2904----------- 2905 2906The value of a symbol is (usually) 32 bits. For a symbol which labels a 2907location in the text, data, bss or absolute sections the value is the 2908number of addresses from the start of that section to the label. 2909Naturally for text, data and bss sections the value of a symbol changes 2910as ‘ld’ changes section base addresses during linking. Absolute 2911symbols’ values do not change during linking: that is why they are 2912called absolute. 2913 2914 The value of an undefined symbol is treated in a special way. If it 2915is 0 then the symbol is not defined in this assembler source file, and 2916‘ld’ tries to determine its value from other files linked into the same 2917program. You make this kind of symbol simply by mentioning a symbol 2918name without defining it. A non-zero value represents a ‘.comm’ common 2919declaration. The value is how much common storage to reserve, in bytes 2920(addresses). The symbol refers to the first address of the allocated 2921storage. 2922 2923 2924File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2925 29265.5.2 Type 2927---------- 2928 2929The type attribute of a symbol contains relocation (section) 2930information, any flag settings indicating that a symbol is external, and 2931(optionally), other information for linkers and debuggers. The exact 2932format depends on the object-code output format in use. 2933 2934 2935File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2936 29375.5.3 Symbol Attributes: ‘a.out’ 2938-------------------------------- 2939 2940* Menu: 2941 2942* Symbol Desc:: Descriptor 2943* Symbol Other:: Other 2944 2945 2946File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2947 29485.5.3.1 Descriptor 2949.................. 2950 2951This is an arbitrary 16-bit value. You may establish a symbol’s 2952descriptor value by using a ‘.desc’ statement (*note ‘.desc’: Desc.). A 2953descriptor value means nothing to ‘as’. 2954 2955 2956File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2957 29585.5.3.2 Other 2959............. 2960 2961This is an arbitrary 8-bit value. It means nothing to ‘as’. 2962 2963 2964File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2965 29665.5.4 Symbol Attributes for COFF 2967-------------------------------- 2968 2969The COFF format supports a multitude of auxiliary symbol attributes; 2970like the primary symbol attributes, they are set between ‘.def’ and 2971‘.endef’ directives. 2972 29735.5.4.1 Primary Attributes 2974.......................... 2975 2976The symbol name is set with ‘.def’; the value and type, respectively, 2977with ‘.val’ and ‘.type’. 2978 29795.5.4.2 Auxiliary Attributes 2980............................ 2981 2982The ‘as’ directives ‘.dim’, ‘.line’, ‘.scl’, ‘.size’, ‘.tag’, and 2983‘.weak’ can generate auxiliary symbol table information for COFF. 2984 2985 2986File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2987 29885.5.5 Symbol Attributes for SOM 2989------------------------------- 2990 2991The SOM format for the HPPA supports a multitude of symbol attributes 2992set with the ‘.EXPORT’ and ‘.IMPORT’ directives. 2993 2994 The attributes are described in ‘HP9000 Series 800 Assembly Language 2995Reference Manual’ (HP 92432-90001) under the ‘IMPORT’ and ‘EXPORT’ 2996assembler directive documentation. 2997 2998 2999File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 3000 30016 Expressions 3002************* 3003 3004An “expression” specifies an address or numeric value. Whitespace may 3005precede and/or follow an expression. 3006 3007 The result of an expression must be an absolute number, or else an 3008offset into a particular section. If an expression is not absolute, and 3009there is not enough information when ‘as’ sees the expression to know 3010its section, a second pass over the source program might be necessary to 3011interpret the expression—but the second pass is currently not 3012implemented. ‘as’ aborts with an error message in this situation. 3013 3014* Menu: 3015 3016* Empty Exprs:: Empty Expressions 3017* Integer Exprs:: Integer Expressions 3018 3019 3020File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 3021 30226.1 Empty Expressions 3023===================== 3024 3025An empty expression has no value: it is just whitespace or null. 3026Wherever an absolute expression is required, you may omit the 3027expression, and ‘as’ assumes a value of (absolute) 0. This is 3028compatible with other assemblers. 3029 3030 3031File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 3032 30336.2 Integer Expressions 3034======================= 3035 3036An “integer expression” is one or more _arguments_ delimited by 3037_operators_. 3038 3039* Menu: 3040 3041* Arguments:: Arguments 3042* Operators:: Operators 3043* Prefix Ops:: Prefix Operators 3044* Infix Ops:: Infix Operators 3045 3046 3047File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 3048 30496.2.1 Arguments 3050--------------- 3051 3052“Arguments” are symbols, numbers or subexpressions. In other contexts 3053arguments are sometimes called “arithmetic operands”. In this manual, 3054to avoid confusing them with the “instruction operands” of the machine 3055language, we use the term “argument” to refer to parts of expressions 3056only, reserving the word “operand” to refer only to machine instruction 3057operands. 3058 3059 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 3060text, data, bss, absolute, or undefined. NNN is a signed, 2’s 3061complement 32 bit integer. 3062 3063 Numbers are usually integers. 3064 3065 A number can be a flonum or bignum. In this case, you are warned 3066that only the low order 32 bits are used, and ‘as’ pretends these 32 3067bits are an integer. You may write integer-manipulating instructions 3068that act on exotic constants, compatible with other assemblers. 3069 3070 Subexpressions are a left parenthesis ‘(’ followed by an integer 3071expression, followed by a right parenthesis ‘)’; or a prefix operator 3072followed by an argument. 3073 3074 3075File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 3076 30776.2.2 Operators 3078--------------- 3079 3080“Operators” are arithmetic functions, like ‘+’ or ‘%’. Prefix operators 3081are followed by an argument. Infix operators appear between their 3082arguments. Operators may be preceded and/or followed by whitespace. 3083 3084 3085File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 3086 30876.2.3 Prefix Operator 3088--------------------- 3089 3090‘as’ has the following “prefix operators”. They each take one argument, 3091which must be absolute. 3092 3093‘-’ 3094 “Negation”. Two’s complement negation. 3095‘~’ 3096 “Complementation”. Bitwise not. 3097 3098 3099File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 3100 31016.2.4 Infix Operators 3102--------------------- 3103 3104“Infix operators” take two arguments, one on either side. Operators 3105have precedence, but operations with equal precedence are performed left 3106to right. Apart from ‘+’ or ‘-’, both arguments must be absolute, and 3107the result is absolute. 3108 3109 1. Highest Precedence 3110 3111 ‘*’ 3112 “Multiplication”. 3113 3114 ‘/’ 3115 “Division”. Truncation is the same as the C operator ‘/’ 3116 3117 ‘%’ 3118 “Remainder”. 3119 3120 ‘<<’ 3121 “Shift Left”. Same as the C operator ‘<<’. 3122 3123 ‘>>’ 3124 “Shift Right”. Same as the C operator ‘>>’. 3125 3126 2. Intermediate precedence 3127 3128 ‘|’ 3129 3130 “Bitwise Inclusive Or”. 3131 3132 ‘&’ 3133 “Bitwise And”. 3134 3135 ‘^’ 3136 “Bitwise Exclusive Or”. 3137 3138 ‘!’ 3139 “Bitwise Or Not”. 3140 3141 3. Low Precedence 3142 3143 ‘+’ 3144 “Addition”. If either argument is absolute, the result has 3145 the section of the other argument. You may not add together 3146 arguments from different sections. 3147 3148 ‘-’ 3149 “Subtraction”. If the right argument is absolute, the result 3150 has the section of the left argument. If both arguments are 3151 in the same section, the result is absolute. You may not 3152 subtract arguments from different sections. 3153 3154 ‘==’ 3155 “Is Equal To” 3156 ‘<>’ 3157 ‘!=’ 3158 “Is Not Equal To” 3159 ‘<’ 3160 “Is Less Than” 3161 ‘>’ 3162 “Is Greater Than” 3163 ‘>=’ 3164 “Is Greater Than Or Equal To” 3165 ‘<=’ 3166 “Is Less Than Or Equal To” 3167 3168 The comparison operators can be used as infix operators. A 3169 true result has a value of -1 whereas a false result has a 3170 value of 0. Note, these operators perform signed comparisons. 3171 3172 4. Lowest Precedence 3173 3174 ‘&&’ 3175 “Logical And”. 3176 3177 ‘||’ 3178 “Logical Or”. 3179 3180 These two logical operations can be used to combine the 3181 results of sub expressions. Note, unlike the comparison 3182 operators a true result returns a value of 1 but a false 3183 result does still return 0. Also note that the logical or 3184 operator has a slightly lower precedence than logical and. 3185 3186 In short, it’s only meaningful to add or subtract the _offsets_ in an 3187address; you can only have a defined section in one of the two 3188arguments. 3189 3190 3191File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 3192 31937 Assembler Directives 3194********************** 3195 3196All assembler directives have names that begin with a period (‘.’). The 3197names are case insensitive for most targets, and usually written in 3198lower case. 3199 3200 This chapter discusses directives that are available regardless of 3201the target machine configuration for the GNU assembler. Some machine 3202configurations provide additional directives. *Note Machine 3203Dependencies::. 3204 3205* Menu: 3206 3207* Abort:: ‘.abort’ 3208* ABORT (COFF):: ‘.ABORT’ 3209 3210* Align:: ‘.align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]’ 3211* Altmacro:: ‘.altmacro’ 3212* Ascii:: ‘.ascii "STRING"’... 3213* Asciz:: ‘.asciz "STRING"’... 3214* Attach_to_group:: ‘.attach_to_group NAME’ 3215* Balign:: ‘.balign [ABS-EXPR[, ABS-EXPR]]’ 3216* Bss:: ‘.bss SUBSECTION’ 3217* Bundle directives:: ‘.bundle_align_mode ABS-EXPR’, etc 3218* Byte:: ‘.byte EXPRESSIONS’ 3219* CFI directives:: ‘.cfi_startproc [simple]’, ‘.cfi_endproc’, etc. 3220* Comm:: ‘.comm SYMBOL , LENGTH ’ 3221* Data:: ‘.data SUBSECTION’ 3222* Dc:: ‘.dc[SIZE] EXPRESSIONS’ 3223* Dcb:: ‘.dcb[SIZE] NUMBER [,FILL]’ 3224* Ds:: ‘.ds[SIZE] NUMBER [,FILL]’ 3225* Def:: ‘.def NAME’ 3226* Desc:: ‘.desc SYMBOL, ABS-EXPRESSION’ 3227* Dim:: ‘.dim’ 3228 3229* Double:: ‘.double FLONUMS’ 3230* Eject:: ‘.eject’ 3231* Else:: ‘.else’ 3232* Elseif:: ‘.elseif’ 3233* End:: ‘.end’ 3234* Endef:: ‘.endef’ 3235 3236* Endfunc:: ‘.endfunc’ 3237* Endif:: ‘.endif’ 3238* Equ:: ‘.equ SYMBOL, EXPRESSION’ 3239* Equiv:: ‘.equiv SYMBOL, EXPRESSION’ 3240* Eqv:: ‘.eqv SYMBOL, EXPRESSION’ 3241* Err:: ‘.err’ 3242* Error:: ‘.error STRING’ 3243* Exitm:: ‘.exitm’ 3244* Extern:: ‘.extern’ 3245* Fail:: ‘.fail’ 3246* File:: ‘.file’ 3247* Fill:: ‘.fill REPEAT , SIZE , VALUE’ 3248* Float:: ‘.float FLONUMS’ 3249* Func:: ‘.func’ 3250* Global:: ‘.global SYMBOL’, ‘.globl SYMBOL’ 3251* Gnu_attribute:: ‘.gnu_attribute TAG,VALUE’ 3252* Hidden:: ‘.hidden NAMES’ 3253 3254* hword:: ‘.hword EXPRESSIONS’ 3255* Ident:: ‘.ident’ 3256* If:: ‘.if ABSOLUTE EXPRESSION’ 3257* Incbin:: ‘.incbin "FILE"[,SKIP[,COUNT]]’ 3258* Include:: ‘.include "FILE"’ 3259* Int:: ‘.int EXPRESSIONS’ 3260* Internal:: ‘.internal NAMES’ 3261 3262* Irp:: ‘.irp SYMBOL,VALUES’... 3263* Irpc:: ‘.irpc SYMBOL,VALUES’... 3264* Lcomm:: ‘.lcomm SYMBOL , LENGTH’ 3265* Lflags:: ‘.lflags’ 3266* Line:: ‘.line LINE-NUMBER’ 3267 3268* Linkonce:: ‘.linkonce [TYPE]’ 3269* List:: ‘.list’ 3270* Ln:: ‘.ln LINE-NUMBER’ 3271* Loc:: ‘.loc FILENO LINENO’ 3272* Loc_mark_labels:: ‘.loc_mark_labels ENABLE’ 3273* Local:: ‘.local NAMES’ 3274 3275* Long:: ‘.long EXPRESSIONS’ 3276 3277* Macro:: ‘.macro NAME ARGS’... 3278* MRI:: ‘.mri VAL’ 3279* Noaltmacro:: ‘.noaltmacro’ 3280* Nolist:: ‘.nolist’ 3281* Nop:: ‘.nop’ 3282* Nops:: ‘.nops SIZE[, CONTROL]’ 3283* Octa:: ‘.octa BIGNUMS’ 3284* Offset:: ‘.offset LOC’ 3285* Org:: ‘.org NEW-LC, FILL’ 3286* P2align:: ‘.p2align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]’ 3287* PopSection:: ‘.popsection’ 3288* Previous:: ‘.previous’ 3289 3290* Print:: ‘.print STRING’ 3291* Protected:: ‘.protected NAMES’ 3292 3293* Psize:: ‘.psize LINES, COLUMNS’ 3294* Purgem:: ‘.purgem NAME’ 3295* PushSection:: ‘.pushsection NAME’ 3296 3297* Quad:: ‘.quad BIGNUMS’ 3298* Reloc:: ‘.reloc OFFSET, RELOC_NAME[, EXPRESSION]’ 3299* Rept:: ‘.rept COUNT’ 3300* Sbttl:: ‘.sbttl "SUBHEADING"’ 3301* Scl:: ‘.scl CLASS’ 3302* Section:: ‘.section NAME[, FLAGS]’ 3303 3304* Set:: ‘.set SYMBOL, EXPRESSION’ 3305* Short:: ‘.short EXPRESSIONS’ 3306* Single:: ‘.single FLONUMS’ 3307* Size:: ‘.size [NAME , EXPRESSION]’ 3308* Skip:: ‘.skip SIZE [,FILL]’ 3309 3310* Sleb128:: ‘.sleb128 EXPRESSIONS’ 3311* Space:: ‘.space SIZE [,FILL]’ 3312* Stab:: ‘.stabd, .stabn, .stabs’ 3313 3314* String:: ‘.string "STR"’, ‘.string8 "STR"’, ‘.string16 "STR"’, ‘.string32 "STR"’, ‘.string64 "STR"’ 3315* Struct:: ‘.struct EXPRESSION’ 3316* SubSection:: ‘.subsection’ 3317* Symver:: ‘.symver NAME,NAME2@NODENAME[,VISIBILITY]’ 3318 3319* Tag:: ‘.tag STRUCTNAME’ 3320 3321* Text:: ‘.text SUBSECTION’ 3322* Title:: ‘.title "HEADING"’ 3323* Tls_common:: ‘.tls_common SYMBOL, LENGTH[, ALIGNMENT]’ 3324* Type:: ‘.type <INT | NAME , TYPE DESCRIPTION>’ 3325 3326* Uleb128:: ‘.uleb128 EXPRESSIONS’ 3327* Val:: ‘.val ADDR’ 3328 3329* Version:: ‘.version "STRING"’ 3330* VTableEntry:: ‘.vtable_entry TABLE, OFFSET’ 3331* VTableInherit:: ‘.vtable_inherit CHILD, PARENT’ 3332 3333* Warning:: ‘.warning STRING’ 3334* Weak:: ‘.weak NAMES’ 3335* Weakref:: ‘.weakref ALIAS, SYMBOL’ 3336* Word:: ‘.word EXPRESSIONS’ 3337* Zero:: ‘.zero SIZE’ 3338* 2byte:: ‘.2byte EXPRESSIONS’ 3339* 4byte:: ‘.4byte EXPRESSIONS’ 3340* 8byte:: ‘.8byte EXPRESSIONS’ 3341* Deprecated:: Deprecated Directives 3342 3343 3344File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3345 33467.1 ‘.abort’ 3347============ 3348 3349This directive stops the assembly immediately. It is for compatibility 3350with other assemblers. The original idea was that the assembly language 3351source would be piped into the assembler. If the sender of the source 3352quit, it could use this directive tells ‘as’ to quit also. One day 3353‘.abort’ will not be supported. 3354 3355 3356File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3357 33587.2 ‘.ABORT’ (COFF) 3359=================== 3360 3361When producing COFF output, ‘as’ accepts this directive as a synonym for 3362‘.abort’. 3363 3364 3365File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3366 33677.3 ‘.align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]’ 3368=============================================== 3369 3370Pad the location counter (in the current subsection) to a particular 3371storage boundary. The first expression (which must be absolute) is the 3372alignment required, as described below. If this expression is omitted 3373then a default value of 0 is used, effectively disabling alignment 3374requirements. 3375 3376 The second expression (also absolute) gives the fill value to be 3377stored in the padding bytes. It (and the comma) may be omitted. If it 3378is omitted, the padding bytes are normally zero. However, on most 3379systems, if the section is marked as containing code and the fill value 3380is omitted, the space is filled with no-op instructions. 3381 3382 The third expression is also absolute, and is also optional. If it 3383is present, it is the maximum number of bytes that should be skipped by 3384this alignment directive. If doing the alignment would require skipping 3385more bytes than the specified maximum, then the alignment is not done at 3386all. You can omit the fill value (the second argument) entirely by 3387simply using two commas after the required alignment; this can be useful 3388if you want the alignment to be filled with no-op instructions when 3389appropriate. 3390 3391 The way the required alignment is specified varies from system to 3392system. For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, s390, 3393sparc, tic4x and xtensa, the first expression is the alignment request 3394in bytes. For example ‘.align 8’ advances the location counter until it 3395is a multiple of 8. If the location counter is already a multiple of 8, 3396no change is needed. For the tic54x, the first expression is the 3397alignment request in words. 3398 3399 For other systems, including ppc, i386 using a.out format, arm and 3400strongarm, it is the number of low-order zero bits the location counter 3401must have after advancement. For example ‘.align 3’ advances the 3402location counter until it is a multiple of 8. If the location counter 3403is already a multiple of 8, no change is needed. 3404 3405 This inconsistency is due to the different behaviors of the various 3406native assemblers for these systems which GAS must emulate. GAS also 3407provides ‘.balign’ and ‘.p2align’ directives, described later, which 3408have a consistent behavior across all architectures (but are specific to 3409GAS). 3410 3411 3412File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3413 34147.4 ‘.altmacro’ 3415=============== 3416 3417Enable alternate macro mode, enabling: 3418 3419‘LOCAL NAME [ , ... ]’ 3420 One additional directive, ‘LOCAL’, is available. It is used to 3421 generate a string replacement for each of the NAME arguments, and 3422 replace any instances of NAME in each macro expansion. The 3423 replacement string is unique in the assembly, and different for 3424 each separate macro expansion. ‘LOCAL’ allows you to write macros 3425 that define symbols, without fear of conflict between separate 3426 macro expansions. 3427 3428‘String delimiters’ 3429 You can write strings delimited in these other ways besides 3430 ‘"STRING"’: 3431 3432 ‘'STRING'’ 3433 You can delimit strings with single-quote characters. 3434 3435 ‘<STRING>’ 3436 You can delimit strings with matching angle brackets. 3437 3438‘single-character string escape’ 3439 To include any single character literally in a string (even if the 3440 character would otherwise have some special meaning), you can 3441 prefix the character with ‘!’ (an exclamation mark). For example, 3442 you can write ‘<4.3 !> 5.4!!>’ to get the literal text ‘4.3 > 3443 5.4!’. 3444 3445‘Expression results as strings’ 3446 You can write ‘%EXPR’ to evaluate the expression EXPR and use the 3447 result as a string. 3448 3449 3450File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3451 34527.5 ‘.ascii "STRING"’... 3453======================== 3454 3455‘.ascii’ expects zero or more string literals (*note Strings::) 3456separated by commas. It assembles each string (with no automatic 3457trailing zero byte) into consecutive addresses. 3458 3459 3460File: as.info, Node: Asciz, Next: Attach_to_group, Prev: Ascii, Up: Pseudo Ops 3461 34627.6 ‘.asciz "STRING"’... 3463======================== 3464 3465‘.asciz’ is just like ‘.ascii’, but each string is followed by a zero 3466byte. The “z” in ‘.asciz’ stands for “zero”. Note that multiple string 3467arguments not separated by commas will be concatenated together and only 3468one final zero byte will be stored. 3469 3470 3471File: as.info, Node: Attach_to_group, Next: Balign, Prev: Asciz, Up: Pseudo Ops 3472 34737.7 ‘.attach_to_group NAME’ 3474=========================== 3475 3476Attaches the current section to the named group. This is like declaring 3477the section with the ‘G’ attribute, but can be done after the section 3478has been created. Note if the group section does not exist at the point 3479that this directive is used then it will be created. 3480 3481 3482File: as.info, Node: Balign, Next: Bss, Prev: Attach_to_group, Up: Pseudo Ops 3483 34847.8 ‘.balign[wl] [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]’ 3485==================================================== 3486 3487Pad the location counter (in the current subsection) to a particular 3488storage boundary. The first expression (which must be absolute) is the 3489alignment request in bytes. For example ‘.balign 8’ advances the 3490location counter until it is a multiple of 8. If the location counter 3491is already a multiple of 8, no change is needed. If the expression is 3492omitted then a default value of 0 is used, effectively disabling 3493alignment requirements. 3494 3495 The second expression (also absolute) gives the fill value to be 3496stored in the padding bytes. It (and the comma) may be omitted. If it 3497is omitted, the padding bytes are normally zero. However, on most 3498systems, if the section is marked as containing code and the fill value 3499is omitted, the space is filled with no-op instructions. 3500 3501 The third expression is also absolute, and is also optional. If it 3502is present, it is the maximum number of bytes that should be skipped by 3503this alignment directive. If doing the alignment would require skipping 3504more bytes than the specified maximum, then the alignment is not done at 3505all. You can omit the fill value (the second argument) entirely by 3506simply using two commas after the required alignment; this can be useful 3507if you want the alignment to be filled with no-op instructions when 3508appropriate. 3509 3510 The ‘.balignw’ and ‘.balignl’ directives are variants of the 3511‘.balign’ directive. The ‘.balignw’ directive treats the fill pattern 3512as a two byte word value. The ‘.balignl’ directives treats the fill 3513pattern as a four byte longword value. For example, ‘.balignw 4,0x368d’ 3514will align to a multiple of 4. If it skips two bytes, they will be 3515filled in with the value 0x368d (the exact placement of the bytes 3516depends upon the endianness of the processor). If it skips 1 or 3 3517bytes, the fill value is undefined. 3518 3519 3520File: as.info, Node: Bss, Next: Bundle directives, Prev: Balign, Up: Pseudo Ops 3521 35227.9 ‘.bss SUBSECTION’ 3523===================== 3524 3525‘.bss’ tells ‘as’ to assemble the following statements onto the end of 3526the bss section. For most ELF based targets an optional SUBSECTION 3527expression (which must evaluate to a positive integer) can be provided. 3528In this case the statements are appended to the end of the indicated bss 3529subsection. 3530 3531 3532File: as.info, Node: Bundle directives, Next: Byte, Prev: Bss, Up: Pseudo Ops 3533 35347.10 Bundle directives 3535====================== 3536 35377.10.1 ‘.bundle_align_mode ABS-EXPR’ 3538------------------------------------ 3539 3540‘.bundle_align_mode’ enables or disables “aligned instruction bundle” 3541mode. In this mode, sequences of adjacent instructions are grouped into 3542fixed-sized “bundles”. If the argument is zero, this mode is disabled 3543(which is the default state). If the argument it not zero, it gives the 3544size of an instruction bundle as a power of two (as for the ‘.p2align’ 3545directive, *note P2align::). 3546 3547 For some targets, it’s an ABI requirement that no instruction may 3548span a certain aligned boundary. A “bundle” is simply a sequence of 3549instructions that starts on an aligned boundary. For example, if 3550ABS-EXPR is ‘5’ then the bundle size is 32, so each aligned chunk of 32 3551bytes is a bundle. When aligned instruction bundle mode is in effect, 3552no single instruction may span a boundary between bundles. If an 3553instruction would start too close to the end of a bundle for the length 3554of that particular instruction to fit within the bundle, then the space 3555at the end of that bundle is filled with no-op instructions so the 3556instruction starts in the next bundle. As a corollary, it’s an error if 3557any single instruction’s encoding is longer than the bundle size. 3558 35597.10.2 ‘.bundle_lock’ and ‘.bundle_unlock’ 3560------------------------------------------ 3561 3562The ‘.bundle_lock’ and directive ‘.bundle_unlock’ directives allow 3563explicit control over instruction bundle padding. These directives are 3564only valid when ‘.bundle_align_mode’ has been used to enable aligned 3565instruction bundle mode. It’s an error if they appear when 3566‘.bundle_align_mode’ has not been used at all, or when the last 3567directive was ‘.bundle_align_mode 0’. 3568 3569 For some targets, it’s an ABI requirement that certain instructions 3570may appear only as part of specified permissible sequences of multiple 3571instructions, all within the same bundle. A pair of ‘.bundle_lock’ and 3572‘.bundle_unlock’ directives define a “bundle-locked” instruction 3573sequence. For purposes of aligned instruction bundle mode, a sequence 3574starting with ‘.bundle_lock’ and ending with ‘.bundle_unlock’ is treated 3575as a single instruction. That is, the entire sequence must fit into a 3576single bundle and may not span a bundle boundary. If necessary, no-op 3577instructions will be inserted before the first instruction of the 3578sequence so that the whole sequence starts on an aligned bundle 3579boundary. It’s an error if the sequence is longer than the bundle size. 3580 3581 For convenience when using ‘.bundle_lock’ and ‘.bundle_unlock’ inside 3582assembler macros (*note Macro::), bundle-locked sequences may be nested. 3583That is, a second ‘.bundle_lock’ directive before the next 3584‘.bundle_unlock’ directive has no effect except that it must be matched 3585by another closing ‘.bundle_unlock’ so that there is the same number of 3586‘.bundle_lock’ and ‘.bundle_unlock’ directives. 3587 3588 3589File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops 3590 35917.11 ‘.byte EXPRESSIONS’ 3592======================== 3593 3594‘.byte’ expects zero or more expressions, separated by commas. Each 3595expression is assembled into the next byte. 3596 3597 Note - this directive is not intended for encoding instructions, and 3598it will not trigger effects like DWARF line number generation. Instead 3599some targets support special directives for encoding arbitrary binary 3600sequences as instructions such as ‘.insn’ or ‘.inst’. 3601 3602 3603File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3604 36057.12 CFI directives 3606=================== 3607 36087.12.1 ‘.cfi_sections SECTION_LIST’ 3609----------------------------------- 3610 3611‘.cfi_sections’ may be used to specify whether CFI directives should 3612emit ‘.eh_frame’ section, ‘.debug_frame’ section and/or ‘.sframe’ 3613section. If SECTION_LIST contains ‘.eh_frame’, ‘.eh_frame’ is emitted, 3614if SECTION_LIST contains ‘.debug_frame’, ‘.debug_frame’ is emitted, and 3615finally, if SECTION_LIST contains ‘.sframe’, ‘.sframe’ is emitted. To 3616emit multiple sections, specify them together in a list. For example, 3617to emit both ‘.eh_frame’ and ‘.debug_frame’, use ‘.eh_frame, 3618.debug_frame’. The default if this directive is not used is 3619‘.cfi_sections .eh_frame’. 3620 3621 On targets that support compact unwinding tables these can be 3622generated by specifying ‘.eh_frame_entry’ instead of ‘.eh_frame’. 3623 3624 Some targets may support an additional name, such as ‘.c6xabi.exidx’ 3625which is used by the target. 3626 3627 The ‘.cfi_sections’ directive can be repeated, with the same or 3628different arguments, provided that CFI generation has not yet started. 3629Once CFI generation has started however the section list is fixed and 3630any attempts to redefine it will result in an error. 3631 36327.12.2 ‘.cfi_startproc [simple]’ 3633-------------------------------- 3634 3635‘.cfi_startproc’ is used at the beginning of each function that should 3636have an entry in ‘.eh_frame’. It initializes some internal data 3637structures. Don’t forget to close the function by ‘.cfi_endproc’. 3638 3639 Unless ‘.cfi_startproc’ is used along with parameter ‘simple’ it also 3640emits some architecture dependent initial CFI instructions. 3641 36427.12.3 ‘.cfi_endproc’ 3643--------------------- 3644 3645‘.cfi_endproc’ is used at the end of a function where it closes its 3646unwind entry previously opened by ‘.cfi_startproc’, and emits it to 3647‘.eh_frame’. 3648 36497.12.4 ‘.cfi_personality ENCODING [, EXP]’ 3650------------------------------------------ 3651 3652‘.cfi_personality’ defines personality routine and its encoding. 3653ENCODING must be a constant determining how the personality should be 3654encoded. If it is 255 (‘DW_EH_PE_omit’), second argument is not 3655present, otherwise second argument should be a constant or a symbol 3656name. When using indirect encodings, the symbol provided should be the 3657location where personality can be loaded from, not the personality 3658routine itself. The default after ‘.cfi_startproc’ is ‘.cfi_personality 36590xff’, no personality routine. 3660 36617.12.5 ‘.cfi_personality_id ID’ 3662------------------------------- 3663 3664‘cfi_personality_id’ defines a personality routine by its index as 3665defined in a compact unwinding format. Only valid when generating 3666compact EH frames (i.e. with ‘.cfi_sections eh_frame_entry’. 3667 36687.12.6 ‘.cfi_fde_data [OPCODE1 [, ...]]’ 3669---------------------------------------- 3670 3671‘cfi_fde_data’ is used to describe the compact unwind opcodes to be used 3672for the current function. These are emitted inline in the 3673‘.eh_frame_entry’ section if small enough and there is no LSDA, or in 3674the ‘.gnu.extab’ section otherwise. Only valid when generating compact 3675EH frames (i.e. with ‘.cfi_sections eh_frame_entry’. 3676 36777.12.7 ‘.cfi_lsda ENCODING [, EXP]’ 3678----------------------------------- 3679 3680‘.cfi_lsda’ defines LSDA and its encoding. ENCODING must be a constant 3681determining how the LSDA should be encoded. If it is 255 3682(‘DW_EH_PE_omit’), the second argument is not present, otherwise the 3683second argument should be a constant or a symbol name. The default 3684after ‘.cfi_startproc’ is ‘.cfi_lsda 0xff’, meaning that no LSDA is 3685present. 3686 36877.12.8 ‘.cfi_inline_lsda’ [ALIGN] 3688--------------------------------- 3689 3690‘.cfi_inline_lsda’ marks the start of a LSDA data section and switches 3691to the corresponding ‘.gnu.extab’ section. Must be preceded by a CFI 3692block containing a ‘.cfi_lsda’ directive. Only valid when generating 3693compact EH frames (i.e. with ‘.cfi_sections eh_frame_entry’. 3694 3695 The table header and unwinding opcodes will be generated at this 3696point, so that they are immediately followed by the LSDA data. The 3697symbol referenced by the ‘.cfi_lsda’ directive should still be defined 3698in case a fallback FDE based encoding is used. The LSDA data is 3699terminated by a section directive. 3700 3701 The optional ALIGN argument specifies the alignment required. The 3702alignment is specified as a power of two, as with the ‘.p2align’ 3703directive. 3704 37057.12.9 ‘.cfi_def_cfa REGISTER, OFFSET’ 3706-------------------------------------- 3707 3708‘.cfi_def_cfa’ defines a rule for computing CFA as: take address from 3709REGISTER and add OFFSET to it. 3710 37117.12.10 ‘.cfi_def_cfa_register REGISTER’ 3712---------------------------------------- 3713 3714‘.cfi_def_cfa_register’ modifies a rule for computing CFA. From now on 3715REGISTER will be used instead of the old one. Offset remains the same. 3716 37177.12.11 ‘.cfi_def_cfa_offset OFFSET’ 3718------------------------------------ 3719 3720‘.cfi_def_cfa_offset’ modifies a rule for computing CFA. Register 3721remains the same, but OFFSET is new. Note that it is the absolute 3722offset that will be added to a defined register to compute CFA address. 3723 37247.12.12 ‘.cfi_adjust_cfa_offset OFFSET’ 3725--------------------------------------- 3726 3727Same as ‘.cfi_def_cfa_offset’ but OFFSET is a relative value that is 3728added/subtracted from the previous offset. 3729 37307.12.13 ‘.cfi_offset REGISTER, OFFSET’ 3731-------------------------------------- 3732 3733Previous value of REGISTER is saved at offset OFFSET from CFA. 3734 37357.12.14 ‘.cfi_val_offset REGISTER, OFFSET’ 3736------------------------------------------ 3737 3738Previous value of REGISTER is CFA + OFFSET. 3739 37407.12.15 ‘.cfi_rel_offset REGISTER, OFFSET’ 3741------------------------------------------ 3742 3743Previous value of REGISTER is saved at offset OFFSET from the current 3744CFA register. This is transformed to ‘.cfi_offset’ using the known 3745displacement of the CFA register from the CFA. This is often easier to 3746use, because the number will match the code it’s annotating. 3747 37487.12.16 ‘.cfi_register REGISTER1, REGISTER2’ 3749-------------------------------------------- 3750 3751Previous value of REGISTER1 is saved in register REGISTER2. 3752 37537.12.17 ‘.cfi_restore REGISTER’ 3754------------------------------- 3755 3756‘.cfi_restore’ says that the rule for REGISTER is now the same as it was 3757at the beginning of the function, after all initial instruction added by 3758‘.cfi_startproc’ were executed. 3759 37607.12.18 ‘.cfi_undefined REGISTER’ 3761--------------------------------- 3762 3763From now on the previous value of REGISTER can’t be restored anymore. 3764 37657.12.19 ‘.cfi_same_value REGISTER’ 3766---------------------------------- 3767 3768Current value of REGISTER is the same like in the previous frame, i.e. 3769no restoration needed. 3770 37717.12.20 ‘.cfi_remember_state’ and ‘.cfi_restore_state’ 3772------------------------------------------------------ 3773 3774‘.cfi_remember_state’ pushes the set of rules for every register onto an 3775implicit stack, while ‘.cfi_restore_state’ pops them off the stack and 3776places them in the current row. This is useful for situations where you 3777have multiple ‘.cfi_*’ directives that need to be undone due to the 3778control flow of the program. For example, we could have something like 3779this (assuming the CFA is the value of ‘rbp’): 3780 3781 je label 3782 popq %rbx 3783 .cfi_restore %rbx 3784 popq %r12 3785 .cfi_restore %r12 3786 popq %rbp 3787 .cfi_restore %rbp 3788 .cfi_def_cfa %rsp, 8 3789 ret 3790 label: 3791 /* Do something else */ 3792 3793 Here, we want the ‘.cfi’ directives to affect only the rows 3794corresponding to the instructions before ‘label’. This means we’d have 3795to add multiple ‘.cfi’ directives after ‘label’ to recreate the original 3796save locations of the registers, as well as setting the CFA back to the 3797value of ‘rbp’. This would be clumsy, and result in a larger binary 3798size. Instead, we can write: 3799 3800 je label 3801 popq %rbx 3802 .cfi_remember_state 3803 .cfi_restore %rbx 3804 popq %r12 3805 .cfi_restore %r12 3806 popq %rbp 3807 .cfi_restore %rbp 3808 .cfi_def_cfa %rsp, 8 3809 ret 3810 label: 3811 .cfi_restore_state 3812 /* Do something else */ 3813 3814 That way, the rules for the instructions after ‘label’ will be the 3815same as before the first ‘.cfi_restore’ without having to use multiple 3816‘.cfi’ directives. 3817 38187.12.21 ‘.cfi_return_column REGISTER’ 3819------------------------------------- 3820 3821Change return column REGISTER, i.e. the return address is either 3822directly in REGISTER or can be accessed by rules for REGISTER. 3823 38247.12.22 ‘.cfi_signal_frame’ 3825--------------------------- 3826 3827Mark current function as signal trampoline. 3828 38297.12.23 ‘.cfi_window_save’ 3830-------------------------- 3831 3832SPARC register window has been saved. 3833 38347.12.24 ‘.cfi_escape’ EXPRESSION[, ...] 3835--------------------------------------- 3836 3837Allows the user to add arbitrary bytes to the unwind info. One might 3838use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS 3839does not yet support. 3840 38417.12.25 ‘.cfi_val_encoded_addr REGISTER, ENCODING, LABEL’ 3842--------------------------------------------------------- 3843 3844The current value of REGISTER is LABEL. The value of LABEL will be 3845encoded in the output file according to ENCODING; see the description of 3846‘.cfi_personality’ for details on this encoding. 3847 3848 The usefulness of equating a register to a fixed label is probably 3849limited to the return address register. Here, it can be useful to mark 3850a code segment that has only one return address which is reached by a 3851direct branch and no copy of the return address exists in memory or 3852another register. 3853 3854 3855File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3856 38577.13 ‘.comm SYMBOL , LENGTH ’ 3858============================= 3859 3860‘.comm’ declares a common symbol named SYMBOL. When linking, a common 3861symbol in one object file may be merged with a defined or common symbol 3862of the same name in another object file. If ‘ld’ does not see a 3863definition for the symbol–just one or more common symbols–then it will 3864allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3865absolute expression. If ‘ld’ sees multiple common symbols with the same 3866name, and they do not all have the same size, it will allocate space 3867using the largest size. 3868 3869 When using ELF or (as a GNU extension) PE, the ‘.comm’ directive 3870takes an optional third argument. This is the desired alignment of the 3871symbol, specified for ELF as a byte boundary (for example, an alignment 3872of 16 means that the least significant 4 bits of the address should be 3873zero), and for PE as a power of two (for example, an alignment of 5 3874means aligned to a 32-byte boundary). The alignment must be an absolute 3875expression, and it must be a power of two. If ‘ld’ allocates 3876uninitialized memory for the common symbol, it will use the alignment 3877when placing the symbol. If no alignment is specified, ‘as’ will set 3878the alignment to the largest power of two less than or equal to the size 3879of the symbol, up to a maximum of 16 on ELF, or the default section 3880alignment of 4 on PE(1). 3881 3882 The syntax for ‘.comm’ differs slightly on the HPPA. The syntax is 3883‘SYMBOL .comm, LENGTH’; SYMBOL is optional. 3884 3885 ---------- Footnotes ---------- 3886 3887 (1) This is not the same as the executable image file alignment 3888controlled by ‘ld’’s ‘--section-alignment’ option; image file sections 3889in PE are aligned to multiples of 4096, which is far too large an 3890alignment for ordinary variables. It is rather the default alignment 3891for (non-debug) sections within object (‘*.o’) files, which are less 3892strictly aligned. 3893 3894 3895File: as.info, Node: Data, Next: Dc, Prev: Comm, Up: Pseudo Ops 3896 38977.14 ‘.data SUBSECTION’ 3898======================= 3899 3900‘.data’ tells ‘as’ to assemble the following statements onto the end of 3901the data subsection numbered SUBSECTION (which is an absolute 3902expression). If SUBSECTION is omitted, it defaults to zero. 3903 3904 3905File: as.info, Node: Dc, Next: Dcb, Prev: Data, Up: Pseudo Ops 3906 39077.15 ‘.dc[SIZE] EXPRESSIONS’ 3908============================ 3909 3910The ‘.dc’ directive expects zero or more EXPRESSIONS separated by 3911commas. These expressions are evaluated and their values inserted into 3912the current section. The size of the emitted value depends upon the 3913suffix to the ‘.dc’ directive: 3914 3915‘‘.a’’ 3916 Emits N-bit values, where N is the size of an address on the target 3917 system. 3918‘‘.b’’ 3919 Emits 8-bit values. 3920‘‘.d’’ 3921 Emits double precision floating-point values. 3922‘‘.l’’ 3923 Emits 32-bit values. 3924‘‘.s’’ 3925 Emits single precision floating-point values. 3926‘‘.w’’ 3927 Emits 16-bit values. Note - this is true even on targets where the 3928 ‘.word’ directive would emit 32-bit values. 3929‘‘.x’’ 3930 Emits long double precision floating-point values. 3931 3932 If no suffix is used then ‘.w’ is assumed. 3933 3934 The byte ordering is target dependent, as is the size and format of 3935floating point values. 3936 3937 Note - these directives are not intended for encoding instructions, 3938and they will not trigger effects like DWARF line number generation. 3939Instead some targets support special directives for encoding arbitrary 3940binary sequences as instructions such as ‘.insn’ or ‘.inst’. 3941 3942 3943File: as.info, Node: Dcb, Next: Ds, Prev: Dc, Up: Pseudo Ops 3944 39457.16 ‘.dcb[SIZE] NUMBER [,FILL]’ 3946================================ 3947 3948This directive emits NUMBER copies of FILL, each of SIZE bytes. Both 3949NUMBER and FILL are absolute expressions. If the comma and FILL are 3950omitted, FILL is assumed to be zero. The SIZE suffix, if present, must 3951be one of: 3952 3953‘‘.b’’ 3954 Emits single byte values. 3955‘‘.d’’ 3956 Emits double-precision floating point values. 3957‘‘.l’’ 3958 Emits 4-byte values. 3959‘‘.s’’ 3960 Emits single-precision floating point values. 3961‘‘.w’’ 3962 Emits 2-byte values. 3963‘‘.x’’ 3964 Emits long double-precision floating point values. 3965 3966 If the SIZE suffix is omitted then ‘.w’ is assumed. 3967 3968 The byte ordering is target dependent, as is the size and format of 3969floating point values. 3970 3971 3972File: as.info, Node: Ds, Next: Def, Prev: Dcb, Up: Pseudo Ops 3973 39747.17 ‘.ds[SIZE] NUMBER [,FILL]’ 3975=============================== 3976 3977This directive emits NUMBER copies of FILL, each of SIZE bytes. Both 3978NUMBER and FILL are absolute expressions. If the comma and FILL are 3979omitted, FILL is assumed to be zero. The SIZE suffix, if present, must 3980be one of: 3981 3982‘‘.b’’ 3983 Emits single byte values. 3984‘‘.d’’ 3985 Emits 8-byte values. 3986‘‘.l’’ 3987 Emits 4-byte values. 3988‘‘.p’’ 3989 Emits values with size matching packed-decimal floating-point ones. 3990‘‘.s’’ 3991 Emits 4-byte values. 3992‘‘.w’’ 3993 Emits 2-byte values. 3994‘‘.x’’ 3995 Emits values with size matching long double precision 3996 floating-point ones. 3997 3998 Note - unlike the ‘.dcb’ directive the ‘.d’, ‘.s’ and ‘.x’ suffixes 3999do not indicate that floating-point values are to be inserted. 4000 4001 If the SIZE suffix is omitted then ‘.w’ is assumed. 4002 4003 The byte ordering is target dependent. 4004 4005 4006File: as.info, Node: Def, Next: Desc, Prev: Ds, Up: Pseudo Ops 4007 40087.18 ‘.def NAME’ 4009================ 4010 4011Begin defining debugging information for a symbol NAME; the definition 4012extends until the ‘.endef’ directive is encountered. 4013 4014 4015File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 4016 40177.19 ‘.desc SYMBOL, ABS-EXPRESSION’ 4018=================================== 4019 4020This directive sets the descriptor of the symbol (*note Symbol 4021Attributes::) to the low 16 bits of an absolute expression. 4022 4023 The ‘.desc’ directive is not available when ‘as’ is configured for 4024COFF output; it is only for ‘a.out’ or ‘b.out’ object format. For the 4025sake of compatibility, ‘as’ accepts it, but produces no output, when 4026configured for COFF. 4027 4028 4029File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 4030 40317.20 ‘.dim’ 4032=========== 4033 4034This directive is generated by compilers to include auxiliary debugging 4035information in the symbol table. It is only permitted inside 4036‘.def’/‘.endef’ pairs. 4037 4038 4039File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 4040 40417.21 ‘.double FLONUMS’ 4042====================== 4043 4044‘.double’ expects zero or more flonums, separated by commas. It 4045assembles floating point numbers. The exact kind of floating point 4046numbers emitted depends on how ‘as’ is configured. *Note Machine 4047Dependencies::. 4048 4049 4050File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 4051 40527.22 ‘.eject’ 4053============= 4054 4055Force a page break at this point, when generating assembly listings. 4056 4057 4058File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 4059 40607.23 ‘.else’ 4061============ 4062 4063‘.else’ is part of the ‘as’ support for conditional assembly; see *note 4064‘.if’: If. It marks the beginning of a section of code to be assembled 4065if the condition for the preceding ‘.if’ was false. 4066 4067 4068File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 4069 40707.24 ‘.elseif’ 4071============== 4072 4073‘.elseif’ is part of the ‘as’ support for conditional assembly; see 4074*note ‘.if’: If. It is shorthand for beginning a new ‘.if’ block that 4075would otherwise fill the entire ‘.else’ section. 4076 4077 4078File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 4079 40807.25 ‘.end’ 4081=========== 4082 4083‘.end’ marks the end of the assembly file. ‘as’ does not process 4084anything in the file past the ‘.end’ directive. 4085 4086 4087File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 4088 40897.26 ‘.endef’ 4090============= 4091 4092This directive flags the end of a symbol definition begun with ‘.def’. 4093 4094 4095File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 4096 40977.27 ‘.endfunc’ 4098=============== 4099 4100‘.endfunc’ marks the end of a function specified with ‘.func’. 4101 4102 4103File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 4104 41057.28 ‘.endif’ 4106============= 4107 4108‘.endif’ is part of the ‘as’ support for conditional assembly; it marks 4109the end of a block of code that is only assembled conditionally. *Note 4110‘.if’: If. 4111 4112 4113File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 4114 41157.29 ‘.equ SYMBOL, EXPRESSION’ 4116============================== 4117 4118This directive sets the value of SYMBOL to EXPRESSION. It is synonymous 4119with ‘.set’; see *note ‘.set’: Set. 4120 4121 The syntax for ‘equ’ on the HPPA is ‘SYMBOL .equ EXPRESSION’. 4122 4123 The syntax for ‘equ’ on the Z80 is ‘SYMBOL equ EXPRESSION’. On the 4124Z80 it is an error if SYMBOL is already defined, but the symbol is not 4125protected from later redefinition. Compare *note Equiv::. 4126 4127 4128File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 4129 41307.30 ‘.equiv SYMBOL, EXPRESSION’ 4131================================ 4132 4133The ‘.equiv’ directive is like ‘.equ’ and ‘.set’, except that the 4134assembler will signal an error if SYMBOL is already defined. Note a 4135symbol which has been referenced but not actually defined is considered 4136to be undefined. 4137 4138 Except for the contents of the error message, this is roughly 4139equivalent to 4140 .ifdef SYM 4141 .err 4142 .endif 4143 .equ SYM,VAL 4144 plus it protects the symbol from later redefinition. 4145 4146 4147File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 4148 41497.31 ‘.eqv SYMBOL, EXPRESSION’ 4150============================== 4151 4152The ‘.eqv’ directive is like ‘.equiv’, but no attempt is made to 4153evaluate the expression or any part of it immediately. Instead each 4154time the resulting symbol is used in an expression, a snapshot of its 4155current value is taken. 4156 4157 4158File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 4159 41607.32 ‘.err’ 4161=========== 4162 4163If ‘as’ assembles a ‘.err’ directive, it will print an error message 4164and, unless the ‘-Z’ option was used, it will not generate an object 4165file. This can be used to signal an error in conditionally compiled 4166code. 4167 4168 4169File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 4170 41717.33 ‘.error "STRING"’ 4172====================== 4173 4174Similarly to ‘.err’, this directive emits an error, but you can specify 4175a string that will be emitted as the error message. If you don’t 4176specify the message, it defaults to ‘".error directive invoked in source 4177file"’. *Note Error and Warning Messages: Errors. 4178 4179 .error "This code has not been assembled and tested." 4180 4181 4182File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 4183 41847.34 ‘.exitm’ 4185============= 4186 4187Exit early from the current macro definition. *Note Macro::. 4188 4189 4190File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 4191 41927.35 ‘.extern’ 4193============== 4194 4195‘.extern’ is accepted in the source program—for compatibility with other 4196assemblers—but it is ignored. ‘as’ treats all undefined symbols as 4197external. 4198 4199 4200File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 4201 42027.36 ‘.fail EXPRESSION’ 4203======================= 4204 4205Generates an error or a warning. If the value of the EXPRESSION is 500 4206or more, ‘as’ will print a warning message. If the value is less than 4207500, ‘as’ will print an error message. The message will include the 4208value of EXPRESSION. This can occasionally be useful inside complex 4209nested macros or conditional assembly. 4210 4211 4212File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 4213 42147.37 ‘.file’ 4215============ 4216 4217There are two different versions of the ‘.file’ directive. Targets that 4218support DWARF2 line number information use the DWARF2 version of 4219‘.file’. Other targets use the default version. 4220 4221Default Version 4222--------------- 4223 4224This version of the ‘.file’ directive tells ‘as’ that we are about to 4225start a new logical file. The syntax is: 4226 4227 .file STRING 4228 4229 STRING is the new file name. In general, the filename is recognized 4230whether or not it is surrounded by quotes ‘"’; but if you wish to 4231specify an empty file name, you must give the quotes–‘""’. This 4232statement may go away in future: it is only recognized to be compatible 4233with old ‘as’ programs. 4234 4235DWARF2 Version 4236-------------- 4237 4238When emitting DWARF2 line number information, ‘.file’ assigns filenames 4239to the ‘.debug_line’ file name table. The syntax is: 4240 4241 .file FILENO FILENAME 4242 4243 The FILENO operand should be a unique positive integer to use as the 4244index of the entry in the table. The FILENAME operand is a C string 4245literal enclosed in double quotes. The FILENAME can include directory 4246elements. If it does, then the directory will be added to the directory 4247table and the basename will be added to the file table. 4248 4249 The detail of filename indices is exposed to the user because the 4250filename table is shared with the ‘.debug_info’ section of the DWARF2 4251debugging information, and thus the user must know the exact indices 4252that table entries will have. 4253 4254 If DWARF5 support has been enabled via the ‘-gdwarf-5’ option then an 4255extended version of ‘.file’ is also allowed: 4256 4257 .file FILENO [DIRNAME] FILENAME [md5 VALUE] 4258 4259 With this version a separate directory name is allowed, although if 4260this is used then FILENAME should not contain any directory component, 4261except for FILENO equal to 0: in this case, DIRNAME is expected to be 4262the current directory and FILENAME the currently processed file, and the 4263latter need not be located in the former. In addition an MD5 hash value 4264of the contents of FILENAME can be provided. This will be stored in the 4265the file table as well, and can be used by tools reading the debug 4266information to verify that the contents of the source file match the 4267contents of the compiled file. 4268 4269 4270File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 4271 42727.38 ‘.fill REPEAT , SIZE , VALUE’ 4273================================== 4274 4275REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 4276copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 4277more, but if it is more than 8, then it is deemed to have the value 8, 4278compatible with other people’s assemblers. The contents of each REPEAT 4279bytes is taken from an 8-byte number. The highest order 4 bytes are 4280zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 4281an integer on the computer ‘as’ is assembling for. Each SIZE bytes in a 4282repetition is taken from the lowest order SIZE bytes of this number. 4283Again, this bizarre behavior is compatible with other people’s 4284assemblers. 4285 4286 SIZE and VALUE are optional. If the second comma and VALUE are 4287absent, VALUE is assumed zero. If the first comma and following tokens 4288are absent, SIZE is assumed to be 1. 4289 4290 4291File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 4292 42937.39 ‘.float FLONUMS’ 4294===================== 4295 4296This directive assembles zero or more flonums, separated by commas. It 4297has the same effect as ‘.single’. The exact kind of floating point 4298numbers emitted depends on how ‘as’ is configured. *Note Machine 4299Dependencies::. 4300 4301 4302File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 4303 43047.40 ‘.func NAME[,LABEL]’ 4305========================= 4306 4307‘.func’ emits debugging information to denote function NAME, and is 4308ignored unless the file is assembled with debugging enabled. Only 4309‘--gstabs[+]’ is currently supported. LABEL is the entry point of the 4310function and if omitted NAME prepended with the ‘leading char’ is used. 4311‘leading char’ is usually ‘_’ or nothing, depending on the target. All 4312functions are currently defined to have ‘void’ return type. The 4313function must be terminated with ‘.endfunc’. 4314 4315 4316File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 4317 43187.41 ‘.global SYMBOL’, ‘.globl SYMBOL’ 4319====================================== 4320 4321‘.global’ makes the symbol visible to ‘ld’. If you define SYMBOL in 4322your partial program, its value is made available to other partial 4323programs that are linked with it. Otherwise, SYMBOL takes its 4324attributes from a symbol of the same name from another file linked into 4325the same program. 4326 4327 Both spellings (‘.globl’ and ‘.global’) are accepted, for 4328compatibility with other assemblers. 4329 4330 On the HPPA, ‘.global’ is not always enough to make it accessible to 4331other partial programs. You may need the HPPA-only ‘.EXPORT’ directive 4332as well. *Note HPPA Assembler Directives: HPPA Directives. 4333 4334 4335File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 4336 43377.42 ‘.gnu_attribute TAG,VALUE’ 4338=============================== 4339 4340Record a GNU object attribute for this file. *Note Object Attributes::. 4341 4342 4343File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 4344 43457.43 ‘.hidden NAMES’ 4346==================== 4347 4348This is one of the ELF visibility directives. The other two are 4349‘.internal’ (*note ‘.internal’: Internal.) and ‘.protected’ (*note 4350‘.protected’: Protected.). 4351 4352 This directive overrides the named symbols default visibility (which 4353is set by their binding: local, global or weak). The directive sets the 4354visibility to ‘hidden’ which means that the symbols are not visible to 4355other components. Such symbols are always considered to be ‘protected’ 4356as well. 4357 4358 4359File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 4360 43617.44 ‘.hword EXPRESSIONS’ 4362========================= 4363 4364This expects zero or more EXPRESSIONS, and emits a 16 bit number for 4365each. 4366 4367 This directive is a synonym for ‘.short’; depending on the target 4368architecture, it may also be a synonym for ‘.word’. 4369 4370 4371File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 4372 43737.45 ‘.ident’ 4374============= 4375 4376This directive is used by some assemblers to place tags in object files. 4377The behavior of this directive varies depending on the target. When 4378using the a.out object file format, ‘as’ simply accepts the directive 4379for source-file compatibility with existing assemblers, but does not 4380emit anything for it. When using COFF, comments are emitted to the 4381‘.comment’ or ‘.rdata’ section, depending on the target. When using 4382ELF, comments are emitted to the ‘.comment’ section. 4383 4384 4385File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 4386 43877.46 ‘.if ABSOLUTE EXPRESSION’ 4388============================== 4389 4390‘.if’ marks the beginning of a section of code which is only considered 4391part of the source program being assembled if the argument (which must 4392be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 4393section of code must be marked by ‘.endif’ (*note ‘.endif’: Endif.); 4394optionally, you may include code for the alternative condition, flagged 4395by ‘.else’ (*note ‘.else’: Else.). If you have several conditions to 4396check, ‘.elseif’ may be used to avoid nesting blocks if/else within each 4397subsequent ‘.else’ block. 4398 4399 The following variants of ‘.if’ are also supported: 4400‘.ifdef SYMBOL’ 4401 Assembles the following section of code if the specified SYMBOL has 4402 been defined. Note a symbol which has been referenced but not yet 4403 defined is considered to be undefined. 4404 4405‘.ifb TEXT’ 4406 Assembles the following section of code if the operand is blank 4407 (empty). 4408 4409‘.ifc STRING1,STRING2’ 4410 Assembles the following section of code if the two strings are the 4411 same. The strings may be optionally quoted with single quotes. If 4412 they are not quoted, the first string stops at the first comma, and 4413 the second string stops at the end of the line. Strings which 4414 contain whitespace should be quoted. The string comparison is case 4415 sensitive. 4416 4417‘.ifeq ABSOLUTE EXPRESSION’ 4418 Assembles the following section of code if the argument is zero. 4419 4420‘.ifeqs STRING1,STRING2’ 4421 Another form of ‘.ifc’. The strings must be quoted using double 4422 quotes. 4423 4424‘.ifge ABSOLUTE EXPRESSION’ 4425 Assembles the following section of code if the argument is greater 4426 than or equal to zero. 4427 4428‘.ifgt ABSOLUTE EXPRESSION’ 4429 Assembles the following section of code if the argument is greater 4430 than zero. 4431 4432‘.ifle ABSOLUTE EXPRESSION’ 4433 Assembles the following section of code if the argument is less 4434 than or equal to zero. 4435 4436‘.iflt ABSOLUTE EXPRESSION’ 4437 Assembles the following section of code if the argument is less 4438 than zero. 4439 4440‘.ifnb TEXT’ 4441 Like ‘.ifb’, but the sense of the test is reversed: this assembles 4442 the following section of code if the operand is non-blank 4443 (non-empty). 4444 4445‘.ifnc STRING1,STRING2.’ 4446 Like ‘.ifc’, but the sense of the test is reversed: this assembles 4447 the following section of code if the two strings are not the same. 4448 4449‘.ifndef SYMBOL’ 4450‘.ifnotdef SYMBOL’ 4451 Assembles the following section of code if the specified SYMBOL has 4452 not been defined. Both spelling variants are equivalent. Note a 4453 symbol which has been referenced but not yet defined is considered 4454 to be undefined. 4455 4456‘.ifne ABSOLUTE EXPRESSION’ 4457 Assembles the following section of code if the argument is not 4458 equal to zero (in other words, this is equivalent to ‘.if’). 4459 4460‘.ifnes STRING1,STRING2’ 4461 Like ‘.ifeqs’, but the sense of the test is reversed: this 4462 assembles the following section of code if the two strings are not 4463 the same. 4464 4465 4466File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 4467 44687.47 ‘.incbin "FILE"[,SKIP[,COUNT]]’ 4469==================================== 4470 4471The ‘incbin’ directive includes FILE verbatim at the current location. 4472You can control the search paths used with the ‘-I’ command-line option 4473(*note Command-Line Options: Invoking.). Quotation marks are required 4474around FILE. 4475 4476 The SKIP argument skips a number of bytes from the start of the FILE. 4477The COUNT argument indicates the maximum number of bytes to read. Note 4478that the data is not aligned in any way, so it is the user’s 4479responsibility to make sure that proper alignment is provided both 4480before and after the ‘incbin’ directive. 4481 4482 4483File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 4484 44857.48 ‘.include "FILE"’ 4486====================== 4487 4488This directive provides a way to include supporting files at specified 4489points in your source program. The code from FILE is assembled as if it 4490followed the point of the ‘.include’; when the end of the included file 4491is reached, assembly of the original file continues. You can control 4492the search paths used with the ‘-I’ command-line option (*note 4493Command-Line Options: Invoking.). Quotation marks are required around 4494FILE. 4495 4496 4497File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 4498 44997.49 ‘.int EXPRESSIONS’ 4500======================= 4501 4502Expect zero or more EXPRESSIONS, of any section, separated by commas. 4503For each expression, emit a number that, at run time, is the value of 4504that expression. The byte order and bit size of the number depends on 4505what kind of target the assembly is for. 4506 4507 Note - this directive is not intended for encoding instructions, and 4508it will not trigger effects like DWARF line number generation. Instead 4509some targets support special directives for encoding arbitrary binary 4510sequences as instructions such as eg ‘.insn’ or ‘.inst’. 4511 4512 4513File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 4514 45157.50 ‘.internal NAMES’ 4516====================== 4517 4518This is one of the ELF visibility directives. The other two are 4519‘.hidden’ (*note ‘.hidden’: Hidden.) and ‘.protected’ (*note 4520‘.protected’: Protected.). 4521 4522 This directive overrides the named symbols default visibility (which 4523is set by their binding: local, global or weak). The directive sets the 4524visibility to ‘internal’ which means that the symbols are considered to 4525be ‘hidden’ (i.e., not visible to other components), and that some 4526extra, processor specific processing must also be performed upon the 4527symbols as well. 4528 4529 4530File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 4531 45327.51 ‘.irp SYMBOL,VALUES’... 4533============================ 4534 4535Evaluate a sequence of statements assigning different values to SYMBOL. 4536The sequence of statements starts at the ‘.irp’ directive, and is 4537terminated by an ‘.endr’ directive. For each VALUE, SYMBOL is set to 4538VALUE, and the sequence of statements is assembled. If no VALUE is 4539listed, the sequence of statements is assembled once, with SYMBOL set to 4540the null string. To refer to SYMBOL within the sequence of statements, 4541use \SYMBOL. 4542 4543 For example, assembling 4544 4545 .irp param,1,2,3 4546 move d\param,sp@- 4547 .endr 4548 4549 is equivalent to assembling 4550 4551 move d1,sp@- 4552 move d2,sp@- 4553 move d3,sp@- 4554 4555 For some caveats with the spelling of SYMBOL, see also *note Macro::. 4556 4557 4558File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 4559 45607.52 ‘.irpc SYMBOL,VALUES’... 4561============================= 4562 4563Evaluate a sequence of statements assigning different values to SYMBOL. 4564The sequence of statements starts at the ‘.irpc’ directive, and is 4565terminated by an ‘.endr’ directive. For each character in VALUE, SYMBOL 4566is set to the character, and the sequence of statements is assembled. 4567If no VALUE is listed, the sequence of statements is assembled once, 4568with SYMBOL set to the null string. To refer to SYMBOL within the 4569sequence of statements, use \SYMBOL. 4570 4571 For example, assembling 4572 4573 .irpc param,123 4574 move d\param,sp@- 4575 .endr 4576 4577 is equivalent to assembling 4578 4579 move d1,sp@- 4580 move d2,sp@- 4581 move d3,sp@- 4582 4583 For some caveats with the spelling of SYMBOL, see also the discussion 4584at *Note Macro::. 4585 4586 4587File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4588 45897.53 ‘.lcomm SYMBOL , LENGTH’ 4590============================= 4591 4592Reserve LENGTH (an absolute expression) bytes for a local common denoted 4593by SYMBOL. The section and value of SYMBOL are those of the new local 4594common. The addresses are allocated in the bss section, so that at 4595run-time the bytes start off zeroed. SYMBOL is not declared global 4596(*note ‘.global’: Global.), so is normally not visible to ‘ld’. 4597 4598 Some targets permit a third argument to be used with ‘.lcomm’. This 4599argument specifies the desired alignment of the symbol in the bss 4600section. 4601 4602 The syntax for ‘.lcomm’ differs slightly on the HPPA. The syntax is 4603‘SYMBOL .lcomm, LENGTH’; SYMBOL is optional. 4604 4605 4606File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4607 46087.54 ‘.lflags’ 4609============== 4610 4611‘as’ accepts this directive, for compatibility with other assemblers, 4612but ignores it. 4613 4614 4615File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4616 46177.55 ‘.line LINE-NUMBER’ 4618======================== 4619 4620Change the logical line number. LINE-NUMBER must be an absolute 4621expression. The next line has that logical line number. Therefore any 4622other statements on the current line (after a statement separator 4623character) are reported as on logical line number LINE-NUMBER − 1. One 4624day ‘as’ will no longer support this directive: it is recognized only 4625for compatibility with existing assembler programs. 4626 4627 Even though this is a directive associated with the ‘a.out’ or 4628‘b.out’ object-code formats, ‘as’ still recognizes it when producing 4629COFF output, and treats ‘.line’ as though it were the COFF ‘.ln’ _if_ it 4630is found outside a ‘.def’/‘.endef’ pair. 4631 4632 Inside a ‘.def’, ‘.line’ is, instead, one of the directives used by 4633compilers to generate auxiliary symbol information for debugging. 4634 4635 4636File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4637 46387.56 ‘.linkonce [TYPE]’ 4639======================= 4640 4641Mark the current section so that the linker only includes a single copy 4642of it. This may be used to include the same section in several 4643different object files, but ensure that the linker will only include it 4644once in the final output file. The ‘.linkonce’ pseudo-op must be used 4645for each instance of the section. Duplicate sections are detected based 4646on the section name, so it should be unique. 4647 4648 This directive is only supported by a few object file formats; as of 4649this writing, the only object file format which supports it is the 4650Portable Executable format used on Windows NT. 4651 4652 The TYPE argument is optional. If specified, it must be one of the 4653following strings. For example: 4654 .linkonce same_size 4655 Not all types may be supported on all object file formats. 4656 4657‘discard’ 4658 Silently discard duplicate sections. This is the default. 4659 4660‘one_only’ 4661 Warn if there are duplicate sections, but still keep only one copy. 4662 4663‘same_size’ 4664 Warn if any of the duplicates have different sizes. 4665 4666‘same_contents’ 4667 Warn if any of the duplicates do not have exactly the same 4668 contents. 4669 4670 4671File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4672 46737.57 ‘.list’ 4674============ 4675 4676Control (in conjunction with the ‘.nolist’ directive) whether or not 4677assembly listings are generated. These two directives maintain an 4678internal counter (which is zero initially). ‘.list’ increments the 4679counter, and ‘.nolist’ decrements it. Assembly listings are generated 4680whenever the counter is greater than zero. 4681 4682 By default, listings are disabled. When you enable them (with the 4683‘-a’ command-line option; *note Command-Line Options: Invoking.), the 4684initial value of the listing counter is one. 4685 4686 4687File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4688 46897.58 ‘.ln LINE-NUMBER’ 4690====================== 4691 4692‘.ln’ is a synonym for ‘.line’. 4693 4694 4695File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4696 46977.59 ‘.loc FILENO LINENO [COLUMN] [OPTIONS]’ 4698============================================ 4699 4700When emitting DWARF2 line number information, the ‘.loc’ directive will 4701add a row to the ‘.debug_line’ line number matrix corresponding to the 4702immediately following assembly instruction. The FILENO, LINENO, and 4703optional COLUMN arguments will be applied to the ‘.debug_line’ state 4704machine before the row is added. It is an error for the input assembly 4705file to generate a non-empty ‘.debug_line’ and also use ‘loc’ 4706directives. 4707 4708 The OPTIONS are a sequence of the following tokens in any order: 4709 4710‘basic_block’ 4711 This option will set the ‘basic_block’ register in the 4712 ‘.debug_line’ state machine to ‘true’. 4713 4714‘prologue_end’ 4715 This option will set the ‘prologue_end’ register in the 4716 ‘.debug_line’ state machine to ‘true’. 4717 4718‘epilogue_begin’ 4719 This option will set the ‘epilogue_begin’ register in the 4720 ‘.debug_line’ state machine to ‘true’. 4721 4722‘is_stmt VALUE’ 4723 This option will set the ‘is_stmt’ register in the ‘.debug_line’ 4724 state machine to ‘value’, which must be either 0 or 1. 4725 4726‘isa VALUE’ 4727 This directive will set the ‘isa’ register in the ‘.debug_line’ 4728 state machine to VALUE, which must be an unsigned integer. 4729 4730‘discriminator VALUE’ 4731 This directive will set the ‘discriminator’ register in the 4732 ‘.debug_line’ state machine to VALUE, which must be an unsigned 4733 integer. 4734 4735‘view VALUE’ 4736 This option causes a row to be added to ‘.debug_line’ in reference 4737 to the current address (which might not be the same as that of the 4738 following assembly instruction), and to associate VALUE with the 4739 ‘view’ register in the ‘.debug_line’ state machine. If VALUE is a 4740 label, both the ‘view’ register and the label are set to the number 4741 of prior ‘.loc’ directives at the same program location. If VALUE 4742 is the literal ‘0’, the ‘view’ register is set to zero, and the 4743 assembler asserts that there aren’t any prior ‘.loc’ directives at 4744 the same program location. If VALUE is the literal ‘-0’, the 4745 assembler arrange for the ‘view’ register to be reset in this row, 4746 even if there are prior ‘.loc’ directives at the same program 4747 location. 4748 4749 4750File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4751 47527.60 ‘.loc_mark_labels ENABLE’ 4753============================== 4754 4755When emitting DWARF2 line number information, the ‘.loc_mark_labels’ 4756directive makes the assembler emit an entry to the ‘.debug_line’ line 4757number matrix with the ‘basic_block’ register in the state machine set 4758whenever a code label is seen. The ENABLE argument should be either 1 4759or 0, to enable or disable this function respectively. 4760 4761 4762File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4763 47647.61 ‘.local NAMES’ 4765=================== 4766 4767This directive, which is available for ELF targets, marks each symbol in 4768the comma-separated list of ‘names’ as a local symbol so that it will 4769not be externally visible. If the symbols do not already exist, they 4770will be created. 4771 4772 For targets where the ‘.lcomm’ directive (*note Lcomm::) does not 4773accept an alignment argument, which is the case for most ELF targets, 4774the ‘.local’ directive can be used in combination with ‘.comm’ (*note 4775Comm::) to define aligned local common data. 4776 4777 4778File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4779 47807.62 ‘.long EXPRESSIONS’ 4781======================== 4782 4783‘.long’ is the same as ‘.int’. *Note ‘.int’: Int. 4784 4785 4786File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4787 47887.63 ‘.macro’ 4789============= 4790 4791The commands ‘.macro’ and ‘.endm’ allow you to define macros that 4792generate assembly output. For example, this definition specifies a 4793macro ‘sum’ that puts a sequence of numbers into memory: 4794 4795 .macro sum from=0, to=5 4796 .long \from 4797 .if \to-\from 4798 sum "(\from+1)",\to 4799 .endif 4800 .endm 4801 4802With that definition, ‘SUM 0,5’ is equivalent to this assembly input: 4803 4804 .long 0 4805 .long 1 4806 .long 2 4807 .long 3 4808 .long 4 4809 .long 5 4810 4811‘.macro MACNAME’ 4812‘.macro MACNAME MACARGS ...’ 4813 Begin the definition of a macro called MACNAME. If your macro 4814 definition requires arguments, specify their names after the macro 4815 name, separated by commas or spaces. You can qualify the macro 4816 argument to indicate whether all invocations must specify a 4817 non-blank value (through ‘:‘req’’), or whether it takes all of the 4818 remaining arguments (through ‘:‘vararg’’). You can supply a 4819 default value for any macro argument by following the name with 4820 ‘=DEFLT’. You cannot define two macros with the same MACNAME 4821 unless it has been subject to the ‘.purgem’ directive (*note 4822 Purgem::) between the two definitions. For example, these are all 4823 valid ‘.macro’ statements: 4824 4825 ‘.macro comm’ 4826 Begin the definition of a macro called ‘comm’, which takes no 4827 arguments. 4828 4829 ‘.macro plus1 p, p1’ 4830 ‘.macro plus1 p p1’ 4831 Either statement begins the definition of a macro called 4832 ‘plus1’, which takes two arguments; within the macro 4833 definition, write ‘\p’ or ‘\p1’ to evaluate the arguments. 4834 4835 ‘.macro reserve_str p1=0 p2’ 4836 Begin the definition of a macro called ‘reserve_str’, with two 4837 arguments. The first argument has a default value, but not 4838 the second. After the definition is complete, you can call 4839 the macro either as ‘reserve_str A,B’ (with ‘\p1’ evaluating 4840 to A and ‘\p2’ evaluating to B), or as ‘reserve_str ,B’ (with 4841 ‘\p1’ evaluating as the default, in this case ‘0’, and ‘\p2’ 4842 evaluating to B). 4843 4844 ‘.macro m p1:req, p2=0, p3:vararg’ 4845 Begin the definition of a macro called ‘m’, with at least 4846 three arguments. The first argument must always have a value 4847 specified, but not the second, which instead has a default 4848 value. The third formal will get assigned all remaining 4849 arguments specified at invocation time. 4850 4851 When you call a macro, you can specify the argument values 4852 either by position, or by keyword. For example, ‘sum 9,17’ is 4853 equivalent to ‘sum to=17, from=9’. 4854 4855 Note that since each of the MACARGS can be an identifier exactly as 4856 any other one permitted by the target architecture, there may be 4857 occasional problems if the target hand-crafts special meanings to 4858 certain characters when they occur in a special position. For 4859 example, if the colon (‘:’) is generally permitted to be part of a 4860 symbol name, but the architecture specific code special-cases it 4861 when occurring as the final character of a symbol (to denote a 4862 label), then the macro parameter replacement code will have no way 4863 of knowing that and consider the whole construct (including the 4864 colon) an identifier, and check only this identifier for being the 4865 subject to parameter substitution. So for example this macro 4866 definition: 4867 4868 .macro label l 4869 \l: 4870 .endm 4871 4872 might not work as expected. Invoking ‘label foo’ might not create 4873 a label called ‘foo’ but instead just insert the text ‘\l:’ into 4874 the assembler source, probably generating an error about an 4875 unrecognised identifier. 4876 4877 Similarly problems might occur with the period character (‘.’) 4878 which is often allowed inside opcode names (and hence identifier 4879 names). So for example constructing a macro to build an opcode 4880 from a base name and a length specifier like this: 4881 4882 .macro opcode base length 4883 \base.\length 4884 .endm 4885 4886 and invoking it as ‘opcode store l’ will not create a ‘store.l’ 4887 instruction but instead generate some kind of error as the 4888 assembler tries to interpret the text ‘\base.\length’. 4889 4890 There are several possible ways around this problem: 4891 4892 ‘Insert white space’ 4893 If it is possible to use white space characters then this is 4894 the simplest solution. eg: 4895 4896 .macro label l 4897 \l : 4898 .endm 4899 4900 ‘Use ‘\()’’ 4901 The string ‘\()’ can be used to separate the end of a macro 4902 argument from the following text. eg: 4903 4904 .macro opcode base length 4905 \base\().\length 4906 .endm 4907 4908 ‘Use the alternate macro syntax mode’ 4909 In the alternative macro syntax mode the ampersand character 4910 (‘&’) can be used as a separator. eg: 4911 4912 .altmacro 4913 .macro label l 4914 l&: 4915 .endm 4916 4917 Note: this problem of correctly identifying string parameters to 4918 pseudo ops also applies to the identifiers used in ‘.irp’ (*note 4919 Irp::) and ‘.irpc’ (*note Irpc::) as well. 4920 4921 Another issue can occur with the actual arguments passed during 4922 macro invocation: Multiple arguments can be separated by blanks or 4923 commas. To have arguments actually contain blanks or commas (or 4924 potentially other non-alpha- numeric characters), individual 4925 arguments will need to be enclosed in either parentheses ‘()’, 4926 square brackets ‘[]’, or double quote ‘"’ characters. The latter 4927 may be the only viable option in certain situations, as only double 4928 quotes are actually stripped while establishing arguments. It may 4929 be important to be aware of two escaping models used when 4930 processing such quoted argument strings: For one two adjacent 4931 double quotes represent a single double quote in the resulting 4932 argument, going along the lines of the stripping of the enclosing 4933 quotes. But then double quotes can also be escaped by a backslash 4934 ‘\’, but this backslash will not be retained in the resulting 4935 actual argument as then seen / used while expanding the macro. 4936 4937 As a consequence to the first of these escaping mechanisms two 4938 string literals intended to be representing separate macro 4939 arguments need to be separated by white space (or, better yet, by a 4940 comma). To state it differently, such adjacent string literals - 4941 even if separated only by a blank - will not be concatenated when 4942 determining macro arguments, even if they’re only separated by 4943 white space. This is unlike certain other pseudo ops, e.g. 4944 ‘.ascii’. 4945 4946‘.endm’ 4947 Mark the end of a macro definition. 4948 4949‘.exitm’ 4950 Exit early from the current macro definition. 4951 4952‘\@’ 4953 ‘as’ maintains a counter of how many macros it has executed in this 4954 pseudo-variable; you can copy that number to your output with ‘\@’, 4955 but _only within a macro definition_. 4956 4957‘LOCAL NAME [ , ... ]’ 4958 _Warning: ‘LOCAL’ is only available if you select “alternate macro 4959 syntax” with ‘--alternate’ or ‘.altmacro’._ *Note ‘.altmacro’: 4960 Altmacro. 4961 4962 4963File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4964 49657.64 ‘.mri VAL’ 4966=============== 4967 4968If VAL is non-zero, this tells ‘as’ to enter MRI mode. If VAL is zero, 4969this tells ‘as’ to exit MRI mode. This change affects code assembled 4970until the next ‘.mri’ directive, or until the end of the file. *Note 4971MRI mode: M. 4972 4973 4974File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4975 49767.65 ‘.noaltmacro’ 4977================== 4978 4979Disable alternate macro mode. *Note Altmacro::. 4980 4981 4982File: as.info, Node: Nolist, Next: Nop, Prev: Noaltmacro, Up: Pseudo Ops 4983 49847.66 ‘.nolist’ 4985============== 4986 4987Control (in conjunction with the ‘.list’ directive) whether or not 4988assembly listings are generated. These two directives maintain an 4989internal counter (which is zero initially). ‘.list’ increments the 4990counter, and ‘.nolist’ decrements it. Assembly listings are generated 4991whenever the counter is greater than zero. 4992 4993 4994File: as.info, Node: Nop, Next: Nops, Prev: Nolist, Up: Pseudo Ops 4995 49967.67 ‘.nop [SIZE]’ 4997================== 4998 4999This directive emits no-op instructions. It is provided on all 5000architectures, allowing the creation of architecture neutral tests 5001involving actual code. The size of the generated instruction is target 5002specific, but if the optional SIZE argument is given and resolves to an 5003absolute positive value at that point in assembly (no forward 5004expressions allowed) then the fewest no-op instructions are emitted that 5005equal or exceed a total SIZE in bytes. ‘.nop’ does affect the 5006generation of DWARF debug line information. Some targets do not support 5007using ‘.nop’ with SIZE. 5008 5009 5010File: as.info, Node: Nops, Next: Octa, Prev: Nop, Up: Pseudo Ops 5011 50127.68 ‘.nops SIZE[, CONTROL]’ 5013============================ 5014 5015This directive emits no-op instructions. It is specific to the Intel 501680386 and AMD x86-64 targets. It takes a SIZE argument and generates 5017SIZE bytes of no-op instructions. SIZE must be absolute and positive. 5018These bytes do not affect the generation of DWARF debug line 5019information. 5020 5021 The optional CONTROL argument specifies a size limit for a single 5022no-op instruction. If not provided then a value of 0 is assumed. The 5023valid values of CONTROL are between 0 and 4 in 16-bit mode, between 0 5024and 7 when tuning for older processors in 32-bit mode, between 0 and 11 5025in 64-bit mode or when tuning for newer processors in 32-bit mode. When 50260 is used, the no-op instruction size limit is set to the maximum 5027supported size. 5028 5029 5030File: as.info, Node: Octa, Next: Offset, Prev: Nops, Up: Pseudo Ops 5031 50327.69 ‘.octa BIGNUMS’ 5033==================== 5034 5035This directive expects zero or more bignums, separated by commas. For 5036each bignum, it emits a 16-byte integer. 5037 5038 The term “octa” comes from contexts in which a “word” is two bytes; 5039hence _octa_-word for 16 bytes. 5040 5041 5042File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops 5043 50447.70 ‘.offset LOC’ 5045================== 5046 5047Set the location counter to LOC in the absolute section. LOC must be an 5048absolute expression. This directive may be useful for defining symbols 5049with absolute values. Do not confuse it with the ‘.org’ directive. 5050 5051 5052File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops 5053 50547.71 ‘.org NEW-LC , FILL’ 5055========================= 5056 5057Advance the location counter of the current section to NEW-LC. NEW-LC 5058is either an absolute expression or an expression with the same section 5059as the current subsection. That is, you can’t use ‘.org’ to cross 5060sections: if NEW-LC has the wrong section, the ‘.org’ directive is 5061ignored. To be compatible with former assemblers, if the section of 5062NEW-LC is absolute, ‘as’ issues a warning, then pretends the section of 5063NEW-LC is the same as the current subsection. 5064 5065 ‘.org’ may only increase the location counter, or leave it unchanged; 5066you cannot use ‘.org’ to move the location counter backwards. 5067 5068 Because ‘as’ tries to assemble programs in one pass, NEW-LC may not 5069be undefined. If you really detest this restriction we eagerly await a 5070chance to share your improved assembler. 5071 5072 Beware that the origin is relative to the start of the section, not 5073to the start of the subsection. This is compatible with other people’s 5074assemblers. 5075 5076 When the location counter (of the current subsection) is advanced, 5077the intervening bytes are filled with FILL which should be an absolute 5078expression. If the comma and FILL are omitted, FILL defaults to zero. 5079 5080 5081File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 5082 50837.72 ‘.p2align[wl] [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]’ 5084====================================================== 5085 5086Pad the location counter (in the current subsection) to a particular 5087storage boundary. The first expression (which must be absolute) is the 5088number of low-order zero bits the location counter must have after 5089advancement. For example ‘.p2align 3’ advances the location counter 5090until it is a multiple of 8. If the location counter is already a 5091multiple of 8, no change is needed. If the expression is omitted then a 5092default value of 0 is used, effectively disabling alignment 5093requirements. 5094 5095 The second expression (also absolute) gives the fill value to be 5096stored in the padding bytes. It (and the comma) may be omitted. If it 5097is omitted, the padding bytes are normally zero. However, on most 5098systems, if the section is marked as containing code and the fill value 5099is omitted, the space is filled with no-op instructions. 5100 5101 The third expression is also absolute, and is also optional. If it 5102is present, it is the maximum number of bytes that should be skipped by 5103this alignment directive. If doing the alignment would require skipping 5104more bytes than the specified maximum, then the alignment is not done at 5105all. You can omit the fill value (the second argument) entirely by 5106simply using two commas after the required alignment; this can be useful 5107if you want the alignment to be filled with no-op instructions when 5108appropriate. 5109 5110 The ‘.p2alignw’ and ‘.p2alignl’ directives are variants of the 5111‘.p2align’ directive. The ‘.p2alignw’ directive treats the fill pattern 5112as a two byte word value. The ‘.p2alignl’ directives treats the fill 5113pattern as a four byte longword value. For example, ‘.p2alignw 51142,0x368d’ will align to a multiple of 4. If it skips two bytes, they 5115will be filled in with the value 0x368d (the exact placement of the 5116bytes depends upon the endianness of the processor). If it skips 1 or 3 5117bytes, the fill value is undefined. 5118 5119 5120File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 5121 51227.73 ‘.popsection’ 5123================== 5124 5125This is one of the ELF section stack manipulation directives. The 5126others are ‘.section’ (*note Section::), ‘.subsection’ (*note 5127SubSection::), ‘.pushsection’ (*note PushSection::), and ‘.previous’ 5128(*note Previous::). 5129 5130 This directive replaces the current section (and subsection) with the 5131top section (and subsection) on the section stack. This section is 5132popped off the stack. 5133 5134 5135File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 5136 51377.74 ‘.previous’ 5138================ 5139 5140This is one of the ELF section stack manipulation directives. The 5141others are ‘.section’ (*note Section::), ‘.subsection’ (*note 5142SubSection::), ‘.pushsection’ (*note PushSection::), and ‘.popsection’ 5143(*note PopSection::). 5144 5145 This directive swaps the current section (and subsection) with most 5146recently referenced section/subsection pair prior to this one. Multiple 5147‘.previous’ directives in a row will flip between two sections (and 5148their subsections). For example: 5149 5150 .section A 5151 .subsection 1 5152 .word 0x1234 5153 .subsection 2 5154 .word 0x5678 5155 .previous 5156 .word 0x9abc 5157 5158 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 5159subsection 2 of section A. Whilst: 5160 5161 .section A 5162 .subsection 1 5163 # Now in section A subsection 1 5164 .word 0x1234 5165 .section B 5166 .subsection 0 5167 # Now in section B subsection 0 5168 .word 0x5678 5169 .subsection 1 5170 # Now in section B subsection 1 5171 .word 0x9abc 5172 .previous 5173 # Now in section B subsection 0 5174 .word 0xdef0 5175 5176 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 5177of section B and 0x9abc into subsection 1 of section B. 5178 5179 In terms of the section stack, this directive swaps the current 5180section with the top section on the section stack. 5181 5182 5183File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 5184 51857.75 ‘.print STRING’ 5186==================== 5187 5188‘as’ will print STRING on the standard output during assembly. You must 5189put STRING in double quotes. 5190 5191 5192File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 5193 51947.76 ‘.protected NAMES’ 5195======================= 5196 5197This is one of the ELF visibility directives. The other two are 5198‘.hidden’ (*note Hidden::) and ‘.internal’ (*note Internal::). 5199 5200 This directive overrides the named symbols default visibility (which 5201is set by their binding: local, global or weak). The directive sets the 5202visibility to ‘protected’ which means that any references to the symbols 5203from within the components that defines them must be resolved to the 5204definition in that component, even if a definition in another component 5205would normally preempt this. 5206 5207 5208File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 5209 52107.77 ‘.psize LINES , COLUMNS’ 5211============================= 5212 5213Use this directive to declare the number of lines—and, optionally, the 5214number of columns—to use for each page, when generating listings. 5215 5216 If you do not use ‘.psize’, listings use a default line-count of 60. 5217You may omit the comma and COLUMNS specification; the default width is 5218200 columns. 5219 5220 ‘as’ generates formfeeds whenever the specified number of lines is 5221exceeded (or whenever you explicitly request one, using ‘.eject’). 5222 5223 If you specify LINES as ‘0’, no formfeeds are generated save those 5224explicitly specified with ‘.eject’. 5225 5226 5227File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 5228 52297.78 ‘.purgem NAME’ 5230=================== 5231 5232Undefine the macro NAME, so that later uses of the string will not be 5233expanded. *Note Macro::. 5234 5235 5236File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 5237 52387.79 ‘.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]’ 5239======================================================================== 5240 5241This is one of the ELF section stack manipulation directives. The 5242others are ‘.section’ (*note Section::), ‘.subsection’ (*note 5243SubSection::), ‘.popsection’ (*note PopSection::), and ‘.previous’ 5244(*note Previous::). 5245 5246 This directive pushes the current section (and subsection) onto the 5247top of the section stack, and then replaces the current section and 5248subsection with ‘name’ and ‘subsection’. The optional ‘flags’, ‘type’ 5249and ‘arguments’ are treated the same as in the ‘.section’ (*note 5250Section::) directive. 5251 5252 5253File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 5254 52557.80 ‘.quad EXPRESSIONS’ 5256======================== 5257 5258For 64-bit architectures, or more generally with any GAS configured to 5259support 64-bit target virtual addresses, this is like ‘.int’, but 5260emitting 64-bit quantities. Otherwise ‘.quad’ expects zero or more 5261bignums, separated by commas. For each item, it emits an 8-byte 5262integer. If a bignum won’t fit in 8 bytes, a warning message is printed 5263and just the lowest order 8 bytes of the bignum are taken. 5264 5265 The term “quad” comes from contexts in which a “word” is two bytes; 5266hence _quad_-word for 8 bytes. 5267 5268 Note - this directive is not intended for encoding instructions, and 5269it will not trigger effects like DWARF line number generation. Instead 5270some targets support special directives for encoding arbitrary binary 5271sequences as instructions such as ‘.insn’ or ‘.inst’. 5272 5273 5274File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 5275 52767.81 ‘.reloc OFFSET, RELOC_NAME[, EXPRESSION]’ 5277============================================== 5278 5279Generate a relocation at OFFSET of type RELOC_NAME with value 5280EXPRESSION. If OFFSET is a number, the relocation is generated in the 5281current section. If OFFSET is an expression that resolves to a symbol 5282plus offset, the relocation is generated in the given symbol’s section. 5283EXPRESSION, if present, must resolve to a symbol plus addend or to an 5284absolute value, but note that not all targets support an addend. e.g. 5285ELF REL targets such as i386 store an addend in the section contents 5286rather than in the relocation. This low level interface does not 5287support addends stored in the section. 5288 5289 5290File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 5291 52927.82 ‘.rept COUNT’ 5293================== 5294 5295Repeat the sequence of lines between the ‘.rept’ directive and the next 5296‘.endr’ directive COUNT times. 5297 5298 For example, assembling 5299 5300 .rept 3 5301 .long 0 5302 .endr 5303 5304 is equivalent to assembling 5305 5306 .long 0 5307 .long 0 5308 .long 0 5309 5310 A count of zero is allowed, but nothing is generated. Negative 5311counts are not allowed and if encountered will be treated as if they 5312were zero. 5313 5314 5315File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 5316 53177.83 ‘.sbttl "SUBHEADING"’ 5318========================== 5319 5320Use SUBHEADING as the title (third line, immediately after the title 5321line) when generating assembly listings. 5322 5323 This directive affects subsequent pages, as well as the current page 5324if it appears within ten lines of the top of a page. 5325 5326 5327File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 5328 53297.84 ‘.scl CLASS’ 5330================= 5331 5332Set the storage-class value for a symbol. This directive may only be 5333used inside a ‘.def’/‘.endef’ pair. Storage class may flag whether a 5334symbol is static or external, or it may record further symbolic 5335debugging information. 5336 5337 5338File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 5339 53407.85 ‘.section NAME’ 5341==================== 5342 5343Use the ‘.section’ directive to assemble the following code into a 5344section named NAME. 5345 5346 This directive is only supported for targets that actually support 5347arbitrarily named sections; on ‘a.out’ targets, for example, it is not 5348accepted, even with a standard ‘a.out’ section name. 5349 5350COFF Version 5351------------ 5352 5353For COFF targets, the ‘.section’ directive is used in one of the 5354following ways: 5355 5356 .section NAME[, "FLAGS"] 5357 .section NAME[, SUBSECTION] 5358 5359 If the optional argument is quoted, it is taken as flags to use for 5360the section. Each flag is a single character. The following flags are 5361recognized: 5362 5363‘b’ 5364 bss section (uninitialized data) 5365‘n’ 5366 section is not loaded 5367‘w’ 5368 writable section 5369‘d’ 5370 data section 5371‘e’ 5372 exclude section from linking 5373‘r’ 5374 read-only section 5375‘x’ 5376 executable section 5377‘s’ 5378 shared section (meaningful for PE targets) 5379‘a’ 5380 ignored. (For compatibility with the ELF version) 5381‘y’ 5382 section is not readable (meaningful for PE targets) 5383‘0-9’ 5384 single-digit power-of-two section alignment (GNU extension) 5385 5386 If no flags are specified, the default flags depend upon the section 5387name. If the section name is not recognized, the default will be for 5388the section to be loaded and writable. Note the ‘n’ and ‘w’ flags 5389remove attributes from the section, rather than adding them, so if they 5390are used on their own it will be as if no flags had been specified at 5391all. 5392 5393 If the optional argument to the ‘.section’ directive is not quoted, 5394it is taken as a subsection number (*note Sub-Sections::). 5395 5396ELF Version 5397----------- 5398 5399This is one of the ELF section stack manipulation directives. The 5400others are ‘.subsection’ (*note SubSection::), ‘.pushsection’ (*note 5401PushSection::), ‘.popsection’ (*note PopSection::), and ‘.previous’ 5402(*note Previous::). 5403 5404 For ELF targets, the ‘.section’ directive is used like this: 5405 5406 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 5407 5408 If the ‘--sectname-subst’ command-line option is provided, the NAME 5409argument may contain a substitution sequence. Only ‘%S’ is supported at 5410the moment, and substitutes the current section name. For example: 5411 5412 .macro exception_code 5413 .section %S.exception 5414 [exception code here] 5415 .previous 5416 .endm 5417 5418 .text 5419 [code] 5420 exception_code 5421 [...] 5422 5423 .section .init 5424 [init code] 5425 exception_code 5426 [...] 5427 5428 The two ‘exception_code’ invocations above would create the 5429‘.text.exception’ and ‘.init.exception’ sections respectively. This is 5430useful e.g. to discriminate between ancillary sections that are tied to 5431setup code to be discarded after use from ancillary sections that need 5432to stay resident without having to define multiple ‘exception_code’ 5433macros just for that purpose. 5434 5435 The optional FLAGS argument is a quoted string which may contain any 5436combination of the following characters: 5437 5438‘a’ 5439 section is allocatable 5440‘d’ 5441 section is a GNU_MBIND section 5442‘e’ 5443 section is excluded from executable and shared library. 5444‘o’ 5445 section references a symbol defined in another section (the 5446 linked-to section) in the same file. 5447‘w’ 5448 section is writable 5449‘x’ 5450 section is executable 5451‘M’ 5452 section is mergeable 5453‘S’ 5454 section contains zero terminated strings 5455‘G’ 5456 section is a member of a section group 5457‘T’ 5458 section is used for thread-local-storage 5459‘?’ 5460 section is a member of the previously-current section’s group, if 5461 any 5462‘+’ 5463 section inherits attributes and (unless explicitly specified) type 5464 from the previously-current section, adding other attributes as 5465 specified 5466‘-’ 5467 section inherits attributes and (unless explicitly specified) type 5468 from the previously-current section, removing other attributes as 5469 specified 5470‘R’ 5471 retained section (apply SHF_GNU_RETAIN to prevent linker garbage 5472 collection, GNU ELF extension) 5473‘<number>’ 5474 a numeric value indicating the bits to be set in the ELF section 5475 header’s flags field. Note - if one or more of the alphabetic 5476 characters described above is also included in the flags field, 5477 their bit values will be ORed into the resulting value. 5478‘<target specific>’ 5479 some targets extend this list with their own flag characters 5480 5481 Note - once a section’s flags have been set they cannot be changed. 5482There are a few exceptions to this rule however. Processor and 5483application specific flags can be added to an already defined section. 5484The ‘.interp’, ‘.strtab’ and ‘.symtab’ sections can have the allocate 5485flag (‘a’) set after they are initially defined, and the 5486‘.note-GNU-stack’ section may have the executable (‘x’) flag added. 5487Also note that the ‘.attach_to_group’ directive can be used to add a 5488section to a group even if the section was not originally declared to be 5489part of that group. 5490 5491 Note further that ‘+’ and ‘-’ need to come first and can only take 5492the effect described here unless overridden by a target. The attributes 5493inherited are those in effect at the time the directive is processed. 5494Attributes added later (see above) will not be inherited. Using either 5495together with ‘?’ is undefined at this point. 5496 5497 The optional TYPE argument may contain one of the following 5498constants: 5499 5500‘@progbits’ 5501 section contains data 5502‘@nobits’ 5503 section does not contain data (i.e., section only occupies space) 5504‘@note’ 5505 section contains data which is used by things other than the 5506 program 5507‘@init_array’ 5508 section contains an array of pointers to init functions 5509‘@fini_array’ 5510 section contains an array of pointers to finish functions 5511‘@preinit_array’ 5512 section contains an array of pointers to pre-init functions 5513‘@<number>’ 5514 a numeric value to be set as the ELF section header’s type field. 5515‘@<target specific>’ 5516 some targets extend this list with their own types 5517 5518 Many targets only support the first three section types. The type 5519may be enclosed in double quotes if necessary. 5520 5521 Note on targets where the ‘@’ character is the start of a comment (eg 5522ARM) then another character is used instead. For example the ARM port 5523uses the ‘%’ character. 5524 5525 Note - some sections, eg ‘.text’ and ‘.data’ are considered to be 5526special and have fixed types. Any attempt to declare them with a 5527different type will generate an error from the assembler. 5528 5529 If FLAGS contains the ‘M’ symbol then the TYPE argument must be 5530specified as well as an extra argument—ENTSIZE—like this: 5531 5532 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 5533 5534 Sections with the ‘M’ flag but not ‘S’ flag must contain fixed size 5535constants, each ENTSIZE octets long. Sections with both ‘M’ and ‘S’ 5536must contain zero terminated strings where each character is ENTSIZE 5537bytes long. The linker may remove duplicates within sections with the 5538same name, same entity size and same flags. ENTSIZE must be an absolute 5539expression. For sections with both ‘M’ and ‘S’, a string which is a 5540suffix of a larger string is considered a duplicate. Thus ‘"def"’ will 5541be merged with ‘"abcdef"’; A reference to the first ‘"def"’ will be 5542changed to a reference to ‘"abcdef"+3’. 5543 5544 If FLAGS contains the ‘o’ flag, then the TYPE argument must be 5545present along with an additional field like this: 5546 5547 .section NAME,"FLAGS"o,@TYPE,SYMBOLNAME|SECTIONINDEX 5548 5549 The SYMBOLNAME field specifies the symbol name which the section 5550references. Alternatively a numeric SECTIONINDEX can be provided. This 5551is not generally a good idea as section indices are rarely known at 5552assembly time, but the facility is provided for testing purposes. An 5553index of zero is allowed. It indicates that the linked-to section has 5554already been discarded. 5555 5556 Note: If both the M and O flags are present, then the fields for the 5557Merge flag should come first, like this: 5558 5559 .section NAME,"FLAGS"Mo,@TYPE,ENTSIZE,SYMBOLNAME 5560 5561 If FLAGS contains the ‘G’ symbol then the TYPE argument must be 5562present along with an additional field like this: 5563 5564 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 5565 5566 The GROUPNAME field specifies the name of the section group to which 5567this particular section belongs. The optional linkage field can 5568contain: 5569 5570‘comdat’ 5571 indicates that only one copy of this section should be retained 5572‘.gnu.linkonce’ 5573 an alias for comdat 5574 5575 Note: if both the M and G flags are present then the fields for the 5576Merge flag should come first, like this: 5577 5578 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 5579 5580 If both ‘o’ flag and ‘G’ flag are present, then the SYMBOLNAME field 5581for ‘o’ comes first, like this: 5582 5583 .section NAME,"FLAGS"oG,@TYPE,SYMBOLNAME,GROUPNAME[,LINKAGE] 5584 5585 If FLAGS contains the ‘?’ symbol then it may not also contain the ‘G’ 5586symbol and the GROUPNAME or LINKAGE fields should not be present. 5587Instead, ‘?’ says to consider the section that’s current before this 5588directive. If that section used ‘G’, then the new section will use ‘G’ 5589with those same GROUPNAME and LINKAGE fields implicitly. If not, then 5590the ‘?’ symbol has no effect. 5591 5592 The optional UNIQUE,‘<NUMBER>’ argument must come last. It assigns 5593‘<NUMBER>’ as a unique section ID to distinguish different sections with 5594the same section name like these: 5595 5596 .section NAME,"FLAGS",@TYPE,UNIQUE,<NUMBER> 5597 .section NAME,"FLAGS"G,@TYPE,GROUPNAME,[LINKAGE],UNIQUE,<NUMBER> 5598 .section NAME,"FLAGS"MG,@TYPE,ENTSIZE,GROUPNAME[,LINKAGE],UNIQUE,<NUMBER> 5599 5600 The valid values of ‘<NUMBER>’ are between 0 and 4294967295. 5601 5602 If no flags are specified, the default flags depend upon the section 5603name. If the section name is not recognized, the default will be for 5604the section to have none of the above flags: it will not be allocated in 5605memory, nor writable, nor executable. The section will contain data. 5606 5607 For SPARC ELF targets, the assembler supports another type of 5608‘.section’ directive for compatibility with the Solaris assembler: 5609 5610 .section "NAME"[, FLAGS...] 5611 5612 Note that the section name is quoted. There may be a sequence of 5613comma separated flags: 5614 5615‘#alloc’ 5616 section is allocatable 5617‘#write’ 5618 section is writable 5619‘#execinstr’ 5620 section is executable 5621‘#exclude’ 5622 section is excluded from executable and shared library. 5623‘#tls’ 5624 section is used for thread local storage 5625 5626 This directive replaces the current section and subsection. See the 5627contents of the gas testsuite directory ‘gas/testsuite/gas/elf’ for some 5628examples of how this directive and the other section stack directives 5629work. 5630 5631 5632File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 5633 56347.86 ‘.set SYMBOL, EXPRESSION’ 5635============================== 5636 5637Set the value of SYMBOL to EXPRESSION. This changes SYMBOL’s value and 5638type to conform to EXPRESSION. If SYMBOL was flagged as external, it 5639remains flagged (*note Symbol Attributes::). 5640 5641 You may ‘.set’ a symbol many times in the same assembly provided that 5642the values given to the symbol are constants. Values that are based on 5643expressions involving other symbols are allowed, but some targets may 5644restrict this to only being done once per assembly. This is because 5645those targets do not set the addresses of symbols at assembly time, but 5646rather delay the assignment until a final link is performed. This 5647allows the linker a chance to change the code in the files, changing the 5648location of, and the relative distance between, various different 5649symbols. 5650 5651 If you ‘.set’ a global symbol, the value stored in the object file is 5652the last value stored into it. 5653 5654 On Z80 ‘set’ is a real instruction, use ‘.set’ or ‘SYMBOL defl 5655EXPRESSION’ instead. 5656 5657 5658File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 5659 56607.87 ‘.short EXPRESSIONS’ 5661========================= 5662 5663‘.short’ is normally the same as ‘.word’. *Note ‘.word’: Word. 5664 5665 In some configurations, however, ‘.short’ and ‘.word’ generate 5666numbers of different lengths. *Note Machine Dependencies::. 5667 5668 Note - this directive is not intended for encoding instructions, and 5669it will not trigger effects like DWARF line number generation. Instead 5670some targets support special directives for encoding arbitrary binary 5671sequences as instructions such as ‘.insn’ or ‘.inst’. 5672 5673 5674File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 5675 56767.88 ‘.single FLONUMS’ 5677====================== 5678 5679This directive assembles zero or more flonums, separated by commas. It 5680has the same effect as ‘.float’. The exact kind of floating point 5681numbers emitted depends on how ‘as’ is configured. *Note Machine 5682Dependencies::. 5683 5684 5685File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 5686 56877.89 ‘.size’ 5688============ 5689 5690This directive is used to set the size associated with a symbol. 5691 5692COFF Version 5693------------ 5694 5695For COFF targets, the ‘.size’ directive is only permitted inside 5696‘.def’/‘.endef’ pairs. It is used like this: 5697 5698 .size EXPRESSION 5699 5700ELF Version 5701----------- 5702 5703For ELF targets, the ‘.size’ directive is used like this: 5704 5705 .size NAME , EXPRESSION 5706 5707 This directive sets the size associated with a symbol NAME. The size 5708in bytes is computed from EXPRESSION which can make use of label 5709arithmetic. This directive is typically used to set the size of 5710function symbols. 5711 5712 5713File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 5714 57157.90 ‘.skip SIZE [,FILL]’ 5716========================= 5717 5718This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5719are absolute expressions. If the comma and FILL are omitted, FILL is 5720assumed to be zero. This is the same as ‘.space’. 5721 5722 5723File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 5724 57257.91 ‘.sleb128 EXPRESSIONS’ 5726=========================== 5727 5728SLEB128 stands for “signed little endian base 128.” This is a compact, 5729variable length representation of numbers used by the DWARF symbolic 5730debugging format. *Note ‘.uleb128’: Uleb128. 5731 5732 5733File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 5734 57357.92 ‘.space SIZE [,FILL]’ 5736========================== 5737 5738This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5739are absolute expressions. If the comma and FILL are omitted, FILL is 5740assumed to be zero. This is the same as ‘.skip’. 5741 5742 _Warning:_ ‘.space’ has a completely different meaning for HPPA 5743 targets; use ‘.block’ as a substitute. See ‘HP9000 Series 800 5744 Assembly Language Reference Manual’ (HP 92432-90001) for the 5745 meaning of the ‘.space’ directive. *Note HPPA Assembler 5746 Directives: HPPA Directives, for a summary. 5747 5748 5749File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 5750 57517.93 ‘.stabd, .stabn, .stabs’ 5752============================= 5753 5754There are three directives that begin ‘.stab’. All emit symbols (*note 5755Symbols::), for use by symbolic debuggers. The symbols are not entered 5756in the ‘as’ hash table: they cannot be referenced elsewhere in the 5757source file. Up to five fields are required: 5758 5759STRING 5760 This is the symbol’s name. It may contain any character except 5761 ‘\000’, so is more general than ordinary symbol names. Some 5762 debuggers used to code arbitrarily complex structures into symbol 5763 names using this field. 5764 5765TYPE 5766 An absolute expression. The symbol’s type is set to the low 8 bits 5767 of this expression. Any bit pattern is permitted, but ‘ld’ and 5768 debuggers choke on silly bit patterns. 5769 5770OTHER 5771 An absolute expression. The symbol’s “other” attribute is set to 5772 the low 8 bits of this expression. 5773 5774DESC 5775 An absolute expression. The symbol’s descriptor is set to the low 5776 16 bits of this expression. 5777 5778VALUE 5779 An absolute expression which becomes the symbol’s value. 5780 5781 If a warning is detected while reading a ‘.stabd’, ‘.stabn’, or 5782‘.stabs’ statement, the symbol has probably already been created; you 5783get a half-formed symbol in your object file. This is compatible with 5784earlier assemblers! 5785 5786‘.stabd TYPE , OTHER , DESC’ 5787 5788 The “name” of the symbol generated is not even an empty string. It 5789 is a null pointer, for compatibility. Older assemblers used a null 5790 pointer so they didn’t waste space in object files with empty 5791 strings. 5792 5793 The symbol’s value is set to the location counter, relocatably. 5794 When your program is linked, the value of this symbol is the 5795 address of the location counter when the ‘.stabd’ was assembled. 5796 5797‘.stabn TYPE , OTHER , DESC , VALUE’ 5798 The name of the symbol is set to the empty string ‘""’. 5799 5800‘.stabs STRING , TYPE , OTHER , DESC , VALUE’ 5801 All five fields are specified. 5802 5803 5804File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5805 58067.94 ‘.string’ "STR", ‘.string8’ "STR", ‘.string16’ 5807=================================================== 5808 5809"STR", ‘.string32’ "STR", ‘.string64’ "STR" 5810 5811 Copy the characters in STR to the object file. You may specify more 5812than one string to copy, separated by commas. Unless otherwise 5813specified for a particular machine, the assembler marks the end of each 5814string with a 0 byte. You can use any of the escape sequences described 5815in *note Strings: Strings. 5816 5817 The variants ‘string16’, ‘string32’ and ‘string64’ differ from the 5818‘string’ pseudo opcode in that each 8-bit character from STR is copied 5819and expanded to 16, 32 or 64 bits respectively. The expanded characters 5820are stored in target endianness byte order. 5821 5822 Example: 5823 .string32 "BYE" 5824 expands to: 5825 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5826 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5827 5828 5829File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5830 58317.95 ‘.struct EXPRESSION’ 5832========================= 5833 5834Switch to the absolute section, and set the section offset to 5835EXPRESSION, which must be an absolute expression. You might use this as 5836follows: 5837 .struct 0 5838 field1: 5839 .struct field1 + 4 5840 field2: 5841 .struct field2 + 4 5842 field3: 5843 This would define the symbol ‘field1’ to have the value 0, the symbol 5844‘field2’ to have the value 4, and the symbol ‘field3’ to have the value 58458. Assembly would be left in the absolute section, and you would need 5846to use a ‘.section’ directive of some sort to change to some other 5847section before further assembly. 5848 5849 5850File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5851 58527.96 ‘.subsection NAME’ 5853======================= 5854 5855This is one of the ELF section stack manipulation directives. The 5856others are ‘.section’ (*note Section::), ‘.pushsection’ (*note 5857PushSection::), ‘.popsection’ (*note PopSection::), and ‘.previous’ 5858(*note Previous::). 5859 5860 This directive replaces the current subsection with ‘name’. The 5861current section is not changed. The replaced subsection is put onto the 5862section stack in place of the then current top of stack subsection. 5863 5864 5865File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5866 58677.97 ‘.symver’ 5868============== 5869 5870Use the ‘.symver’ directive to bind symbols to specific version nodes 5871within a source file. This is only supported on ELF platforms, and is 5872typically used when assembling files to be linked into a shared library. 5873There are cases where it may make sense to use this in objects to be 5874bound into an application itself so as to override a versioned symbol 5875from a shared library. 5876 5877 For ELF targets, the ‘.symver’ directive can be used like this: 5878 .symver NAME, NAME2@NODENAME[ ,VISIBILITY] 5879 If the original symbol NAME is defined within the file being 5880assembled, the ‘.symver’ directive effectively creates a symbol alias 5881with the name NAME2@NODENAME, and in fact the main reason that we just 5882don’t try and create a regular alias is that the @ character isn’t 5883permitted in symbol names. The NAME2 part of the name is the actual 5884name of the symbol by which it will be externally referenced. The name 5885NAME itself is merely a name of convenience that is used so that it is 5886possible to have definitions for multiple versions of a function within 5887a single source file, and so that the compiler can unambiguously know 5888which version of a function is being mentioned. The NODENAME portion of 5889the alias should be the name of a node specified in the version script 5890supplied to the linker when building a shared library. If you are 5891attempting to override a versioned symbol from a shared library, then 5892NODENAME should correspond to the nodename of the symbol you are trying 5893to override. The optional argument VISIBILITY updates the visibility of 5894the original symbol. The valid visibilities are ‘local’, ‘hidden’, and 5895‘remove’. The ‘local’ visibility makes the original symbol a local 5896symbol (*note Local::). The ‘hidden’ visibility sets the visibility of 5897the original symbol to ‘hidden’ (*note Hidden::). The ‘remove’ 5898visibility removes the original symbol from the symbol table. If 5899visibility isn’t specified, the original symbol is unchanged. 5900 5901 If the symbol NAME is not defined within the file being assembled, 5902all references to NAME will be changed to NAME2@NODENAME. If no 5903reference to NAME is made, NAME2@NODENAME will be removed from the 5904symbol table. 5905 5906 Another usage of the ‘.symver’ directive is: 5907 .symver NAME, NAME2@@NODENAME 5908 In this case, the symbol NAME must exist and be defined within the 5909file being assembled. It is similar to NAME2@NODENAME. The difference 5910is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5911the linker. 5912 5913 The third usage of the ‘.symver’ directive is: 5914 .symver NAME, NAME2@@@NODENAME 5915 When NAME is not defined within the file being assembled, it is 5916treated as NAME2@NODENAME. When NAME is defined within the file being 5917assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5918 5919 5920File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5921 59227.98 ‘.tag STRUCTNAME’ 5923====================== 5924 5925This directive is generated by compilers to include auxiliary debugging 5926information in the symbol table. It is only permitted inside 5927‘.def’/‘.endef’ pairs. Tags are used to link structure definitions in 5928the symbol table with instances of those structures. 5929 5930 5931File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5932 59337.99 ‘.text SUBSECTION’ 5934======================= 5935 5936Tells ‘as’ to assemble the following statements onto the end of the text 5937subsection numbered SUBSECTION, which is an absolute expression. If 5938SUBSECTION is omitted, subsection number zero is used. 5939 5940 5941File: as.info, Node: Title, Next: Tls_common, Prev: Text, Up: Pseudo Ops 5942 59437.100 ‘.title "HEADING"’ 5944======================== 5945 5946Use HEADING as the title (second line, immediately after the source file 5947name and pagenumber) when generating assembly listings. 5948 5949 This directive affects subsequent pages, as well as the current page 5950if it appears within ten lines of the top of a page. 5951 5952 5953File: as.info, Node: Tls_common, Next: Type, Prev: Title, Up: Pseudo Ops 5954 59557.101 ‘.tls_common SYMBOL, LENGTH[, ALIGNMENT]’ 5956=============================================== 5957 5958This directive behaves in the same way as the ‘.comm’ directive (*note 5959Comm::) except that SYMBOL has type of STT_TLS instead of STT_OBJECT. 5960 5961 5962File: as.info, Node: Type, Next: Uleb128, Prev: Tls_common, Up: Pseudo Ops 5963 59647.102 ‘.type’ 5965============= 5966 5967This directive is used to set the type of a symbol. 5968 5969COFF Version 5970------------ 5971 5972For COFF targets, this directive is permitted only within 5973‘.def’/‘.endef’ pairs. It is used like this: 5974 5975 .type INT 5976 5977 This records the integer INT as the type attribute of a symbol table 5978entry. 5979 5980ELF Version 5981----------- 5982 5983For ELF targets, the ‘.type’ directive is used like this: 5984 5985 .type NAME , TYPE DESCRIPTION 5986 5987 This sets the type of symbol NAME to be either a function symbol or 5988an object symbol. There are five different syntaxes supported for the 5989TYPE DESCRIPTION field, in order to provide compatibility with various 5990other assemblers. 5991 5992 Because some of the characters used in these syntaxes (such as ‘@’ 5993and ‘#’) are comment characters for some architectures, some of the 5994syntaxes below do not work on all architectures. The first variant will 5995be accepted by the GNU assembler on all architectures so that variant 5996should be used for maximum portability, if you do not need to assemble 5997your code with other assemblers. 5998 5999 The syntaxes supported are: 6000 6001 .type <name> STT_<TYPE_IN_UPPER_CASE> 6002 .type <name>,#<type> 6003 .type <name>,@<type> 6004 .type <name>,%<type> 6005 .type <name>,"<type>" 6006 6007 The types supported are: 6008 6009‘STT_FUNC’ 6010‘function’ 6011 Mark the symbol as being a function name. 6012 6013‘STT_GNU_IFUNC’ 6014‘gnu_indirect_function’ 6015 Mark the symbol as an indirect function when evaluated during reloc 6016 processing. (This is only supported on assemblers targeting GNU 6017 systems). 6018 6019‘STT_OBJECT’ 6020‘object’ 6021 Mark the symbol as being a data object. 6022 6023‘STT_TLS’ 6024‘tls_object’ 6025 Mark the symbol as being a thread-local data object. 6026 6027‘STT_COMMON’ 6028‘common’ 6029 Mark the symbol as being a common data object. 6030 6031‘STT_NOTYPE’ 6032‘notype’ 6033 Does not mark the symbol in any way. It is supported just for 6034 completeness. 6035 6036‘gnu_unique_object’ 6037 Marks the symbol as being a globally unique data object. The 6038 dynamic linker will make sure that in the entire process there is 6039 just one symbol with this name and type in use. (This is only 6040 supported on assemblers targeting GNU systems). 6041 6042 Changing between incompatible types other than from/to STT_NOTYPE 6043will result in a diagnostic. An intermediate change to STT_NOTYPE will 6044silence this. 6045 6046 Note: Some targets support extra types in addition to those listed 6047above. 6048 6049 6050File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 6051 60527.103 ‘.uleb128 EXPRESSIONS’ 6053============================ 6054 6055ULEB128 stands for “unsigned little endian base 128.” This is a compact, 6056variable length representation of numbers used by the DWARF symbolic 6057debugging format. *Note ‘.sleb128’: Sleb128. 6058 6059 6060File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 6061 60627.104 ‘.val ADDR’ 6063================= 6064 6065This directive, permitted only within ‘.def’/‘.endef’ pairs, records the 6066address ADDR as the value attribute of a symbol table entry. 6067 6068 6069File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 6070 60717.105 ‘.version "STRING"’ 6072========================= 6073 6074This directive creates a ‘.note’ section and places into it an ELF 6075formatted note of type NT_VERSION. The note’s name is set to ‘string’. 6076 6077 6078File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 6079 60807.106 ‘.vtable_entry TABLE, OFFSET’ 6081=================================== 6082 6083This directive finds or creates a symbol ‘table’ and creates a 6084‘VTABLE_ENTRY’ relocation for it with an addend of ‘offset’. 6085 6086 6087File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 6088 60897.107 ‘.vtable_inherit CHILD, PARENT’ 6090===================================== 6091 6092This directive finds the symbol ‘child’ and finds or creates the symbol 6093‘parent’ and then creates a ‘VTABLE_INHERIT’ relocation for the parent 6094whose addend is the value of the child symbol. As a special case the 6095parent name of ‘0’ is treated as referring to the ‘*ABS*’ section. 6096 6097 6098File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 6099 61007.108 ‘.warning "STRING"’ 6101========================= 6102 6103Similar to the directive ‘.error’ (*note ‘.error "STRING"’: Error.), but 6104just emits a warning. 6105 6106 6107File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 6108 61097.109 ‘.weak NAMES’ 6110=================== 6111 6112This directive sets the weak attribute on the comma separated list of 6113symbol ‘names’. If the symbols do not already exist, they will be 6114created. 6115 6116 On COFF targets other than PE, weak symbols are a GNU extension. 6117This directive sets the weak attribute on the comma separated list of 6118symbol ‘names’. If the symbols do not already exist, they will be 6119created. 6120 6121 On the PE target, weak symbols are supported natively as weak 6122aliases. When a weak symbol is created that is not an alias, GAS 6123creates an alternate symbol to hold the default value. 6124 6125 6126File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 6127 61287.110 ‘.weakref ALIAS, TARGET’ 6129============================== 6130 6131This directive creates an alias to the target symbol that enables the 6132symbol to be referenced with weak-symbol semantics, but without actually 6133making it weak. If direct references or definitions of the symbol are 6134present, then the symbol will not be weak, but if all references to it 6135are through weak references, the symbol will be marked as weak in the 6136symbol table. 6137 6138 The effect is equivalent to moving all references to the alias to a 6139separate assembly source file, renaming the alias to the symbol in it, 6140declaring the symbol as weak there, and running a reloadable link to 6141merge the object files resulting from the assembly of the new source 6142file and the old source file that had the references to the alias 6143removed. 6144 6145 The alias itself never makes to the symbol table, and is entirely 6146handled within the assembler. 6147 6148 6149File: as.info, Node: Word, Next: Zero, Prev: Weakref, Up: Pseudo Ops 6150 61517.111 ‘.word EXPRESSIONS’ 6152========================= 6153 6154This directive expects zero or more EXPRESSIONS, of any section, 6155separated by commas. 6156 6157 The size of the number emitted, and its byte order, depend on what 6158target computer the assembly is for. 6159 6160 _Warning: Special Treatment to support Compilers_ 6161 6162 Machines with a 32-bit address space, but that do less than 32-bit 6163addressing, require the following special treatment. If the machine of 6164interest to you does 32-bit addressing (or doesn’t require it; *note 6165Machine Dependencies::), you can ignore this issue. 6166 6167 In order to assemble compiler output into something that works, ‘as’ 6168occasionally does strange things to ‘.word’ directives. Directives of 6169the form ‘.word sym1-sym2’ are often emitted by compilers as part of 6170jump tables. Therefore, when ‘as’ assembles a directive of the form 6171‘.word sym1-sym2’, and the difference between ‘sym1’ and ‘sym2’ does not 6172fit in 16 bits, ‘as’ creates a “secondary jump table”, immediately 6173before the next label. This secondary jump table is preceded by a 6174short-jump to the first byte after the secondary table. This short-jump 6175prevents the flow of control from accidentally falling into the new 6176table. Inside the table is a long-jump to ‘sym2’. The original ‘.word’ 6177contains ‘sym1’ minus the address of the long-jump to ‘sym2’. 6178 6179 If there were several occurrences of ‘.word sym1-sym2’ before the 6180secondary jump table, all of them are adjusted. If there was a ‘.word 6181sym3-sym4’, that also did not fit in sixteen bits, a long-jump to ‘sym4’ 6182is included in the secondary jump table, and the ‘.word’ directives are 6183adjusted to contain ‘sym3’ minus the address of the long-jump to ‘sym4’; 6184and so on, for as many entries in the original jump table as necessary. 6185 6186 6187File: as.info, Node: Zero, Next: 2byte, Prev: Word, Up: Pseudo Ops 6188 61897.112 ‘.zero SIZE’ 6190================== 6191 6192This directive emits SIZE 0-valued bytes. SIZE must be an absolute 6193expression. This directive is actually an alias for the ‘.skip’ 6194directive so it can take an optional second argument of the value to 6195store in the bytes instead of zero. Using ‘.zero’ in this way would be 6196confusing however. 6197 6198 6199File: as.info, Node: 2byte, Next: 4byte, Prev: Zero, Up: Pseudo Ops 6200 62017.113 ‘.2byte EXPRESSION [, EXPRESSION]*’ 6202========================================= 6203 6204This directive expects zero or more expressions, separated by commas. 6205If there are no expressions then the directive does nothing. Otherwise 6206each expression is evaluated in turn and placed in the next two bytes of 6207the current output section, using the endian model of the target. If an 6208expression will not fit in two bytes, a warning message is displayed and 6209the least significant two bytes of the expression’s value are used. If 6210an expression cannot be evaluated at assembly time then relocations will 6211be generated in order to compute the value at link time. 6212 6213 This directive does not apply any alignment before or after inserting 6214the values. As a result of this, if relocations are generated, they may 6215be different from those used for inserting values with a guaranteed 6216alignment. 6217 6218 6219File: as.info, Node: 4byte, Next: 8byte, Prev: 2byte, Up: Pseudo Ops 6220 62217.114 ‘.4byte EXPRESSION [, EXPRESSION]*’ 6222========================================= 6223 6224Like the ‘.2byte’ directive, except that it inserts unaligned, four byte 6225long values into the output. 6226 6227 6228File: as.info, Node: 8byte, Next: Deprecated, Prev: 4byte, Up: Pseudo Ops 6229 62307.115 ‘.8byte EXPRESSION [, EXPRESSION]*’ 6231========================================= 6232 6233For 64-bit architectures, or more generally with any GAS configured to 6234support 64-bit target virtual addresses, this is like the ‘.2byte’ 6235directive, except that it inserts unaligned, eight byte long values into 6236the output. Otherwise, like *note ‘.quad EXPRESSIONS’: Quad, it expects 6237zero or more bignums, separated by commas. 6238 6239 6240File: as.info, Node: Deprecated, Prev: 8byte, Up: Pseudo Ops 6241 62427.116 Deprecated Directives 6243=========================== 6244 6245One day these directives won’t work. They are included for 6246compatibility with older assemblers. 6247.abort 6248.line 6249 6250 6251File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 6252 62538 Object Attributes 6254******************* 6255 6256‘as’ assembles source files written for a specific architecture into 6257object files for that architecture. But not all object files are alike. 6258Many architectures support incompatible variations. For instance, 6259floating point arguments might be passed in floating point registers if 6260the object file requires hardware floating point support—or floating 6261point arguments might be passed in integer registers if the object file 6262supports processors with no hardware floating point unit. Or, if two 6263objects are built for different generations of the same architecture, 6264the combination may require the newer generation at run-time. 6265 6266 This information is useful during and after linking. At link time, 6267‘ld’ can warn about incompatible object files. After link time, tools 6268like ‘gdb’ can use it to process the linked file correctly. 6269 6270 Compatibility information is recorded as a series of object 6271attributes. Each attribute has a “vendor”, “tag”, and “value”. The 6272vendor is a string, and indicates who sets the meaning of the tag. The 6273tag is an integer, and indicates what property the attribute describes. 6274The value may be a string or an integer, and indicates how the property 6275affects this object. Missing attributes are the same as attributes with 6276a zero value or empty string value. 6277 6278 Object attributes were developed as part of the ABI for the ARM 6279Architecture. The file format is documented in ‘ELF for the ARM 6280Architecture’. 6281 6282* Menu: 6283 6284* GNU Object Attributes:: GNU Object Attributes 6285* Defining New Object Attributes:: Defining New Object Attributes 6286 6287 6288File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 6289 62908.1 GNU Object Attributes 6291========================= 6292 6293The ‘.gnu_attribute’ directive records an object attribute with vendor 6294‘gnu’. 6295 6296 Except for ‘Tag_compatibility’, which has both an integer and a 6297string for its value, GNU attributes have a string value if the tag 6298number is odd and an integer value if the tag number is even. The 6299second bit (‘TAG & 2’ is set for architecture-independent attributes and 6300clear for architecture-dependent ones. 6301 63028.1.1 Common GNU attributes 6303--------------------------- 6304 6305These attributes are valid on all architectures. 6306 6307Tag_compatibility (32) 6308 The compatibility attribute takes an integer flag value and a 6309 vendor name. If the flag value is 0, the file is compatible with 6310 other toolchains. If it is 1, then the file is only compatible 6311 with the named toolchain. If it is greater than 1, the file can 6312 only be processed by other toolchains under some private 6313 arrangement indicated by the flag value and the vendor name. 6314 63158.1.2 M680x0 Attributes 6316----------------------- 6317 6318Tag_GNU_M68K_ABI_FP (4) 6319 The floating-point ABI used by this object file. The value will 6320 be: 6321 6322 • 0 for files not affected by the floating-point ABI. 6323 • 1 for files using double-precision hardware floating-point 6324 ABI. 6325 • 2 for files using the software floating-point ABI. 6326 63278.1.3 MIPS Attributes 6328--------------------- 6329 6330Tag_GNU_MIPS_ABI_FP (4) 6331 The floating-point ABI used by this object file. The value will 6332 be: 6333 6334 • 0 for files not affected by the floating-point ABI. 6335 • 1 for files using the hardware floating-point ABI with a 6336 standard double-precision FPU. 6337 • 2 for files using the hardware floating-point ABI with a 6338 single-precision FPU. 6339 • 3 for files using the software floating-point ABI. 6340 • 4 for files using the deprecated hardware floating-point ABI 6341 which used 64-bit floating-point registers, 32-bit 6342 general-purpose registers and increased the number of 6343 callee-saved floating-point registers. 6344 • 5 for files using the hardware floating-point ABI with a 6345 double-precision FPU with either 32-bit or 64-bit 6346 floating-point registers and 32-bit general-purpose registers. 6347 • 6 for files using the hardware floating-point ABI with 64-bit 6348 floating-point registers and 32-bit general-purpose registers. 6349 • 7 for files using the hardware floating-point ABI with 64-bit 6350 floating-point registers, 32-bit general-purpose registers and 6351 a rule that forbids the direct use of odd-numbered 6352 single-precision floating-point registers. 6353 6354Tag_GNU_MIPS_ABI_MSA (8) 6355 The MIPS SIMD Architecture (MSA) ABI used by this object file. The 6356 value will be: 6357 6358 • 0 for files not affected by the MSA ABI. 6359 • 1 for files using the 128-bit MSA ABI. 6360 63618.1.4 PowerPC Attributes 6362------------------------ 6363 6364Tag_GNU_Power_ABI_FP (4) 6365 The floating-point ABI used by this object file. The value will 6366 be: 6367 6368 • 0 for files not affected by the floating-point ABI. 6369 • 1 for files using double-precision hardware floating-point 6370 ABI. 6371 • 2 for files using the software floating-point ABI. 6372 • 3 for files using single-precision hardware floating-point 6373 ABI. 6374 6375Tag_GNU_Power_ABI_Vector (8) 6376 The vector ABI used by this object file. The value will be: 6377 6378 • 0 for files not affected by the vector ABI. 6379 • 1 for files using general purpose registers to pass vectors. 6380 • 2 for files using AltiVec registers to pass vectors. 6381 • 3 for files using SPE registers to pass vectors. 6382 63838.1.5 IBM z Systems Attributes 6384------------------------------ 6385 6386Tag_GNU_S390_ABI_Vector (8) 6387 The vector ABI used by this object file. The value will be: 6388 6389 • 0 for files not affected by the vector ABI. 6390 • 1 for files using software vector ABI. 6391 • 2 for files using hardware vector ABI. 6392 63938.1.6 MSP430 Attributes 6394----------------------- 6395 6396Tag_GNU_MSP430_Data_Region (4) 6397 The data region used by this object file. The value will be: 6398 6399 • 0 for files not using the large memory model. 6400 • 1 for files which have been compiled with the condition that 6401 all data is in the lower memory region, i.e. below address 6402 0x10000. 6403 • 2 for files which allow data to be placed in the full 20-bit 6404 memory range. 6405 6406 6407File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 6408 64098.2 Defining New Object Attributes 6410================================== 6411 6412If you want to define a new GNU object attribute, here are the places 6413you will need to modify. New attributes should be discussed on the 6414‘binutils’ mailing list. 6415 6416 • This manual, which is the official register of attributes. 6417 • The header for your architecture ‘include/elf’, to define the tag. 6418 • The ‘bfd’ support file for your architecture, to merge the 6419 attribute and issue any appropriate link warnings. 6420 • Test cases in ‘ld/testsuite’ for merging and link warnings. 6421 • ‘binutils/readelf.c’ to display your attribute. 6422 • GCC, if you want the compiler to mark the attribute automatically. 6423 6424 6425File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 6426 64279 Machine Dependent Features 6428**************************** 6429 6430The machine instruction sets are (almost by definition) different on 6431each machine where ‘as’ runs. Floating point representations vary as 6432well, and ‘as’ often supports a few additional directives or 6433command-line options for compatibility with other assemblers on a 6434particular platform. Finally, some versions of ‘as’ support special 6435pseudo-instructions for branch optimization. 6436 6437 This chapter discusses most of these differences, though it does not 6438include details on any machine’s instruction set. For details on that 6439subject, see the hardware manufacturer’s manual. 6440 6441* Menu: 6442 6443* AArch64-Dependent:: AArch64 Dependent Features 6444* Alpha-Dependent:: Alpha Dependent Features 6445* ARC-Dependent:: ARC Dependent Features 6446* ARM-Dependent:: ARM Dependent Features 6447* AVR-Dependent:: AVR Dependent Features 6448* Blackfin-Dependent:: Blackfin Dependent Features 6449* BPF-Dependent:: BPF Dependent Features 6450* CR16-Dependent:: CR16 Dependent Features 6451* CRIS-Dependent:: CRIS Dependent Features 6452* C-SKY-Dependent:: C-SKY Dependent Features 6453* D10V-Dependent:: D10V Dependent Features 6454* D30V-Dependent:: D30V Dependent Features 6455* Epiphany-Dependent:: EPIPHANY Dependent Features 6456* H8/300-Dependent:: Renesas H8/300 Dependent Features 6457* HPPA-Dependent:: HPPA Dependent Features 6458* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 6459* IA-64-Dependent:: Intel IA-64 Dependent Features 6460* IP2K-Dependent:: IP2K Dependent Features 6461* LM32-Dependent:: LM32 Dependent Features 6462* KVX-Dependent:: KVX Dependent Features 6463* M32C-Dependent:: M32C Dependent Features 6464* M32R-Dependent:: M32R Dependent Features 6465* M68K-Dependent:: M680x0 Dependent Features 6466* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 6467* S12Z-Dependent:: S12Z Dependent Features 6468* Meta-Dependent :: Meta Dependent Features 6469* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 6470* MIPS-Dependent:: MIPS Dependent Features 6471* MMIX-Dependent:: MMIX Dependent Features 6472* MSP430-Dependent:: MSP430 Dependent Features 6473* NDS32-Dependent:: Andes NDS32 Dependent Features 6474* NiosII-Dependent:: Altera Nios II Dependent Features 6475* NS32K-Dependent:: NS32K Dependent Features 6476* OpenRISC-Dependent:: OpenRISC 1000 Features 6477* PDP-11-Dependent:: PDP-11 Dependent Features 6478* PJ-Dependent:: picoJava Dependent Features 6479* PPC-Dependent:: PowerPC Dependent Features 6480* PRU-Dependent:: PRU Dependent Features 6481* RISC-V-Dependent:: RISC-V Dependent Features 6482* RL78-Dependent:: RL78 Dependent Features 6483* RX-Dependent:: RX Dependent Features 6484* S/390-Dependent:: IBM S/390 Dependent Features 6485* SCORE-Dependent:: SCORE Dependent Features 6486* SH-Dependent:: Renesas / SuperH SH Dependent Features 6487* Sparc-Dependent:: SPARC Dependent Features 6488* TIC54X-Dependent:: TI TMS320C54x Dependent Features 6489* TIC6X-Dependent :: TI TMS320C6x Dependent Features 6490* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features 6491* TILEPro-Dependent :: Tilera TILEPro Dependent Features 6492* V850-Dependent:: V850 Dependent Features 6493* Vax-Dependent:: VAX Dependent Features 6494* Visium-Dependent:: Visium Dependent Features 6495* WebAssembly-Dependent:: WebAssembly Dependent Features 6496* XGATE-Dependent:: XGATE Dependent Features 6497* XSTORMY16-Dependent:: XStormy16 Dependent Features 6498* Xtensa-Dependent:: Xtensa Dependent Features 6499* Z80-Dependent:: Z80 Dependent Features 6500* Z8000-Dependent:: Z8000 Dependent Features 6501 6502 6503File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies 6504 65059.1 AArch64 Dependent Features 6506============================== 6507 6508* Menu: 6509 6510* AArch64 Options:: Options 6511* AArch64 Extensions:: Extensions 6512* AArch64 Syntax:: Syntax 6513* AArch64 Floating Point:: Floating Point 6514* AArch64 Directives:: AArch64 Machine Directives 6515* AArch64 Opcodes:: Opcodes 6516* AArch64 Mapping Symbols:: Mapping Symbols 6517 6518 6519File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent 6520 65219.1.1 Options 6522------------- 6523 6524‘-EB’ 6525 This option specifies that the output generated by the assembler 6526 should be marked as being encoded for a big-endian processor. 6527 6528‘-EL’ 6529 This option specifies that the output generated by the assembler 6530 should be marked as being encoded for a little-endian processor. 6531 6532‘-mabi=ABI’ 6533 Specify which ABI the source code uses. The recognized arguments 6534 are: ‘ilp32’ and ‘lp64’, which decides the generated object file in 6535 ELF32 and ELF64 format respectively. The default is ‘lp64’. 6536 6537‘-mcpu=PROCESSOR[+EXTENSION...]’ 6538 This option specifies the target processor. The assembler will 6539 issue an error message if an attempt is made to assemble an 6540 instruction which will not execute on the target processor. The 6541 following processor names are recognized: ‘cortex-a34’, 6542 ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, 6543 ‘cortex-a65’, ‘cortex-a65ae’, ‘cortex-a72’, ‘cortex-a73’, 6544 ‘cortex-a75’, ‘cortex-a76’, ‘cortex-a76ae’, ‘cortex-a77’, 6545 ‘cortex-a78’, ‘cortex-a78ae’, ‘cortex-a78c’, ‘cortex-a510’, 6546 ‘cortex-a520’, ‘cortex-a710’, ‘cortex-a720’, ‘ares’, ‘exynos-m1’, 6547 ‘falkor’, ‘neoverse-n1’, ‘neoverse-n2’, ‘neoverse-e1’, 6548 ‘neoverse-v1’, ‘qdf24xx’, ‘saphira’, ‘thunderx’, ‘vulcan’, ‘xgene1’ 6549 ‘xgene2’, ‘cortex-r82’, ‘cortex-x1’, ‘cortex-x2’, ‘cortex-x3’, and 6550 ‘cortex-x4’. The special name ‘all’ may be used to allow the 6551 assembler to accept instructions valid for any supported processor, 6552 including all optional extensions. 6553 6554 In addition to the basic instruction set, the assembler can be told 6555 to accept, or restrict, various extension mnemonics that extend the 6556 processor. *Note AArch64 Extensions::. 6557 6558 If some implementations of a particular processor can have an 6559 extension, then then those extensions are automatically enabled. 6560 Consequently, you will not normally have to specify any additional 6561 extensions. 6562 6563‘-march=ARCHITECTURE[+EXTENSION...]’ 6564 This option specifies the target architecture. The assembler will 6565 issue an error message if an attempt is made to assemble an 6566 instruction which will not execute on the target architecture. The 6567 following architecture names are recognized: ‘armv8-a’, 6568 ‘armv8.1-a’, ‘armv8.2-a’, ‘armv8.3-a’, ‘armv8.4-a’ ‘armv8.5-a’, 6569 ‘armv8.6-a’, ‘armv8.7-a’, ‘armv8.8-a’, ‘armv8.9-a’, ‘armv8-r’, 6570 ‘armv9-a’, ‘armv9.1-a’, ‘armv9.2-a’, ‘armv9.3-a’ and ‘armv9.4-a’. 6571 6572 If both ‘-mcpu’ and ‘-march’ are specified, the assembler will use 6573 the setting for ‘-mcpu’. If neither are specified, the assembler 6574 will default to ‘-mcpu=all’. 6575 6576 The architecture option can be extended with the same instruction 6577 set extension options as the ‘-mcpu’ option. Unlike ‘-mcpu’, 6578 extensions are not always enabled by default. *Note AArch64 6579 Extensions::. 6580 6581‘-mverbose-error’ 6582 This option enables verbose error messages for AArch64 gas. This 6583 option is enabled by default. 6584 6585‘-mno-verbose-error’ 6586 This option disables verbose error messages in AArch64 gas. 6587 6588 6589File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent 6590 65919.1.2 Architecture Extensions 6592----------------------------- 6593 6594The tables below lists the permitted architecture extensions and 6595architecture versions that are supported by the assembler, including a 6596brief description and a list of other extensions that they depend upon. 6597 6598 Multiple extensions may be specified, separated by a ‘+’. Extension 6599mnemonics may also be removed from those the assembler accepts. This is 6600done by prepending ‘no’ to the option that adds the extension. 6601Extensions that are removed must be listed after all extensions that 6602have been added. 6603 6604 Enabling an extension that depends upon other extensions (either 6605directly or recursively) will automatically cause those extensions to be 6606enabled. Similarly, disabling an extension that is required by other 6607extensions will automatically cause those extensions to be disabled. 6608 6609Extension Depends upon Description 6610---------------------------------------------------------------------------- 6611‘aes’ ‘simd’ Enable the AES and PMULL cryptographic 6612 extensions. 6613‘b16b16’ ‘sve2’ Enable BFloat16 to BFloat16 arithmetic for 6614 SVE2 and SME2. 6615‘bf16’ ‘fp’ Enable BFloat16 extension. 6616‘chk’ Enable the Check Feature Status Extension. 6617‘compnum’ ‘simd’ Enable the complex number SIMD extensions. 6618 An alias of ‘fcma’. 6619‘crc’ Enable CRC instructions. 6620‘crypto’ ‘simd’ Enable cryptographic extensions. This is 6621 equivalent to ‘aes+sha2’. 6622‘cssc’ Enable the Armv8.9-A Common Short Sequence 6623 Compression instructions. 6624‘d128’ ‘lse128’ Enable the 128-bit Page Descriptor 6625 Extension. This implies ‘lse128’. 6626‘dotprod’ ‘simd’ Enable the Dot Product extension. 6627‘f32mm’ ‘sve’ Enable the F32 Matrix Multiply extension 6628‘f64mm’ ‘sve’ Enable the F64 Matrix Multiply extension. 6629‘fcma’ ‘fp16’, ‘simd’ Enable the complex number SIMD extensions. 6630‘flagm’ Enable Flag Manipulation instructions. 6631‘flagm2’ ‘flagm’ Enable FlagM2 flag conversion instructions. 6632‘fp16fml’ ‘fp16’ Enable Armv8.2 16-bit floating-point 6633 multiplication variant support. 6634‘fp16’ ‘fp’ Enable Armv8.2 16-bit floating-point 6635 support. 6636‘fp’ Enable floating-point extensions. 6637‘frintts’ ‘simd’ Enable floating-point round to integral 6638 value instructions. 6639‘gcs’ Enable the Guarded Control Stack Extension. 6640‘hbc’ Enable Armv8.8-A hinted conditional branch 6641 instructions 6642‘i8mm’ ‘simd’ Enable the Int8 Matrix Multiply extension. 6643‘ite’ Enable the TRCIT instruction. 6644‘jscvt’ ‘fp’ Enable the ‘fjcvtzs’ JavaScript conversion 6645 instruction. 6646‘lor’ Enable Limited Ordering Regions extensions. 6647‘ls64’ Enable the 64 Byte Loads/Stores extensions. 6648‘lse’ Enable Large System extensions. 6649‘lse128’ ‘lse’ Enable the 128-bit Atomic Instructions 6650 extension. 6651‘memtag’ Enable Armv8.5-A Memory Tagging Extensions. 6652‘mops’ Enable Armv8.8-A memcpy and memset 6653 acceleration instructions 6654‘pan’ Enable Privileged Access Never support. 6655‘pauth’ Enable Pointer Authentication. 6656‘predres’ Enable the Execution and Data and 6657 Prediction instructions. 6658‘predres2’ ‘predres’ Enable Prediction instructions. 6659‘profile’ Enable statistical profiling extensions. 6660‘ras’ Enable the Reliability, Availability and 6661 Serviceability extension. 6662‘rasv2’ ‘ras’ Enable the Reliability, Availability and 6663 Serviceability extension v2. 6664‘rcpc’ Enable the Load-Acquire RCpc instructions 6665 extension. 6666‘rcpc2’ ‘rcpc’ Enable the Load-Acquire RCpc instructions 6667 extension v2. 6668‘rcpc3’ ‘rcpc2’ Enable the Load-Acquire RCpc instructions 6669 extension v3. 6670‘rdma’ ‘simd’ Enable rounding doubling multiply 6671 accumulate instructions. 6672‘rdm’ ‘simd’ An alias of ‘rdma’. 6673‘rng’ Enable Armv8.5-A random number 6674 instructions. 6675‘sb’ Enable the speculation barrier instruction 6676 sb. 6677‘sha2’ ‘simd’ Enable the SHA1 and SHA256 cryptographic 6678 extensions. 6679‘sha3’ ‘sha2’ Enable the SHA512 and SHA3 cryptographic 6680 extensions. 6681‘simd’ ‘fp’ Enable Advanced SIMD extensions. 6682‘sm4’ ‘simd’ Enable the SM3 and SM4 cryptographic 6683 extensions. 6684‘sme’ ‘sve2’, ‘bf16’ Enable the Scalable Matrix Extension. 6685‘sme-f64f64’ ‘sme’ Enable SME F64F64 Extension. 6686‘sme-i16i64’ ‘sme’ Enable SME I16I64 Extension. 6687‘sme2’ ‘sme’ Enable SME2. 6688‘sme2p1’ ‘sme2’ Enable SME2.1. 6689‘ssbs’ Enable Speculative Store Bypassing Safe 6690 state read and write. 6691‘sve’ ‘fcma’ Enable the Scalable Vector Extension. 6692‘sve2’ ‘sve’ Enable SVE2. 6693‘sve2-aes’ ‘sve2’, ‘aes’ Enable the SVE2 AES and PMULL Extensions. 6694‘sve2-bitperm’‘sve2’ Enable the SVE2 BITPERM Extension. 6695‘sve2-sha3’ ‘sve2’, ‘sha3’ Enable the SVE2 SHA3 Extension. 6696‘sve2-sm4’ ‘sve2’, ‘sm4’ Enable the SVE2 SM4 Extension. 6697‘sve2p1’ ‘sve2’ Enable SVE2.1. 6698‘the’ Enable the Translation Hardening Extension. 6699‘tme’ Enable the Transactional Memory Extension. 6700‘wfxt’ Enable ‘wfet’ and ‘wfit’ instructions. 6701‘xs’ Enable the XS memory attribute extension. 6702 6703Architecture Includes 6704Version 6705-------------------------------------------------------------------------- 6706‘armv8-a’ ‘simd’, ‘chk’, ‘ras’ 6707‘armv8.1-a’ ‘armv8-a’, ‘crc’, ‘lse’, ‘rdma’, ‘pan’, ‘lor’ 6708‘armv8.2-a’ ‘armv8.1-a’ 6709‘armv8.3-a’ ‘armv8.2-a’, ‘fcma’, ‘jscvt’, ‘pauth’, ‘rcpc’ 6710‘armv8.4-a’ ‘armv8.3-a’, ‘fp16fml’, ‘dotprod’, ‘flagm’, ‘rcpc2’ 6711‘armv8.5-a’ ‘armv8.4-a’, ‘frintts’, ‘flagm2’, ‘predres’, ‘sb’, 6712 ‘ssbs’ 6713‘armv8.6-a’ ‘armv8.5-a’, ‘bf16’, ‘i8mm’ 6714‘armv8.7-a’ ‘armv8.6-a’, ‘ls64’, ‘xs’, ‘wfxt’ 6715‘armv8.8-a’ ‘armv8.7-a’, ‘hbc’, ‘mops’ 6716‘armv8.9-a’ ‘armv8.8-a’, ‘rasv2’, ‘predres2’ 6717‘armv9-a’ ‘armv8.5-a’, ‘sve2’ 6718‘armv9.1-a’ ‘armv9-a’, ‘armv8.6-a’ 6719‘armv9.2-a’ ‘armv9.1-a’, ‘armv8.7-a’ 6720‘armv9.3-a’ ‘armv9.2-a’, ‘armv8.8-a’ 6721‘armv9.4-a’ ‘armv9.3-a’, ‘armv8.9-a’ 6722‘armv8-r’ ‘armv8.4-a+nolor’ 6723 6724 6725File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent 6726 67279.1.3 Syntax 6728------------ 6729 6730* Menu: 6731 6732* AArch64-Chars:: Special Characters 6733* AArch64-Regs:: Register Names 6734* AArch64-Relocations:: Relocations 6735 6736 6737File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax 6738 67399.1.3.1 Special Characters 6740.......................... 6741 6742The presence of a ‘//’ on a line indicates the start of a comment that 6743extends to the end of the current line. If a ‘#’ appears as the first 6744character of a line, the whole line is treated as a comment. 6745 6746 The ‘;’ character can be used instead of a newline to separate 6747statements. 6748 6749 The ‘#’ can be optionally used to indicate immediate operands. 6750 6751 6752File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax 6753 67549.1.3.2 Register Names 6755...................... 6756 6757Please refer to the section ‘4.4 Register Names’ of ‘ARMv8 Instruction 6758Set Overview’, which is available at <http://infocenter.arm.com>. 6759 6760 6761File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax 6762 67639.1.3.3 Relocations 6764................... 6765 6766Relocations for ‘MOVZ’ and ‘MOVK’ instructions can be generated by 6767prefixing the label with ‘#:abs_g2:’ etc. For example to load the 676848-bit absolute address of FOO into x0: 6769 6770 movz x0, #:abs_g2:foo // bits 32-47, overflow check 6771 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 6772 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 6773 6774 Relocations for ‘ADRP’, and ‘ADD’, ‘LDR’ or ‘STR’ instructions can be 6775generated by prefixing the label with ‘:pg_hi21:’ and ‘#:lo12:’ 6776respectively. 6777 6778 For example to use 33-bit (+/-4GB) pc-relative addressing to load the 6779address of FOO into x0: 6780 6781 adrp x0, :pg_hi21:foo 6782 add x0, x0, #:lo12:foo 6783 6784 Or to load the value of FOO into x0: 6785 6786 adrp x0, :pg_hi21:foo 6787 ldr x0, [x0, #:lo12:foo] 6788 6789 Note that ‘:pg_hi21:’ is optional. 6790 6791 adrp x0, foo 6792 6793 is equivalent to 6794 6795 adrp x0, :pg_hi21:foo 6796 6797 6798File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent 6799 68009.1.4 Floating Point 6801-------------------- 6802 6803The AArch64 architecture uses IEEE floating-point numbers. 6804 6805 6806File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent 6807 68089.1.5 AArch64 Machine Directives 6809-------------------------------- 6810 6811‘.arch NAME’ 6812 Select the target architecture. Valid values for NAME are the same 6813 as for the ‘-march’ command-line option. 6814 6815 Specifying ‘.arch’ clears any previously selected architecture 6816 extensions. 6817 6818‘.arch_extension NAME’ 6819 Add or remove an architecture extension to the target architecture. 6820 Valid values for NAME are the same as those accepted as 6821 architectural extensions by the ‘-mcpu’ command-line option. 6822 6823 ‘.arch_extension’ may be used multiple times to add or remove 6824 extensions incrementally to the architecture being compiled for. 6825 6826‘.cpu NAME’ 6827 Set the target processor. Valid values for NAME are the same as 6828 those accepted by the ‘-mcpu=’ command-line option. 6829 6830‘.dword EXPRESSIONS’ 6831 The ‘.dword’ directive produces 64 bit values. 6832 6833‘.even’ 6834 The ‘.even’ directive aligns the output on the next even byte 6835 boundary. 6836 6837‘.float16 VALUE [,...,VALUE_N]’ 6838 Place the half precision floating point representation of one or 6839 more floating-point values into the current section. The format 6840 used to encode the floating point values is always the IEEE 6841 754-2008 half precision floating point format. 6842 6843‘.inst EXPRESSIONS’ 6844 Inserts the expressions into the output as if they were 6845 instructions, rather than data. 6846 6847‘.ltorg’ 6848 This directive causes the current contents of the literal pool to 6849 be dumped into the current section (which is assumed to be the 6850 .text section) at the current location (aligned to a word 6851 boundary). GAS maintains a separate literal pool for each section 6852 and each sub-section. The ‘.ltorg’ directive will only affect the 6853 literal pool of the current section and sub-section. At the end of 6854 assembly all remaining, un-empty literal pools will automatically 6855 be dumped. 6856 6857 Note - older versions of GAS would dump the current literal pool 6858 any time a section change occurred. This is no longer done, since 6859 it prevents accurate control of the placement of literal pools. 6860 6861‘.pool’ 6862 This is a synonym for .ltorg. 6863 6864‘NAME .req REGISTER NAME’ 6865 This creates an alias for REGISTER NAME called NAME. For example: 6866 6867 foo .req w0 6868 6869 ip0, ip1, lr and fp are automatically defined to alias to X16, X17, 6870 X30 and X29 respectively. 6871 6872‘.tlsdescadd’ 6873 Emits a TLSDESC_ADD reloc on the next instruction. 6874 6875‘.tlsdesccall’ 6876 Emits a TLSDESC_CALL reloc on the next instruction. 6877 6878‘.tlsdescldr’ 6879 Emits a TLSDESC_LDR reloc on the next instruction. 6880 6881‘.unreq ALIAS-NAME’ 6882 This undefines a register alias which was previously defined using 6883 the ‘req’ directive. For example: 6884 6885 foo .req w0 6886 .unreq foo 6887 6888 An error occurs if the name is undefined. Note - this pseudo op 6889 can be used to delete builtin in register name aliases (eg ’w0’). 6890 This should only be done if it is really necessary. 6891 6892‘.variant_pcs SYMBOL’ 6893 This directive marks SYMBOL referencing a function that may follow 6894 a variant procedure call standard with different register usage 6895 convention from the base procedure call standard. 6896 6897‘.xword EXPRESSIONS’ 6898 The ‘.xword’ directive produces 64 bit values. This is the same as 6899 the ‘.dword’ directive. 6900 6901‘.cfi_b_key_frame’ 6902 The ‘.cfi_b_key_frame’ directive inserts a ’B’ character into the 6903 CIE corresponding to the current frame’s FDE, meaning that its 6904 return address has been signed with the B-key. If two frames are 6905 signed with differing keys then they will not share the same CIE. 6906 This information is intended to be used by the stack unwinder in 6907 order to properly authenticate return addresses. 6908 6909 6910File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent 6911 69129.1.6 Opcodes 6913------------- 6914 6915GAS implements all the standard AArch64 opcodes. It also implements 6916several pseudo opcodes, including several synthetic load instructions. 6917 6918‘LDR =’ 6919 ldr <register> , =<expression> 6920 6921 The constant expression will be placed into the nearest literal 6922 pool (if it not already there) and a PC-relative LDR instruction 6923 will be generated. 6924 6925 For more information on the AArch64 instruction set and assembly 6926language notation, see ‘ARMv8 Instruction Set Overview’ available at 6927<http://infocenter.arm.com>. 6928 6929 6930File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent 6931 69329.1.7 Mapping Symbols 6933--------------------- 6934 6935The AArch64 ELF specification requires that special symbols be inserted 6936into object files to mark certain features: 6937 6938‘$x’ 6939 At the start of a region of code containing AArch64 instructions. 6940 6941‘$d’ 6942 At the start of a region of data. 6943 6944 6945File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies 6946 69479.2 Alpha Dependent Features 6948============================ 6949 6950* Menu: 6951 6952* Alpha Notes:: Notes 6953* Alpha Options:: Options 6954* Alpha Syntax:: Syntax 6955* Alpha Floating Point:: Floating Point 6956* Alpha Directives:: Alpha Machine Directives 6957* Alpha Opcodes:: Opcodes 6958 6959 6960File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 6961 69629.2.1 Notes 6963----------- 6964 6965The documentation here is primarily for the ELF object format. ‘as’ 6966also supports the ECOFF and EVAX formats, but features specific to these 6967formats are not yet documented. 6968 6969 6970File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 6971 69729.2.2 Options 6973------------- 6974 6975‘-mCPU’ 6976 This option specifies the target processor. If an attempt is made 6977 to assemble an instruction which will not execute on the target 6978 processor, the assembler may either expand the instruction as a 6979 macro or issue an error message. This option is equivalent to the 6980 ‘.arch’ directive. 6981 6982 The following processor names are recognized: ‘21064’, ‘21064a’, 6983 ‘21066’, ‘21068’, ‘21164’, ‘21164a’, ‘21164pc’, ‘21264’, ‘21264a’, 6984 ‘21264b’, ‘ev4’, ‘ev5’, ‘lca45’, ‘ev5’, ‘ev56’, ‘pca56’, ‘ev6’, 6985 ‘ev67’, ‘ev68’. The special name ‘all’ may be used to allow the 6986 assembler to accept instructions valid for any Alpha processor. 6987 6988 In order to support existing practice in OSF/1 with respect to 6989 ‘.arch’, and existing practice within ‘MILO’ (the Linux ARC 6990 bootloader), the numbered processor names (e.g. 21064) enable the 6991 processor-specific PALcode instructions, while the “electro-vlasic” 6992 names (e.g. ‘ev4’) do not. 6993 6994‘-mdebug’ 6995‘-no-mdebug’ 6996 Enables or disables the generation of ‘.mdebug’ encapsulation for 6997 stabs directives and procedure descriptors. The default is to 6998 automatically enable ‘.mdebug’ when the first stabs directive is 6999 seen. 7000 7001‘-relax’ 7002 This option forces all relocations to be put into the object file, 7003 instead of saving space and resolving some relocations at assembly 7004 time. Note that this option does not propagate all symbol 7005 arithmetic into the object file, because not all symbol arithmetic 7006 can be represented. However, the option can still be useful in 7007 specific applications. 7008 7009‘-replace’ 7010‘-noreplace’ 7011 Enables or disables the optimization of procedure calls, both at 7012 assemblage and at link time. These options are only available for 7013 VMS targets and ‘-replace’ is the default. See section 1.4.1 of 7014 the OpenVMS Linker Utility Manual. 7015 7016‘-g’ 7017 This option is used when the compiler generates debug information. 7018 When ‘gcc’ is using ‘mips-tfile’ to generate debug information for 7019 ECOFF, local labels must be passed through to the object file. 7020 Otherwise this option has no effect. 7021 7022‘-GSIZE’ 7023 A local common symbol larger than SIZE is placed in ‘.bss’, while 7024 smaller symbols are placed in ‘.sbss’. 7025 7026‘-F’ 7027‘-32addr’ 7028 These options are ignored for backward compatibility. 7029 7030 7031File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 7032 70339.2.3 Syntax 7034------------ 7035 7036The assembler syntax closely follow the Alpha Reference Manual; 7037assembler directives and general syntax closely follow the OSF/1 and 7038OpenVMS syntax, with a few differences for ELF. 7039 7040* Menu: 7041 7042* Alpha-Chars:: Special Characters 7043* Alpha-Regs:: Register Names 7044* Alpha-Relocs:: Relocations 7045 7046 7047File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 7048 70499.2.3.1 Special Characters 7050.......................... 7051 7052‘#’ is the line comment character. Note that if ‘#’ is the first 7053character on a line then it can also be a logical line number directive 7054(*note Comments::) or a preprocessor control command (*note 7055Preprocessing::). 7056 7057 ‘;’ can be used instead of a newline to separate statements. 7058 7059 7060File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 7061 70629.2.3.2 Register Names 7063...................... 7064 7065The 32 integer registers are referred to as ‘$N’ or ‘$rN’. In addition, 7066registers 15, 28, 29, and 30 may be referred to by the symbols ‘$fp’, 7067‘$at’, ‘$gp’, and ‘$sp’ respectively. 7068 7069 The 32 floating-point registers are referred to as ‘$fN’. 7070 7071 7072File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 7073 70749.2.3.3 Relocations 7075................... 7076 7077Some of these relocations are available for ECOFF, but mostly only for 7078ELF. They are modeled after the relocation format introduced in Digital 7079Unix 4.0, but there are additions. 7080 7081 The format is ‘!TAG’ or ‘!TAG!NUMBER’ where TAG is the name of the 7082relocation. In some cases NUMBER is used to relate specific 7083instructions. 7084 7085 The relocation is placed at the end of the instruction like so: 7086 7087 ldah $0,a($29) !gprelhigh 7088 lda $0,a($0) !gprellow 7089 ldq $1,b($29) !literal!100 7090 ldl $2,0($1) !lituse_base!100 7091 7092‘!literal’ 7093‘!literal!N’ 7094 Used with an ‘ldq’ instruction to load the address of a symbol from 7095 the GOT. 7096 7097 A sequence number N is optional, and if present is used to pair 7098 ‘lituse’ relocations with this ‘literal’ relocation. The ‘lituse’ 7099 relocations are used by the linker to optimize the code based on 7100 the final location of the symbol. 7101 7102 Note that these optimizations are dependent on the data flow of the 7103 program. Therefore, if _any_ ‘lituse’ is paired with a ‘literal’ 7104 relocation, then _all_ uses of the register set by the ‘literal’ 7105 instruction must also be marked with ‘lituse’ relocations. This is 7106 because the original ‘literal’ instruction may be deleted or 7107 transformed into another instruction. 7108 7109 Also note that there may be a one-to-many relationship between 7110 ‘literal’ and ‘lituse’, but not a many-to-one. That is, if there 7111 are two code paths that load up the same address and feed the value 7112 to a single use, then the use may not use a ‘lituse’ relocation. 7113 7114‘!lituse_base!N’ 7115 Used with any memory format instruction (e.g. ‘ldl’) to indicate 7116 that the literal is used for an address load. The offset field of 7117 the instruction must be zero. During relaxation, the code may be 7118 altered to use a gp-relative load. 7119 7120‘!lituse_jsr!N’ 7121 Used with a register branch format instruction (e.g. ‘jsr’) to 7122 indicate that the literal is used for a call. During relaxation, 7123 the code may be altered to use a direct branch (e.g. ‘bsr’). 7124 7125‘!lituse_jsrdirect!N’ 7126 Similar to ‘lituse_jsr’, but also that this call cannot be vectored 7127 through a PLT entry. This is useful for functions with special 7128 calling conventions which do not allow the normal call-clobbered 7129 registers to be clobbered. 7130 7131‘!lituse_bytoff!N’ 7132 Used with a byte mask instruction (e.g. ‘extbl’) to indicate that 7133 only the low 3 bits of the address are relevant. During 7134 relaxation, the code may be altered to use an immediate instead of 7135 a register shift. 7136 7137‘!lituse_addr!N’ 7138 Used with any other instruction to indicate that the original 7139 address is in fact used, and the original ‘ldq’ instruction may not 7140 be altered or deleted. This is useful in conjunction with 7141 ‘lituse_jsr’ to test whether a weak symbol is defined. 7142 7143 ldq $27,foo($29) !literal!1 7144 beq $27,is_undef !lituse_addr!1 7145 jsr $26,($27),foo !lituse_jsr!1 7146 7147‘!lituse_tlsgd!N’ 7148 Used with a register branch format instruction to indicate that the 7149 literal is the call to ‘__tls_get_addr’ used to compute the address 7150 of the thread-local storage variable whose descriptor was loaded 7151 with ‘!tlsgd!N’. 7152 7153‘!lituse_tlsldm!N’ 7154 Used with a register branch format instruction to indicate that the 7155 literal is the call to ‘__tls_get_addr’ used to compute the address 7156 of the base of the thread-local storage block for the current 7157 module. The descriptor for the module must have been loaded with 7158 ‘!tlsldm!N’. 7159 7160‘!gpdisp!N’ 7161 Used with ‘ldah’ and ‘lda’ to load the GP from the current address, 7162 a-la the ‘ldgp’ macro. The source register for the ‘ldah’ 7163 instruction must contain the address of the ‘ldah’ instruction. 7164 There must be exactly one ‘lda’ instruction paired with the ‘ldah’ 7165 instruction, though it may appear anywhere in the instruction 7166 stream. The immediate operands must be zero. 7167 7168 bsr $26,foo 7169 ldah $29,0($26) !gpdisp!1 7170 lda $29,0($29) !gpdisp!1 7171 7172‘!gprelhigh’ 7173 Used with an ‘ldah’ instruction to add the high 16 bits of a 32-bit 7174 displacement from the GP. 7175 7176‘!gprellow’ 7177 Used with any memory format instruction to add the low 16 bits of a 7178 32-bit displacement from the GP. 7179 7180‘!gprel’ 7181 Used with any memory format instruction to add a 16-bit 7182 displacement from the GP. 7183 7184‘!samegp’ 7185 Used with any branch format instruction to skip the GP load at the 7186 target address. The referenced symbol must have the same GP as the 7187 source object file, and it must be declared to either not use ‘$27’ 7188 or perform a standard GP load in the first two instructions via the 7189 ‘.prologue’ directive. 7190 7191‘!tlsgd’ 7192‘!tlsgd!N’ 7193 Used with an ‘lda’ instruction to load the address of a TLS 7194 descriptor for a symbol in the GOT. 7195 7196 The sequence number N is optional, and if present it used to pair 7197 the descriptor load with both the ‘literal’ loading the address of 7198 the ‘__tls_get_addr’ function and the ‘lituse_tlsgd’ marking the 7199 call to that function. 7200 7201 For proper relaxation, both the ‘tlsgd’, ‘literal’ and ‘lituse’ 7202 relocations must be in the same extended basic block. That is, the 7203 relocation with the lowest address must be executed first at 7204 runtime. 7205 7206‘!tlsldm’ 7207‘!tlsldm!N’ 7208 Used with an ‘lda’ instruction to load the address of a TLS 7209 descriptor for the current module in the GOT. 7210 7211 Similar in other respects to ‘tlsgd’. 7212 7213‘!gotdtprel’ 7214 Used with an ‘ldq’ instruction to load the offset of the TLS symbol 7215 within its module’s thread-local storage block. Also known as the 7216 dynamic thread pointer offset or dtp-relative offset. 7217 7218‘!dtprelhi’ 7219‘!dtprello’ 7220‘!dtprel’ 7221 Like ‘gprel’ relocations except they compute dtp-relative offsets. 7222 7223‘!gottprel’ 7224 Used with an ‘ldq’ instruction to load the offset of the TLS symbol 7225 from the thread pointer. Also known as the tp-relative offset. 7226 7227‘!tprelhi’ 7228‘!tprello’ 7229‘!tprel’ 7230 Like ‘gprel’ relocations except they compute tp-relative offsets. 7231 7232 7233File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 7234 72359.2.4 Floating Point 7236-------------------- 7237 7238The Alpha family uses both IEEE and VAX floating-point numbers. 7239 7240 7241File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 7242 72439.2.5 Alpha Assembler Directives 7244-------------------------------- 7245 7246‘as’ for the Alpha supports many additional directives for compatibility 7247with the native assembler. This section describes them only briefly. 7248 7249 These are the additional directives in ‘as’ for the Alpha: 7250 7251‘.arch CPU’ 7252 Specifies the target processor. This is equivalent to the ‘-mCPU’ 7253 command-line option. *Note Options: Alpha Options, for a list of 7254 values for CPU. 7255 7256‘.ent FUNCTION[, N]’ 7257 Mark the beginning of FUNCTION. An optional number may follow for 7258 compatibility with the OSF/1 assembler, but is ignored. When 7259 generating ‘.mdebug’ information, this will create a procedure 7260 descriptor for the function. In ELF, it will mark the symbol as a 7261 function a-la the generic ‘.type’ directive. 7262 7263‘.end FUNCTION’ 7264 Mark the end of FUNCTION. In ELF, it will set the size of the 7265 symbol a-la the generic ‘.size’ directive. 7266 7267‘.mask MASK, OFFSET’ 7268 Indicate which of the integer registers are saved in the current 7269 function’s stack frame. MASK is interpreted a bit mask in which 7270 bit N set indicates that register N is saved. The registers are 7271 saved in a block located OFFSET bytes from the “canonical frame 7272 address” (CFA) which is the value of the stack pointer on entry to 7273 the function. The registers are saved sequentially, except that 7274 the return address register (normally ‘$26’) is saved first. 7275 7276 This and the other directives that describe the stack frame are 7277 currently only used when generating ‘.mdebug’ information. They 7278 may in the future be used to generate DWARF2 ‘.debug_frame’ unwind 7279 information for hand written assembly. 7280 7281‘.fmask MASK, OFFSET’ 7282 Indicate which of the floating-point registers are saved in the 7283 current stack frame. The MASK and OFFSET parameters are 7284 interpreted as with ‘.mask’. 7285 7286‘.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]’ 7287 Describes the shape of the stack frame. The frame pointer in use 7288 is FRAMEREG; normally this is either ‘$fp’ or ‘$sp’. The frame 7289 pointer is FRAMEOFFSET bytes below the CFA. The return address is 7290 initially located in RETREG until it is saved as indicated in 7291 ‘.mask’. For compatibility with OSF/1 an optional ARGOFFSET 7292 parameter is accepted and ignored. It is believed to indicate the 7293 offset from the CFA to the saved argument registers. 7294 7295‘.prologue N’ 7296 Indicate that the stack frame is set up and all registers have been 7297 spilled. The argument N indicates whether and how the function 7298 uses the incoming “procedure vector” (the address of the called 7299 function) in ‘$27’. 0 indicates that ‘$27’ is not used; 1 7300 indicates that the first two instructions of the function use ‘$27’ 7301 to perform a load of the GP register; 2 indicates that ‘$27’ is 7302 used in some non-standard way and so the linker cannot elide the 7303 load of the procedure vector during relaxation. 7304 7305‘.usepv FUNCTION, WHICH’ 7306 Used to indicate the use of the ‘$27’ register, similar to 7307 ‘.prologue’, but without the other semantics of needing to be 7308 inside an open ‘.ent’/‘.end’ block. 7309 7310 The WHICH argument should be either ‘no’, indicating that ‘$27’ is 7311 not used, or ‘std’, indicating that the first two instructions of 7312 the function perform a GP load. 7313 7314 One might use this directive instead of ‘.prologue’ if you are also 7315 using dwarf2 CFI directives. 7316 7317‘.gprel32 EXPRESSION’ 7318 Computes the difference between the address in EXPRESSION and the 7319 GP for the current object file, and stores it in 4 bytes. In 7320 addition to being smaller than a full 8 byte address, this also 7321 does not require a dynamic relocation when used in a shared 7322 library. 7323 7324‘.t_floating EXPRESSION’ 7325 Stores EXPRESSION as an IEEE double precision value. 7326 7327‘.s_floating EXPRESSION’ 7328 Stores EXPRESSION as an IEEE single precision value. 7329 7330‘.f_floating EXPRESSION’ 7331 Stores EXPRESSION as a VAX F format value. 7332 7333‘.g_floating EXPRESSION’ 7334 Stores EXPRESSION as a VAX G format value. 7335 7336‘.d_floating EXPRESSION’ 7337 Stores EXPRESSION as a VAX D format value. 7338 7339‘.set FEATURE’ 7340 Enables or disables various assembler features. Using the positive 7341 name of the feature enables while using ‘noFEATURE’ disables. 7342 7343 ‘at’ 7344 Indicates that macro expansions may clobber the “assembler 7345 temporary” (‘$at’ or ‘$28’) register. Some macros may not be 7346 expanded without this and will generate an error message if 7347 ‘noat’ is in effect. When ‘at’ is in effect, a warning will 7348 be generated if ‘$at’ is used by the programmer. 7349 7350 ‘macro’ 7351 Enables the expansion of macro instructions. Note that 7352 variants of real instructions, such as ‘br label’ vs ‘br 7353 $31,label’ are considered alternate forms and not macros. 7354 7355 ‘move’ 7356 ‘reorder’ 7357 ‘volatile’ 7358 These control whether and how the assembler may re-order 7359 instructions. Accepted for compatibility with the OSF/1 7360 assembler, but ‘as’ does not do instruction scheduling, so 7361 these features are ignored. 7362 7363 The following directives are recognized for compatibility with the 7364OSF/1 assembler but are ignored. 7365 7366 .proc .aproc 7367 .reguse .livereg 7368 .option .aent 7369 .ugen .eflag 7370 .alias .noalias 7371 7372 7373File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 7374 73759.2.6 Opcodes 7376------------- 7377 7378For detailed information on the Alpha machine instruction set, see the 7379Alpha Architecture Handbook 7380(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 7381 7382 7383File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 7384 73859.3 ARC Dependent Features 7386========================== 7387 7388* Menu: 7389 7390* ARC Options:: Options 7391* ARC Syntax:: Syntax 7392* ARC Directives:: ARC Machine Directives 7393* ARC Modifiers:: ARC Assembler Modifiers 7394* ARC Symbols:: ARC Pre-defined Symbols 7395* ARC Opcodes:: Opcodes 7396 7397 7398File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 7399 74009.3.1 Options 7401------------- 7402 7403The following options control the type of CPU for which code is 7404assembled, and generic constraints on the code generated: 7405 7406‘-mcpu=CPU’ 7407 Set architecture type and register usage for CPU. There are also 7408 shortcut alias options available for backward compatibility and 7409 convenience. Supported values for CPU are 7410 7411 ‘arc600’ 7412 Assemble for ARC 600. Aliases: ‘-mA6’, ‘-mARC600’. 7413 7414 ‘arc600_norm’ 7415 Assemble for ARC 600 with norm instructions. 7416 7417 ‘arc600_mul64’ 7418 Assemble for ARC 600 with mul64 instructions. 7419 7420 ‘arc600_mul32x16’ 7421 Assemble for ARC 600 with mul32x16 instructions. 7422 7423 ‘arc601’ 7424 Assemble for ARC 601. Alias: ‘-mARC601’. 7425 7426 ‘arc601_norm’ 7427 Assemble for ARC 601 with norm instructions. 7428 7429 ‘arc601_mul64’ 7430 Assemble for ARC 601 with mul64 instructions. 7431 7432 ‘arc601_mul32x16’ 7433 Assemble for ARC 601 with mul32x16 instructions. 7434 7435 ‘arc700’ 7436 Assemble for ARC 700. Aliases: ‘-mA7’, ‘-mARC700’. 7437 7438 ‘arcem’ 7439 Assemble for ARC EM. Aliases: ‘-mEM’ 7440 7441 ‘em’ 7442 Assemble for ARC EM, identical as arcem variant. 7443 7444 ‘em4’ 7445 Assemble for ARC EM with code-density instructions. 7446 7447 ‘em4_dmips’ 7448 Assemble for ARC EM with code-density instructions. 7449 7450 ‘em4_fpus’ 7451 Assemble for ARC EM with code-density instructions. 7452 7453 ‘em4_fpuda’ 7454 Assemble for ARC EM with code-density, and double-precision 7455 assist instructions. 7456 7457 ‘quarkse_em’ 7458 Assemble for QuarkSE-EM cpu. 7459 7460 ‘archs’ 7461 Assemble for ARC HS. Aliases: ‘-mHS’, ‘-mav2hs’. 7462 7463 ‘hs’ 7464 Assemble for ARC HS. 7465 7466 ‘hs34’ 7467 Assemble for ARC HS34. 7468 7469 ‘hs38’ 7470 Assemble for ARC HS38. 7471 7472 ‘hs38_linux’ 7473 Assemble for ARC HS38 with floating point support on. 7474 7475 ‘nps400’ 7476 Assemble for ARC 700 with NPS-400 extended instructions. 7477 7478 Note: the ‘.cpu’ directive (*note ARC Directives::) can to be used 7479 to select a core variant from within assembly code. 7480 7481‘-EB’ 7482 This option specifies that the output generated by the assembler 7483 should be marked as being encoded for a big-endian processor. 7484 7485‘-EL’ 7486 This option specifies that the output generated by the assembler 7487 should be marked as being encoded for a little-endian processor - 7488 this is the default. 7489 7490‘-mcode-density’ 7491 This option turns on Code Density instructions. Only valid for ARC 7492 EM processors. 7493 7494‘-mrelax’ 7495 Enable support for assembly-time relaxation. The assembler will 7496 replace a longer version of an instruction with a shorter one, 7497 whenever it is possible. 7498 7499‘-mnps400’ 7500 Enable support for NPS-400 extended instructions. 7501 7502‘-mspfp’ 7503 Enable support for single-precision floating point instructions. 7504 7505‘-mdpfp’ 7506 Enable support for double-precision floating point instructions. 7507 7508‘-mfpuda’ 7509 Enable support for double-precision assist floating point 7510 instructions. Only valid for ARC EM processors. 7511 7512 7513File: as.info, Node: ARC Syntax, Next: ARC Directives, Prev: ARC Options, Up: ARC-Dependent 7514 75159.3.2 Syntax 7516------------ 7517 7518* Menu: 7519 7520* ARC-Chars:: Special Characters 7521* ARC-Regs:: Register Names 7522 7523 7524File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 7525 75269.3.2.1 Special Characters 7527.......................... 7528 7529‘%’ 7530 A register name can optionally be prefixed by a ‘%’ character. So 7531 register ‘%r0’ is equivalent to ‘r0’ in the assembly code. 7532 7533‘#’ 7534 The presence of a ‘#’ character within a line (but not at the start 7535 of a line) indicates the start of a comment that extends to the end 7536 of the current line. 7537 7538 _Note:_ if a line starts with a ‘#’ character then it can also be a 7539 logical line number directive (*note Comments::) or a preprocessor 7540 control command (*note Preprocessing::). 7541 7542‘@’ 7543 Prefixing an operand with an ‘@’ specifies that the operand is a 7544 symbol and not a register. This is how the assembler disambiguates 7545 the use of an ARC register name as a symbol. So the instruction 7546 mov r0, @r0 7547 moves the address of symbol ‘r0’ into register ‘r0’. 7548 7549‘`’ 7550 The ‘`’ (backtick) character is used to separate statements on a 7551 single line. 7552 7553‘-’ 7554 Used as a separator to obtain a sequence of commands from a C 7555 preprocessor macro. 7556 7557 7558File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 7559 75609.3.2.2 Register Names 7561...................... 7562 7563The ARC assembler uses the following register names for its core 7564registers: 7565 7566‘r0-r31’ 7567 The core general registers. Registers ‘r26’ through ‘r31’ have 7568 special functions, and are usually referred to by those synonyms. 7569 7570‘gp’ 7571 The global pointer and a synonym for ‘r26’. 7572 7573‘fp’ 7574 The frame pointer and a synonym for ‘r27’. 7575 7576‘sp’ 7577 The stack pointer and a synonym for ‘r28’. 7578 7579‘ilink1’ 7580 For ARC 600 and ARC 700, the level 1 interrupt link register and a 7581 synonym for ‘r29’. Not supported for ARCv2. 7582 7583‘ilink’ 7584 For ARCv2, the interrupt link register and a synonym for ‘r29’. 7585 Not supported for ARC 600 and ARC 700. 7586 7587‘ilink2’ 7588 For ARC 600 and ARC 700, the level 2 interrupt link register and a 7589 synonym for ‘r30’. Not supported for ARC v2. 7590 7591‘blink’ 7592 The link register and a synonym for ‘r31’. 7593 7594‘r32-r59’ 7595 The extension core registers. 7596 7597‘lp_count’ 7598 The loop count register. 7599 7600‘pcl’ 7601 The word aligned program counter. 7602 7603 In addition the ARC processor has a large number of _auxiliary 7604registers_. The precise set depends on the extensions being supported, 7605but the following baseline set are always defined: 7606 7607‘identity’ 7608 Processor Identification register. Auxiliary register address 0x4. 7609 7610‘pc’ 7611 Program Counter. Auxiliary register address 0x6. 7612 7613‘status32’ 7614 Status register. Auxiliary register address 0x0a. 7615 7616‘bta’ 7617 Branch Target Address. Auxiliary register address 0x412. 7618 7619‘ecr’ 7620 Exception Cause Register. Auxiliary register address 0x403. 7621 7622‘int_vector_base’ 7623 Interrupt Vector Base address. Auxiliary register address 0x25. 7624 7625‘status32_p0’ 7626 Stored STATUS32 register on entry to level P0 interrupts. 7627 Auxiliary register address 0xb. 7628 7629‘aux_user_sp’ 7630 Saved User Stack Pointer. Auxiliary register address 0xd. 7631 7632‘eret’ 7633 Exception Return Address. Auxiliary register address 0x400. 7634 7635‘erbta’ 7636 BTA saved on exception entry. Auxiliary register address 0x401. 7637 7638‘erstatus’ 7639 STATUS32 saved on exception. Auxiliary register address 0x402. 7640 7641‘bcr_ver’ 7642 Build Configuration Registers Version. Auxiliary register address 7643 0x60. 7644 7645‘bta_link_build’ 7646 Build configuration for: BTA Registers. Auxiliary register address 7647 0x63. 7648 7649‘vecbase_ac_build’ 7650 Build configuration for: Interrupts. Auxiliary register address 7651 0x68. 7652 7653‘rf_build’ 7654 Build configuration for: Core Registers. Auxiliary register 7655 address 0x6e. 7656 7657‘dccm_build’ 7658 DCCM RAM Configuration Register. Auxiliary register address 0xc1. 7659 7660 Additional auxiliary register names are defined according to the 7661processor architecture version and extensions selected by the options. 7662 7663 7664File: as.info, Node: ARC Directives, Next: ARC Modifiers, Prev: ARC Syntax, Up: ARC-Dependent 7665 76669.3.3 ARC Machine Directives 7667---------------------------- 7668 7669The ARC version of ‘as’ supports the following additional machine 7670directives: 7671 7672‘.lcomm SYMBOL, LENGTH[, ALIGNMENT]’ 7673 Reserve LENGTH (an absolute expression) bytes for a local common 7674 denoted by SYMBOL. The section and value of SYMBOL are those of 7675 the new local common. The addresses are allocated in the bss 7676 section, so that at run-time the bytes start off zeroed. Since 7677 SYMBOL is not declared global, it is normally not visible to ‘ld’. 7678 The optional third parameter, ALIGNMENT, specifies the desired 7679 alignment of the symbol in the bss section, specified as a byte 7680 boundary (for example, an alignment of 16 means that the least 7681 significant 4 bits of the address should be zero). The alignment 7682 must be an absolute expression, and it must be a power of two. If 7683 no alignment is specified, as will set the alignment to the largest 7684 power of two less than or equal to the size of the symbol, up to a 7685 maximum of 16. 7686 7687‘.lcommon SYMBOL, LENGTH[, ALIGNMENT]’ 7688 The same as ‘lcomm’ directive. 7689 7690‘.cpu CPU’ 7691 The ‘.cpu’ directive must be followed by the desired core version. 7692 Permitted values for CPU are: 7693 ‘ARC600’ 7694 Assemble for the ARC600 instruction set. 7695 7696 ‘arc600_norm’ 7697 Assemble for ARC 600 with norm instructions. 7698 7699 ‘arc600_mul64’ 7700 Assemble for ARC 600 with mul64 instructions. 7701 7702 ‘arc600_mul32x16’ 7703 Assemble for ARC 600 with mul32x16 instructions. 7704 7705 ‘arc601’ 7706 Assemble for ARC 601 instruction set. 7707 7708 ‘arc601_norm’ 7709 Assemble for ARC 601 with norm instructions. 7710 7711 ‘arc601_mul64’ 7712 Assemble for ARC 601 with mul64 instructions. 7713 7714 ‘arc601_mul32x16’ 7715 Assemble for ARC 601 with mul32x16 instructions. 7716 7717 ‘ARC700’ 7718 Assemble for the ARC700 instruction set. 7719 7720 ‘NPS400’ 7721 Assemble for the NPS400 instruction set. 7722 7723 ‘EM’ 7724 Assemble for the ARC EM instruction set. 7725 7726 ‘arcem’ 7727 Assemble for ARC EM instruction set 7728 7729 ‘em4’ 7730 Assemble for ARC EM with code-density instructions. 7731 7732 ‘em4_dmips’ 7733 Assemble for ARC EM with code-density instructions. 7734 7735 ‘em4_fpus’ 7736 Assemble for ARC EM with code-density instructions. 7737 7738 ‘em4_fpuda’ 7739 Assemble for ARC EM with code-density, and double-precision 7740 assist instructions. 7741 7742 ‘quarkse_em’ 7743 Assemble for QuarkSE-EM instruction set. 7744 7745 ‘HS’ 7746 Assemble for the ARC HS instruction set. 7747 7748 ‘archs’ 7749 Assemble for ARC HS instruction set. 7750 7751 ‘hs’ 7752 Assemble for ARC HS instruction set. 7753 7754 ‘hs34’ 7755 Assemble for ARC HS34 instruction set. 7756 7757 ‘hs38’ 7758 Assemble for ARC HS38 instruction set. 7759 7760 ‘hs38_linux’ 7761 Assemble for ARC HS38 with floating point support on. 7762 7763 Note: the ‘.cpu’ directive overrides the command-line option 7764 ‘-mcpu=CPU’; a warning is emitted when the version is not 7765 consistent between the two. 7766 7767‘.extAuxRegister NAME, ADDR, MODE’ 7768 Auxiliary registers can be defined in the assembler source code by 7769 using this directive. The first parameter, NAME, is the name of 7770 the new auxiliary register. The second parameter, ADDR, is address 7771 the of the auxiliary register. The third parameter, MODE, 7772 specifies whether the register is readable and/or writable and is 7773 one of: 7774 ‘r’ 7775 Read only; 7776 7777 ‘w’ 7778 Write only; 7779 7780 ‘r|w’ 7781 Read and write. 7782 7783 For example: 7784 .extAuxRegister mulhi, 0x12, w 7785 specifies a write only extension auxiliary register, MULHI at 7786 address 0x12. 7787 7788‘.extCondCode SUFFIX, VAL’ 7789 ARC supports extensible condition codes. This directive defines a 7790 new condition code, to be known by the suffix, SUFFIX and will 7791 depend on the value, VAL in the condition code. 7792 7793 For example: 7794 .extCondCode is_busy,0x14 7795 add.is_busy r1,r2,r3 7796 will only execute the ‘add’ instruction if the condition code value 7797 is 0x14. 7798 7799‘.extCoreRegister NAME, REGNUM, MODE, SHORTCUT’ 7800 Specifies an extension core register named NAME as a synonym for 7801 the register numbered REGNUM. The register number must be between 7802 32 and 59. The third argument, MODE, indicates whether the 7803 register is readable and/or writable and is one of: 7804 ‘r’ 7805 Read only; 7806 7807 ‘w’ 7808 Write only; 7809 7810 ‘r|w’ 7811 Read and write. 7812 7813 The final parameter, SHORTCUT indicates whether the register has a 7814 short cut in the pipeline. The valid values are: 7815 ‘can_shortcut’ 7816 The register has a short cut in the pipeline; 7817 7818 ‘cannot_shortcut’ 7819 The register does not have a short cut in the pipeline. 7820 7821 For example: 7822 .extCoreRegister mlo, 57, r , can_shortcut 7823 defines a read only extension core register, ‘mlo’, which is 7824 register 57, and can short cut the pipeline. 7825 7826‘.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS’ 7827 ARC allows the user to specify extension instructions. These 7828 extension instructions are not macros; the assembler creates 7829 encodings for use of these instructions according to the 7830 specification by the user. 7831 7832 The first argument, NAME, gives the name of the instruction. 7833 7834 The second argument, OPCODE, is the opcode to be used (bits 31:27 7835 in the encoding). 7836 7837 The third argument, SUBOPCODE, is the sub-opcode to be used, but 7838 the correct value also depends on the fifth argument, SYNTAXCLASS 7839 7840 The fourth argument, SUFFIXCLASS, determines the kinds of suffixes 7841 to be allowed. Valid values are: 7842 ‘SUFFIX_NONE’ 7843 No suffixes are permitted; 7844 7845 ‘SUFFIX_COND’ 7846 Conditional suffixes are permitted; 7847 7848 ‘SUFFIX_FLAG’ 7849 Flag setting suffixes are permitted. 7850 7851 ‘SUFFIX_COND|SUFFIX_FLAG’ 7852 Both conditional and flag setting suffices are permitted. 7853 7854 The fifth and final argument, SYNTAXCLASS, determines the syntax 7855 class for the instruction. It can have the following values: 7856 ‘SYNTAX_2OP’ 7857 Two Operand Instruction; 7858 7859 ‘SYNTAX_3OP’ 7860 Three Operand Instruction. 7861 7862 ‘SYNTAX_1OP’ 7863 One Operand Instruction. 7864 7865 ‘SYNTAX_NOP’ 7866 No Operand Instruction. 7867 7868 The syntax class may be followed by ‘|’ and one of the following 7869 modifiers. 7870 7871 ‘OP1_MUST_BE_IMM’ 7872 Modifies syntax class ‘SYNTAX_3OP’, specifying that the first 7873 operand of a three-operand instruction must be an immediate 7874 (i.e., the result is discarded). This is usually used to set 7875 the flags using specific instructions and not retain results. 7876 7877 ‘OP1_IMM_IMPLIED’ 7878 Modifies syntax class ‘SYNTAX_20P’, specifying that there is 7879 an implied immediate destination operand which does not appear 7880 in the syntax. 7881 7882 For example, if the source code contains an instruction like: 7883 inst r1,r2 7884 the first argument is an implied immediate (that is, the 7885 result is discarded). This is the same as though the source 7886 code were: inst 0,r1,r2. 7887 7888 For example, defining a 64-bit multiplier with immediate operands: 7889 .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, 7890 SYNTAX_3OP|OP1_MUST_BE_IMM 7891 which specifies an extension instruction named ‘mp64’ with 3 7892 operands. It sets the flags and can be used with a condition code, 7893 for which the first operand is an immediate, i.e. equivalent to 7894 discarding the result of the operation. 7895 7896 A two operands instruction variant would be: 7897 .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, 7898 SYNTAX_2OP|OP1_IMM_IMPLIED 7899 which describes a two operand instruction with an implicit first 7900 immediate operand. The result of this operation would be 7901 discarded. 7902 7903‘.arc_attribute TAG, VALUE’ 7904 Set the ARC object attribute TAG to VALUE. 7905 7906 The TAG is either an attribute number, or one of the following: 7907 ‘Tag_ARC_PCS_config’, ‘Tag_ARC_CPU_base’, ‘Tag_ARC_CPU_variation’, 7908 ‘Tag_ARC_CPU_name’, ‘Tag_ARC_ABI_rf16’, ‘Tag_ARC_ABI_osver’, 7909 ‘Tag_ARC_ABI_sda’, ‘Tag_ARC_ABI_pic’, ‘Tag_ARC_ABI_tls’, 7910 ‘Tag_ARC_ABI_enumsize’, ‘Tag_ARC_ABI_exceptions’, 7911 ‘Tag_ARC_ABI_double_size’, ‘Tag_ARC_ISA_config’, 7912 ‘Tag_ARC_ISA_apex’, ‘Tag_ARC_ISA_mpy_option’ 7913 7914 The VALUE is either a ‘number’, ‘"string"’, or ‘number, "string"’ 7915 depending on the tag. 7916 7917 7918File: as.info, Node: ARC Modifiers, Next: ARC Symbols, Prev: ARC Directives, Up: ARC-Dependent 7919 79209.3.4 ARC Assembler Modifiers 7921----------------------------- 7922 7923The following additional assembler modifiers have been added for 7924position-independent code. These modifiers are available only with the 7925ARC 700 and above processors and generate relocation entries, which are 7926interpreted by the linker as follows: 7927 7928‘@pcl(SYMBOL)’ 7929 Relative distance of SYMBOL’s from the current program counter 7930 location. 7931 7932‘@gotpc(SYMBOL)’ 7933 Relative distance of SYMBOL’s Global Offset Table entry from the 7934 current program counter location. 7935 7936‘@gotoff(SYMBOL)’ 7937 Distance of SYMBOL from the base of the Global Offset Table. 7938 7939‘@plt(SYMBOL)’ 7940 Distance of SYMBOL’s Procedure Linkage Table entry from the current 7941 program counter. This is valid only with branch and link 7942 instructions and PC-relative calls. 7943 7944‘@sda(SYMBOL)’ 7945 Relative distance of SYMBOL from the base of the Small Data 7946 Pointer. 7947 7948 7949File: as.info, Node: ARC Symbols, Next: ARC Opcodes, Prev: ARC Modifiers, Up: ARC-Dependent 7950 79519.3.5 ARC Pre-defined Symbols 7952----------------------------- 7953 7954The following assembler symbols will prove useful when developing 7955position-independent code. These symbols are available only with the 7956ARC 700 and above processors. 7957 7958‘__GLOBAL_OFFSET_TABLE__’ 7959 Symbol referring to the base of the Global Offset Table. 7960 7961‘__DYNAMIC__’ 7962 An alias for the Global Offset Table ‘Base__GLOBAL_OFFSET_TABLE__’. 7963 It can be used only with ‘@gotpc’ modifiers. 7964 7965 7966File: as.info, Node: ARC Opcodes, Prev: ARC Symbols, Up: ARC-Dependent 7967 79689.3.6 Opcodes 7969------------- 7970 7971For information on the ARC instruction set, see ‘ARC Programmers 7972Reference Manual’, available where you download the processor IP 7973library. 7974 7975 7976File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 7977 79789.4 ARM Dependent Features 7979========================== 7980 7981* Menu: 7982 7983* ARM Options:: Options 7984* ARM Syntax:: Syntax 7985* ARM Floating Point:: Floating Point 7986* ARM Directives:: ARM Machine Directives 7987* ARM Opcodes:: Opcodes 7988* ARM Mapping Symbols:: Mapping Symbols 7989* ARM Unwinding Tutorial:: Unwinding 7990 7991 7992File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 7993 79949.4.1 Options 7995------------- 7996 7997‘-mcpu=PROCESSOR[+EXTENSION...]’ 7998 This option specifies the target processor. The assembler will 7999 issue an error message if an attempt is made to assemble an 8000 instruction which will not execute on the target processor. The 8001 following processor names are recognized: ‘arm1’, ‘arm2’, ‘arm250’, 8002 ‘arm3’, ‘arm6’, ‘arm60’, ‘arm600’, ‘arm610’, ‘arm620’, ‘arm7’, 8003 ‘arm7m’, ‘arm7d’, ‘arm7dm’, ‘arm7di’, ‘arm7dmi’, ‘arm70’, ‘arm700’, 8004 ‘arm700i’, ‘arm710’, ‘arm710t’, ‘arm720’, ‘arm720t’, ‘arm740t’, 8005 ‘arm710c’, ‘arm7100’, ‘arm7500’, ‘arm7500fe’, ‘arm7t’, ‘arm7tdmi’, 8006 ‘arm7tdmi-s’, ‘arm8’, ‘arm810’, ‘strongarm’, ‘strongarm1’, 8007 ‘strongarm110’, ‘strongarm1100’, ‘strongarm1110’, ‘arm9’, ‘arm920’, 8008 ‘arm920t’, ‘arm922t’, ‘arm940t’, ‘arm9tdmi’, ‘fa526’ (Faraday FA526 8009 processor), ‘fa626’ (Faraday FA626 processor), ‘arm9e’, ‘arm926e’, 8010 ‘arm926ej-s’, ‘arm946e-r0’, ‘arm946e’, ‘arm946e-s’, ‘arm966e-r0’, 8011 ‘arm966e’, ‘arm966e-s’, ‘arm968e-s’, ‘arm10t’, ‘arm10tdmi’, 8012 ‘arm10e’, ‘arm1020’, ‘arm1020t’, ‘arm1020e’, ‘arm1022e’, 8013 ‘arm1026ej-s’, ‘fa606te’ (Faraday FA606TE processor), ‘fa616te’ 8014 (Faraday FA616TE processor), ‘fa626te’ (Faraday FA626TE processor), 8015 ‘fmp626’ (Faraday FMP626 processor), ‘fa726te’ (Faraday FA726TE 8016 processor), ‘arm1136j-s’, ‘arm1136jf-s’, ‘arm1156t2-s’, 8017 ‘arm1156t2f-s’, ‘arm1176jz-s’, ‘arm1176jzf-s’, ‘mpcore’, 8018 ‘mpcorenovfp’, ‘cortex-a5’, ‘cortex-a7’, ‘cortex-a8’, ‘cortex-a9’, 8019 ‘cortex-a15’, ‘cortex-a17’, ‘cortex-a32’, ‘cortex-a35’, 8020 ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, ‘cortex-a72’, 8021 ‘cortex-a73’, ‘cortex-a75’, ‘cortex-a76’, ‘cortex-a76ae’, 8022 ‘cortex-a77’, ‘cortex-a78’, ‘cortex-a78ae’, ‘cortex-a78c’, 8023 ‘cortex-a710’, ‘ares’, ‘cortex-r4’, ‘cortex-r4f’, ‘cortex-r5’, 8024 ‘cortex-r7’, ‘cortex-r8’, ‘cortex-r52’, ‘cortex-r52plus’, 8025 ‘cortex-m35p’, ‘cortex-m33’, ‘cortex-m23’, ‘cortex-m7’, 8026 ‘cortex-m4’, ‘cortex-m3’, ‘cortex-m1’, ‘cortex-m0’, 8027 ‘cortex-m0plus’, ‘cortex-x1’, ‘cortex-x1c’, ‘exynos-m1’, 8028 ‘marvell-pj4’, ‘marvell-whitney’, ‘neoverse-n1’, ‘neoverse-n2’, 8029 ‘neoverse-v1’, ‘xgene1’, ‘xgene2’, ‘ep9312’ (ARM920 with Cirrus 8030 Maverick coprocessor), ‘i80200’ (Intel XScale processor) ‘iwmmxt’ 8031 (Intel XScale processor with Wireless MMX technology coprocessor) 8032 and ‘xscale’. The special name ‘all’ may be used to allow the 8033 assembler to accept instructions valid for any ARM processor. 8034 8035 In addition to the basic instruction set, the assembler can be told 8036 to accept various extension mnemonics that extend the processor 8037 using the co-processor instruction space. For example, 8038 ‘-mcpu=arm920+maverick’ is equivalent to specifying ‘-mcpu=ep9312’. 8039 8040 Multiple extensions may be specified, separated by a ‘+’. The 8041 extensions should be specified in ascending alphabetical order. 8042 8043 Some extensions may be restricted to particular architectures; this 8044 is documented in the list of extensions below. 8045 8046 Extension mnemonics may also be removed from those the assembler 8047 accepts. This is done be prepending ‘no’ to the option that adds 8048 the extension. Extensions that are removed should be listed after 8049 all extensions which have been added, again in ascending 8050 alphabetical order. For example, ‘-mcpu=ep9312+nomaverick’ is 8051 equivalent to specifying ‘-mcpu=arm920’. 8052 8053 The following extensions are currently supported: ‘bf16’ (BFloat16 8054 extensions for v8.6-A architecture), ‘i8mm’ (Int8 Matrix Multiply 8055 extensions for v8.6-A architecture), ‘crc’ ‘crypto’ (Cryptography 8056 Extensions for v8-A architecture, implies ‘fp+simd’), ‘dotprod’ 8057 (Dot Product Extensions for v8.2-A architecture, implies 8058 ‘fp+simd’), ‘fp’ (Floating Point Extensions for v8-A architecture), 8059 ‘fp16’ (FP16 Extensions for v8.2-A architecture, implies ‘fp’), 8060 ‘fp16fml’ (FP16 Floating Point Multiplication Variant Extensions 8061 for v8.2-A architecture, implies ‘fp16’), ‘idiv’ (Integer Divide 8062 Extensions for v7-A and v7-R architectures), ‘iwmmxt’, ‘iwmmxt2’, 8063 ‘xscale’, ‘maverick’, ‘mp’ (Multiprocessing Extensions for v7-A and 8064 v7-R architectures), ‘os’ (Operating System for v6M architecture), 8065 ‘predres’ (Execution and Data Prediction Restriction Instruction 8066 for v8-A architectures, added by default from v8.5-A), ‘sb’ 8067 (Speculation Barrier Instruction for v8-A architectures, added by 8068 default from v8.5-A), ‘sec’ (Security Extensions for v6K and v7-A 8069 architectures), ‘simd’ (Advanced SIMD Extensions for v8-A 8070 architecture, implies ‘fp’), ‘virt’ (Virtualization Extensions for 8071 v7-A architecture, implies ‘idiv’), ‘pan’ (Privileged Access Never 8072 Extensions for v8-A architecture), ‘ras’ (Reliability, Availability 8073 and Serviceability extensions for v8-A architecture), ‘rdma’ 8074 (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies 8075 ‘simd’) and ‘xscale’. 8076 8077‘-march=ARCHITECTURE[+EXTENSION...]’ 8078 This option specifies the target architecture. The assembler will 8079 issue an error message if an attempt is made to assemble an 8080 instruction which will not execute on the target architecture. The 8081 following architecture names are recognized: ‘armv1’, ‘armv2’, 8082 ‘armv2a’, ‘armv2s’, ‘armv3’, ‘armv3m’, ‘armv4’, ‘armv4xm’, 8083 ‘armv4t’, ‘armv4txm’, ‘armv5’, ‘armv5t’, ‘armv5txm’, ‘armv5te’, 8084 ‘armv5texp’, ‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6z’, ‘armv6kz’, 8085 ‘armv6-m’, ‘armv6s-m’, ‘armv7’, ‘armv7-a’, ‘armv7ve’, ‘armv7-r’, 8086 ‘armv7-m’, ‘armv7e-m’, ‘armv8-a’, ‘armv8.1-a’, ‘armv8.2-a’, 8087 ‘armv8.3-a’, ‘armv8-r’, ‘armv8.4-a’, ‘armv8.5-a’, ‘armv8-m.base’, 8088 ‘armv8-m.main’, ‘armv8.1-m.main’, ‘armv8.6-a’, ‘armv8.7-a’, 8089 ‘armv8.8-a’, ‘armv8.9-a’, ‘armv9-a’, ‘armv9.1-a’, ‘armv9.2-a’, 8090 ‘armv9.3-a’, ‘armv9.4-a’, ‘iwmmxt’, ‘iwmmxt2’ and ‘xscale’. If 8091 both ‘-mcpu’ and ‘-march’ are specified, the assembler will use the 8092 setting for ‘-mcpu’. 8093 8094 The architecture option can be extended with a set extension 8095 options. These extensions are context sensitive, i.e. the same 8096 extension may mean different things when used with different 8097 architectures. When used together with a ‘-mfpu’ option, the union 8098 of both feature enablement is taken. See their availability and 8099 meaning below: 8100 8101 For ‘armv5te’, ‘armv5texp’, ‘armv5tej’, ‘armv6’, ‘armv6j’, 8102 ‘armv6k’, ‘armv6z’, ‘armv6kz’, ‘armv6zk’, ‘armv6t2’, ‘armv6kt2’ and 8103 ‘armv6zt2’: 8104 8105 ‘+fp’: Enables VFPv2 instructions. 8106 ‘+nofp’: Disables all FPU instrunctions. 8107 8108 For ‘armv7’: 8109 8110 ‘+fp’: Enables VFPv3 instructions with 16 double-word 8111 registers. 8112 ‘+nofp’: Disables all FPU instructions. 8113 8114 For ‘armv7-a’: 8115 8116 ‘+fp’: Enables VFPv3 instructions with 16 double-word 8117 registers. 8118 ‘+vfpv3-d16’: Alias for ‘+fp’. 8119 ‘+vfpv3’: Enables VFPv3 instructions with 32 double-word 8120 registers. 8121 ‘+vfpv3-d16-fp16’: Enables VFPv3 with half precision 8122 floating-point conversion instructions and 16 double-word 8123 registers. 8124 ‘+vfpv3-fp16’: Enables VFPv3 with half precision 8125 floating-point conversion instructions and 32 double-word 8126 registers. 8127 ‘+vfpv4-d16’: Enables VFPv4 instructions with 16 double-word 8128 registers. 8129 ‘+vfpv4’: Enables VFPv4 instructions with 32 double-word 8130 registers. 8131 ‘+simd’: Enables VFPv3 and NEONv1 instructions with 32 8132 double-word registers. 8133 ‘+neon’: Alias for ‘+simd’. 8134 ‘+neon-vfpv3’: Alias for ‘+simd’. 8135 ‘+neon-fp16’: Enables VFPv3, half precision floating-point 8136 conversion and NEONv1 instructions with 32 double-word 8137 registers. 8138 ‘+neon-vfpv4’: Enables VFPv4 and NEONv1 with Fused-MAC 8139 instructions and 32 double-word registers. 8140 ‘+mp’: Enables Multiprocessing Extensions. 8141 ‘+sec’: Enables Security Extensions. 8142 ‘+nofp’: Disables all FPU and NEON instructions. 8143 ‘+nosimd’: Disables all NEON instructions. 8144 8145 For ‘armv7ve’: 8146 8147 ‘+fp’: Enables VFPv4 instructions with 16 double-word 8148 registers. 8149 ‘+vfpv4-d16’: Alias for ‘+fp’. 8150 ‘+vfpv3-d16’: Enables VFPv3 instructions with 16 double-word 8151 registers. 8152 ‘+vfpv3’: Enables VFPv3 instructions with 32 double-word 8153 registers. 8154 ‘+vfpv3-d16-fp16’: Enables VFPv3 with half precision 8155 floating-point conversion instructions and 16 double-word 8156 registers. 8157 ‘+vfpv3-fp16’: Enables VFPv3 with half precision 8158 floating-point conversion instructions and 32 double-word 8159 registers. 8160 ‘+vfpv4’: Enables VFPv4 instructions with 32 double-word 8161 registers. 8162 ‘+simd’: Enables VFPv4 and NEONv1 with Fused-MAC instructions 8163 and 32 double-word registers. 8164 ‘+neon-vfpv4’: Alias for ‘+simd’. 8165 ‘+neon’: Enables VFPv3 and NEONv1 instructions with 32 8166 double-word registers. 8167 ‘+neon-vfpv3’: Alias for ‘+neon’. 8168 ‘+neon-fp16’: Enables VFPv3, half precision floating-point 8169 conversion and NEONv1 instructions with 32 double-word 8170 registers. double-word registers. 8171 ‘+nofp’: Disables all FPU and NEON instructions. 8172 ‘+nosimd’: Disables all NEON instructions. 8173 8174 For ‘armv7-r’: 8175 8176 ‘+fp.sp’: Enables single-precision only VFPv3 instructions 8177 with 16 double-word registers. 8178 ‘+vfpv3xd’: Alias for ‘+fp.sp’. 8179 ‘+fp’: Enables VFPv3 instructions with 16 double-word 8180 registers. 8181 ‘+vfpv3-d16’: Alias for ‘+fp’. 8182 ‘+vfpv3xd-fp16’: Enables single-precision only VFPv3 and half 8183 floating-point conversion instructions with 16 double-word 8184 registers. 8185 ‘+vfpv3-d16-fp16’: Enables VFPv3 and half precision 8186 floating-point conversion instructions with 16 double-word 8187 registers. 8188 ‘+idiv’: Enables integer division instructions in ARM mode. 8189 ‘+nofp’: Disables all FPU instructions. 8190 8191 For ‘armv7e-m’: 8192 8193 ‘+fp’: Enables single-precision only VFPv4 instructions with 8194 16 double-word registers. 8195 ‘+vfpvf4-sp-d16’: Alias for ‘+fp’. 8196 ‘+fpv5’: Enables single-precision only VFPv5 instructions with 8197 16 double-word registers. 8198 ‘+fp.dp’: Enables VFPv5 instructions with 16 double-word 8199 registers. 8200 ‘+fpv5-d16"’: Alias for ‘+fp.dp’. 8201 ‘+nofp’: Disables all FPU instructions. 8202 8203 For ‘armv8-m.main’: 8204 8205 ‘+dsp’: Enables DSP Extension. 8206 ‘+fp’: Enables single-precision only VFPv5 instructions with 8207 16 double-word registers. 8208 ‘+fp.dp’: Enables VFPv5 instructions with 16 double-word 8209 registers. 8210 ‘+cdecp0’ (CDE extensions for v8-m architecture with 8211 coprocessor 0), 8212 ‘+cdecp1’ (CDE extensions for v8-m architecture with 8213 coprocessor 1), 8214 ‘+cdecp2’ (CDE extensions for v8-m architecture with 8215 coprocessor 2), 8216 ‘+cdecp3’ (CDE extensions for v8-m architecture with 8217 coprocessor 3), 8218 ‘+cdecp4’ (CDE extensions for v8-m architecture with 8219 coprocessor 4), 8220 ‘+cdecp5’ (CDE extensions for v8-m architecture with 8221 coprocessor 5), 8222 ‘+cdecp6’ (CDE extensions for v8-m architecture with 8223 coprocessor 6), 8224 ‘+cdecp7’ (CDE extensions for v8-m architecture with 8225 coprocessor 7), 8226 ‘+nofp’: Disables all FPU instructions. 8227 ‘+nodsp’: Disables DSP Extension. 8228 8229 For ‘armv8.1-m.main’: 8230 8231 ‘+dsp’: Enables DSP Extension. 8232 ‘+fp’: Enables single and half precision scalar Floating Point 8233 Extensions for Armv8.1-M Mainline with 16 double-word 8234 registers. 8235 ‘+fp.dp’: Enables double precision scalar Floating Point 8236 Extensions for Armv8.1-M Mainline, implies ‘+fp’. 8237 ‘+mve’: Enables integer only M-profile Vector Extension for 8238 Armv8.1-M Mainline, implies ‘+dsp’. 8239 ‘+mve.fp’: Enables Floating Point M-profile Vector Extension 8240 for Armv8.1-M Mainline, implies ‘+mve’ and ‘+fp’. 8241 ‘+nofp’: Disables all FPU instructions. 8242 ‘+nodsp’: Disables DSP Extension. 8243 ‘+nomve’: Disables all M-profile Vector Extensions. 8244 8245 For ‘armv8-a’: 8246 8247 ‘+crc’: Enables CRC32 Extension. 8248 ‘+simd’: Enables VFP and NEON for Armv8-A. 8249 ‘+crypto’: Enables Cryptography Extensions for Armv8-A, 8250 implies ‘+simd’. 8251 ‘+sb’: Enables Speculation Barrier Instruction for Armv8-A. 8252 ‘+predres’: Enables Execution and Data Prediction Restriction 8253 Instruction for Armv8-A. 8254 ‘+nofp’: Disables all FPU, NEON and Cryptography Extensions. 8255 ‘+nocrypto’: Disables Cryptography Extensions. 8256 8257 For ‘armv8.1-a’: 8258 8259 ‘+simd’: Enables VFP and NEON for Armv8.1-A. 8260 ‘+crypto’: Enables Cryptography Extensions for Armv8-A, 8261 implies ‘+simd’. 8262 ‘+sb’: Enables Speculation Barrier Instruction for Armv8-A. 8263 ‘+predres’: Enables Execution and Data Prediction Restriction 8264 Instruction for Armv8-A. 8265 ‘+nofp’: Disables all FPU, NEON and Cryptography Extensions. 8266 ‘+nocrypto’: Disables Cryptography Extensions. 8267 8268 For ‘armv8.2-a’ and ‘armv8.3-a’: 8269 8270 ‘+simd’: Enables VFP and NEON for Armv8.1-A. 8271 ‘+fp16’: Enables FP16 Extension for Armv8.2-A, implies 8272 ‘+simd’. 8273 ‘+fp16fml’: Enables FP16 Floating Point Multiplication Variant 8274 Extensions for Armv8.2-A, implies ‘+fp16’. 8275 ‘+crypto’: Enables Cryptography Extensions for Armv8-A, 8276 implies ‘+simd’. 8277 ‘+dotprod’: Enables Dot Product Extensions for Armv8.2-A, 8278 implies ‘+simd’. 8279 ‘+sb’: Enables Speculation Barrier Instruction for Armv8-A. 8280 ‘+predres’: Enables Execution and Data Prediction Restriction 8281 Instruction for Armv8-A. 8282 ‘+nofp’: Disables all FPU, NEON, Cryptography and Dot Product 8283 Extensions. 8284 ‘+nocrypto’: Disables Cryptography Extensions. 8285 8286 For ‘armv8.4-a’: 8287 8288 ‘+simd’: Enables VFP and NEON for Armv8.1-A and Dot Product 8289 Extensions for Armv8.2-A. 8290 ‘+fp16’: Enables FP16 Floating Point and Floating Point 8291 Multiplication Variant Extensions for Armv8.2-A, implies 8292 ‘+simd’. 8293 ‘+crypto’: Enables Cryptography Extensions for Armv8-A, 8294 implies ‘+simd’. 8295 ‘+sb’: Enables Speculation Barrier Instruction for Armv8-A. 8296 ‘+predres’: Enables Execution and Data Prediction Restriction 8297 Instruction for Armv8-A. 8298 ‘+nofp’: Disables all FPU, NEON, Cryptography and Dot Product 8299 Extensions. 8300 ‘+nocryptp’: Disables Cryptography Extensions. 8301 8302 For ‘armv8.5-a’: 8303 8304 ‘+simd’: Enables VFP and NEON for Armv8.1-A and Dot Product 8305 Extensions for Armv8.2-A. 8306 ‘+fp16’: Enables FP16 Floating Point and Floating Point 8307 Multiplication Variant Extensions for Armv8.2-A, implies 8308 ‘+simd’. 8309 ‘+crypto’: Enables Cryptography Extensions for Armv8-A, 8310 implies ‘+simd’. 8311 ‘+nofp’: Disables all FPU, NEON, Cryptography and Dot Product 8312 Extensions. 8313 ‘+nocryptp’: Disables Cryptography Extensions. 8314 8315‘-mfpu=FLOATING-POINT-FORMAT’ 8316 8317 This option specifies the floating point format to assemble for. 8318 The assembler will issue an error message if an attempt is made to 8319 assemble an instruction which will not execute on the target 8320 floating point unit. The following format options are recognized: 8321 ‘softfpa’, ‘fpe’, ‘fpe2’, ‘fpe3’, ‘fpa’, ‘fpa10’, ‘fpa11’, 8322 ‘arm7500fe’, ‘softvfp’, ‘softvfp+vfp’, ‘vfp’, ‘vfp10’, ‘vfp10-r0’, 8323 ‘vfp9’, ‘vfpxd’, ‘vfpv2’, ‘vfpv3’, ‘vfpv3-fp16’, ‘vfpv3-d16’, 8324 ‘vfpv3-d16-fp16’, ‘vfpv3xd’, ‘vfpv3xd-d16’, ‘vfpv4’, ‘vfpv4-d16’, 8325 ‘fpv4-sp-d16’, ‘fpv5-sp-d16’, ‘fpv5-d16’, ‘fp-armv8’, ‘arm1020t’, 8326 ‘arm1020e’, ‘arm1136jf-s’, ‘maverick’, ‘neon’, ‘neon-vfpv3’, 8327 ‘neon-fp16’, ‘neon-vfpv4’, ‘neon-fp-armv8’, ‘crypto-neon-fp-armv8’, 8328 ‘neon-fp-armv8.1’ and ‘crypto-neon-fp-armv8.1’. 8329 8330 In addition to determining which instructions are assembled, this 8331 option also affects the way in which the ‘.double’ assembler 8332 directive behaves when assembling little-endian code. 8333 8334 The default is dependent on the processor selected. For 8335 Architecture 5 or later, the default is to assemble for VFP 8336 instructions; for earlier architectures the default is to assemble 8337 for FPA instructions. 8338 8339‘-mfp16-format=FORMAT’ 8340 This option specifies the half-precision floating point format to 8341 use when assembling floating point numbers emitted by the 8342 ‘.float16’ directive. The following format options are recognized: 8343 ‘ieee’, ‘alternative’. If ‘ieee’ is specified then the IEEE 8344 754-2008 half-precision floating point format is used, if 8345 ‘alternative’ is specified then the Arm alternative half-precision 8346 format is used. If this option is set on the command line then the 8347 format is fixed and cannot be changed with the ‘float16_format’ 8348 directive. If this value is not set then the IEEE 754-2008 format 8349 is used until the format is explicitly set with the 8350 ‘float16_format’ directive. 8351 8352‘-mthumb’ 8353 This option specifies that the assembler should start assembling 8354 Thumb instructions; that is, it should behave as though the file 8355 starts with a ‘.code 16’ directive. 8356 8357‘-mthumb-interwork’ 8358 This option specifies that the output generated by the assembler 8359 should be marked as supporting interworking. It also affects the 8360 behaviour of the ‘ADR’ and ‘ADRL’ pseudo opcodes. 8361 8362‘-mimplicit-it=never’ 8363‘-mimplicit-it=always’ 8364‘-mimplicit-it=arm’ 8365‘-mimplicit-it=thumb’ 8366 The ‘-mimplicit-it’ option controls the behavior of the assembler 8367 when conditional instructions are not enclosed in IT blocks. There 8368 are four possible behaviors. If ‘never’ is specified, such 8369 constructs cause a warning in ARM code and an error in Thumb-2 8370 code. If ‘always’ is specified, such constructs are accepted in 8371 both ARM and Thumb-2 code, where the IT instruction is added 8372 implicitly. If ‘arm’ is specified, such constructs are accepted in 8373 ARM code and cause an error in Thumb-2 code. If ‘thumb’ is 8374 specified, such constructs cause a warning in ARM code and are 8375 accepted in Thumb-2 code. If you omit this option, the behavior is 8376 equivalent to ‘-mimplicit-it=arm’. 8377 8378‘-mapcs-26’ 8379‘-mapcs-32’ 8380 These options specify that the output generated by the assembler 8381 should be marked as supporting the indicated version of the Arm 8382 Procedure. Calling Standard. 8383 8384‘-matpcs’ 8385 This option specifies that the output generated by the assembler 8386 should be marked as supporting the Arm/Thumb Procedure Calling 8387 Standard. If enabled this option will cause the assembler to 8388 create an empty debugging section in the object file called 8389 .arm.atpcs. Debuggers can use this to determine the ABI being used 8390 by. 8391 8392‘-mapcs-float’ 8393 This indicates the floating point variant of the APCS should be 8394 used. In this variant floating point arguments are passed in FP 8395 registers rather than integer registers. 8396 8397‘-mapcs-reentrant’ 8398 This indicates that the reentrant variant of the APCS should be 8399 used. This variant supports position independent code. 8400 8401‘-mfloat-abi=ABI’ 8402 This option specifies that the output generated by the assembler 8403 should be marked as using specified floating point ABI. The 8404 following values are recognized: ‘soft’, ‘softfp’ and ‘hard’. 8405 8406‘-meabi=VER’ 8407 This option specifies which EABI version the produced object files 8408 should conform to. The following values are recognized: ‘gnu’, ‘4’ 8409 and ‘5’. 8410 8411‘-EB’ 8412 This option specifies that the output generated by the assembler 8413 should be marked as being encoded for a big-endian processor. 8414 8415 Note: If a program is being built for a system with big-endian data 8416 and little-endian instructions then it should be assembled with the 8417 ‘-EB’ option, (all of it, code and data) and then linked with the 8418 ‘--be8’ option. This will reverse the endianness of the 8419 instructions back to little-endian, but leave the data as 8420 big-endian. 8421 8422‘-EL’ 8423 This option specifies that the output generated by the assembler 8424 should be marked as being encoded for a little-endian processor. 8425 8426‘-k’ 8427 This option specifies that the output of the assembler should be 8428 marked as position-independent code (PIC). 8429 8430‘--fix-v4bx’ 8431 Allow ‘BX’ instructions in ARMv4 code. This is intended for use 8432 with the linker option of the same name. 8433 8434‘-mwarn-deprecated’ 8435‘-mno-warn-deprecated’ 8436 Enable or disable warnings about using deprecated options or 8437 features. The default is to warn. 8438 8439‘-mccs’ 8440 Turns on CodeComposer Studio assembly syntax compatibility mode. 8441 8442‘-mwarn-syms’ 8443‘-mno-warn-syms’ 8444 Enable or disable warnings about symbols that match the names of 8445 ARM instructions. The default is to warn. 8446 8447 8448File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 8449 84509.4.2 Syntax 8451------------ 8452 8453* Menu: 8454 8455* ARM-Instruction-Set:: Instruction Set 8456* ARM-Chars:: Special Characters 8457* ARM-Regs:: Register Names 8458* ARM-Relocations:: Relocations 8459* ARM-Neon-Alignment:: NEON Alignment Specifiers 8460 8461 8462File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 8463 84649.4.2.1 Instruction Set Syntax 8465.............................. 8466 8467Two slightly different syntaxes are support for ARM and THUMB 8468instructions. The default, ‘divided’, uses the old style where ARM and 8469THUMB instructions had their own, separate syntaxes. The new, ‘unified’ 8470syntax, which can be selected via the ‘.syntax’ directive, and has the 8471following main features: 8472 8473 • Immediate operands do not require a ‘#’ prefix. 8474 8475 • The ‘IT’ instruction may appear, and if it does it is validated 8476 against subsequent conditional affixes. In ARM mode it does not 8477 generate machine code, in THUMB mode it does. 8478 8479 • For ARM instructions the conditional affixes always appear at the 8480 end of the instruction. For THUMB instructions conditional affixes 8481 can be used, but only inside the scope of an ‘IT’ instruction. 8482 8483 • All of the instructions new to the V6T2 architecture (and later) 8484 are available. (Only a few such instructions can be written in the 8485 ‘divided’ syntax). 8486 8487 • The ‘.N’ and ‘.W’ suffixes are recognized and honored. 8488 8489 • All instructions set the flags if and only if they have an ‘s’ 8490 affix. 8491 8492 8493File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 8494 84959.4.2.2 Special Characters 8496.......................... 8497 8498The presence of a ‘@’ anywhere on a line indicates the start of a 8499comment that extends to the end of that line. 8500 8501 If a ‘#’ appears as the first character of a line then the whole line 8502is treated as a comment, but in this case the line could also be a 8503logical line number directive (*note Comments::) or a preprocessor 8504control command (*note Preprocessing::). 8505 8506 The ‘;’ character can be used instead of a newline to separate 8507statements. 8508 8509 Either ‘#’ or ‘$’ can be used to indicate immediate operands. 8510 8511 *TODO* Explain about /data modifier on symbols. 8512 8513 8514File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 8515 85169.4.2.3 Register Names 8517...................... 8518 8519*TODO* Explain about ARM register naming, and the predefined names. 8520 8521 8522File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 8523 85249.4.2.4 ARM relocation generation 8525................................. 8526 8527Specific data relocations can be generated by putting the relocation 8528name in parentheses after the symbol name. For example: 8529 8530 .word foo(TARGET1) 8531 8532 This will generate an ‘R_ARM_TARGET1’ relocation against the symbol 8533FOO. The following relocations are supported: ‘GOT’, ‘GOTOFF’, 8534‘TARGET1’, ‘TARGET2’, ‘SBREL’, ‘TLSGD’, ‘TLSLDM’, ‘TLSLDO’, ‘TLSDESC’, 8535‘TLSCALL’, ‘GOTTPOFF’, ‘GOT_PREL’ and ‘TPOFF’. 8536 8537 For compatibility with older toolchains the assembler also accepts 8538‘(PLT)’ after branch targets. On legacy targets this will generate the 8539deprecated ‘R_ARM_PLT32’ relocation. On EABI targets it will encode 8540either the ‘R_ARM_CALL’ or ‘R_ARM_JUMP24’ relocation, as appropriate. 8541 8542 Relocations for ‘MOVW’ and ‘MOVT’ instructions can be generated by 8543prefixing the value with ‘#:lower16:’ and ‘#:upper16’ respectively. For 8544example to load the 32-bit address of foo into r0: 8545 8546 MOVW r0, #:lower16:foo 8547 MOVT r0, #:upper16:foo 8548 8549 Relocations ‘R_ARM_THM_ALU_ABS_G0_NC’, ‘R_ARM_THM_ALU_ABS_G1_NC’, 8550‘R_ARM_THM_ALU_ABS_G2_NC’ and ‘R_ARM_THM_ALU_ABS_G3_NC’ can be generated 8551by prefixing the value with ‘#:lower0_7:#’, ‘#:lower8_15:#’, 8552‘#:upper0_7:#’ and ‘#:upper8_15:#’ respectively. For example to load 8553the 32-bit address of foo into r0: 8554 8555 MOVS r0, #:upper8_15:#foo 8556 LSLS r0, r0, #8 8557 ADDS r0, #:upper0_7:#foo 8558 LSLS r0, r0, #8 8559 ADDS r0, #:lower8_15:#foo 8560 LSLS r0, r0, #8 8561 ADDS r0, #:lower0_7:#foo 8562 8563 8564File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 8565 85669.4.2.5 NEON Alignment Specifiers 8567................................. 8568 8569Some NEON load/store instructions allow an optional address alignment 8570qualifier. The ARM documentation specifies that this is indicated by ‘@ 8571ALIGN’. However GAS already interprets the ‘@’ character as a "line 8572comment" start, so ‘: ALIGN’ is used instead. For example: 8573 8574 vld1.8 {q0}, [r0, :128] 8575 8576 8577File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 8578 85799.4.3 Floating Point 8580-------------------- 8581 8582The ARM family uses IEEE floating-point numbers. 8583 8584 8585File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 8586 85879.4.4 ARM Machine Directives 8588---------------------------- 8589 8590‘.align EXPRESSION [, EXPRESSION]’ 8591 This is the generic .ALIGN directive. For the ARM however if the 8592 first argument is zero (ie no alignment is needed) the assembler 8593 will behave as if the argument had been 2 (ie pad to the next four 8594 byte boundary). This is for compatibility with ARM’s own 8595 assembler. 8596 8597‘.arch NAME’ 8598 Select the target architecture. Valid values for NAME are the same 8599 as for the ‘-march’ command-line option without the instruction set 8600 extension. 8601 8602 Specifying ‘.arch’ clears any previously selected architecture 8603 extensions. 8604 8605‘.arch_extension NAME’ 8606 Add or remove an architecture extension to the target architecture. 8607 Valid values for NAME are the same as those accepted as 8608 architectural extensions by the ‘-mcpu’ and ‘-march’ command-line 8609 options. 8610 8611 ‘.arch_extension’ may be used multiple times to add or remove 8612 extensions incrementally to the architecture being compiled for. 8613 8614‘.arm’ 8615 This performs the same action as .CODE 32. 8616 8617‘.cantunwind’ 8618 Prevents unwinding through the current function. No personality 8619 routine or exception table data is required or permitted. 8620 8621‘.code [16|32]’ 8622 This directive selects the instruction set being generated. The 8623 value 16 selects Thumb, with the value 32 selecting ARM. 8624 8625‘.cpu NAME’ 8626 Select the target processor. Valid values for NAME are the same as 8627 for the ‘-mcpu’ command-line option without the instruction set 8628 extension. 8629 8630 Specifying ‘.cpu’ clears any previously selected architecture 8631 extensions. 8632 8633‘NAME .dn REGISTER NAME [.TYPE] [[INDEX]]’ 8634‘NAME .qn REGISTER NAME [.TYPE] [[INDEX]]’ 8635 8636 The ‘dn’ and ‘qn’ directives are used to create typed and/or 8637 indexed register aliases for use in Advanced SIMD Extension (Neon) 8638 instructions. The former should be used to create aliases of 8639 double-precision registers, and the latter to create aliases of 8640 quad-precision registers. 8641 8642 If these directives are used to create typed aliases, those aliases 8643 can be used in Neon instructions instead of writing types after the 8644 mnemonic or after each operand. For example: 8645 8646 x .dn d2.f32 8647 y .dn d3.f32 8648 z .dn d4.f32[1] 8649 vmul x,y,z 8650 8651 This is equivalent to writing the following: 8652 8653 vmul.f32 d2,d3,d4[1] 8654 8655 Aliases created using ‘dn’ or ‘qn’ can be destroyed using ‘unreq’. 8656 8657‘.eabi_attribute TAG, VALUE’ 8658 Set the EABI object attribute TAG to VALUE. 8659 8660 The TAG is either an attribute number, or one of the following: 8661 ‘Tag_CPU_raw_name’, ‘Tag_CPU_name’, ‘Tag_CPU_arch’, 8662 ‘Tag_CPU_arch_profile’, ‘Tag_ARM_ISA_use’, ‘Tag_THUMB_ISA_use’, 8663 ‘Tag_FP_arch’, ‘Tag_WMMX_arch’, ‘Tag_Advanced_SIMD_arch’, 8664 ‘Tag_MVE_arch’, ‘Tag_PCS_config’, ‘Tag_ABI_PCS_R9_use’, 8665 ‘Tag_ABI_PCS_RW_data’, ‘Tag_ABI_PCS_RO_data’, 8666 ‘Tag_ABI_PCS_GOT_use’, ‘Tag_ABI_PCS_wchar_t’, 8667 ‘Tag_ABI_FP_rounding’, ‘Tag_ABI_FP_denormal’, 8668 ‘Tag_ABI_FP_exceptions’, ‘Tag_ABI_FP_user_exceptions’, 8669 ‘Tag_ABI_FP_number_model’, ‘Tag_ABI_align_needed’, 8670 ‘Tag_ABI_align_preserved’, ‘Tag_ABI_enum_size’, 8671 ‘Tag_ABI_HardFP_use’, ‘Tag_ABI_VFP_args’, ‘Tag_ABI_WMMX_args’, 8672 ‘Tag_ABI_optimization_goals’, ‘Tag_ABI_FP_optimization_goals’, 8673 ‘Tag_compatibility’, ‘Tag_CPU_unaligned_access’, 8674 ‘Tag_FP_HP_extension’, ‘Tag_ABI_FP_16bit_format’, 8675 ‘Tag_MPextension_use’, ‘Tag_DIV_use’, ‘Tag_nodefaults’, 8676 ‘Tag_also_compatible_with’, ‘Tag_conformance’, ‘Tag_T2EE_use’, 8677 ‘Tag_Virtualization_use’ 8678 8679 The VALUE is either a ‘number’, ‘"string"’, or ‘number, "string"’ 8680 depending on the tag. 8681 8682 Note - the following legacy values are also accepted by TAG: 8683 ‘Tag_VFP_arch’, ‘Tag_ABI_align8_needed’, 8684 ‘Tag_ABI_align8_preserved’, ‘Tag_VFP_HP_extension’, 8685 8686‘.even’ 8687 This directive aligns to an even-numbered address. 8688 8689‘.extend EXPRESSION [, EXPRESSION]*’ 8690‘.ldouble EXPRESSION [, EXPRESSION]*’ 8691 These directives write 12byte long double floating-point values to 8692 the output section. These are not compatible with current ARM 8693 processors or ABIs. 8694 8695‘.float16 VALUE [,...,VALUE_N]’ 8696 Place the half precision floating point representation of one or 8697 more floating-point values into the current section. The exact 8698 format of the encoding is specified by ‘.float16_format’. If the 8699 format has not been explicitly set yet (either via the 8700 ‘.float16_format’ directive or the command line option) then the 8701 IEEE 754-2008 format is used. 8702 8703‘.float16_format FORMAT’ 8704 Set the format to use when encoding float16 values emitted by the 8705 ‘.float16’ directive. Once the format has been set it cannot be 8706 changed. ‘format’ should be one of the following: ‘ieee’ (encode 8707 in the IEEE 754-2008 half precision format) or ‘alternative’ 8708 (encode in the Arm alternative half precision format). 8709 8710‘.fnend’ 8711 Marks the end of a function with an unwind table entry. The unwind 8712 index table entry is created when this directive is processed. 8713 8714 If no personality routine has been specified then standard 8715 personality routine 0 or 1 will be used, depending on the number of 8716 unwind opcodes required. 8717 8718‘.fnstart’ 8719 Marks the start of a function with an unwind table entry. 8720 8721‘.force_thumb’ 8722 This directive forces the selection of Thumb instructions, even if 8723 the target processor does not support those instructions 8724 8725‘.fpu NAME’ 8726 Select the floating-point unit to assemble for. Valid values for 8727 NAME are the same as for the ‘-mfpu’ command-line option. 8728 8729‘.handlerdata’ 8730 Marks the end of the current function, and the start of the 8731 exception table entry for that function. Anything between this 8732 directive and the ‘.fnend’ directive will be added to the exception 8733 table entry. 8734 8735 Must be preceded by a ‘.personality’ or ‘.personalityindex’ 8736 directive. 8737 8738‘.inst OPCODE [ , ... ]’ 8739‘.inst.n OPCODE [ , ... ]’ 8740‘.inst.w OPCODE [ , ... ]’ 8741 Generates the instruction corresponding to the numerical value 8742 OPCODE. ‘.inst.n’ and ‘.inst.w’ allow the Thumb instruction size 8743 to be specified explicitly, overriding the normal encoding rules. 8744 8745‘.ldouble EXPRESSION [, EXPRESSION]*’ 8746 See ‘.extend’. 8747 8748‘.ltorg’ 8749 This directive causes the current contents of the literal pool to 8750 be dumped into the current section (which is assumed to be the 8751 .text section) at the current location (aligned to a word 8752 boundary). ‘GAS’ maintains a separate literal pool for each 8753 section and each sub-section. The ‘.ltorg’ directive will only 8754 affect the literal pool of the current section and sub-section. At 8755 the end of assembly all remaining, un-empty literal pools will 8756 automatically be dumped. 8757 8758 Note - older versions of ‘GAS’ would dump the current literal pool 8759 any time a section change occurred. This is no longer done, since 8760 it prevents accurate control of the placement of literal pools. 8761 8762‘.movsp REG [, #OFFSET]’ 8763 Tell the unwinder that REG contains an offset from the current 8764 stack pointer. If OFFSET is not specified then it is assumed to be 8765 zero. 8766 8767‘.object_arch NAME’ 8768 Override the architecture recorded in the EABI object attribute 8769 section. Valid values for NAME are the same as for the ‘.arch’ 8770 directive. Typically this is useful when code uses runtime 8771 detection of CPU features. 8772 8773‘.packed EXPRESSION [, EXPRESSION]*’ 8774 This directive writes 12-byte packed floating-point values to the 8775 output section. These are not compatible with current ARM 8776 processors or ABIs. 8777 8778‘.pacspval’ 8779 Generate unwinder annotations to use effective vsp as modifier in 8780 PAC validation. 8781 8782‘.pad #COUNT’ 8783 Generate unwinder annotations for a stack adjustment of COUNT 8784 bytes. A positive value indicates the function prologue allocated 8785 stack space by decrementing the stack pointer. 8786 8787‘.personality NAME’ 8788 Sets the personality routine for the current function to NAME. 8789 8790‘.personalityindex INDEX’ 8791 Sets the personality routine for the current function to the EABI 8792 standard routine number INDEX 8793 8794‘.pool’ 8795 This is a synonym for .ltorg. 8796 8797‘NAME .req REGISTER NAME’ 8798 This creates an alias for REGISTER NAME called NAME. For example: 8799 8800 foo .req r0 8801 8802‘.save REGLIST’ 8803 Generate unwinder annotations to restore the registers in REGLIST. 8804 The format of REGLIST is the same as the corresponding 8805 store-multiple instruction. 8806 8807 _core registers_ 8808 .save {r4, r5, r6, lr} 8809 stmfd sp!, {r4, r5, r6, lr} 8810 _FPA registers_ 8811 .save f4, 2 8812 sfmfd f4, 2, [sp]! 8813 _VFP registers_ 8814 .save {d8, d9, d10} 8815 fstmdx sp!, {d8, d9, d10} 8816 _iWMMXt registers_ 8817 .save {wr10, wr11} 8818 wstrd wr11, [sp, #-8]! 8819 wstrd wr10, [sp, #-8]! 8820 or 8821 .save wr11 8822 wstrd wr11, [sp, #-8]! 8823 .save wr10 8824 wstrd wr10, [sp, #-8]! 8825 8826‘.setfp FPREG, SPREG [, #OFFSET]’ 8827 Make all unwinder annotations relative to a frame pointer. Without 8828 this the unwinder will use offsets from the stack pointer. 8829 8830 The syntax of this directive is the same as the ‘add’ or ‘mov’ 8831 instruction used to set the frame pointer. SPREG must be either 8832 ‘sp’ or mentioned in a previous ‘.movsp’ directive. 8833 8834 .movsp ip 8835 mov ip, sp 8836 ... 8837 .setfp fp, ip, #4 8838 add fp, ip, #4 8839 8840‘.secrel32 EXPRESSION [, EXPRESSION]*’ 8841 This directive emits relocations that evaluate to the 8842 section-relative offset of each expression’s symbol. This 8843 directive is only supported for PE targets. 8844 8845‘.syntax [unified | divided]’ 8846 This directive sets the Instruction Set Syntax as described in the 8847 *note ARM-Instruction-Set:: section. 8848 8849‘.thumb’ 8850 This performs the same action as .CODE 16. 8851 8852‘.thumb_func’ 8853 This directive specifies that the following symbol is the name of a 8854 Thumb encoded function. This information is necessary in order to 8855 allow the assembler and linker to generate correct code for 8856 interworking between Arm and Thumb instructions and should be used 8857 even if interworking is not going to be performed. The presence of 8858 this directive also implies ‘.thumb’ 8859 8860 This directive is not necessary when generating EABI objects. On 8861 these targets the encoding is implicit when generating Thumb code. 8862 8863‘.thumb_set’ 8864 This performs the equivalent of a ‘.set’ directive in that it 8865 creates a symbol which is an alias for another symbol (possibly not 8866 yet defined). This directive also has the added property in that 8867 it marks the aliased symbol as being a thumb function entry point, 8868 in the same way that the ‘.thumb_func’ directive does. 8869 8870‘.tlsdescseq TLS-VARIABLE’ 8871 This directive is used to annotate parts of an inlined TLS 8872 descriptor trampoline. Normally the trampoline is provided by the 8873 linker, and this directive is not needed. 8874 8875‘.unreq ALIAS-NAME’ 8876 This undefines a register alias which was previously defined using 8877 the ‘req’, ‘dn’ or ‘qn’ directives. For example: 8878 8879 foo .req r0 8880 .unreq foo 8881 8882 An error occurs if the name is undefined. Note - this pseudo op 8883 can be used to delete builtin in register name aliases (eg ’r0’). 8884 This should only be done if it is really necessary. 8885 8886‘.unwind_raw OFFSET, BYTE1, ...’ 8887 Insert one of more arbitrary unwind opcode bytes, which are known 8888 to adjust the stack pointer by OFFSET bytes. 8889 8890 For example ‘.unwind_raw 4, 0xb1, 0x01’ is equivalent to ‘.save 8891 {r0}’ 8892 8893‘.vsave VFP-REGLIST’ 8894 Generate unwinder annotations to restore the VFP registers in 8895 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to 8896 be restored using VLDM. The format of VFP-REGLIST is the same as 8897 the corresponding store-multiple instruction. 8898 8899 _VFP registers_ 8900 .vsave {d8, d9, d10} 8901 fstmdd sp!, {d8, d9, d10} 8902 _VFPv3 registers_ 8903 .vsave {d15, d16, d17} 8904 vstm sp!, {d15, d16, d17} 8905 8906 Since FLDMX and FSTMX are now deprecated, this directive should be 8907 used in favour of ‘.save’ for saving VFP registers for ARMv6 and 8908 above. 8909 8910 8911File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 8912 89139.4.5 Opcodes 8914------------- 8915 8916‘as’ implements all the standard ARM opcodes. It also implements 8917several pseudo opcodes, including several synthetic load instructions. 8918 8919‘NOP’ 8920 nop 8921 8922 This pseudo op will always evaluate to a legal ARM instruction that 8923 does nothing. Currently it will evaluate to MOV r0, r0. 8924 8925‘LDR’ 8926 ldr <register> , = <expression> 8927 8928 If expression evaluates to a numeric constant then a MOV or MVN 8929 instruction will be used in place of the LDR instruction, if the 8930 constant can be generated by either of these instructions. 8931 Otherwise the constant will be placed into the nearest literal pool 8932 (if it not already there) and a PC relative LDR instruction will be 8933 generated. 8934 8935‘ADR’ 8936 adr <register> <label> 8937 8938 This instruction will load the address of LABEL into the indicated 8939 register. The instruction will evaluate to a PC relative ADD or 8940 SUB instruction depending upon where the label is located. If the 8941 label is out of range, or if it is not defined in the same file 8942 (and section) as the ADR instruction, then an error will be 8943 generated. This instruction will not make use of the literal pool. 8944 8945 If LABEL is a thumb function symbol, and thumb interworking has 8946 been enabled via the ‘-mthumb-interwork’ option then the bottom bit 8947 of the value stored into REGISTER will be set. This allows the 8948 following sequence to work as expected: 8949 8950 adr r0, thumb_function 8951 blx r0 8952 8953‘ADRL’ 8954 adrl <register> <label> 8955 8956 This instruction will load the address of LABEL into the indicated 8957 register. The instruction will evaluate to one or two PC relative 8958 ADD or SUB instructions depending upon where the label is located. 8959 If a second instruction is not needed a NOP instruction will be 8960 generated in its place, so that this instruction is always 8 bytes 8961 long. 8962 8963 If the label is out of range, or if it is not defined in the same 8964 file (and section) as the ADRL instruction, then an error will be 8965 generated. This instruction will not make use of the literal pool. 8966 8967 If LABEL is a thumb function symbol, and thumb interworking has 8968 been enabled via the ‘-mthumb-interwork’ option then the bottom bit 8969 of the value stored into REGISTER will be set. 8970 8971 For information on the ARM or Thumb instruction sets, see ‘ARM 8972Software Development Toolkit Reference Manual’, Advanced RISC Machines 8973Ltd. 8974 8975 8976File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 8977 89789.4.6 Mapping Symbols 8979--------------------- 8980 8981The ARM ELF specification requires that special symbols be inserted into 8982object files to mark certain features: 8983 8984‘$a’ 8985 At the start of a region of code containing ARM instructions. 8986 8987‘$t’ 8988 At the start of a region of code containing THUMB instructions. 8989 8990‘$d’ 8991 At the start of a region of data. 8992 8993 The assembler will automatically insert these symbols for you - there 8994is no need to code them yourself. Support for tagging symbols ($b, $f, 8995$p and $m) which is also mentioned in the current ARM ELF specification 8996is not implemented. This is because they have been dropped from the new 8997EABI and so tools cannot rely upon their presence. 8998 8999 9000File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 9001 90029.4.7 Unwinding 9003--------------- 9004 9005The ABI for the ARM Architecture specifies a standard format for 9006exception unwind information. This information is used when an 9007exception is thrown to determine where control should be transferred. 9008In particular, the unwind information is used to determine which 9009function called the function that threw the exception, and which 9010function called that one, and so forth. This information is also used 9011to restore the values of callee-saved registers in the function catching 9012the exception. 9013 9014 If you are writing functions in assembly code, and those functions 9015call other functions that throw exceptions, you must use assembly pseudo 9016ops to ensure that appropriate exception unwind information is 9017generated. Otherwise, if one of the functions called by your assembly 9018code throws an exception, the run-time library will be unable to unwind 9019the stack through your assembly code and your program will not behave 9020correctly. 9021 9022 To illustrate the use of these pseudo ops, we will examine the code 9023that G++ generates for the following C++ input: 9024 9025void callee (int *); 9026 9027int 9028caller () 9029{ 9030 int i; 9031 callee (&i); 9032 return i; 9033} 9034 9035 This example does not show how to throw or catch an exception from 9036assembly code. That is a much more complex operation and should always 9037be done in a high-level language, such as C++, that directly supports 9038exceptions. 9039 9040 The code generated by one particular version of G++ when compiling 9041the example above is: 9042 9043_Z6callerv: 9044 .fnstart 9045.LFB2: 9046 @ Function supports interworking. 9047 @ args = 0, pretend = 0, frame = 8 9048 @ frame_needed = 1, uses_anonymous_args = 0 9049 stmfd sp!, {fp, lr} 9050 .save {fp, lr} 9051.LCFI0: 9052 .setfp fp, sp, #4 9053 add fp, sp, #4 9054.LCFI1: 9055 .pad #8 9056 sub sp, sp, #8 9057.LCFI2: 9058 sub r3, fp, #8 9059 mov r0, r3 9060 bl _Z6calleePi 9061 ldr r3, [fp, #-8] 9062 mov r0, r3 9063 sub sp, fp, #4 9064 ldmfd sp!, {fp, lr} 9065 bx lr 9066.LFE2: 9067 .fnend 9068 9069 Of course, the sequence of instructions varies based on the options 9070you pass to GCC and on the version of GCC in use. The exact 9071instructions are not important since we are focusing on the pseudo ops 9072that are used to generate unwind information. 9073 9074 An important assumption made by the unwinder is that the stack frame 9075does not change during the body of the function. In particular, since 9076we assume that the assembly code does not itself throw an exception, the 9077only point where an exception can be thrown is from a call, such as the 9078‘bl’ instruction above. At each call site, the same saved registers 9079(including ‘lr’, which indicates the return address) must be located in 9080the same locations relative to the frame pointer. 9081 9082 The ‘.fnstart’ (*note .fnstart pseudo op: arm_fnstart.) pseudo op 9083appears immediately before the first instruction of the function while 9084the ‘.fnend’ (*note .fnend pseudo op: arm_fnend.) pseudo op appears 9085immediately after the last instruction of the function. These pseudo 9086ops specify the range of the function. 9087 9088 Only the order of the other pseudos ops (e.g., ‘.setfp’ or ‘.pad’) 9089matters; their exact locations are irrelevant. In the example above, 9090the compiler emits the pseudo ops with particular instructions. That 9091makes it easier to understand the code, but it is not required for 9092correctness. It would work just as well to emit all of the pseudo ops 9093other than ‘.fnend’ in the same order, but immediately after ‘.fnstart’. 9094 9095 The ‘.save’ (*note .save pseudo op: arm_save.) pseudo op indicates 9096registers that have been saved to the stack so that they can be restored 9097before the function returns. The argument to the ‘.save’ pseudo op is a 9098list of registers to save. If a register is “callee-saved” (as 9099specified by the ABI) and is modified by the function you are writing, 9100then your code must save the value before it is modified and restore the 9101original value before the function returns. If an exception is thrown, 9102the run-time library restores the values of these registers from their 9103locations on the stack before returning control to the exception 9104handler. (Of course, if an exception is not thrown, the function that 9105contains the ‘.save’ pseudo op restores these registers in the function 9106epilogue, as is done with the ‘ldmfd’ instruction above.) 9107 9108 You do not have to save callee-saved registers at the very beginning 9109of the function and you do not need to use the ‘.save’ pseudo op 9110immediately following the point at which the registers are saved. 9111However, if you modify a callee-saved register, you must save it on the 9112stack before modifying it and before calling any functions which might 9113throw an exception. And, you must use the ‘.save’ pseudo op to indicate 9114that you have done so. 9115 9116 The ‘.pad’ (*note .pad: arm_pad.) pseudo op indicates a modification 9117of the stack pointer that does not save any registers. The argument is 9118the number of bytes (in decimal) that are subtracted from the stack 9119pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 9120the stack pointer increases the size of the stack.) 9121 9122 The ‘.setfp’ (*note .setfp pseudo op: arm_setfp.) pseudo op indicates 9123the register that contains the frame pointer. The first argument is the 9124register that is set, which is typically ‘fp’. The second argument 9125indicates the register from which the frame pointer takes its value. 9126The third argument, if present, is the value (in decimal) added to the 9127register specified by the second argument to compute the value of the 9128frame pointer. You should not modify the frame pointer in the body of 9129the function. 9130 9131 If you do not use a frame pointer, then you should not use the 9132‘.setfp’ pseudo op. If you do not use a frame pointer, then you should 9133avoid modifying the stack pointer outside of the function prologue. 9134Otherwise, the run-time library will be unable to find saved registers 9135when it is unwinding the stack. 9136 9137 The pseudo ops described above are sufficient for writing assembly 9138code that calls functions which may throw exceptions. If you need to 9139know more about the object-file format used to represent unwind 9140information, you may consult the ‘Exception Handling ABI for the ARM 9141Architecture’ available from <http://infocenter.arm.com>. 9142 9143 9144File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 9145 91469.5 AVR Dependent Features 9147========================== 9148 9149* Menu: 9150 9151* AVR Options:: Options 9152* AVR Syntax:: Syntax 9153* AVR Opcodes:: Opcodes 9154* AVR Pseudo Instructions:: Pseudo Instructions 9155 9156 9157File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 9158 91599.5.1 Options 9160------------- 9161 9162‘-mmcu=MCU’ 9163 Specify ATMEL AVR instruction set or MCU type. 9164 9165 Instruction set avr1 is for the minimal AVR core, not supported by 9166 the C compiler, only for assembler programs (MCU types: at90s1200, 9167 attiny11, attiny12, attiny15, attiny28). 9168 9169 Instruction set avr2 (default) is for the classic AVR core with up 9170 to 8K program memory space (MCU types: at90s2313, at90s2323, 9171 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 9172 at90s4434, at90s8515, at90c8534, at90s8535). 9173 9174 Instruction set avr25 is for the classic AVR core with up to 8K 9175 program memory space plus the MOVW instruction (MCU types: 9176 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 9177 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 9178 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 9179 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 9180 attiny828, at86rf401, ata6289, ata5272). 9181 9182 Instruction set avr3 is for the classic AVR core with up to 128K 9183 program memory space (MCU types: at43usb355, at76c711). 9184 9185 Instruction set avr31 is for the classic AVR core with exactly 128K 9186 program memory space (MCU types: atmega103, at43usb320). 9187 9188 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 9189 JMP instructions (MCU types: attiny167, attiny1634, at90usb82, 9190 at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505). 9191 9192 Instruction set avr4 is for the enhanced AVR core with up to 8K 9193 program memory space (MCU types: atmega48, atmega48a, atmega48pa, 9194 atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p, 9195 atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, 9196 at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285, ata6286). 9197 9198 Instruction set avr5 is for the enhanced AVR core with up to 128K 9199 program memory space (MCU types: at90pwm161, atmega16, atmega16a, 9200 atmega161, atmega162, atmega163, atmega164a, atmega164p, 9201 atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, 9202 atmega168, atmega168a, atmega168p, atmega168pa, atmega169, 9203 atmega169a, atmega169p, atmega169pa, atmega32, atmega323, 9204 atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, 9205 atmega32, atmega32a, atmega323, atmega324a, atmega324p, 9206 atmega324pa, atmega325, atmega325a, atmega325p, atmega325p, 9207 atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, 9208 atmega328, atmega328p, atmega329, atmega329a, atmega329p, 9209 atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406, 9210 atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640, 9211 atmega644, atmega644a, atmega644p, atmega644pa, atmega645, 9212 atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, 9213 atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, 9214 atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, 9215 atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, 9216 at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, 9217 atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, 9218 atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, 9219 at90scr100, ata5790, ata5795). 9220 9221 Instruction set avr51 is for the enhanced AVR core with exactly 9222 128K program memory space (MCU types: atmega128, atmega128a, 9223 atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, 9224 atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 9225 at90usb1287, m3000). 9226 9227 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 9228 (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 9229 9230 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 9231 program memory space and less than 64K data space (MCU types: 9232 atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, 9233 atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, 9234 atxmega8e5, atxmega32e5, atxmega32x1). 9235 9236 Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K 9237 of combined program memory and RAM, and with program memory visible 9238 in the RAM address space (MCU types: attiny212, attiny214, 9239 attiny412, attiny414, attiny416, attiny417, attiny814, attiny816, 9240 attiny817, attiny1614, attiny1616, attiny1617, attiny3214, 9241 attiny3216, attiny3217). 9242 9243 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 9244 program memory space and less than 64K data space (MCU types: 9245 atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, 9246 atxmega64c3, atxmega64d3, atxmega64d4). 9247 9248 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 9249 program memory space and greater than 64K data space (MCU types: 9250 atxmega64a1, atxmega64a1u). 9251 9252 Instruction set avrxmega6 is for the XMEGA AVR core with larger 9253 than 64K program memory space and less than 64K data space (MCU 9254 types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, 9255 atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1, 9256 atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3, 9257 atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, 9258 atxmega256d3, atxmega384c3, atxmega256d3). 9259 9260 Instruction set avrxmega7 is for the XMEGA AVR core with larger 9261 than 64K program memory space and greater than 64K data space (MCU 9262 types: atxmega128a1, atxmega128a1u, atxmega128a4u). 9263 9264 Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 9265 microcontrollers. 9266 9267‘-mall-opcodes’ 9268 Accept all AVR opcodes, even if not supported by ‘-mmcu’. 9269 9270‘-mno-skip-bug’ 9271 This option disable warnings for skipping two-word instructions. 9272 9273‘-mno-wrap’ 9274 This option reject ‘rjmp/rcall’ instructions with 8K wrap-around. 9275 9276‘-mrmw’ 9277 Accept Read-Modify-Write (‘XCH,LAC,LAS,LAT’) instructions. 9278 9279‘-mlink-relax’ 9280 Enable support for link-time relaxation. This is now on by default 9281 and this flag no longer has any effect. 9282 9283‘-mno-link-relax’ 9284 Disable support for link-time relaxation. The assembler will 9285 resolve relocations when it can, and may be able to better compress 9286 some debug information. 9287 9288‘-mgcc-isr’ 9289 Enable the ‘__gcc_isr’ pseudo instruction. 9290 9291‘-mno-dollar-line-separator’ 9292 Do not treat the ‘$’ character as a line separator character. This 9293 is for languages where ‘$’ is valid character inside symbol names. 9294 9295 9296File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 9297 92989.5.2 Syntax 9299------------ 9300 9301* Menu: 9302 9303* AVR-Chars:: Special Characters 9304* AVR-Regs:: Register Names 9305* AVR-Modifiers:: Relocatable Expression Modifiers 9306 9307 9308File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 9309 93109.5.2.1 Special Characters 9311.......................... 9312 9313The presence of a ‘;’ anywhere on a line indicates the start of a 9314comment that extends to the end of that line. 9315 9316 If a ‘#’ appears as the first character of a line, the whole line is 9317treated as a comment, but in this case the line can also be a logical 9318line number directive (*note Comments::) or a preprocessor control 9319command (*note Preprocessing::). 9320 9321 The ‘$’ character can be used instead of a newline to separate 9322statements. Note: the ‘-mno-dollar-line-separator’ option disables this 9323behaviour. 9324 9325 9326File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 9327 93289.5.2.2 Register Names 9329...................... 9330 9331The AVR has 32 x 8-bit general purpose working registers ‘r0’, ‘r1’, ... 9332‘r31’. Six of the 32 registers can be used as three 16-bit indirect 9333address register pointers for Data Space addressing. One of the these 9334address pointers can also be used as an address pointer for look up 9335tables in Flash program memory. These added function registers are the 933616-bit ‘X’, ‘Y’ and ‘Z’ - registers. 9337 9338 X = r26:r27 9339 Y = r28:r29 9340 Z = r30:r31 9341 9342 9343File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 9344 93459.5.2.3 Relocatable Expression Modifiers 9346........................................ 9347 9348The assembler supports several modifiers when using relocatable 9349addresses in AVR instruction operands. The general syntax is the 9350following: 9351 9352 modifier(relocatable-expression) 9353 9354‘lo8’ 9355 9356 This modifier allows you to use bits 0 through 7 of an address 9357 expression as an 8 bit relocatable expression. 9358 9359‘hi8’ 9360 9361 This modifier allows you to use bits 7 through 15 of an address 9362 expression as an 8 bit relocatable expression. This is useful 9363 with, for example, the AVR ‘ldi’ instruction and ‘lo8’ modifier. 9364 9365 For example 9366 9367 ldi r26, lo8(sym+10) 9368 ldi r27, hi8(sym+10) 9369 9370‘hh8’ 9371 9372 This modifier allows you to use bits 16 through 23 of an address 9373 expression as an 8 bit relocatable expression. Also, can be useful 9374 for loading 32 bit constants. 9375 9376‘hlo8’ 9377 9378 Synonym of ‘hh8’. 9379 9380‘hhi8’ 9381 9382 This modifier allows you to use bits 24 through 31 of an expression 9383 as an 8 bit expression. This is useful with, for example, the AVR 9384 ‘ldi’ instruction and ‘lo8’, ‘hi8’, ‘hlo8’, ‘hhi8’, modifier. 9385 9386 For example 9387 9388 ldi r26, lo8(285774925) 9389 ldi r27, hi8(285774925) 9390 ldi r28, hlo8(285774925) 9391 ldi r29, hhi8(285774925) 9392 ; r29,r28,r27,r26 = 285774925 9393 9394‘pm_lo8’ 9395 9396 This modifier allows you to use bits 0 through 7 of an address 9397 expression as an 8 bit relocatable expression. This modifier is 9398 useful for addressing data or code from Flash/Program memory by 9399 two-byte words. The use of ‘pm_lo8’ is similar to ‘lo8’. 9400 9401‘pm_hi8’ 9402 9403 This modifier allows you to use bits 8 through 15 of an address 9404 expression as an 8 bit relocatable expression. This modifier is 9405 useful for addressing data or code from Flash/Program memory by 9406 two-byte words. 9407 9408 For example, when setting the AVR ‘Z’ register with the ‘ldi’ 9409 instruction for subsequent use by the ‘ijmp’ instruction: 9410 9411 ldi r30, pm_lo8(sym) 9412 ldi r31, pm_hi8(sym) 9413 ijmp 9414 9415‘pm_hh8’ 9416 9417 This modifier allows you to use bits 15 through 23 of an address 9418 expression as an 8 bit relocatable expression. This modifier is 9419 useful for addressing data or code from Flash/Program memory by 9420 two-byte words. 9421 9422 9423File: as.info, Node: AVR Opcodes, Next: AVR Pseudo Instructions, Prev: AVR Syntax, Up: AVR-Dependent 9424 94259.5.3 Opcodes 9426------------- 9427 9428For detailed information on the AVR machine instruction set, see 9429<www.atmel.com/products/AVR>. 9430 9431 ‘as’ implements all the standard AVR opcodes. The following table 9432summarizes the AVR opcodes, and their arguments. 9433 9434 Legend: 9435 r any register 9436 d ‘ldi’ register (r16-r31) 9437 v ‘movw’ even register (r0, r2, ..., r28, r30) 9438 a ‘fmul’ register (r16-r23) 9439 w ‘adiw’ register (r24,r26,r28,r30) 9440 e pointer registers (X,Y,Z) 9441 b base pointer register and displacement ([YZ]+disp) 9442 z Z pointer register (for [e]lpm Rd,Z[+]) 9443 M immediate value from 0 to 255 9444 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 9445 s immediate value from 0 to 7 9446 P Port address value from 0 to 63. (in, out) 9447 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 9448 K immediate value from 0 to 63 (used in ‘adiw’, ‘sbiw’) 9449 i immediate value 9450 l signed pc relative offset from -64 to 63 9451 L signed pc relative offset from -2048 to 2047 9452 h absolute code address (call, jmp) 9453 S immediate value from 0 to 7 (S = s << 4) 9454 ? use this opcode entry if no parameters, else use next opcode entry 9455 9456 1001010010001000 clc 9457 1001010011011000 clh 9458 1001010011111000 cli 9459 1001010010101000 cln 9460 1001010011001000 cls 9461 1001010011101000 clt 9462 1001010010111000 clv 9463 1001010010011000 clz 9464 1001010000001000 sec 9465 1001010001011000 seh 9466 1001010001111000 sei 9467 1001010000101000 sen 9468 1001010001001000 ses 9469 1001010001101000 set 9470 1001010000111000 sev 9471 1001010000011000 sez 9472 100101001SSS1000 bclr S 9473 100101000SSS1000 bset S 9474 1001010100001001 icall 9475 1001010000001001 ijmp 9476 1001010111001000 lpm ? 9477 1001000ddddd010+ lpm r,z 9478 1001010111011000 elpm ? 9479 1001000ddddd011+ elpm r,z 9480 0000000000000000 nop 9481 1001010100001000 ret 9482 1001010100011000 reti 9483 1001010110001000 sleep 9484 1001010110011000 break 9485 1001010110101000 wdr 9486 1001010111101000 spm 9487 000111rdddddrrrr adc r,r 9488 000011rdddddrrrr add r,r 9489 001000rdddddrrrr and r,r 9490 000101rdddddrrrr cp r,r 9491 000001rdddddrrrr cpc r,r 9492 000100rdddddrrrr cpse r,r 9493 001001rdddddrrrr eor r,r 9494 001011rdddddrrrr mov r,r 9495 100111rdddddrrrr mul r,r 9496 001010rdddddrrrr or r,r 9497 000010rdddddrrrr sbc r,r 9498 000110rdddddrrrr sub r,r 9499 001001rdddddrrrr clr r 9500 000011rdddddrrrr lsl r 9501 000111rdddddrrrr rol r 9502 001000rdddddrrrr tst r 9503 0111KKKKddddKKKK andi d,M 9504 0111KKKKddddKKKK cbr d,n 9505 1110KKKKddddKKKK ldi d,M 9506 11101111dddd1111 ser d 9507 0110KKKKddddKKKK ori d,M 9508 0110KKKKddddKKKK sbr d,M 9509 0011KKKKddddKKKK cpi d,M 9510 0100KKKKddddKKKK sbci d,M 9511 0101KKKKddddKKKK subi d,M 9512 1111110rrrrr0sss sbrc r,s 9513 1111111rrrrr0sss sbrs r,s 9514 1111100ddddd0sss bld r,s 9515 1111101ddddd0sss bst r,s 9516 10110PPdddddPPPP in r,P 9517 10111PPrrrrrPPPP out P,r 9518 10010110KKddKKKK adiw w,K 9519 10010111KKddKKKK sbiw w,K 9520 10011000pppppsss cbi p,s 9521 10011010pppppsss sbi p,s 9522 10011001pppppsss sbic p,s 9523 10011011pppppsss sbis p,s 9524 111101lllllll000 brcc l 9525 111100lllllll000 brcs l 9526 111100lllllll001 breq l 9527 111101lllllll100 brge l 9528 111101lllllll101 brhc l 9529 111100lllllll101 brhs l 9530 111101lllllll111 brid l 9531 111100lllllll111 brie l 9532 111100lllllll000 brlo l 9533 111100lllllll100 brlt l 9534 111100lllllll010 brmi l 9535 111101lllllll001 brne l 9536 111101lllllll010 brpl l 9537 111101lllllll000 brsh l 9538 111101lllllll110 brtc l 9539 111100lllllll110 brts l 9540 111101lllllll011 brvc l 9541 111100lllllll011 brvs l 9542 111101lllllllsss brbc s,l 9543 111100lllllllsss brbs s,l 9544 1101LLLLLLLLLLLL rcall L 9545 1100LLLLLLLLLLLL rjmp L 9546 1001010hhhhh111h call h 9547 1001010hhhhh110h jmp h 9548 1001010rrrrr0101 asr r 9549 1001010rrrrr0000 com r 9550 1001010rrrrr1010 dec r 9551 1001010rrrrr0011 inc r 9552 1001010rrrrr0110 lsr r 9553 1001010rrrrr0001 neg r 9554 1001000rrrrr1111 pop r 9555 1001001rrrrr1111 push r 9556 1001010rrrrr0111 ror r 9557 1001010rrrrr0010 swap r 9558 00000001ddddrrrr movw v,v 9559 00000010ddddrrrr muls d,d 9560 000000110ddd0rrr mulsu a,a 9561 000000110ddd1rrr fmul a,a 9562 000000111ddd0rrr fmuls a,a 9563 000000111ddd1rrr fmulsu a,a 9564 1001001ddddd0000 sts i,r 9565 1001000ddddd0000 lds r,i 9566 10o0oo0dddddbooo ldd r,b 9567 100!000dddddee-+ ld r,e 9568 10o0oo1rrrrrbooo std b,r 9569 100!001rrrrree-+ st e,r 9570 1001010100011001 eicall 9571 1001010000011001 eijmp 9572 9573 9574File: as.info, Node: AVR Pseudo Instructions, Prev: AVR Opcodes, Up: AVR-Dependent 9575 95769.5.4 Pseudo Instructions 9577------------------------- 9578 9579The only available pseudo-instruction ‘__gcc_isr’ can be activated by 9580option ‘-mgcc-isr’. 9581 9582‘__gcc_isr 1’ 9583 Emit code chunk to be used in avr-gcc ISR prologue. It will expand 9584 to at most six 1-word instructions, all optional: push of 9585 ‘tmp_reg’, push of ‘SREG’, push and clear of ‘zero_reg’, push of 9586 REG. 9587 9588‘__gcc_isr 2’ 9589 Emit code chunk to be used in an avr-gcc ISR epilogue. It will 9590 expand to at most five 1-word instructions, all optional: pop of 9591 REG, pop of ‘zero_reg’, pop of ‘SREG’, pop of ‘tmp_reg’. 9592 9593‘__gcc_isr 0, REG’ 9594 Finish avr-gcc ISR function. Scan code since the last prologue for 9595 usage of: ‘SREG’, ‘tmp_reg’, ‘zero_reg’. Prologue chunk and 9596 epilogue chunks will be replaced by appropriate code to save / 9597 restore ‘SREG’, ‘tmp_reg’, ‘zero_reg’ and REG. 9598 9599 Example input: 9600 9601 __vector1: 9602 __gcc_isr 1 9603 lds r24, var 9604 inc r24 9605 sts var, r24 9606 __gcc_isr 2 9607 reti 9608 __gcc_isr 0, r24 9609 9610 Example output: 9611 9612 00000000 <__vector1>: 9613 0: 8f 93 push r24 9614 2: 8f b7 in r24, 0x3f 9615 4: 8f 93 push r24 9616 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> 9617 a: 83 95 inc r24 9618 c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> 9619 10: 8f 91 pop r24 9620 12: 8f bf out 0x3f, r24 9621 14: 8f 91 pop r24 9622 16: 18 95 reti 9623 9624 9625File: as.info, Node: Blackfin-Dependent, Next: BPF-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 9626 96279.6 Blackfin Dependent Features 9628=============================== 9629 9630* Menu: 9631 9632* Blackfin Options:: Blackfin Options 9633* Blackfin Syntax:: Blackfin Syntax 9634* Blackfin Directives:: Blackfin Directives 9635 9636 9637File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 9638 96399.6.1 Options 9640------------- 9641 9642‘-mcpu=PROCESSOR[-SIREVISION]’ 9643 This option specifies the target processor. The optional 9644 SIREVISION is not used in assembler. It’s here such that GCC can 9645 easily pass down its ‘-mcpu=’ option. The assembler will issue an 9646 error message if an attempt is made to assemble an instruction 9647 which will not execute on the target processor. The following 9648 processor names are recognized: ‘bf504’, ‘bf506’, ‘bf512’, ‘bf514’, 9649 ‘bf516’, ‘bf518’, ‘bf522’, ‘bf523’, ‘bf524’, ‘bf525’, ‘bf526’, 9650 ‘bf527’, ‘bf531’, ‘bf532’, ‘bf533’, ‘bf534’, ‘bf535’ (not 9651 implemented yet), ‘bf536’, ‘bf537’, ‘bf538’, ‘bf539’, ‘bf542’, 9652 ‘bf542m’, ‘bf544’, ‘bf544m’, ‘bf547’, ‘bf547m’, ‘bf548’, ‘bf548m’, 9653 ‘bf549’, ‘bf549m’, ‘bf561’, and ‘bf592’. 9654 9655‘-mfdpic’ 9656 Assemble for the FDPIC ABI. 9657 9658‘-mno-fdpic’ 9659‘-mnopic’ 9660 Disable -mfdpic. 9661 9662 9663File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 9664 96659.6.2 Syntax 9666------------ 9667 9668‘Special Characters’ 9669 Assembler input is free format and may appear anywhere on the line. 9670 One instruction may extend across multiple lines or more than one 9671 instruction may appear on the same line. White space (space, tab, 9672 comments or newline) may appear anywhere between tokens. A token 9673 must not have embedded spaces. Tokens include numbers, register 9674 names, keywords, user identifiers, and also some multicharacter 9675 special symbols like "+=", "/*" or "||". 9676 9677 Comments are introduced by the ‘#’ character and extend to the end 9678 of the current line. If the ‘#’ appears as the first character of 9679 a line, the whole line is treated as a comment, but in this case 9680 the line can also be a logical line number directive (*note 9681 Comments::) or a preprocessor control command (*note 9682 Preprocessing::). 9683 9684‘Instruction Delimiting’ 9685 A semicolon must terminate every instruction. Sometimes a complete 9686 instruction will consist of more than one operation. There are two 9687 cases where this occurs. The first is when two general operations 9688 are combined. Normally a comma separates the different parts, as 9689 in 9690 9691 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 9692 9693 The second case occurs when a general instruction is combined with 9694 one or two memory references for joint issue. The latter portions 9695 are set off by a "||" token. 9696 9697 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 9698 9699 Multiple instructions can occur on the same line. Each must be 9700 terminated by a semicolon character. 9701 9702‘Register Names’ 9703 9704 The assembler treats register names and instruction keywords in a 9705 case insensitive manner. User identifiers are case sensitive. 9706 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 9707 assembler. 9708 9709 Register names are reserved and may not be used as program 9710 identifiers. 9711 9712 Some operations (such as "Move Register") require a register pair. 9713 Register pairs are always data registers and are denoted using a 9714 colon, eg., R3:2. The larger number must be written firsts. Note 9715 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 9716 R3:2, and R1:0. 9717 9718 Some instructions (such as –SP (Push Multiple)) require a group of 9719 adjacent registers. Adjacent registers are denoted in the syntax 9720 by the range enclosed in parentheses and separated by a colon, eg., 9721 (R7:3). Again, the larger number appears first. 9722 9723 Portions of a particular register may be individually specified. 9724 This is written with a dot (".") following the register name and 9725 then a letter denoting the desired portion. For 32-bit registers, 9726 ".H" denotes the most significant ("High") portion. ".L" denotes 9727 the least-significant portion. The subdivisions of the 40-bit 9728 registers are described later. 9729 9730‘Accumulators’ 9731 The set of 40-bit registers A1 and A0 that normally contain data 9732 that is being manipulated. Each accumulator can be accessed in 9733 four ways. 9734 9735 ‘one 40-bit register’ 9736 The register will be referred to as A1 or A0. 9737 ‘one 32-bit register’ 9738 The registers are designated as A1.W or A0.W. 9739 ‘two 16-bit registers’ 9740 The registers are designated as A1.H, A1.L, A0.H or A0.L. 9741 ‘one 8-bit register’ 9742 The registers are designated as A1.X or A0.X for the bits that 9743 extend beyond bit 31. 9744 9745‘Data Registers’ 9746 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 9747 that normally contain data for manipulation. These are abbreviated 9748 as D-register or Dreg. Data registers can be accessed as 32-bit 9749 registers or as two independent 16-bit registers. The least 9750 significant 16 bits of each register is called the "low" half and 9751 is designated with ".L" following the register name. The most 9752 significant 16 bits are called the "high" half and is designated 9753 with ".H" following the name. 9754 9755 R7.L, r2.h, r4.L, R0.H 9756 9757‘Pointer Registers’ 9758 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 9759 that normally contain byte addresses of data structures. These are 9760 abbreviated as P-register or Preg. 9761 9762 p2, p5, fp, sp 9763 9764‘Stack Pointer SP’ 9765 The stack pointer contains the 32-bit address of the last occupied 9766 byte location in the stack. The stack grows by decrementing the 9767 stack pointer. 9768 9769‘Frame Pointer FP’ 9770 The frame pointer contains the 32-bit address of the previous frame 9771 pointer in the stack. It is located at the top of a frame. 9772 9773‘Loop Top’ 9774 LT0 and LT1. These registers contain the 32-bit address of the top 9775 of a zero overhead loop. 9776 9777‘Loop Count’ 9778 LC0 and LC1. These registers contain the 32-bit counter of the 9779 zero overhead loop executions. 9780 9781‘Loop Bottom’ 9782 LB0 and LB1. These registers contain the 32-bit address of the 9783 bottom of a zero overhead loop. 9784 9785‘Index Registers’ 9786 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 9787 byte addresses of data structures. Abbreviated I-register or Ireg. 9788 9789‘Modify Registers’ 9790 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 9791 offset values that are added and subtracted to one of the index 9792 registers. Abbreviated as Mreg. 9793 9794‘Length Registers’ 9795 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 9796 the length in bytes of the circular buffer. Abbreviated as Lreg. 9797 Clear the Lreg to disable circular addressing for the corresponding 9798 Ireg. 9799 9800‘Base Registers’ 9801 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 9802 the base address in bytes of the circular buffer. Abbreviated as 9803 Breg. 9804 9805‘Floating Point’ 9806 The Blackfin family has no hardware floating point but the .float 9807 directive generates ieee floating point numbers for use with 9808 software floating point libraries. 9809 9810‘Blackfin Opcodes’ 9811 For detailed information on the Blackfin machine instruction set, 9812 see the Blackfin Processor Instruction Set Reference. 9813 9814 9815File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 9816 98179.6.3 Directives 9818---------------- 9819 9820The following directives are provided for compatibility with the VDSP 9821assembler. 9822 9823‘.byte2’ 9824 Initializes a two byte data object. 9825 9826 This maps to the ‘.short’ directive. 9827‘.byte4’ 9828 Initializes a four byte data object. 9829 9830 This maps to the ‘.int’ directive. 9831‘.db’ 9832 Initializes a single byte data object. 9833 9834 This directive is a synonym for ‘.byte’. 9835‘.dw’ 9836 Initializes a two byte data object. 9837 9838 This directive is a synonym for ‘.byte2’. 9839‘.dd’ 9840 Initializes a four byte data object. 9841 9842 This directive is a synonym for ‘.byte4’. 9843‘.var’ 9844 Define and initialize a 32 bit data object. 9845 9846 9847File: as.info, Node: BPF-Dependent, Next: CR16-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 9848 98499.7 BPF Dependent Features 9850========================== 9851 9852* Menu: 9853 9854* BPF Options:: BPF specific command-line options. 9855* BPF Special Characters:: Comments and statements. 9856* BPF Registers:: Register names. 9857* BPF Directives:: Machine directives. 9858* BPF Instructions:: Machine instructions. 9859 9860 9861File: as.info, Node: BPF Options, Next: BPF Special Characters, Up: BPF-Dependent 9862 98639.7.1 BPF Options 9864----------------- 9865 9866‘-EB’ 9867 This option specifies that the assembler should emit big-endian 9868 eBPF. 9869 9870‘-EL’ 9871 This option specifies that the assembler should emit little-endian 9872 eBPF. 9873 9874‘-mdialect=DIALECT’ 9875 This option specifies the assembly language dialect to recognize 9876 while assembling. The assembler supports ‘normal’ and ‘pseudoc’. 9877 9878‘-misa-spec=SPEC’ 9879 This option specifies the version of the BPF instruction set to use 9880 when assembling. The BPF ISA versions supported are ‘v1’ ‘v2’, 9881 ‘v3’ and ‘v4’. 9882 9883 The value ‘xbpf’ can be specified to recognize extra instructions 9884 that are used by GCC for testing purposes. But beware this is not 9885 valid BPF. 9886 9887‘-mno-relax’ 9888 This option tells the assembler to not relax instructions. 9889 9890 Note that if no endianness option is specified in the command line, 9891the host endianness is used. 9892 9893 9894File: as.info, Node: BPF Special Characters, Next: BPF Registers, Prev: BPF Options, Up: BPF-Dependent 9895 98969.7.2 BPF Special Characters 9897---------------------------- 9898 9899The presence of a ‘#’ or ‘//’ anywhere on a line indicates the start of 9900a comment that extends to the end of the line. 9901 9902 The presence of the ‘/*’ sequence indicates the beginning of a block 9903(multi-line) comment, whose contents span until the next ‘*/’ sequence. 9904It is not possible to nest block comments. 9905 9906 Statements and assembly directives are separated by newlines and ‘;’ 9907characters. 9908 9909 9910File: as.info, Node: BPF Registers, Next: BPF Directives, Prev: BPF Special Characters, Up: BPF-Dependent 9911 99129.7.3 BPF Registers 9913------------------- 9914 9915The eBPF processor provides ten general-purpose 64-bit registers, which 9916are read-write, and a read-only frame pointer register: 9917 9918In normal syntax: 9919 9920‘%r0 .. %r9’ 9921 General-purpose registers. 9922‘%r10’ 9923‘%fp’ 9924 Read-only frame pointer register. 9925 9926 All BPF registers are 64-bit long. However, in the Pseudo-C syntax 9927registers can be referred using different names, which actually reflect 9928the kind of instruction they appear on: 9929 9930In pseudoc syntax: 9931 9932‘r0..r9’ 9933 General-purpose register in an instruction that operates on its 9934 value as if it was a 64-bit value. 9935‘w0..w9’ 9936 General-purpose register in an instruction that operates on its 9937 value as if it was a 32-bit value. 9938‘r10’ 9939 Read-only frame pointer register. 9940 9941Note that in the Pseudo-C syntax register names are not preceded by ‘%’ 9942characters. A consequence of that is that in contexts like instruction 9943operands, where both register names and expressions involving symbols 9944are expected, there is no way to disambiguate between them. In order to 9945keep things simple, this assembler does not allow to refer to symbols 9946whose names collide with register names in instruction operands. 9947 9948 9949File: as.info, Node: BPF Directives, Next: BPF Instructions, Prev: BPF Registers, Up: BPF-Dependent 9950 99519.7.4 BPF Directives 9952-------------------- 9953 9954The BPF version of ‘as’ supports the following additional machine 9955directives: 9956 9957‘.word’ 9958 The ‘.half’ directive produces a 16 bit value. 9959 9960‘.word’ 9961 The ‘.word’ directive produces a 32 bit value. 9962 9963‘.dword’ 9964 The ‘.dword’ directive produces a 64 bit value. 9965 9966 9967File: as.info, Node: BPF Instructions, Prev: BPF Directives, Up: BPF-Dependent 9968 99699.7.5 BPF Instructions 9970---------------------- 9971 9972In the instruction descriptions below the following field descriptors 9973are used: 9974 9975‘rd’ 9976 Destination general-purpose register whose role is to be the 9977 destination of an operation. 9978‘rs’ 9979 Source general-purpose register whose role is to be the source of 9980 an operation. 9981‘disp16’ 9982 16-bit signed PC-relative offset, measured in number of 64-bit 9983 words, minus one. 9984‘disp32’ 9985 32-bit signed PC-relative offset, measured in number of 64-bit 9986 words, minus one. 9987‘offset16’ 9988 Signed 16-bit immediate representing an offset in bytes. 9989‘disp16’ 9990 Signed 16-bit immediate representing a displacement to a target, 9991 measured in number of 64-bit words _minus one_. 9992‘disp32’ 9993 Signed 32-bit immediate representing a displacement to a target, 9994 measured in number of 64-bit words _minus one_. 9995‘imm32’ 9996 Signed 32-bit immediate. 9997‘imm64’ 9998 Signed 64-bit immediate. 9999 10000Note that the assembler allows to express the value for an immediate 10001using any numerical literal whose two’s complement encoding fits in the 10002immediate field. For example, ‘-2’, ‘0xfffffffe’ and ‘4294967294’ all 10003denote the same encoded 32-bit immediate, whose value may be then 10004interpreted by different instructions as either as a negative or a 10005positive number. 10006 100079.7.5.1 Arithmetic instructions 10008............................... 10009 10010The destination register in these instructions act like an accumulator. 10011 10012 Note that in pseudoc syntax these instructions should use ‘r’ 10013registers. 10014 10015‘add rd, rs’ 10016‘add rd, imm32’ 10017‘rd += rs’ 10018‘rd += imm32’ 10019 64-bit arithmetic addition. 10020 10021‘sub rd, rs’ 10022‘sub rd, rs’ 10023‘rd -= rs’ 10024‘rd -= imm32’ 10025 64-bit arithmetic subtraction. 10026 10027‘mul rd, rs’ 10028‘mul rd, imm32’ 10029‘rd *= rs’ 10030‘rd *= imm32’ 10031 64-bit arithmetic multiplication. 10032 10033‘div rd, rs’ 10034‘div rd, imm32’ 10035‘rd /= rs’ 10036‘rd /= imm32’ 10037 64-bit arithmetic integer division. 10038 10039‘mod rd, rs’ 10040‘mod rd, imm32’ 10041‘rd %= rs’ 10042‘rd %= imm32’ 10043 64-bit integer remainder. 10044 10045‘and rd, rs’ 10046‘and rd, imm32’ 10047‘rd &= rs’ 10048‘rd &= imm32’ 10049 64-bit bit-wise “and” operation. 10050 10051‘or rd, rs’ 10052‘or rd, imm32’ 10053‘rd |= rs’ 10054‘rd |= imm32’ 10055 64-bit bit-wise “or” operation. 10056 10057‘xor rd, imm32’ 10058‘xor rd, rs’ 10059‘rd ^= rs’ 10060‘rd ^= imm32’ 10061 64-bit bit-wise exclusive-or operation. 10062 10063‘lsh rd, rs’ 10064‘ldh rd, imm32’ 10065‘rd <<= rs’ 10066‘rd <<= imm32’ 10067 64-bit left shift, by ‘rs’ or ‘imm32’ bits. 10068 10069‘rsh %d, %s’ 10070‘rsh rd, imm32’ 10071‘rd >>= rs’ 10072‘rd >>= imm32’ 10073 64-bit right logical shift, by ‘rs’ or ‘imm32’ bits. 10074 10075‘arsh rd, rs’ 10076‘arsh rd, imm32’ 10077‘rd s>>= rs’ 10078‘rd s>>= imm32’ 10079 64-bit right arithmetic shift, by ‘rs’ or ‘imm32’ bits. 10080 10081‘neg rd’ 10082‘rd = - rd’ 10083 64-bit arithmetic negation. 10084 10085‘mov rd, rs’ 10086‘mov rd, imm32’ 10087‘rd = rs’ 10088‘rd = imm32’ 10089 Move the 64-bit value of ‘rs’ in ‘rd’, or load ‘imm32’ in ‘rd’. 10090 10091‘movs rd, rs, 8’ 10092‘rd = (s8) rs’ 10093 Move the sign-extended 8-bit value in ‘rs’ to ‘rd’. 10094 10095‘movs rd, rs, 16’ 10096‘rd = (s16) rs’ 10097 Move the sign-extended 16-bit value in ‘rs’ to ‘rd’. 10098 10099‘movs rd, rs, 32’ 10100‘rd = (s32) rs’ 10101 Move the sign-extended 32-bit value in ‘rs’ to ‘rd’. 10102 101039.7.5.2 32-bit arithmetic instructions 10104...................................... 10105 10106The destination register in these instructions act as an accumulator. 10107 10108 Note that in pseudoc syntax these instructions should use ‘w’ 10109registers. It is not allowed to mix ‘w’ and ‘r’ registers in the same 10110instruction. 10111 10112‘add32 rd, rs’ 10113‘add32 rd, imm32’ 10114‘rd += rs’ 10115‘rd += imm32’ 10116 32-bit arithmetic addition. 10117 10118‘sub32 rd, rs’ 10119‘sub32 rd, imm32’ 10120‘rd -= rs’ 10121‘rd += imm32’ 10122 32-bit arithmetic subtraction. 10123 10124‘mul32 rd, rs’ 10125‘mul32 rd, imm32’ 10126‘rd *= rs’ 10127‘rd *= imm32’ 10128 32-bit arithmetic multiplication. 10129 10130‘div32 rd, rs’ 10131‘div32 rd, imm32’ 10132‘rd /= rs’ 10133‘rd /= imm32’ 10134 32-bit arithmetic integer division. 10135 10136‘mod32 rd, rs’ 10137‘mod32 rd, imm32’ 10138‘rd %= rs’ 10139‘rd %= imm32’ 10140 32-bit integer remainder. 10141 10142‘and32 rd, rs’ 10143‘and32 rd, imm32’ 10144‘rd &= rs’ 10145‘rd &= imm32’ 10146 32-bit bit-wise “and” operation. 10147 10148‘or32 rd, rs’ 10149‘or32 rd, imm32’ 10150‘rd |= rs’ 10151‘rd |= imm32’ 10152 32-bit bit-wise “or” operation. 10153 10154‘xor32 rd, rs’ 10155‘xor32 rd, imm32’ 10156‘rd ^= rs’ 10157‘rd ^= imm32’ 10158 32-bit bit-wise exclusive-or operation. 10159 10160‘lsh32 rd, rs’ 10161‘lsh32 rd, imm32’ 10162‘rd <<= rs’ 10163‘rd <<= imm32’ 10164 32-bit left shift, by ‘rs’ or ‘imm32’ bits. 10165 10166‘rsh32 rd, rs’ 10167‘rsh32 rd, imm32’ 10168‘rd >>= rs’ 10169‘rd >>= imm32’ 10170 32-bit right logical shift, by ‘rs’ or ‘imm32’ bits. 10171 10172‘arsh32 rd, rs’ 10173‘arsh32 rd, imm32’ 10174‘rd s>>= rs’ 10175‘rd s>>= imm32’ 10176 32-bit right arithmetic shift, by ‘rs’ or ‘imm32’ bits. 10177 10178‘neg32 rd’ 10179‘rd = - rd’ 10180 32-bit arithmetic negation. 10181 10182‘mov32 rd, rs’ 10183‘mov32 rd, imm32’ 10184‘rd = rs’ 10185‘rd = imm32’ 10186 Move the 32-bit value of ‘rs’ in ‘rd’, or load ‘imm32’ in ‘rd’. 10187 10188‘mov32s rd, rs, 8’ 10189‘rd = (s8) rs’ 10190 Move the sign-extended 8-bit value in ‘rs’ to ‘rd’. 10191 10192‘mov32s rd, rs, 16’ 10193‘rd = (s16) rs’ 10194 Move the sign-extended 16-bit value in ‘rs’ to ‘rd’. 10195 10196‘mov32s rd, rs, 32’ 10197‘rd = (s32) rs’ 10198 Move the sign-extended 32-bit value in ‘rs’ to ‘rd’. 10199 102009.7.5.3 Endianness conversion instructions 10201.......................................... 10202 10203‘endle rd, 16’ 10204‘endle rd, 32’ 10205‘endle rd, 64’ 10206‘rd = le16 rd’ 10207‘rd = le32 rd’ 10208‘rd = le64 rd’ 10209 Convert the 16-bit, 32-bit or 64-bit value in ‘rd’ to little-endian 10210 and store it back in ‘rd’. 10211‘endbe %d, 16’ 10212‘endbe %d, 32’ 10213‘endbe %d, 64’ 10214‘rd = be16 rd’ 10215‘rd = be32 rd’ 10216‘rd = be64 rd’ 10217 Convert the 16-bit, 32-bit or 64-bit value in ‘rd’ to big-endian 10218 and store it back in ‘rd’. 10219 102209.7.5.4 Byte swap instructions 10221.............................. 10222 10223‘bswap rd, 16’ 10224‘rd = bswap16 rd’ 10225 Swap the least-significant 16-bit word in ‘rd’ with the 10226 most-significant 16-bit word. 10227 10228‘bswap rd, 32’ 10229‘rd = bswap32 rd’ 10230 Swap the least-significant 32-bit word in ‘rd’ with the 10231 most-significant 32-bit word. 10232 10233‘bswap rd, 64’ 10234‘rd = bswap64 rd’ 10235 Swap the least-significant 64-bit word in ‘rd’ with the 10236 most-significant 64-bit word. 10237 102389.7.5.5 64-bit load and pseudo maps 10239................................... 10240 10241‘lddw rd, imm64’ 10242‘rd = imm64 ll’ 10243 Load the given signed 64-bit immediate to the destination register 10244 ‘rd’. 10245 102469.7.5.6 Load instructions for socket filters 10247............................................ 10248 10249The following instructions are intended to be used in socket filters, 10250and are therefore not general-purpose: they make assumptions on the 10251contents of several registers. See the file 10252‘Documentation/networking/filter.txt’ in the Linux kernel source tree 10253for more information. 10254 10255 Absolute loads: 10256 10257‘ldabsdw imm32’ 10258‘r0 = *(u64 *) skb[imm32]’ 10259 Absolute 64-bit load. 10260 10261‘ldabsw imm32’ 10262‘r0 = *(u32 *) skb[imm32]’ 10263 Absolute 32-bit load. 10264 10265‘ldabsh imm32’ 10266‘r0 = *(u16 *) skb[imm32]’ 10267 Absolute 16-bit load. 10268 10269‘ldabsb imm32’ 10270‘r0 = *(u8 *) skb[imm32]’ 10271 Absolute 8-bit load. 10272 10273 Indirect loads: 10274 10275‘ldinddw rs, imm32’ 10276‘r0 = *(u64 *) skb[rs + imm32]’ 10277 Indirect 64-bit load. 10278 10279‘ldindw rs, imm32’ 10280‘r0 = *(u32 *) skb[rs + imm32]’ 10281 Indirect 32-bit load. 10282 10283‘ldindh rs, imm32’ 10284‘r0 = *(u16 *) skb[rs + imm32]’ 10285 Indirect 16-bit load. 10286 10287‘ldindb %s, imm32’ 10288‘r0 = *(u8 *) skb[rs + imm32]’ 10289 Indirect 8-bit load. 10290 102919.7.5.7 Generic load/store instructions 10292....................................... 10293 10294General-purpose load and store instructions are provided for several 10295word sizes. 10296 10297 Load to register instructions: 10298 10299‘ldxdw rd, [rs + offset16]’ 10300‘rd = *(u64 *) (rs + offset16)’ 10301 Generic 64-bit load. 10302 10303‘ldxw rd, [rs + offset16]’ 10304‘rd = *(u32 *) (rs + offset16)’ 10305 Generic 32-bit load. 10306 10307‘ldxh rd, [rs + offset16]’ 10308‘rd = *(u16 *) (rs + offset16)’ 10309 Generic 16-bit load. 10310 10311‘ldxb rd, [rs + offset16]’ 10312‘rd = *(u8 *) (rs + offset16)’ 10313 Generic 8-bit load. 10314 10315 Signed load to register instructions: 10316 10317‘ldxsdw rd, [rs + offset16]’ 10318‘rd = *(s64 *) (rs + offset16)’ 10319 Generic 64-bit signed load. 10320 10321‘ldxsw rd, [rs + offset16]’ 10322‘rd = *(s32 *) (rs + offset16)’ 10323 Generic 32-bit signed load. 10324 10325‘ldxsh rd, [rs + offset16]’ 10326‘rd = *(s16 *) (rs + offset16)’ 10327 Generic 16-bit signed load. 10328 10329‘ldxsb rd, [rs + offset16]’ 10330‘rd = *(s8 *) (rs + offset16)’ 10331 Generic 8-bit signed load. 10332 10333 Store from register instructions: 10334 10335‘stxdw [rd + offset16], %s’ 10336‘*(u64 *) (rd + offset16)’ 10337 Generic 64-bit store. 10338 10339‘stxw [rd + offset16], %s’ 10340‘*(u32 *) (rd + offset16)’ 10341 Generic 32-bit store. 10342 10343‘stxh [rd + offset16], %s’ 10344‘*(u16 *) (rd + offset16)’ 10345 Generic 16-bit store. 10346 10347‘stxb [rd + offset16], %s’ 10348‘*(u8 *) (rd + offset16)’ 10349 Generic 8-bit store. 10350 10351 Store from immediates instructions: 10352 10353‘stdw [rd + offset16], imm32’ 10354‘*(u64 *) (rd + offset16) = imm32’ 10355 Store immediate as 64-bit. 10356 10357‘stw [rd + offset16], imm32’ 10358‘*(u32 *) (rd + offset16) = imm32’ 10359 Store immediate as 32-bit. 10360 10361‘sth [rd + offset16], imm32’ 10362‘*(u16 *) (rd + offset16) = imm32’ 10363 Store immediate as 16-bit. 10364 10365‘stb [rd + offset16], imm32’ 10366‘*(u8 *) (rd + offset16) = imm32’ 10367 Store immediate as 8-bit. 10368 103699.7.5.8 Jump instructions 10370......................... 10371 10372eBPF provides the following compare-and-jump instructions, which compare 10373the values of the two given registers, or the values of a register and 10374an immediate, and perform a branch in case the comparison holds true. 10375 10376‘ja disp16’ 10377‘goto disp16’ 10378 Jump-always. 10379 10380‘jal disp32’ 10381‘gotol disp32’ 10382 Jump-always, long range. 10383 10384‘jeq rd, rs, disp16’ 10385‘jeq rd, imm32, disp16’ 10386‘if rd == rs goto disp16’ 10387‘if rd == imm32 goto disp16’ 10388 Jump if equal, unsigned. 10389 10390‘jgt rd, rs, disp16’ 10391‘jgt rd, imm32, disp16’ 10392‘if rd > rs goto disp16’ 10393‘if rd > imm32 goto disp16’ 10394 Jump if greater, unsigned. 10395 10396‘jge rd, rs, disp16’ 10397‘jge rd, imm32, disp16’ 10398‘if rd >= rs goto disp16’ 10399‘if rd >= imm32 goto disp16’ 10400 Jump if greater or equal. 10401 10402‘jlt rd, rs, disp16’ 10403‘jlt rd, imm32, disp16’ 10404‘if rd < rs goto disp16’ 10405‘if rd < imm32 goto disp16’ 10406 Jump if lesser. 10407 10408‘jle rd , rs, disp16’ 10409‘jle rd, imm32, disp16’ 10410‘if rd <= rs goto disp16’ 10411‘if rd <= imm32 goto disp16’ 10412 Jump if lesser or equal. 10413 10414‘jset rd, rs, disp16’ 10415‘jset rd, imm32, disp16’ 10416‘if rd & rs goto disp16’ 10417‘if rd & imm32 goto disp16’ 10418 Jump if signed equal. 10419 10420‘jne rd, rs, disp16’ 10421‘jne rd, imm32, disp16’ 10422‘if rd != rs goto disp16’ 10423‘if rd != imm32 goto disp16’ 10424 Jump if not equal. 10425 10426‘jsgt rd, rs, disp16’ 10427‘jsgt rd, imm32, disp16’ 10428‘if rd s> rs goto disp16’ 10429‘if rd s> imm32 goto disp16’ 10430 Jump if signed greater. 10431 10432‘jsge rd, rs, disp16’ 10433‘jsge rd, imm32, disp16’ 10434‘if rd s>= rd goto disp16’ 10435‘if rd s>= imm32 goto disp16’ 10436 Jump if signed greater or equal. 10437 10438‘jslt rd, rs, disp16’ 10439‘jslt rd, imm32, disp16’ 10440‘if rd s< rs goto disp16’ 10441‘if rd s< imm32 goto disp16’ 10442 Jump if signed lesser. 10443 10444‘jsle rd, rs, disp16’ 10445‘jsle rd, imm32, disp16’ 10446‘if rd s<= rs goto disp16’ 10447‘if rd s<= imm32 goto disp16’ 10448 Jump if signed lesser or equal. 10449 10450 A call instruction is provided in order to perform calls to other 10451eBPF functions, or to external kernel helpers: 10452 10453‘call disp32’ 10454‘call imm32’ 10455 Jump and link to the offset _disp32_, or to the kernel helper 10456 function identified by _imm32_. 10457 10458 Finally: 10459 10460‘exit’ 10461 Terminate the eBPF program. 10462 104639.7.5.9 32-bit jump instructions 10464................................ 10465 10466eBPF provides the following compare-and-jump instructions, which compare 10467the 32-bit values of the two given registers, or the values of a 10468register and an immediate, and perform a branch in case the comparison 10469holds true. 10470 10471 These instructions are only available in BPF v3 or later. 10472 10473‘jeq32 rd, rs, disp16’ 10474‘jeq32 rd, imm32, disp16’ 10475‘if rd == rs goto disp16’ 10476‘if rd == imm32 goto disp16’ 10477 Jump if equal, unsigned. 10478 10479‘jgt32 rd, rs, disp16’ 10480‘jgt32 rd, imm32, disp16’ 10481‘if rd > rs goto disp16’ 10482‘if rd > imm32 goto disp16’ 10483 Jump if greater, unsigned. 10484 10485‘jge32 rd, rs, disp16’ 10486‘jge32 rd, imm32, disp16’ 10487‘if rd >= rs goto disp16’ 10488‘if rd >= imm32 goto disp16’ 10489 Jump if greater or equal. 10490 10491‘jlt32 rd, rs, disp16’ 10492‘jlt32 rd, imm32, disp16’ 10493‘if rd < rs goto disp16’ 10494‘if rd < imm32 goto disp16’ 10495 Jump if lesser. 10496 10497‘jle32 rd , rs, disp16’ 10498‘jle32 rd, imm32, disp16’ 10499‘if rd <= rs goto disp16’ 10500‘if rd <= imm32 goto disp16’ 10501 Jump if lesser or equal. 10502 10503‘jset32 rd, rs, disp16’ 10504‘jset32 rd, imm32, disp16’ 10505‘if rd & rs goto disp16’ 10506‘if rd & imm32 goto disp16’ 10507 Jump if signed equal. 10508 10509‘jne32 rd, rs, disp16’ 10510‘jne32 rd, imm32, disp16’ 10511‘if rd != rs goto disp16’ 10512‘if rd != imm32 goto disp16’ 10513 Jump if not equal. 10514 10515‘jsgt32 rd, rs, disp16’ 10516‘jsgt32 rd, imm32, disp16’ 10517‘if rd s> rs goto disp16’ 10518‘if rd s> imm32 goto disp16’ 10519 Jump if signed greater. 10520 10521‘jsge32 rd, rs, disp16’ 10522‘jsge32 rd, imm32, disp16’ 10523‘if rd s>= rd goto disp16’ 10524‘if rd s>= imm32 goto disp16’ 10525 Jump if signed greater or equal. 10526 10527‘jslt32 rd, rs, disp16’ 10528‘jslt32 rd, imm32, disp16’ 10529‘if rd s< rs goto disp16’ 10530‘if rd s< imm32 goto disp16’ 10531 Jump if signed lesser. 10532 10533‘jsle32 rd, rs, disp16’ 10534‘jsle32 rd, imm32, disp16’ 10535‘if rd s<= rs goto disp16’ 10536‘if rd s<= imm32 goto disp16’ 10537 Jump if signed lesser or equal. 10538 105399.7.5.10 Atomic instructions 10540............................ 10541 10542Atomic exchange instructions are provided in two flavors: one for 10543compare-and-swap, one for unconditional exchange. 10544 10545‘acmp [rd + offset16], rs’ 10546‘r0 = cmpxchg_64 (rd + offset16, r0, rs)’ 10547 Atomic compare-and-swap. Compares value in ‘r0’ to value addressed 10548 by ‘rd + offset16’. On match, the value addressed by ‘rd + 10549 offset16’ is replaced with the value in ‘rs’. Regardless, the 10550 value that was at ‘rd + offset16’ is zero-extended and loaded into 10551 ‘r0’. 10552 10553‘axchg [rd + offset16], rs’ 10554‘rs = xchg_64 (rd + offset16, rs)’ 10555 Atomic exchange. Atomically exchanges the value in ‘rs’ with the 10556 value addressed by ‘rd + offset16’. 10557 10558The following instructions provide atomic arithmetic operations. 10559 10560‘aadd [rd + offset16], rs’ 10561‘lock *(u64 *)(rd + offset16) = rs’ 10562 Atomic add instruction. 10563 10564‘aor [rd + offset16], rs’ 10565‘lock *(u64 *) (rd + offset16) |= rs’ 10566 Atomic or instruction. 10567 10568‘aand [rd + offset16], rs’ 10569‘lock *(u64 *) (rd + offset16) &= rs’ 10570 Atomic and instruction. 10571 10572‘axor [rd + offset16], rs’ 10573‘lock *(u64 *) (rd + offset16) ^= rs’ 10574 Atomic xor instruction. 10575 10576The following variants perform fetching before the atomic operation. 10577 10578‘afadd [rd + offset16], rs’ 10579‘rs = atomic_fetch_add ((u64 *)(rd + offset16), rs)’ 10580 Atomic fetch-and-add instruction. 10581 10582‘afor [rd + offset16], rs’ 10583‘rs = atomic_fetch_or ((u64 *)(rd + offset16), rs)’ 10584 Atomic fetch-and-or instruction. 10585 10586‘afand [rd + offset16], rs’ 10587‘rs = atomic_fetch_and ((u64 *)(rd + offset16), rs)’ 10588 Atomic fetch-and-and instruction. 10589 10590‘afxor [rd + offset16], rs’ 10591‘rs = atomic_fetch_xor ((u64 *)(rd + offset16), rs)’ 10592 Atomic fetch-and-or instruction. 10593 10594 The above instructions were introduced in the V3 of the BPF 10595instruction set. The following instruction is supported for backwards 10596compatibility: 10597 10598‘xadddw [rd + offset16], rs’ 10599 Alias to ‘aadd’. 10600 106019.7.5.11 32-bit atomic instructions 10602................................... 10603 1060432-bit atomic exchange instructions are provided in two flavors: one for 10605compare-and-swap, one for unconditional exchange. 10606 10607‘acmp32 [rd + offset16], rs’ 10608‘w0 = cmpxchg32_32 (rd + offset16, w0, ws)’ 10609 Atomic compare-and-swap. Compares value in ‘w0’ to value addressed 10610 by ‘rd + offset16’. On match, the value addressed by ‘rd + 10611 offset16’ is replaced with the value in ‘ws’. Regardless, the 10612 value that was at ‘rd + offset16’ is zero-extended and loaded into 10613 ‘w0’. 10614 10615‘axchg [rd + offset16], rs’ 10616‘ws = xchg32_32 (rd + offset16, ws)’ 10617 Atomic exchange. Atomically exchanges the value in ‘ws’ with the 10618 value addressed by ‘rd + offset16’. 10619 10620The following instructions provide 32-bit atomic arithmetic operations. 10621 10622‘aadd32 [rd + offset16], rs’ 10623‘lock *(u32 *)(rd + offset16) = rs’ 10624 Atomic add instruction. 10625 10626‘aor32 [rd + offset16], rs’ 10627‘lock *(u32 *) (rd + offset16) |= rs’ 10628 Atomic or instruction. 10629 10630‘aand32 [rd + offset16], rs’ 10631‘lock *(u32 *) (rd + offset16) &= rs’ 10632 Atomic and instruction. 10633 10634‘axor32 [rd + offset16], rs’ 10635‘lock *(u32 *) (rd + offset16) ^= rs’ 10636 Atomic xor instruction 10637 10638The following variants perform fetching before the atomic operation. 10639 10640‘afadd32 [dr + offset16], rs’ 10641‘ws = atomic_fetch_add ((u32 *)(rd + offset16), ws)’ 10642 Atomic fetch-and-add instruction. 10643 10644‘afor32 [dr + offset16], rs’ 10645‘ws = atomic_fetch_or ((u32 *)(rd + offset16), ws)’ 10646 Atomic fetch-and-or instruction. 10647 10648‘afand32 [dr + offset16], rs’ 10649‘ws = atomic_fetch_and ((u32 *)(rd + offset16), ws)’ 10650 Atomic fetch-and-and instruction. 10651 10652‘afxor32 [dr + offset16], rs’ 10653‘ws = atomic_fetch_xor ((u32 *)(rd + offset16), ws)’ 10654 Atomic fetch-and-or instruction 10655 10656 The above instructions were introduced in the V3 of the BPF 10657instruction set. The following instruction is supported for backwards 10658compatibility: 10659 10660‘xaddw [rd + offset16], rs’ 10661 Alias to ‘aadd32’. 10662 10663 10664File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: BPF-Dependent, Up: Machine Dependencies 10665 106669.8 CR16 Dependent Features 10667=========================== 10668 10669* Menu: 10670 10671* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 10672* CR16 Syntax:: Syntax for the CR16 10673 10674 10675File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent 10676 106779.8.1 CR16 Operand Qualifiers 10678----------------------------- 10679 10680The National Semiconductor CR16 target of ‘as’ has a few machine 10681dependent operand qualifiers. 10682 10683 Operand expression type qualifier is an optional field in the 10684instruction operand, to determines the type of the expression field of 10685an operand. The ‘@’ is required. CR16 architecture uses one of the 10686following expression qualifiers: 10687 10688‘s’ 10689 - ‘Specifies expression operand type as small’ 10690‘m’ 10691 - ‘Specifies expression operand type as medium’ 10692‘l’ 10693 - ‘Specifies expression operand type as large’ 10694‘c’ 10695 - ‘Specifies the CR16 Assembler generates a relocation entry for 10696 the operand, where pc has implied bit, the expression is adjusted 10697 accordingly. The linker uses the relocation entry to update the 10698 operand address at link time.’ 10699‘got/GOT’ 10700 - ‘Specifies the CR16 Assembler generates a relocation entry for 10701 the operand, offset from Global Offset Table. The linker uses this 10702 relocation entry to update the operand address at link time’ 10703‘cgot/cGOT’ 10704 - ‘Specifies the CompactRISC Assembler generates a relocation entry 10705 for the operand, where pc has implied bit, the expression is 10706 adjusted accordingly. The linker uses the relocation entry to 10707 update the operand address at link time.’ 10708 10709 CR16 target operand qualifiers and its size (in bits): 10710 10711‘Immediate Operand: s’ 10712 4 bits. 10713 10714‘Immediate Operand: m’ 10715 16 bits, for movb and movw instructions. 10716 10717‘Immediate Operand: m’ 10718 20 bits, movd instructions. 10719 10720‘Immediate Operand: l’ 10721 32 bits. 10722 10723‘Absolute Operand: s’ 10724 Illegal specifier for this operand. 10725 10726‘Absolute Operand: m’ 10727 20 bits, movd instructions. 10728 10729‘Displacement Operand: s’ 10730 8 bits. 10731 10732‘Displacement Operand: m’ 10733 16 bits. 10734 10735‘Displacement Operand: l’ 10736 24 bits. 10737 10738 For example: 10739 1 movw $_myfun@c,r1 10740 10741 This loads the address of _myfun, shifted right by 1, into r1. 10742 10743 2 movd $_myfun@c,(r2,r1) 10744 10745 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 10746 10747 3 _myfun_ptr: 10748 .long _myfun@c 10749 loadd _myfun_ptr, (r1,r0) 10750 jal (r1,r0) 10751 10752 This .long directive, the address of _myfunc, shifted right by 1 at link time. 10753 10754 4 loadd _data1@GOT(r12), (r1,r0) 10755 10756 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 10757 10758 5 loadd _myfunc@cGOT(r12), (r1,r0) 10759 10760 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 10761 10762 10763File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent 10764 107659.8.2 CR16 Syntax 10766----------------- 10767 10768* Menu: 10769 10770* CR16-Chars:: Special Characters 10771 10772 10773File: as.info, Node: CR16-Chars, Up: CR16 Syntax 10774 107759.8.2.1 Special Characters 10776.......................... 10777 10778The presence of a ‘#’ on a line indicates the start of a comment that 10779extends to the end of the current line. If the ‘#’ appears as the first 10780character of a line, the whole line is treated as a comment, but in this 10781case the line can also be a logical line number directive (*note 10782Comments::) or a preprocessor control command (*note Preprocessing::). 10783 10784 The ‘;’ character can be used to separate statements on the same 10785line. 10786 10787 10788File: as.info, Node: CRIS-Dependent, Next: C-SKY-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 10789 107909.9 CRIS Dependent Features 10791=========================== 10792 10793* Menu: 10794 10795* CRIS-Opts:: Command-line Options 10796* CRIS-Expand:: Instruction expansion 10797* CRIS-Symbols:: Symbols 10798* CRIS-Syntax:: Syntax 10799 10800 10801File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 10802 108039.9.1 Command-line Options 10804-------------------------- 10805 10806The CRIS version of ‘as’ has these machine-dependent command-line 10807options. 10808 10809 The format of the generated object files can be either ELF or a.out, 10810specified by the command-line options ‘--emulation=crisaout’ and 10811‘--emulation=criself’. The default is ELF (criself), unless ‘as’ has 10812been configured specifically for a.out by using the configuration name 10813‘cris-axis-aout’. 10814 10815 There are two different link-incompatible ELF object file variants 10816for CRIS, for use in environments where symbols are expected to be 10817prefixed by a leading ‘_’ character and for environments without such a 10818symbol prefix. The variant used for GNU/Linux port has no symbol 10819prefix. Which variant to produce is specified by either of the options 10820‘--underscore’ and ‘--no-underscore’. The default is ‘--underscore’. 10821Since symbols in CRIS a.out objects are expected to have a ‘_’ prefix, 10822specifying ‘--no-underscore’ when generating a.out objects is an error. 10823Besides the object format difference, the effect of this option is to 10824parse register names differently (*note crisnous::). The 10825‘--no-underscore’ option makes a ‘$’ register prefix mandatory. 10826 10827 The option ‘--pic’ must be passed to ‘as’ in order to recognize the 10828symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 10829crispic::). This will also affect expansion of instructions. The 10830expansion with ‘--pic’ will use PC-relative rather than (slightly 10831faster) absolute addresses in those expansions. This option is only 10832valid when generating ELF format object files. 10833 10834 The option ‘--march=ARCHITECTURE’ specifies the recognized 10835instruction set and recognized register names. It also controls the 10836architecture type of the object file. Valid values for ARCHITECTURE 10837are: 10838 10839‘v0_v10’ 10840 All instructions and register names for any architecture variant in 10841 the set v0...v10 are recognized. This is the default if the target 10842 is configured as cris-*. 10843 10844‘v10’ 10845 Only instructions and register names for CRIS v10 (as found in 10846 ETRAX 100 LX) are recognized. This is the default if the target is 10847 configured as crisv10-*. 10848 10849‘v32’ 10850 Only instructions and register names for CRIS v32 (code name 10851 Guinness) are recognized. This is the default if the target is 10852 configured as crisv32-*. This value implies ‘--no-mul-bug-abort’. 10853 (A subsequent ‘--mul-bug-abort’ will turn it back on.) 10854 10855‘common_v10_v32’ 10856 Only instructions with register names and addressing modes with 10857 opcodes common to the v10 and v32 are recognized. 10858 10859 When ‘-N’ is specified, ‘as’ will emit a warning when a 16-bit branch 10860instruction is expanded into a 32-bit multiple-instruction construct 10861(*note CRIS-Expand::). 10862 10863 Some versions of the CRIS v10, for example in the Etrax 100 LX, 10864contain a bug that causes destabilizing memory accesses when a multiply 10865instruction is executed with certain values in the first operand just 10866before a cache-miss. When the ‘--mul-bug-abort’ command-line option is 10867active (the default value), ‘as’ will refuse to assemble a file 10868containing a multiply instruction at a dangerous offset, one that could 10869be the last on a cache-line, or is in a section with insufficient 10870alignment. This placement checking does not catch any case where the 10871multiply instruction is dangerously placed because it is located in a 10872delay-slot. The ‘--mul-bug-abort’ command-line option turns off the 10873checking. 10874 10875 10876File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 10877 108789.9.2 Instruction expansion 10879--------------------------- 10880 10881‘as’ will silently choose an instruction that fits the operand size for 10882‘[register+constant]’ operands. For example, the offset ‘127’ in 10883‘move.d [r3+127],r4’ fits in an instruction using a signed-byte offset. 10884Similarly, ‘move.d [r2+32767],r1’ will generate an instruction using a 1088516-bit offset. For symbolic expressions and constants that do not fit 10886in 16 bits including the sign bit, a 32-bit offset is generated. 10887 10888 For branches, ‘as’ will expand from a 16-bit branch instruction into 10889a sequence of instructions that can reach a full 32-bit address. Since 10890this does not correspond to a single instruction, such expansions can 10891optionally be warned about. *Note CRIS-Opts::. 10892 10893 If the operand is found to fit the range, a ‘lapc’ mnemonic will 10894translate to a ‘lapcq’ instruction. Use ‘lapc.d’ to force the 32-bit 10895‘lapc’ instruction. 10896 10897 Similarly, the ‘addo’ mnemonic will translate to the shortest fitting 10898instruction of ‘addoq’, ‘addo.w’ and ‘addo.d’, when used with a operand 10899that is a constant known at assembly time. 10900 10901 10902File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 10903 109049.9.3 Symbols 10905------------- 10906 10907Some symbols are defined by the assembler. They’re intended to be used 10908in conditional assembly, for example: 10909 .if ..asm.arch.cris.v32 10910 CODE FOR CRIS V32 10911 .elseif ..asm.arch.cris.common_v10_v32 10912 CODE COMMON TO CRIS V32 AND CRIS V10 10913 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 10914 CODE FOR V10 10915 .else 10916 .error "Code needs to be added here." 10917 .endif 10918 10919 These symbols are defined in the assembler, reflecting command-line 10920options, either when specified or the default. They are always defined, 10921to 0 or 1. 10922 10923‘..asm.arch.cris.any_v0_v10’ 10924 This symbol is non-zero when ‘--march=v0_v10’ is specified or the 10925 default. 10926 10927‘..asm.arch.cris.common_v10_v32’ 10928 Set according to the option ‘--march=common_v10_v32’. 10929 10930‘..asm.arch.cris.v10’ 10931 Reflects the option ‘--march=v10’. 10932 10933‘..asm.arch.cris.v32’ 10934 Corresponds to ‘--march=v10’. 10935 10936 Speaking of symbols, when a symbol is used in code, it can have a 10937suffix modifying its value for use in position-independent code. *Note 10938CRIS-Pic::. 10939 10940 10941File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 10942 109439.9.4 Syntax 10944------------ 10945 10946There are different aspects of the CRIS assembly syntax. 10947 10948* Menu: 10949 10950* CRIS-Chars:: Special Characters 10951* CRIS-Pic:: Position-Independent Code Symbols 10952* CRIS-Regs:: Register Names 10953* CRIS-Pseudos:: Assembler Directives 10954 10955 10956File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 10957 109589.9.4.1 Special Characters 10959.......................... 10960 10961The character ‘#’ is a line comment character. It starts a comment if 10962and only if it is placed at the beginning of a line. 10963 10964 A ‘;’ character starts a comment anywhere on the line, causing all 10965characters up to the end of the line to be ignored. 10966 10967 A ‘@’ character is handled as a line separator equivalent to a 10968logical new-line character (except in a comment), so separate 10969instructions can be specified on a single line. 10970 10971 10972File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 10973 109749.9.4.2 Symbols in position-independent code 10975............................................ 10976 10977When generating position-independent code (SVR4 PIC) for use in 10978cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 10979suffixes are used to specify what kind of run-time symbol lookup will be 10980used, expressed in the object as different _relocation types_. Usually, 10981all absolute symbol values must be located in a table, the _global 10982offset table_, leaving the code position-independent; independent of 10983values of global symbols and independent of the address of the code. 10984The suffix modifies the value of the symbol, into for example an index 10985into the global offset table where the real symbol value is entered, or 10986a PC-relative value, or a value relative to the start of the global 10987offset table. All symbol suffixes start with the character ‘:’ (omitted 10988in the list below). Every symbol use in code or a read-only section 10989must therefore have a PIC suffix to enable a useful shared library to be 10990created. Usually, these constructs must not be used with an additive 10991constant offset as is usually allowed, i.e. no 4 as in ‘symbol + 4’ is 10992allowed. This restriction is checked at link-time, not at 10993assembly-time. 10994 10995‘GOT’ 10996 10997 Attaching this suffix to a symbol in an instruction causes the 10998 symbol to be entered into the global offset table. The value is a 10999 32-bit index for that symbol into the global offset table. The 11000 name of the corresponding relocation is ‘R_CRIS_32_GOT’. Example: 11001 ‘move.d [$r0+extsym:GOT],$r9’ 11002 11003‘GOT16’ 11004 11005 Same as for ‘GOT’, but the value is a 16-bit index into the global 11006 offset table. The corresponding relocation is ‘R_CRIS_16_GOT’. 11007 Example: ‘move.d [$r0+asymbol:GOT16],$r10’ 11008 11009‘PLT’ 11010 11011 This suffix is used for function symbols. It causes a _procedure 11012 linkage table_, an array of code stubs, to be created at the time 11013 the shared object is created or linked against, together with a 11014 global offset table entry. The value is a pc-relative offset to 11015 the corresponding stub code in the procedure linkage table. This 11016 arrangement causes the run-time symbol resolver to be called to 11017 look up and set the value of the symbol the first time the function 11018 is called (at latest; depending environment variables). It is only 11019 safe to leave the symbol unresolved this way if all references are 11020 function calls. The name of the relocation is 11021 ‘R_CRIS_32_PLT_PCREL’. Example: ‘add.d fnname:PLT,$pc’ 11022 11023‘PLTG’ 11024 11025 Like PLT, but the value is relative to the beginning of the global 11026 offset table. The relocation is ‘R_CRIS_32_PLT_GOTREL’. Example: 11027 ‘move.d fnname:PLTG,$r3’ 11028 11029‘GOTPLT’ 11030 11031 Similar to ‘PLT’, but the value of the symbol is a 32-bit index 11032 into the global offset table. This is somewhat of a mix between 11033 the effect of the ‘GOT’ and the ‘PLT’ suffix; the difference to 11034 ‘GOT’ is that there will be a procedure linkage table entry 11035 created, and that the symbol is assumed to be a function entry and 11036 will be resolved by the run-time resolver as with ‘PLT’. The 11037 relocation is ‘R_CRIS_32_GOTPLT’. Example: ‘jsr 11038 [$r0+fnname:GOTPLT]’ 11039 11040‘GOTPLT16’ 11041 11042 A variant of ‘GOTPLT’ giving a 16-bit value. Its relocation name 11043 is ‘R_CRIS_16_GOTPLT’. Example: ‘jsr [$r0+fnname:GOTPLT16]’ 11044 11045‘GOTOFF’ 11046 11047 This suffix must only be attached to a local symbol, but may be 11048 used in an expression adding an offset. The value is the address 11049 of the symbol relative to the start of the global offset table. 11050 The relocation name is ‘R_CRIS_32_GOTREL’. Example: ‘move.d 11051 [$r0+localsym:GOTOFF],r3’ 11052 11053 11054File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 11055 110569.9.4.3 Register names 11057...................... 11058 11059A ‘$’ character may always prefix a general or special register name in 11060an instruction operand but is mandatory when the option 11061‘--no-underscore’ is specified or when the ‘.syntax register_prefix’ 11062directive is in effect (*note crisnous::). Register names are 11063case-insensitive. 11064 11065 11066File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 11067 110689.9.4.4 Assembler Directives 11069............................ 11070 11071There are a few CRIS-specific pseudo-directives in addition to the 11072generic ones. *Note Pseudo Ops::. Constants emitted by 11073pseudo-directives are in little-endian order for CRIS. There is no 11074support for floating-point-specific directives for CRIS. 11075 11076‘.dword EXPRESSIONS’ 11077 11078 The ‘.dword’ directive is a synonym for ‘.int’, expecting zero or 11079 more EXPRESSIONS, separated by commas. For each expression, a 11080 32-bit little-endian constant is emitted. 11081 11082‘.syntax ARGUMENT’ 11083 The ‘.syntax’ directive takes as ARGUMENT one of the following 11084 case-sensitive choices. 11085 11086 ‘no_register_prefix’ 11087 11088 The ‘.syntax no_register_prefix’ directive makes a ‘$’ 11089 character prefix on all registers optional. It overrides a 11090 previous setting, including the corresponding effect of the 11091 option ‘--no-underscore’. If this directive is used when 11092 ordinary symbols do not have a ‘_’ character prefix, care must 11093 be taken to avoid ambiguities whether an operand is a register 11094 or a symbol; using symbols with names the same as general or 11095 special registers then invoke undefined behavior. 11096 11097 ‘register_prefix’ 11098 11099 This directive makes a ‘$’ character prefix on all registers 11100 mandatory. It overrides a previous setting, including the 11101 corresponding effect of the option ‘--underscore’. 11102 11103 ‘leading_underscore’ 11104 11105 This is an assertion directive, emitting an error if the 11106 ‘--no-underscore’ option is in effect. 11107 11108 ‘no_leading_underscore’ 11109 11110 This is the opposite of the ‘.syntax leading_underscore’ 11111 directive and emits an error if the option ‘--underscore’ is 11112 in effect. 11113 11114‘.arch ARGUMENT’ 11115 This is an assertion directive, giving an error if the specified 11116 ARGUMENT is not the same as the specified or default value for the 11117 ‘--march=ARCHITECTURE’ option (*note march-option::). 11118 11119 11120File: as.info, Node: C-SKY-Dependent, Next: D10V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 11121 111229.10 C-SKY Dependent Features 11123============================= 11124 11125* Menu: 11126 11127* C-SKY Options:: Options 11128* C-SKY Syntax:: Syntax 11129 11130 11131File: as.info, Node: C-SKY Options, Next: C-SKY Syntax, Up: C-SKY-Dependent 11132 111339.10.1 Options 11134-------------- 11135 11136‘-march=ARCHNAME’ 11137 Assemble for architecture ARCHNAME. The ‘--help’ option lists 11138 valid values for ARCHNAME. 11139 11140‘-mcpu=CPUNAME’ 11141 Assemble for architecture CPUNAME. The ‘--help’ option lists valid 11142 values for CPUNAME. 11143 11144‘-EL’ 11145‘-mlittle-endian’ 11146 Generate little-endian output. 11147 11148‘-EB’ 11149‘-mbig-endian’ 11150 Generate big-endian output. 11151 11152‘-fpic’ 11153‘-pic’ 11154 Generate position-independent code. 11155 11156‘-mljump’ 11157‘-mno-ljump’ 11158 Enable/disable transformation of the short branch instructions 11159 ‘jbf’, ‘jbt’, and ‘jbr’ to ‘jmpi’. This option is for V2 11160 processors only. It is ignored on CK801 and CK802 targets, which 11161 do not support the ‘jmpi’ instruction, and is enabled by default 11162 for other processors. 11163 11164‘-mbranch-stub’ 11165‘-mno-branch-stub’ 11166 Pass through ‘R_CKCORE_PCREL_IMM26BY2’ relocations for ‘bsr’ 11167 instructions to the linker. 11168 11169 This option is only available for bare-metal C-SKY V2 ELF targets, 11170 where it is enabled by default. It cannot be used in code that 11171 will be dynamically linked against shared libraries. 11172 11173‘-force2bsr’ 11174‘-mforce2bsr’ 11175‘-no-force2bsr’ 11176‘-mno-force2bsr’ 11177 Enable/disable transformation of ‘jbsr’ instructions to ‘bsr’. 11178 This option is always enabled (and ‘-mno-force2bsr’ is ignored) for 11179 CK801/CK802 targets. It is also always enabled when 11180 ‘-mbranch-stub’ is in effect. 11181 11182‘-jsri2bsr’ 11183‘-mjsri2bsr’ 11184‘-no-jsri2bsr’ 11185‘-mno-jsri2bsr’ 11186 Enable/disable transformation of ‘jsri’ instructions to ‘bsr’. 11187 This option is enabled by default. 11188 11189‘-mnolrw’ 11190‘-mno-lrw’ 11191 Enable/disable transformation of ‘lrw’ instructions into a 11192 ‘movih’/‘ori’ pair. 11193 11194‘-melrw’ 11195‘-mno-elrw’ 11196 Enable/disable extended ‘lrw’ instructions. This option is enabled 11197 by default for CK800-series processors. 11198 11199‘-mlaf’ 11200‘-mliterals-after-func’ 11201‘-mno-laf’ 11202‘-mno-literals-after-func’ 11203 Enable/disable placement of literal pools after each function. 11204 11205‘-mlabr’ 11206‘-mliterals-after-br’ 11207‘-mno-labr’ 11208‘-mnoliterals-after-br’ 11209 Enable/disable placement of literal pools after unconditional 11210 branches. This option is enabled by default. 11211 11212‘-mistack’ 11213‘-mno-istack’ 11214 Enable/disable interrupt stack instructions. This option is 11215 enabled by default on CK801, CK802, and CK802 processors. 11216 11217 The following options explicitly enable certain optional 11218instructions. These features are also enabled implicitly by using 11219‘-mcpu=’ to specify a processor that supports it. 11220 11221‘-mhard-float’ 11222 Enable hard float instructions. 11223 11224‘-mmp’ 11225 Enable multiprocessor instructions. 11226 11227‘-mcp’ 11228 Enable coprocessor instructions. 11229 11230‘-mcache’ 11231 Enable cache prefetch instruction. 11232 11233‘-msecurity’ 11234 Enable C-SKY security instructions. 11235 11236‘-mtrust’ 11237 Enable C-SKY trust instructions. 11238 11239‘-mdsp’ 11240 Enable DSP instructions. 11241 11242‘-medsp’ 11243 Enable enhanced DSP instructions. 11244 11245‘-mvdsp’ 11246 Enable vector DSP instructions. 11247 11248 11249File: as.info, Node: C-SKY Syntax, Prev: C-SKY Options, Up: C-SKY-Dependent 11250 112519.10.2 Syntax 11252------------- 11253 11254‘as’ implements the standard C-SKY assembler syntax documented in the 11255‘C-SKY V2 CPU Applications Binary Interface Standards Manual’. 11256 11257 11258File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: C-SKY-Dependent, Up: Machine Dependencies 11259 112609.11 D10V Dependent Features 11261============================ 11262 11263* Menu: 11264 11265* D10V-Opts:: D10V Options 11266* D10V-Syntax:: Syntax 11267* D10V-Float:: Floating Point 11268* D10V-Opcodes:: Opcodes 11269 11270 11271File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 11272 112739.11.1 D10V Options 11274------------------- 11275 11276The Mitsubishi D10V version of ‘as’ has a few machine dependent options. 11277 11278‘-O’ 11279 The D10V can often execute two sub-instructions in parallel. When 11280 this option is used, ‘as’ will attempt to optimize its output by 11281 detecting when instructions can be executed in parallel. 11282‘--nowarnswap’ 11283 To optimize execution performance, ‘as’ will sometimes swap the 11284 order of instructions. Normally this generates a warning. When 11285 this option is used, no warning will be generated when instructions 11286 are swapped. 11287‘--gstabs-packing’ 11288‘--no-gstabs-packing’ 11289 ‘as’ packs adjacent short instructions into a single packed 11290 instruction. ‘--no-gstabs-packing’ turns instruction packing off 11291 if ‘--gstabs’ is specified as well; ‘--gstabs-packing’ (the 11292 default) turns instruction packing on even when ‘--gstabs’ is 11293 specified. 11294 11295 11296File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 11297 112989.11.2 Syntax 11299------------- 11300 11301The D10V syntax is based on the syntax in Mitsubishi’s D10V architecture 11302manual. The differences are detailed below. 11303 11304* Menu: 11305 11306* D10V-Size:: Size Modifiers 11307* D10V-Subs:: Sub-Instructions 11308* D10V-Chars:: Special Characters 11309* D10V-Regs:: Register Names 11310* D10V-Addressing:: Addressing Modes 11311* D10V-Word:: @WORD Modifier 11312 11313 11314File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 11315 113169.11.2.1 Size Modifiers 11317....................... 11318 11319The D10V version of ‘as’ uses the instruction names in the D10V 11320Architecture Manual. However, the names in the manual are sometimes 11321ambiguous. There are instruction names that can assemble to a short or 11322long form opcode. How does the assembler pick the correct form? ‘as’ 11323will always pick the smallest form if it can. When dealing with a 11324symbol that is not defined yet when a line is being assembled, it will 11325always use the long form. If you need to force the assembler to use 11326either the short or long form of the instruction, you can append either 11327‘.s’ (short) or ‘.l’ (long) to it. For example, if you are writing an 11328assembly program and you want to do a branch to a symbol that is defined 11329later in your program, you can write ‘bra.s foo’. Objdump and GDB will 11330always append ‘.s’ or ‘.l’ to instructions which have both short and 11331long forms. 11332 11333 11334File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 11335 113369.11.2.2 Sub-Instructions 11337......................... 11338 11339The D10V assembler takes as input a series of instructions, either 11340one-per-line, or in the special two-per-line format described in the 11341next section. Some of these instructions will be short-form or 11342sub-instructions. These sub-instructions can be packed into a single 11343instruction. The assembler will do this automatically. It will also 11344detect when it should not pack instructions. For example, when a label 11345is defined, the next instruction will never be packaged with the 11346previous one. Whenever a branch and link instruction is called, it will 11347not be packaged with the next instruction so the return address will be 11348valid. Nops are automatically inserted when necessary. 11349 11350 If you do not want the assembler automatically making these 11351decisions, you can control the packaging and execution type (parallel or 11352sequential) with the special execution symbols described in the next 11353section. 11354 11355 11356File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 11357 113589.11.2.3 Special Characters 11359........................... 11360 11361A semicolon (‘;’) can be used anywhere on a line to start a comment that 11362extends to the end of the line. 11363 11364 If a ‘#’ appears as the first character of a line, the whole line is 11365treated as a comment, but in this case the line could also be a logical 11366line number directive (*note Comments::) or a preprocessor control 11367command (*note Preprocessing::). 11368 11369 Sub-instructions may be executed in order, in reverse-order, or in 11370parallel. Instructions listed in the standard one-per-line format will 11371be executed sequentially. To specify the executing order, use the 11372following symbols: 11373‘->’ 11374 Sequential with instruction on the left first. 11375‘<-’ 11376 Sequential with instruction on the right first. 11377‘||’ 11378 Parallel 11379 The D10V syntax allows either one instruction per line, one 11380instruction per line with the execution symbol, or two instructions per 11381line. For example 11382‘abs a1 -> abs r0’ 11383 Execute these sequentially. The instruction on the right is in the 11384 right container and is executed second. 11385‘abs r0 <- abs a1’ 11386 Execute these reverse-sequentially. The instruction on the right 11387 is in the right container, and is executed first. 11388‘ld2w r2,@r8+ || mac a0,r0,r7’ 11389 Execute these in parallel. 11390‘ld2w r2,@r8+ ||’ 11391‘mac a0,r0,r7’ 11392 Two-line format. Execute these in parallel. 11393‘ld2w r2,@r8+’ 11394‘mac a0,r0,r7’ 11395 Two-line format. Execute these sequentially. Assembler will put 11396 them in the proper containers. 11397‘ld2w r2,@r8+ ->’ 11398‘mac a0,r0,r7’ 11399 Two-line format. Execute these sequentially. Same as above but 11400 second instruction will always go into right container. 11401 Since ‘$’ has no special meaning, you may use it in symbol names. 11402 11403 11404File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 11405 114069.11.2.4 Register Names 11407....................... 11408 11409You can use the predefined symbols ‘r0’ through ‘r15’ to refer to the 11410D10V registers. You can also use ‘sp’ as an alias for ‘r15’. The 11411accumulators are ‘a0’ and ‘a1’. There are special register-pair names 11412that may optionally be used in opcodes that require even-numbered 11413registers. Register names are not case sensitive. 11414 11415 Register Pairs 11416‘r0-r1’ 11417‘r2-r3’ 11418‘r4-r5’ 11419‘r6-r7’ 11420‘r8-r9’ 11421‘r10-r11’ 11422‘r12-r13’ 11423‘r14-r15’ 11424 11425 The D10V also has predefined symbols for these control registers and 11426status bits: 11427‘psw’ 11428 Processor Status Word 11429‘bpsw’ 11430 Backup Processor Status Word 11431‘pc’ 11432 Program Counter 11433‘bpc’ 11434 Backup Program Counter 11435‘rpt_c’ 11436 Repeat Count 11437‘rpt_s’ 11438 Repeat Start address 11439‘rpt_e’ 11440 Repeat End address 11441‘mod_s’ 11442 Modulo Start address 11443‘mod_e’ 11444 Modulo End address 11445‘iba’ 11446 Instruction Break Address 11447‘f0’ 11448 Flag 0 11449‘f1’ 11450 Flag 1 11451‘c’ 11452 Carry flag 11453 11454 11455File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 11456 114579.11.2.5 Addressing Modes 11458......................... 11459 11460‘as’ understands the following addressing modes for the D10V. ‘RN’ in 11461the following refers to any of the numbered registers, but _not_ the 11462control registers. 11463‘RN’ 11464 Register direct 11465‘@RN’ 11466 Register indirect 11467‘@RN+’ 11468 Register indirect with post-increment 11469‘@RN-’ 11470 Register indirect with post-decrement 11471‘@-SP’ 11472 Register indirect with pre-decrement 11473‘@(DISP, RN)’ 11474 Register indirect with displacement 11475‘ADDR’ 11476 PC relative address (for branch or rep). 11477‘#IMM’ 11478 Immediate data (the ‘#’ is optional and ignored) 11479 11480 11481File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 11482 114839.11.2.6 @WORD Modifier 11484....................... 11485 11486Any symbol followed by ‘@word’ will be replaced by the symbol’s value 11487shifted right by 2. This is used in situations such as loading a 11488register with the address of a function (or any other code fragment). 11489For example, if you want to load a register with the location of the 11490function ‘main’ then jump to that function, you could do it as follows: 11491 ldi r2, main@word 11492 jmp r2 11493 11494 11495File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 11496 114979.11.3 Floating Point 11498--------------------- 11499 11500The D10V has no hardware floating point, but the ‘.float’ and ‘.double’ 11501directives generates IEEE floating-point numbers for compatibility with 11502other development tools. 11503 11504 11505File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 11506 115079.11.4 Opcodes 11508-------------- 11509 11510For detailed information on the D10V machine instruction set, see ‘D10V 11511Architecture: A VLIW Microprocessor for Multimedia Applications’ 11512(Mitsubishi Electric Corp.). ‘as’ implements all the standard D10V 11513opcodes. The only changes are those described in the section on size 11514modifiers 11515 11516 11517File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 11518 115199.12 D30V Dependent Features 11520============================ 11521 11522* Menu: 11523 11524* D30V-Opts:: D30V Options 11525* D30V-Syntax:: Syntax 11526* D30V-Float:: Floating Point 11527* D30V-Opcodes:: Opcodes 11528 11529 11530File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 11531 115329.12.1 D30V Options 11533------------------- 11534 11535The Mitsubishi D30V version of ‘as’ has a few machine dependent options. 11536 11537‘-O’ 11538 The D30V can often execute two sub-instructions in parallel. When 11539 this option is used, ‘as’ will attempt to optimize its output by 11540 detecting when instructions can be executed in parallel. 11541 11542‘-n’ 11543 When this option is used, ‘as’ will issue a warning every time it 11544 adds a nop instruction. 11545 11546‘-N’ 11547 When this option is used, ‘as’ will issue a warning if it needs to 11548 insert a nop after a 32-bit multiply before a load or 16-bit 11549 multiply instruction. 11550 11551 11552File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 11553 115549.12.2 Syntax 11555------------- 11556 11557The D30V syntax is based on the syntax in Mitsubishi’s D30V architecture 11558manual. The differences are detailed below. 11559 11560* Menu: 11561 11562* D30V-Size:: Size Modifiers 11563* D30V-Subs:: Sub-Instructions 11564* D30V-Chars:: Special Characters 11565* D30V-Guarded:: Guarded Execution 11566* D30V-Regs:: Register Names 11567* D30V-Addressing:: Addressing Modes 11568 11569 11570File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 11571 115729.12.2.1 Size Modifiers 11573....................... 11574 11575The D30V version of ‘as’ uses the instruction names in the D30V 11576Architecture Manual. However, the names in the manual are sometimes 11577ambiguous. There are instruction names that can assemble to a short or 11578long form opcode. How does the assembler pick the correct form? ‘as’ 11579will always pick the smallest form if it can. When dealing with a 11580symbol that is not defined yet when a line is being assembled, it will 11581always use the long form. If you need to force the assembler to use 11582either the short or long form of the instruction, you can append either 11583‘.s’ (short) or ‘.l’ (long) to it. For example, if you are writing an 11584assembly program and you want to do a branch to a symbol that is defined 11585later in your program, you can write ‘bra.s foo’. Objdump and GDB will 11586always append ‘.s’ or ‘.l’ to instructions which have both short and 11587long forms. 11588 11589 11590File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 11591 115929.12.2.2 Sub-Instructions 11593......................... 11594 11595The D30V assembler takes as input a series of instructions, either 11596one-per-line, or in the special two-per-line format described in the 11597next section. Some of these instructions will be short-form or 11598sub-instructions. These sub-instructions can be packed into a single 11599instruction. The assembler will do this automatically. It will also 11600detect when it should not pack instructions. For example, when a label 11601is defined, the next instruction will never be packaged with the 11602previous one. Whenever a branch and link instruction is called, it will 11603not be packaged with the next instruction so the return address will be 11604valid. Nops are automatically inserted when necessary. 11605 11606 If you do not want the assembler automatically making these 11607decisions, you can control the packaging and execution type (parallel or 11608sequential) with the special execution symbols described in the next 11609section. 11610 11611 11612File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 11613 116149.12.2.3 Special Characters 11615........................... 11616 11617A semicolon (‘;’) can be used anywhere on a line to start a comment that 11618extends to the end of the line. 11619 11620 If a ‘#’ appears as the first character of a line, the whole line is 11621treated as a comment, but in this case the line could also be a logical 11622line number directive (*note Comments::) or a preprocessor control 11623command (*note Preprocessing::). 11624 11625 Sub-instructions may be executed in order, in reverse-order, or in 11626parallel. Instructions listed in the standard one-per-line format will 11627be executed sequentially unless you use the ‘-O’ option. 11628 11629 To specify the executing order, use the following symbols: 11630‘->’ 11631 Sequential with instruction on the left first. 11632 11633‘<-’ 11634 Sequential with instruction on the right first. 11635 11636‘||’ 11637 Parallel 11638 11639 The D30V syntax allows either one instruction per line, one 11640instruction per line with the execution symbol, or two instructions per 11641line. For example 11642‘abs r2,r3 -> abs r4,r5’ 11643 Execute these sequentially. The instruction on the right is in the 11644 right container and is executed second. 11645 11646‘abs r2,r3 <- abs r4,r5’ 11647 Execute these reverse-sequentially. The instruction on the right 11648 is in the right container, and is executed first. 11649 11650‘abs r2,r3 || abs r4,r5’ 11651 Execute these in parallel. 11652 11653‘ldw r2,@(r3,r4) ||’ 11654‘mulx r6,r8,r9’ 11655 Two-line format. Execute these in parallel. 11656 11657‘mulx a0,r8,r9’ 11658‘stw r2,@(r3,r4)’ 11659 Two-line format. Execute these sequentially unless ‘-O’ option is 11660 used. If the ‘-O’ option is used, the assembler will determine if 11661 the instructions could be done in parallel (the above two 11662 instructions can be done in parallel), and if so, emit them as 11663 parallel instructions. The assembler will put them in the proper 11664 containers. In the above example, the assembler will put the ‘stw’ 11665 instruction in left container and the ‘mulx’ instruction in the 11666 right container. 11667 11668‘stw r2,@(r3,r4) ->’ 11669‘mulx a0,r8,r9’ 11670 Two-line format. Execute the ‘stw’ instruction followed by the 11671 ‘mulx’ instruction sequentially. The first instruction goes in the 11672 left container and the second instruction goes into right 11673 container. The assembler will give an error if the machine 11674 ordering constraints are violated. 11675 11676‘stw r2,@(r3,r4) <-’ 11677‘mulx a0,r8,r9’ 11678 Same as previous example, except that the ‘mulx’ instruction is 11679 executed before the ‘stw’ instruction. 11680 11681 Since ‘$’ has no special meaning, you may use it in symbol names. 11682 11683 11684File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 11685 116869.12.2.4 Guarded Execution 11687.......................... 11688 11689‘as’ supports the full range of guarded execution directives for each 11690instruction. Just append the directive after the instruction proper. 11691The directives are: 11692 11693‘/tx’ 11694 Execute the instruction if flag f0 is true. 11695‘/fx’ 11696 Execute the instruction if flag f0 is false. 11697‘/xt’ 11698 Execute the instruction if flag f1 is true. 11699‘/xf’ 11700 Execute the instruction if flag f1 is false. 11701‘/tt’ 11702 Execute the instruction if both flags f0 and f1 are true. 11703‘/tf’ 11704 Execute the instruction if flag f0 is true and flag f1 is false. 11705 11706 11707File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 11708 117099.12.2.5 Register Names 11710....................... 11711 11712You can use the predefined symbols ‘r0’ through ‘r63’ to refer to the 11713D30V registers. You can also use ‘sp’ as an alias for ‘r63’ and ‘link’ 11714as an alias for ‘r62’. The accumulators are ‘a0’ and ‘a1’. 11715 11716 The D30V also has predefined symbols for these control registers and 11717status bits: 11718‘psw’ 11719 Processor Status Word 11720‘bpsw’ 11721 Backup Processor Status Word 11722‘pc’ 11723 Program Counter 11724‘bpc’ 11725 Backup Program Counter 11726‘rpt_c’ 11727 Repeat Count 11728‘rpt_s’ 11729 Repeat Start address 11730‘rpt_e’ 11731 Repeat End address 11732‘mod_s’ 11733 Modulo Start address 11734‘mod_e’ 11735 Modulo End address 11736‘iba’ 11737 Instruction Break Address 11738‘f0’ 11739 Flag 0 11740‘f1’ 11741 Flag 1 11742‘f2’ 11743 Flag 2 11744‘f3’ 11745 Flag 3 11746‘f4’ 11747 Flag 4 11748‘f5’ 11749 Flag 5 11750‘f6’ 11751 Flag 6 11752‘f7’ 11753 Flag 7 11754‘s’ 11755 Same as flag 4 (saturation flag) 11756‘v’ 11757 Same as flag 5 (overflow flag) 11758‘va’ 11759 Same as flag 6 (sticky overflow flag) 11760‘c’ 11761 Same as flag 7 (carry/borrow flag) 11762‘b’ 11763 Same as flag 7 (carry/borrow flag) 11764 11765 11766File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 11767 117689.12.2.6 Addressing Modes 11769......................... 11770 11771‘as’ understands the following addressing modes for the D30V. ‘RN’ in 11772the following refers to any of the numbered registers, but _not_ the 11773control registers. 11774‘RN’ 11775 Register direct 11776‘@RN’ 11777 Register indirect 11778‘@RN+’ 11779 Register indirect with post-increment 11780‘@RN-’ 11781 Register indirect with post-decrement 11782‘@-SP’ 11783 Register indirect with pre-decrement 11784‘@(DISP, RN)’ 11785 Register indirect with displacement 11786‘ADDR’ 11787 PC relative address (for branch or rep). 11788‘#IMM’ 11789 Immediate data (the ‘#’ is optional and ignored) 11790 11791 11792File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 11793 117949.12.3 Floating Point 11795--------------------- 11796 11797The D30V has no hardware floating point, but the ‘.float’ and ‘.double’ 11798directives generates IEEE floating-point numbers for compatibility with 11799other development tools. 11800 11801 11802File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 11803 118049.12.4 Opcodes 11805-------------- 11806 11807For detailed information on the D30V machine instruction set, see ‘D30V 11808Architecture: A VLIW Microprocessor for Multimedia Applications’ 11809(Mitsubishi Electric Corp.). ‘as’ implements all the standard D30V 11810opcodes. The only changes are those described in the section on size 11811modifiers 11812 11813 11814File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 11815 118169.13 Epiphany Dependent Features 11817================================ 11818 11819* Menu: 11820 11821* Epiphany Options:: Options 11822* Epiphany Syntax:: Epiphany Syntax 11823 11824 11825File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent 11826 118279.13.1 Options 11828-------------- 11829 11830‘as’ has two additional command-line options for the Epiphany 11831architecture. 11832 11833‘-mepiphany’ 11834 Specifies that the both 32 and 16 bit instructions are allowed. 11835 This is the default behavior. 11836 11837‘-mepiphany16’ 11838 Restricts the permitted instructions to just the 16 bit set. 11839 11840 11841File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent 11842 118439.13.2 Epiphany Syntax 11844---------------------- 11845 11846* Menu: 11847 11848* Epiphany-Chars:: Special Characters 11849 11850 11851File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax 11852 118539.13.2.1 Special Characters 11854........................... 11855 11856The presence of a ‘;’ on a line indicates the start of a comment that 11857extends to the end of the current line. 11858 11859 If a ‘#’ appears as the first character of a line then the whole line 11860is treated as a comment, but in this case the line could also be a 11861logical line number directive (*note Comments::) or a preprocessor 11862control command (*note Preprocessing::). 11863 11864 The ‘`’ character can be used to separate statements on the same 11865line. 11866 11867 11868File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies 11869 118709.14 H8/300 Dependent Features 11871============================== 11872 11873* Menu: 11874 11875* H8/300 Options:: Options 11876* H8/300 Syntax:: Syntax 11877* H8/300 Floating Point:: Floating Point 11878* H8/300 Directives:: H8/300 Machine Directives 11879* H8/300 Opcodes:: Opcodes 11880 11881 11882File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 11883 118849.14.1 Options 11885-------------- 11886 11887The Renesas H8/300 version of ‘as’ has one machine-dependent option: 11888 11889‘-h-tick-hex’ 11890 Support H’00 style hex constants in addition to 0x00 style. 11891 11892‘-mach=NAME’ 11893 Sets the H8300 machine variant. The following machine names are 11894 recognised: ‘h8300h’, ‘h8300hn’, ‘h8300s’, ‘h8300sn’, ‘h8300sx’ and 11895 ‘h8300sxn’. 11896 11897 11898File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 11899 119009.14.2 Syntax 11901------------- 11902 11903* Menu: 11904 11905* H8/300-Chars:: Special Characters 11906* H8/300-Regs:: Register Names 11907* H8/300-Addressing:: Addressing Modes 11908 11909 11910File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 11911 119129.14.2.1 Special Characters 11913........................... 11914 11915‘;’ is the line comment character. 11916 11917 ‘$’ can be used instead of a newline to separate statements. 11918Therefore _you may not use ‘$’ in symbol names_ on the H8/300. 11919 11920 11921File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 11922 119239.14.2.2 Register Names 11924....................... 11925 11926You can use predefined symbols of the form ‘rNh’ and ‘rNl’ to refer to 11927the H8/300 registers as sixteen 8-bit general-purpose registers. N is a 11928digit from ‘0’ to ‘7’); for instance, both ‘r0h’ and ‘r7l’ are valid 11929register names. 11930 11931 You can also use the eight predefined symbols ‘rN’ to refer to the 11932H8/300 registers as 16-bit registers (you must use this form for 11933addressing). 11934 11935 On the H8/300H, you can also use the eight predefined symbols ‘erN’ 11936(‘er0’ ... ‘er7’) to refer to the 32-bit general purpose registers. 11937 11938 The two control registers are called ‘pc’ (program counter; a 16-bit 11939register, except on the H8/300H where it is 24 bits) and ‘ccr’ 11940(condition code register; an 8-bit register). ‘r7’ is used as the stack 11941pointer, and can also be called ‘sp’. 11942 11943 11944File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 11945 119469.14.2.3 Addressing Modes 11947......................... 11948 11949as understands the following addressing modes for the H8/300: 11950‘rN’ 11951 Register direct 11952 11953‘@rN’ 11954 Register indirect 11955 11956‘@(D, rN)’ 11957‘@(D:16, rN)’ 11958‘@(D:24, rN)’ 11959 Register indirect: 16-bit or 24-bit displacement D from register N. 11960 (24-bit displacements are only meaningful on the H8/300H.) 11961 11962‘@rN+’ 11963 Register indirect with post-increment 11964 11965‘@-rN’ 11966 Register indirect with pre-decrement 11967 11968‘@AA’ 11969‘@AA:8’ 11970‘@AA:16’ 11971‘@AA:24’ 11972 Absolute address ‘aa’. (The address size ‘:24’ only makes sense on 11973 the H8/300H.) 11974 11975‘#XX’ 11976‘#XX:8’ 11977‘#XX:16’ 11978‘#XX:32’ 11979 Immediate data XX. You may specify the ‘:8’, ‘:16’, or ‘:32’ for 11980 clarity, if you wish; but ‘as’ neither requires this nor uses 11981 it—the data size required is taken from context. 11982 11983‘@@AA’ 11984‘@@AA:8’ 11985 Memory indirect. You may specify the ‘:8’ for clarity, if you 11986 wish; but ‘as’ neither requires this nor uses it. 11987 11988 11989File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 11990 119919.14.3 Floating Point 11992--------------------- 11993 11994The H8/300 family has no hardware floating point, but the ‘.float’ 11995directive generates IEEE floating-point numbers for compatibility with 11996other development tools. 11997 11998 11999File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 12000 120019.14.4 H8/300 Machine Directives 12002-------------------------------- 12003 12004‘as’ has the following machine-dependent directives for the H8/300: 12005 12006‘.h8300h’ 12007 Recognize and emit additional instructions for the H8/300H variant, 12008 and also make ‘.int’ emit 32-bit numbers rather than the usual 12009 (16-bit) for the H8/300 family. 12010 12011‘.h8300s’ 12012 Recognize and emit additional instructions for the H8S variant, and 12013 also make ‘.int’ emit 32-bit numbers rather than the usual (16-bit) 12014 for the H8/300 family. 12015 12016‘.h8300hn’ 12017 Recognize and emit additional instructions for the H8/300H variant 12018 in normal mode, and also make ‘.int’ emit 32-bit numbers rather 12019 than the usual (16-bit) for the H8/300 family. 12020 12021‘.h8300sn’ 12022 Recognize and emit additional instructions for the H8S variant in 12023 normal mode, and also make ‘.int’ emit 32-bit numbers rather than 12024 the usual (16-bit) for the H8/300 family. 12025 12026 On the H8/300 family (including the H8/300H) ‘.word’ directives 12027generate 16-bit numbers. 12028 12029 12030File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 12031 120329.14.5 Opcodes 12033-------------- 12034 12035For detailed information on the H8/300 machine instruction set, see 12036‘H8/300 Series Programming Manual’. For information specific to the 12037H8/300H, see ‘H8/300H Series Programming Manual’ (Renesas). 12038 12039 ‘as’ implements all the standard H8/300 opcodes. No additional 12040pseudo-instructions are needed on this family. 12041 12042 The following table summarizes the H8/300 opcodes, and their 12043arguments. Entries marked ‘*’ are opcodes used only on the H8/300H. 12044 12045 Legend: 12046 Rs source register 12047 Rd destination register 12048 abs absolute address 12049 imm immediate data 12050 disp:N N-bit displacement from a register 12051 pcrel:N N-bit displacement relative to program counter 12052 12053 add.b #imm,rd * andc #imm,ccr 12054 add.b rs,rd band #imm,rd 12055 add.w rs,rd band #imm,@rd 12056 * add.w #imm,rd band #imm,@abs:8 12057 * add.l rs,rd bra pcrel:8 12058 * add.l #imm,rd * bra pcrel:16 12059 adds #imm,rd bt pcrel:8 12060 addx #imm,rd * bt pcrel:16 12061 addx rs,rd brn pcrel:8 12062 and.b #imm,rd * brn pcrel:16 12063 and.b rs,rd bf pcrel:8 12064 * and.w rs,rd * bf pcrel:16 12065 * and.w #imm,rd bhi pcrel:8 12066 * and.l #imm,rd * bhi pcrel:16 12067 * and.l rs,rd bls pcrel:8 12068 * bls pcrel:16 bld #imm,rd 12069 bcc pcrel:8 bld #imm,@rd 12070 * bcc pcrel:16 bld #imm,@abs:8 12071 bhs pcrel:8 bnot #imm,rd 12072 * bhs pcrel:16 bnot #imm,@rd 12073 bcs pcrel:8 bnot #imm,@abs:8 12074 * bcs pcrel:16 bnot rs,rd 12075 blo pcrel:8 bnot rs,@rd 12076 * blo pcrel:16 bnot rs,@abs:8 12077 bne pcrel:8 bor #imm,rd 12078 * bne pcrel:16 bor #imm,@rd 12079 beq pcrel:8 bor #imm,@abs:8 12080 * beq pcrel:16 bset #imm,rd 12081 bvc pcrel:8 bset #imm,@rd 12082 * bvc pcrel:16 bset #imm,@abs:8 12083 bvs pcrel:8 bset rs,rd 12084 * bvs pcrel:16 bset rs,@rd 12085 bpl pcrel:8 bset rs,@abs:8 12086 * bpl pcrel:16 bsr pcrel:8 12087 bmi pcrel:8 bsr pcrel:16 12088 * bmi pcrel:16 bst #imm,rd 12089 bge pcrel:8 bst #imm,@rd 12090 * bge pcrel:16 bst #imm,@abs:8 12091 blt pcrel:8 btst #imm,rd 12092 * blt pcrel:16 btst #imm,@rd 12093 bgt pcrel:8 btst #imm,@abs:8 12094 * bgt pcrel:16 btst rs,rd 12095 ble pcrel:8 btst rs,@rd 12096 * ble pcrel:16 btst rs,@abs:8 12097 bclr #imm,rd bxor #imm,rd 12098 bclr #imm,@rd bxor #imm,@rd 12099 bclr #imm,@abs:8 bxor #imm,@abs:8 12100 bclr rs,rd cmp.b #imm,rd 12101 bclr rs,@rd cmp.b rs,rd 12102 bclr rs,@abs:8 cmp.w rs,rd 12103 biand #imm,rd cmp.w rs,rd 12104 biand #imm,@rd * cmp.w #imm,rd 12105 biand #imm,@abs:8 * cmp.l #imm,rd 12106 bild #imm,rd * cmp.l rs,rd 12107 bild #imm,@rd daa rs 12108 bild #imm,@abs:8 das rs 12109 bior #imm,rd dec.b rs 12110 bior #imm,@rd * dec.w #imm,rd 12111 bior #imm,@abs:8 * dec.l #imm,rd 12112 bist #imm,rd divxu.b rs,rd 12113 bist #imm,@rd * divxu.w rs,rd 12114 bist #imm,@abs:8 * divxs.b rs,rd 12115 bixor #imm,rd * divxs.w rs,rd 12116 bixor #imm,@rd eepmov 12117 bixor #imm,@abs:8 * eepmovw 12118 * exts.w rd mov.w rs,@abs:16 12119 * exts.l rd * mov.l #imm,rd 12120 * extu.w rd * mov.l rs,rd 12121 * extu.l rd * mov.l @rs,rd 12122 inc rs * mov.l @(disp:16,rs),rd 12123 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 12124 * inc.l #imm,rd * mov.l @rs+,rd 12125 jmp @rs * mov.l @abs:16,rd 12126 jmp abs * mov.l @abs:24,rd 12127 jmp @@abs:8 * mov.l rs,@rd 12128 jsr @rs * mov.l rs,@(disp:16,rd) 12129 jsr abs * mov.l rs,@(disp:24,rd) 12130 jsr @@abs:8 * mov.l rs,@-rd 12131 ldc #imm,ccr * mov.l rs,@abs:16 12132 ldc rs,ccr * mov.l rs,@abs:24 12133 * ldc @abs:16,ccr movfpe @abs:16,rd 12134 * ldc @abs:24,ccr movtpe rs,@abs:16 12135 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 12136 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 12137 * ldc @rs+,ccr * mulxs.b rs,rd 12138 * ldc @rs,ccr * mulxs.w rs,rd 12139 * mov.b @(disp:24,rs),rd neg.b rs 12140 * mov.b rs,@(disp:24,rd) * neg.w rs 12141 mov.b @abs:16,rd * neg.l rs 12142 mov.b rs,rd nop 12143 mov.b @abs:8,rd not.b rs 12144 mov.b rs,@abs:8 * not.w rs 12145 mov.b rs,rd * not.l rs 12146 mov.b #imm,rd or.b #imm,rd 12147 mov.b @rs,rd or.b rs,rd 12148 mov.b @(disp:16,rs),rd * or.w #imm,rd 12149 mov.b @rs+,rd * or.w rs,rd 12150 mov.b @abs:8,rd * or.l #imm,rd 12151 mov.b rs,@rd * or.l rs,rd 12152 mov.b rs,@(disp:16,rd) orc #imm,ccr 12153 mov.b rs,@-rd pop.w rs 12154 mov.b rs,@abs:8 * pop.l rs 12155 mov.w rs,@rd push.w rs 12156 * mov.w @(disp:24,rs),rd * push.l rs 12157 * mov.w rs,@(disp:24,rd) rotl.b rs 12158 * mov.w @abs:24,rd * rotl.w rs 12159 * mov.w rs,@abs:24 * rotl.l rs 12160 mov.w rs,rd rotr.b rs 12161 mov.w #imm,rd * rotr.w rs 12162 mov.w @rs,rd * rotr.l rs 12163 mov.w @(disp:16,rs),rd rotxl.b rs 12164 mov.w @rs+,rd * rotxl.w rs 12165 mov.w @abs:16,rd * rotxl.l rs 12166 mov.w rs,@(disp:16,rd) rotxr.b rs 12167 mov.w rs,@-rd * rotxr.w rs 12168 * rotxr.l rs * stc ccr,@(disp:24,rd) 12169 bpt * stc ccr,@-rd 12170 rte * stc ccr,@abs:16 12171 rts * stc ccr,@abs:24 12172 shal.b rs sub.b rs,rd 12173 * shal.w rs sub.w rs,rd 12174 * shal.l rs * sub.w #imm,rd 12175 shar.b rs * sub.l rs,rd 12176 * shar.w rs * sub.l #imm,rd 12177 * shar.l rs subs #imm,rd 12178 shll.b rs subx #imm,rd 12179 * shll.w rs subx rs,rd 12180 * shll.l rs * trapa #imm 12181 shlr.b rs xor #imm,rd 12182 * shlr.w rs xor rs,rd 12183 * shlr.l rs * xor.w #imm,rd 12184 sleep * xor.w rs,rd 12185 stc ccr,rd * xor.l #imm,rd 12186 * stc ccr,@rs * xor.l rs,rd 12187 * stc ccr,@(disp:16,rd) xorc #imm,ccr 12188 12189 Four H8/300 instructions (‘add’, ‘cmp’, ‘mov’, ‘sub’) are defined 12190with variants using the suffixes ‘.b’, ‘.w’, and ‘.l’ to specify the 12191size of a memory operand. ‘as’ supports these suffixes, but does not 12192require them; since one of the operands is always a register, ‘as’ can 12193deduce the correct size. 12194 12195 For example, since ‘r0’ refers to a 16-bit register, 12196 mov r0,@foo 12197is equivalent to 12198 mov.w r0,@foo 12199 12200 If you use the size suffixes, ‘as’ issues a warning when the suffix 12201and the register size do not match. 12202 12203 12204File: as.info, Node: HPPA-Dependent, Next: i386-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 12205 122069.15 HPPA Dependent Features 12207============================ 12208 12209* Menu: 12210 12211* HPPA Notes:: Notes 12212* HPPA Options:: Options 12213* HPPA Syntax:: Syntax 12214* HPPA Floating Point:: Floating Point 12215* HPPA Directives:: HPPA Machine Directives 12216* HPPA Opcodes:: Opcodes 12217 12218 12219File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 12220 122219.15.1 Notes 12222------------ 12223 12224As a back end for GNU CC ‘as’ has been thoroughly tested and should work 12225extremely well. We have tested it only minimally on hand written 12226assembly code and no one has tested it much on the assembly output from 12227the HP compilers. 12228 12229 The format of the debugging sections has changed since the original 12230‘as’ port (version 1.3X) was released; therefore, you must rebuild all 12231HPPA objects and libraries with the new assembler so that you can debug 12232the final executable. 12233 12234 The HPPA ‘as’ port generates a small subset of the relocations 12235available in the SOM and ELF object file formats. Additional relocation 12236support will be added as it becomes necessary. 12237 12238 12239File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 12240 122419.15.2 Options 12242-------------- 12243 12244‘as’ has no machine-dependent command-line options for the HPPA. 12245 12246 12247File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 12248 122499.15.3 Syntax 12250------------- 12251 12252The assembler syntax closely follows the HPPA instruction set reference 12253manual; assembler directives and general syntax closely follow the HPPA 12254assembly language reference manual, with a few noteworthy differences. 12255 12256 First, a colon may immediately follow a label definition. This is 12257simply for compatibility with how most assembly language programmers 12258write code. 12259 12260 Some obscure expression parsing problems may affect hand written code 12261which uses the ‘spop’ instructions, or code which makes significant use 12262of the ‘!’ line separator. 12263 12264 ‘as’ is much less forgiving about missing arguments and other similar 12265oversights than the HP assembler. ‘as’ notifies you of missing 12266arguments as syntax errors; this is regarded as a feature, not a bug. 12267 12268 Finally, ‘as’ allows you to use an external symbol without explicitly 12269importing the symbol. _Warning:_ in the future this will be an error 12270for HPPA targets. 12271 12272 Special characters for HPPA targets include: 12273 12274 ‘;’ is the line comment character. 12275 12276 ‘!’ can be used instead of a newline to separate statements. 12277 12278 Since ‘$’ has no special meaning, you may use it in symbol names. 12279 12280 12281File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 12282 122839.15.4 Floating Point 12284--------------------- 12285 12286The HPPA family uses IEEE floating-point numbers. 12287 12288 12289File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 12290 122919.15.5 HPPA Assembler Directives 12292-------------------------------- 12293 12294‘as’ for the HPPA supports many additional directives for compatibility 12295with the native assembler. This section describes them only briefly. 12296For detailed information on HPPA-specific assembler directives, see 12297‘HP9000 Series 800 Assembly Language Reference Manual’ (HP 92432-90001). 12298 12299 ‘as’ does _not_ support the following assembler directives described 12300in the HP manual: 12301 12302 .endm .liston 12303 .enter .locct 12304 .leave .macro 12305 .listoff 12306 12307 Beyond those implemented for compatibility, ‘as’ supports one 12308additional assembler directive for the HPPA: ‘.param’. It conveys 12309register argument locations for static functions. Its syntax closely 12310follows the ‘.export’ directive. 12311 12312 These are the additional directives in ‘as’ for the HPPA: 12313 12314‘.block N’ 12315‘.blockz N’ 12316 Reserve N bytes of storage, and initialize them to zero. 12317 12318‘.call’ 12319 Mark the beginning of a procedure call. Only the special case with 12320 _no arguments_ is allowed. 12321 12322‘.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]’ 12323 Specify a number of parameters and flags that define the 12324 environment for a procedure. 12325 12326 PARAM may be any of ‘frame’ (frame size), ‘entry_gr’ (end of 12327 general register range), ‘entry_fr’ (end of float register range), 12328 ‘entry_sr’ (end of space register range). 12329 12330 The values for FLAG are ‘calls’ or ‘caller’ (proc has subroutines), 12331 ‘no_calls’ (proc does not call subroutines), ‘save_rp’ (preserve 12332 return pointer), ‘save_sp’ (proc preserves stack pointer), 12333 ‘no_unwind’ (do not unwind this proc), ‘hpux_int’ (proc is 12334 interrupt routine). 12335 12336‘.code’ 12337 Assemble into the standard section called ‘$TEXT$’, subsection 12338 ‘$CODE$’. 12339 12340‘.copyright "STRING"’ 12341 In the SOM object format, insert STRING into the object code, 12342 marked as a copyright string. 12343 12344‘.copyright "STRING"’ 12345 In the ELF object format, insert STRING into the object code, 12346 marked as a version string. 12347 12348‘.enter’ 12349 Not yet supported; the assembler rejects programs containing this 12350 directive. 12351 12352‘.entry’ 12353 Mark the beginning of a procedure. 12354 12355‘.exit’ 12356 Mark the end of a procedure. 12357 12358‘.export NAME [ ,TYP ] [ ,PARAM=R ]’ 12359 Make a procedure NAME available to callers. TYP, if present, must 12360 be one of ‘absolute’, ‘code’ (ELF only, not SOM), ‘data’, ‘entry’, 12361 ‘data’, ‘entry’, ‘millicode’, ‘plabel’, ‘pri_prog’, or ‘sec_prog’. 12362 12363 PARAM, if present, provides either relocation information for the 12364 procedure arguments and result, or a privilege level. PARAM may be 12365 ‘argwN’ (where N ranges from ‘0’ to ‘3’, and indicates one of four 12366 one-word arguments); ‘rtnval’ (the procedure’s result); or 12367 ‘priv_lev’ (privilege level). For arguments or the result, R 12368 specifies how to relocate, and must be one of ‘no’ (not 12369 relocatable), ‘gr’ (argument is in general register), ‘fr’ (in 12370 floating point register), or ‘fu’ (upper half of float register). 12371 For ‘priv_lev’, R is an integer. 12372 12373‘.half N’ 12374 Define a two-byte integer constant N; synonym for the portable ‘as’ 12375 directive ‘.short’. 12376 12377‘.import NAME [ ,TYP ]’ 12378 Converse of ‘.export’; make a procedure available to call. The 12379 arguments use the same conventions as the first two arguments for 12380 ‘.export’. 12381 12382‘.label NAME’ 12383 Define NAME as a label for the current assembly location. 12384 12385‘.leave’ 12386 Not yet supported; the assembler rejects programs containing this 12387 directive. 12388 12389‘.origin LC’ 12390 Advance location counter to LC. Synonym for the ‘as’ portable 12391 directive ‘.org’. 12392 12393‘.param NAME [ ,TYP ] [ ,PARAM=R ]’ 12394 Similar to ‘.export’, but used for static procedures. 12395 12396‘.proc’ 12397 Use preceding the first statement of a procedure. 12398 12399‘.procend’ 12400 Use following the last statement of a procedure. 12401 12402‘LABEL .reg EXPR’ 12403 Synonym for ‘.equ’; define LABEL with the absolute expression EXPR 12404 as its value. 12405 12406‘.space SECNAME [ ,PARAMS ]’ 12407 Switch to section SECNAME, creating a new section by that name if 12408 necessary. You may only use PARAMS when creating a new section, 12409 not when switching to an existing one. SECNAME may identify a 12410 section by number rather than by name. 12411 12412 If specified, the list PARAMS declares attributes of the section, 12413 identified by keywords. The keywords recognized are ‘spnum=EXP’ 12414 (identify this section by the number EXP, an absolute expression), 12415 ‘sort=EXP’ (order sections according to this sort key when linking; 12416 EXP is an absolute expression), ‘unloadable’ (section contains no 12417 loadable data), ‘notdefined’ (this section defined elsewhere), and 12418 ‘private’ (data in this section not available to other programs). 12419 12420‘.spnum SECNAM’ 12421 Allocate four bytes of storage, and initialize them with the 12422 section number of the section named SECNAM. (You can define the 12423 section number with the HPPA ‘.space’ directive.) 12424 12425‘.string "STR"’ 12426 Copy the characters in the string STR to the object file. *Note 12427 Strings: Strings, for information on escape sequences you can use 12428 in ‘as’ strings. 12429 12430 _Warning!_ The HPPA version of ‘.string’ differs from the usual 12431 ‘as’ definition: it does _not_ write a zero byte after copying STR. 12432 12433‘.stringz "STR"’ 12434 Like ‘.string’, but appends a zero byte after copying STR to object 12435 file. 12436 12437‘.subspa NAME [ ,PARAMS ]’ 12438‘.nsubspa NAME [ ,PARAMS ]’ 12439 Similar to ‘.space’, but selects a subsection NAME within the 12440 current section. You may only specify PARAMS when you create a 12441 subsection (in the first instance of ‘.subspa’ for this NAME). 12442 12443 If specified, the list PARAMS declares attributes of the 12444 subsection, identified by keywords. The keywords recognized are 12445 ‘quad=EXPR’ (“quadrant” for this subsection), ‘align=EXPR’ 12446 (alignment for beginning of this subsection; a power of two), 12447 ‘access=EXPR’ (value for “access rights” field), ‘sort=EXPR’ 12448 (sorting order for this subspace in link), ‘code_only’ (subsection 12449 contains only code), ‘unloadable’ (subsection cannot be loaded into 12450 memory), ‘comdat’ (subsection is comdat), ‘common’ (subsection is 12451 common block), ‘dup_comm’ (subsection may have duplicate names), or 12452 ‘zero’ (subsection is all zeros, do not write in object file). 12453 12454 ‘.nsubspa’ always creates a new subspace with the given name, even 12455 if one with the same name already exists. 12456 12457 ‘comdat’, ‘common’ and ‘dup_comm’ can be used to implement various 12458 flavors of one-only support when using the SOM linker. The SOM 12459 linker only supports specific combinations of these flags. The 12460 details are not documented. A brief description is provided here. 12461 12462 ‘comdat’ provides a form of linkonce support. It is useful for 12463 both code and data subspaces. A ‘comdat’ subspace has a key symbol 12464 marked by the ‘is_comdat’ flag or ‘ST_COMDAT’. Only the first 12465 subspace for any given key is selected. The key symbol becomes 12466 universal in shared links. This is similar to the behavior of 12467 ‘secondary_def’ symbols. 12468 12469 ‘common’ provides Fortran named common support. It is only useful 12470 for data subspaces. Symbols with the flag ‘is_common’ retain this 12471 flag in shared links. Referencing a ‘is_common’ symbol in a shared 12472 library from outside the library doesn’t work. Thus, ‘is_common’ 12473 symbols must be output whenever they are needed. 12474 12475 ‘common’ and ‘dup_comm’ together provide Cobol common support. The 12476 subspaces in this case must all be the same length. Otherwise, 12477 this support is similar to the Fortran common support. 12478 12479 ‘dup_comm’ by itself provides a type of one-only support for code. 12480 Only the first ‘dup_comm’ subspace is selected. There is a rather 12481 complex algorithm to compare subspaces. Code symbols marked with 12482 the ‘dup_common’ flag are hidden. This support was intended for 12483 "C++ duplicate inlines". 12484 12485 A simplified technique is used to mark the flags of symbols based 12486 on the flags of their subspace. A symbol with the scope 12487 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 12488 the corresponding settings of ‘comdat’, ‘common’ and ‘dup_comm’ 12489 from the subspace, respectively. This avoids having to introduce 12490 additional directives to mark these symbols. The HP assembler sets 12491 ‘is_common’ from ‘common’. However, it doesn’t set the 12492 ‘dup_common’ from ‘dup_comm’. It doesn’t have ‘comdat’ support. 12493 12494‘.version "STR"’ 12495 Write STR as version identifier in object code. 12496 12497 12498File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 12499 125009.15.6 Opcodes 12501-------------- 12502 12503For detailed information on the HPPA machine instruction set, see 12504‘PA-RISC Architecture and Instruction Set Reference Manual’ (HP 1250509740-90039). 12506 12507 12508File: as.info, Node: i386-Dependent, Next: IA-64-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 12509 125109.16 80386 Dependent Features 12511============================= 12512 12513The i386 version ‘as’ supports both the original Intel 386 architecture 12514in both 16 and 32-bit mode as well as AMD x86-64 architecture extending 12515the Intel architecture to 64-bits. 12516 12517* Menu: 12518 12519* i386-Options:: Options 12520* i386-Directives:: X86 specific directives 12521* i386-Syntax:: Syntactical considerations 12522* i386-Mnemonics:: Instruction Naming 12523* i386-Regs:: Register Naming 12524* i386-Prefixes:: Instruction Prefixes 12525* i386-Memory:: Memory References 12526* i386-Jumps:: Handling of Jump Instructions 12527* i386-Float:: Floating Point 12528* i386-SIMD:: Intel’s MMX and AMD’s 3DNow! SIMD Operations 12529* i386-LWP:: AMD’s Lightweight Profiling Instructions 12530* i386-BMI:: Bit Manipulation Instruction 12531* i386-TBM:: AMD’s Trailing Bit Manipulation Instructions 12532* i386-16bit:: Writing 16-bit Code 12533* i386-Arch:: Specifying an x86 CPU architecture 12534* i386-ISA:: AMD64 ISA vs. Intel64 ISA 12535* i386-Bugs:: AT&T Syntax bugs 12536* i386-Notes:: Notes 12537 12538 12539File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 12540 125419.16.1 Options 12542-------------- 12543 12544The i386 version of ‘as’ has a few machine dependent options: 12545 12546‘--32 | --x32 | --64’ 12547 Select the word size, either 32 bits or 64 bits. ‘--32’ implies 12548 Intel i386 architecture, while ‘--x32’ and ‘--64’ imply AMD x86-64 12549 architecture with 32-bit or 64-bit word-size respectively. 12550 12551 These options are only available with the ELF object file format, 12552 and require that the necessary BFD support has been included (on a 12553 32-bit platform you have to add –enable-64-bit-bfd to configure 12554 enable 64-bit usage and use x86-64 as target platform). 12555 12556‘-n’ 12557 By default, x86 GAS replaces multiple nop instructions used for 12558 alignment within code sections with multi-byte nop instructions 12559 such as leal 0(%esi,1),%esi. This switch disables the optimization 12560 if a single byte nop (0x90) is explicitly specified as the fill 12561 byte for alignment. 12562 12563‘--divide’ 12564 On SVR4-derived platforms, the character ‘/’ is treated as a 12565 comment character, which means that it cannot be used in 12566 expressions. The ‘--divide’ option turns ‘/’ into a normal 12567 character. This does not disable ‘/’ at the beginning of a line 12568 starting a comment, or affect using ‘#’ for starting a comment. 12569 12570‘-march=CPU[+EXTENSION...]’ 12571 This option specifies the target processor. The assembler will 12572 issue an error message if an attempt is made to assemble an 12573 instruction which will not execute on the target processor. The 12574 following processor names are recognized: ‘i8086’, ‘i186’, ‘i286’, 12575 ‘i386’, ‘i486’, ‘i586’, ‘i686’, ‘pentium’, ‘pentiumpro’, 12576 ‘pentiumii’, ‘pentiumiii’, ‘pentium4’, ‘prescott’, ‘nocona’, 12577 ‘core’, ‘core2’, ‘corei7’, ‘iamcu’, ‘k6’, ‘k6_2’, ‘athlon’, 12578 ‘opteron’, ‘k8’, ‘amdfam10’, ‘bdver1’, ‘bdver2’, ‘bdver3’, 12579 ‘bdver4’, ‘znver1’, ‘znver2’, ‘znver3’, ‘znver4’, ‘znver5’, 12580 ‘btver1’, ‘btver2’, ‘generic32’ and ‘generic64’. 12581 12582 In addition to the basic instruction set, the assembler can be told 12583 to accept various extension mnemonics. For example, 12584 ‘-march=i686+sse4+vmx’ extends I686 with SSE4 and VMX. The 12585 following extensions are currently supported: ‘8087’, ‘287’, ‘387’, 12586 ‘687’, ‘cmov’, ‘fxsr’, ‘mmx’, ‘sse’, ‘sse2’, ‘sse3’, ‘sse4a’, 12587 ‘ssse3’, ‘sse4.1’, ‘sse4.2’, ‘sse4’, ‘avx’, ‘avx2’, ‘lahf_sahf’, 12588 ‘monitor’, ‘adx’, ‘rdseed’, ‘prfchw’, ‘smap’, ‘mpx’, ‘sha’, 12589 ‘rdpid’, ‘ptwrite’, ‘cet’, ‘gfni’, ‘vaes’, ‘vpclmulqdq’, 12590 ‘prefetchwt1’, ‘clflushopt’, ‘se1’, ‘clwb’, ‘movdiri’, ‘movdir64b’, 12591 ‘enqcmd’, ‘serialize’, ‘tsxldtrk’, ‘kl’, ‘widekl’, ‘hreset’, 12592 ‘avx512f’, ‘avx512cd’, ‘avx512er’, ‘avx512pf’, ‘avx512vl’, 12593 ‘avx512bw’, ‘avx512dq’, ‘avx512ifma’, ‘avx512vbmi’, 12594 ‘avx512_4fmaps’, ‘avx512_4vnniw’, ‘avx512_vpopcntdq’, 12595 ‘avx512_vbmi2’, ‘avx512_vnni’, ‘avx512_bitalg’, 12596 ‘avx512_vp2intersect’, ‘tdx’, ‘avx512_bf16’, ‘avx_vnni’, 12597 ‘avx512_fp16’, ‘prefetchi’, ‘avx_ifma’, ‘avx_vnni_int8’, 12598 ‘cmpccxadd’, ‘wrmsrns’, ‘msrlist’, ‘avx_ne_convert’, ‘rao_int’, 12599 ‘fred’, ‘lkgs’, ‘avx_vnni_int16’, ‘sha512’, ‘sm3’, ‘sm4’, ‘pbndkb’, 12600 ‘avx10.1’, ‘avx10.1/512’, ‘avx10.1/256’, ‘avx10.1/128’, ‘user_msr’, 12601 ‘apx_f’, ‘amx_int8’, ‘amx_bf16’, ‘amx_fp16’, ‘amx_complex’, 12602 ‘amx_tile’, ‘vmx’, ‘vmfunc’, ‘smx’, ‘xsave’, ‘xsaveopt’, ‘xsavec’, 12603 ‘xsaves’, ‘aes’, ‘pclmul’, ‘fsgsbase’, ‘rdrnd’, ‘f16c’, ‘bmi2’, 12604 ‘fma’, ‘movbe’, ‘ept’, ‘lzcnt’, ‘popcnt’, ‘hle’, ‘rtm’, ‘tsx’, 12605 ‘invpcid’, ‘clflush’, ‘mwaitx’, ‘clzero’, ‘wbnoinvd’, ‘pconfig’, 12606 ‘waitpkg’, ‘uintr’, ‘cldemote’, ‘rdpru’, ‘mcommit’, ‘sev_es’, 12607 ‘lwp’, ‘fma4’, ‘xop’, ‘cx16’, ‘syscall’, ‘rdtscp’, ‘3dnow’, 12608 ‘3dnowa’, ‘sse4a’, ‘sse5’, ‘snp’, ‘invlpgb’, ‘tlbsync’, ‘svme’ and 12609 ‘padlock’. Note that these extension mnemonics can be prefixed 12610 with ‘no’ to revoke the respective (and any dependent) 12611 functionality. Note further that the suffixes permitted on 12612 ‘-march=avx10.<N>’ enforce a vector length restriction, i.e. 12613 despite these otherwise being "enabling" options, using these 12614 suffixes will disable all insns with wider vector or mask register 12615 operands. 12616 12617 When the ‘.arch’ directive is used with ‘-march’, the ‘.arch’ 12618 directive will take precedent. 12619 12620‘-mtune=CPU’ 12621 This option specifies a processor to optimize for. When used in 12622 conjunction with the ‘-march’ option, only instructions of the 12623 processor specified by the ‘-march’ option will be generated. 12624 12625 Valid CPU values are identical to the processor list of 12626 ‘-march=CPU’. 12627 12628‘-msse2avx’ 12629 This option specifies that the assembler should encode SSE 12630 instructions with VEX prefix. 12631 12632‘-muse-unaligned-vector-move’ 12633 This option specifies that the assembler should encode aligned 12634 vector move as unaligned vector move. 12635 12636‘-msse-check=NONE’ 12637‘-msse-check=WARNING’ 12638‘-msse-check=ERROR’ 12639 These options control if the assembler should check SSE 12640 instructions. ‘-msse-check=NONE’ will make the assembler not to 12641 check SSE instructions, which is the default. 12642 ‘-msse-check=WARNING’ will make the assembler issue a warning for 12643 any SSE instruction. ‘-msse-check=ERROR’ will make the assembler 12644 issue an error for any SSE instruction. 12645 12646‘-mavxscalar=128’ 12647‘-mavxscalar=256’ 12648 These options control how the assembler should encode scalar AVX 12649 instructions. ‘-mavxscalar=128’ will encode scalar AVX 12650 instructions with 128bit vector length, which is the default. 12651 ‘-mavxscalar=256’ will encode scalar AVX instructions with 256bit 12652 vector length. 12653 12654 WARNING: Don’t use this for production code - due to CPU errata the 12655 resulting code may not work on certain models. 12656 12657‘-mvexwig=0’ 12658‘-mvexwig=1’ 12659 These options control how the assembler should encode VEX.W-ignored 12660 (WIG) VEX instructions. ‘-mvexwig=0’ will encode WIG VEX 12661 instructions with vex.w = 0, which is the default. ‘-mvexwig=1’ 12662 will encode WIG EVEX instructions with vex.w = 1. 12663 12664 WARNING: Don’t use this for production code - due to CPU errata the 12665 resulting code may not work on certain models. 12666 12667‘-mevexlig=128’ 12668‘-mevexlig=256’ 12669‘-mevexlig=512’ 12670 These options control how the assembler should encode 12671 length-ignored (LIG) EVEX instructions. ‘-mevexlig=128’ will 12672 encode LIG EVEX instructions with 128bit vector length, which is 12673 the default. ‘-mevexlig=256’ and ‘-mevexlig=512’ will encode LIG 12674 EVEX instructions with 256bit and 512bit vector length, 12675 respectively. 12676 12677‘-mevexwig=0’ 12678‘-mevexwig=1’ 12679 These options control how the assembler should encode w-ignored 12680 (WIG) EVEX instructions. ‘-mevexwig=0’ will encode WIG EVEX 12681 instructions with evex.w = 0, which is the default. ‘-mevexwig=1’ 12682 will encode WIG EVEX instructions with evex.w = 1. 12683 12684‘-mmnemonic=ATT’ 12685‘-mmnemonic=INTEL’ 12686 This option specifies instruction mnemonic for matching 12687 instructions. The ‘.att_mnemonic’ and ‘.intel_mnemonic’ directives 12688 will take precedent. 12689 12690‘-msyntax=ATT’ 12691‘-msyntax=INTEL’ 12692 This option specifies instruction syntax when processing 12693 instructions. The ‘.att_syntax’ and ‘.intel_syntax’ directives 12694 will take precedent. 12695 12696‘-mnaked-reg’ 12697 This option specifies that registers don’t require a ‘%’ prefix. 12698 The ‘.att_syntax’ and ‘.intel_syntax’ directives will take 12699 precedent. 12700 12701‘-madd-bnd-prefix’ 12702 This option forces the assembler to add BND prefix to all branches, 12703 even if such prefix was not explicitly specified in the source 12704 code. 12705 12706‘-mno-shared’ 12707 On ELF target, the assembler normally optimizes out non-PLT 12708 relocations against defined non-weak global branch targets with 12709 default visibility. The ‘-mshared’ option tells the assembler to 12710 generate code which may go into a shared library where all non-weak 12711 global branch targets with default visibility can be preempted. 12712 The resulting code is slightly bigger. This option only affects 12713 the handling of branch instructions. 12714 12715‘-mbig-obj’ 12716 On PE/COFF target this option forces the use of big object file 12717 format, which allows more than 32768 sections. 12718 12719‘-momit-lock-prefix=NO’ 12720‘-momit-lock-prefix=YES’ 12721 These options control how the assembler should encode lock prefix. 12722 This option is intended as a workaround for processors, that fail 12723 on lock prefix. This option can only be safely used with 12724 single-core, single-thread computers ‘-momit-lock-prefix=YES’ will 12725 omit all lock prefixes. ‘-momit-lock-prefix=NO’ will encode lock 12726 prefix as usual, which is the default. 12727 12728‘-mfence-as-lock-add=NO’ 12729‘-mfence-as-lock-add=YES’ 12730 These options control how the assembler should encode lfence, 12731 mfence and sfence. ‘-mfence-as-lock-add=YES’ will encode lfence, 12732 mfence and sfence as ‘lock addl $0x0, (%rsp)’ in 64-bit mode and 12733 ‘lock addl $0x0, (%esp)’ in 32-bit mode. ‘-mfence-as-lock-add=NO’ 12734 will encode lfence, mfence and sfence as usual, which is the 12735 default. 12736 12737‘-mrelax-relocations=NO’ 12738‘-mrelax-relocations=YES’ 12739 These options control whether the assembler should generate relax 12740 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX 12741 and R_X86_64_REX_GOTPCRELX, in 64-bit mode. 12742 ‘-mrelax-relocations=YES’ will generate relax relocations. 12743 ‘-mrelax-relocations=NO’ will not generate relax relocations. The 12744 default can be controlled by a configure option 12745 ‘--enable-x86-relax-relocations’. 12746 12747‘-malign-branch-boundary=NUM’ 12748 This option controls how the assembler should align branches with 12749 segment prefixes or NOP. NUM must be a power of 2. It should be 0 12750 or no less than 16. Branches will be aligned within NUM byte 12751 boundary. ‘-malign-branch-boundary=0’, which is the default, 12752 doesn’t align branches. 12753 12754‘-malign-branch=TYPE[+TYPE...]’ 12755 This option specifies types of branches to align. TYPE is 12756 combination of ‘jcc’, which aligns conditional jumps, ‘fused’, 12757 which aligns fused conditional jumps, ‘jmp’, which aligns 12758 unconditional jumps, ‘call’ which aligns calls, ‘ret’, which aligns 12759 rets, ‘indirect’, which aligns indirect jumps and calls. The 12760 default is ‘-malign-branch=jcc+fused+jmp’. 12761 12762‘-malign-branch-prefix-size=NUM’ 12763 This option specifies the maximum number of prefixes on an 12764 instruction to align branches. NUM should be between 0 and 5. The 12765 default NUM is 5. 12766 12767‘-mbranches-within-32B-boundaries’ 12768 This option aligns conditional jumps, fused conditional jumps and 12769 unconditional jumps within 32 byte boundary with up to 5 segment 12770 prefixes on an instruction. It is equivalent to 12771 ‘-malign-branch-boundary=32’ ‘-malign-branch=jcc+fused+jmp’ 12772 ‘-malign-branch-prefix-size=5’. The default doesn’t align 12773 branches. 12774 12775‘-mlfence-after-load=NO’ 12776‘-mlfence-after-load=YES’ 12777 These options control whether the assembler should generate lfence 12778 after load instructions. ‘-mlfence-after-load=YES’ will generate 12779 lfence. ‘-mlfence-after-load=NO’ will not generate lfence, which 12780 is the default. 12781 12782‘-mlfence-before-indirect-branch=NONE’ 12783‘-mlfence-before-indirect-branch=ALL’ 12784‘-mlfence-before-indirect-branch=REGISTER’ 12785‘-mlfence-before-indirect-branch=MEMORY’ 12786 These options control whether the assembler should generate lfence 12787 before indirect near branch instructions. 12788 ‘-mlfence-before-indirect-branch=ALL’ will generate lfence before 12789 indirect near branch via register and issue a warning before 12790 indirect near branch via memory. It also implicitly sets 12791 ‘-mlfence-before-ret=SHL’ when there’s no explicit 12792 ‘-mlfence-before-ret=’. ‘-mlfence-before-indirect-branch=REGISTER’ 12793 will generate lfence before indirect near branch via register. 12794 ‘-mlfence-before-indirect-branch=MEMORY’ will issue a warning 12795 before indirect near branch via memory. 12796 ‘-mlfence-before-indirect-branch=NONE’ will not generate lfence nor 12797 issue warning, which is the default. Note that lfence won’t be 12798 generated before indirect near branch via register with 12799 ‘-mlfence-after-load=YES’ since lfence will be generated after 12800 loading branch target register. 12801 12802‘-mlfence-before-ret=NONE’ 12803‘-mlfence-before-ret=SHL’ 12804‘-mlfence-before-ret=OR’ 12805‘-mlfence-before-ret=YES’ 12806‘-mlfence-before-ret=NOT’ 12807 These options control whether the assembler should generate lfence 12808 before ret. ‘-mlfence-before-ret=OR’ will generate generate or 12809 instruction with lfence. ‘-mlfence-before-ret=SHL/YES’ will 12810 generate shl instruction with lfence. ‘-mlfence-before-ret=NOT’ 12811 will generate not instruction with lfence. 12812 ‘-mlfence-before-ret=NONE’ will not generate lfence, which is the 12813 default. 12814 12815‘-mx86-used-note=NO’ 12816‘-mx86-used-note=YES’ 12817 These options control whether the assembler should generate 12818 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU 12819 property notes. The default can be controlled by the 12820 ‘--enable-x86-used-note’ configure option. 12821 12822‘-mevexrcig=RNE’ 12823‘-mevexrcig=RD’ 12824‘-mevexrcig=RU’ 12825‘-mevexrcig=RZ’ 12826 These options control how the assembler should encode SAE-only EVEX 12827 instructions. ‘-mevexrcig=RNE’ will encode RC bits of EVEX 12828 instruction with 00, which is the default. ‘-mevexrcig=RD’, 12829 ‘-mevexrcig=RU’ and ‘-mevexrcig=RZ’ will encode SAE-only EVEX 12830 instructions with 01, 10 and 11 RC bits, respectively. 12831 12832‘-mamd64’ 12833‘-mintel64’ 12834 This option specifies that the assembler should accept only AMD64 12835 or Intel64 ISA in 64-bit mode. The default is to accept common, 12836 Intel64 only and AMD64 ISAs. 12837 12838‘-O0 | -O | -O1 | -O2 | -Os’ 12839 Optimize instruction encoding with smaller instruction size. ‘-O’ 12840 and ‘-O1’ encode 64-bit register load instructions with 64-bit 12841 immediate as 32-bit register load instructions with 31-bit or 12842 32-bits immediates, encode 64-bit register clearing instructions 12843 with 32-bit register clearing instructions, encode 256-bit/512-bit 12844 VEX/EVEX vector register clearing instructions with 128-bit VEX 12845 vector register clearing instructions, encode 128-bit/256-bit EVEX 12846 vector register load/store instructions with VEX vector register 12847 load/store instructions, and encode 128-bit/256-bit EVEX packed 12848 integer logical instructions with 128-bit/256-bit VEX packed 12849 integer logical. 12850 12851 ‘-O2’ includes ‘-O1’ optimization plus encodes 256-bit/512-bit EVEX 12852 vector register clearing instructions with 128-bit EVEX vector 12853 register clearing instructions. In 64-bit mode VEX encoded 12854 instructions with commutative source operands will also have their 12855 source operands swapped if this allows using the 2-byte VEX prefix 12856 form instead of the 3-byte one. Certain forms of AND as well as OR 12857 with the same (register) operand specified twice will also be 12858 changed to TEST. 12859 12860 ‘-Os’ includes ‘-O2’ optimization plus encodes 16-bit, 32-bit and 12861 64-bit register tests with immediate as 8-bit register test with 12862 immediate. ‘-O0’ turns off this optimization. 12863 12864 12865File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 12866 128679.16.2 x86 specific Directives 12868------------------------------ 12869 12870‘.lcomm SYMBOL , LENGTH[, ALIGNMENT]’ 12871 Reserve LENGTH (an absolute expression) bytes for a local common 12872 denoted by SYMBOL. The section and value of SYMBOL are those of 12873 the new local common. The addresses are allocated in the bss 12874 section, so that at run-time the bytes start off zeroed. Since 12875 SYMBOL is not declared global, it is normally not visible to ‘ld’. 12876 The optional third parameter, ALIGNMENT, specifies the desired 12877 alignment of the symbol in the bss section. 12878 12879 This directive is only available for COFF based x86 targets. 12880 12881‘.largecomm SYMBOL , LENGTH[, ALIGNMENT]’ 12882 This directive behaves in the same way as the ‘comm’ directive 12883 except that the data is placed into the .LBSS section instead of 12884 the .BSS section *note Comm::. 12885 12886 The directive is intended to be used for data which requires a 12887 large amount of space, and it is only available for ELF based 12888 x86_64 targets. 12889 12890‘.value EXPRESSION [, EXPRESSION]’ 12891 This directive behaves in the same way as the ‘.short’ directive, 12892 taking a series of comma separated expressions and storing them as 12893 two-byte wide values into the current section. 12894 12895‘.insn [PREFIX[,...]] [ENCODING] MAJOR-OPCODE[+r|/EXTENSION] [,OPERAND[,...]]’ 12896 This directive allows composing instructions which ‘as’ may not 12897 know about yet, or which it has no way of expressing (which can be 12898 the case for certain alternative encodings). It assumes certain 12899 basic structure in how operands are encoded, and it also only 12900 recognizes - with a few extensions as per below - operands 12901 otherwise valid for instructions. Therefore there is no guarantee 12902 that everything can be expressed (e.g. the original Intel Xeon 12903 Phi’s MVEX encodings cannot be expressed). 12904 12905 • PREFIX expresses one or more opcode prefixes in the usual way. 12906 Legacy encoding prefixes altering meaning (0x66, 0xF2, 0xF3) 12907 may be specified as high byte of <major-opcode> (perhaps 12908 already including an encoding space prefix). Note that there 12909 can only be one such prefix. Segment overrides are better 12910 specified in the respective memory operand, as long as there 12911 is one. 12912 12913 • ENCODING is used to specify VEX, XOP, or EVEX encodings. The 12914 syntax tries to resemble that used in documentation: 12915 • ‘VEX’[‘.LEN’][‘.PREFIX’][‘.SPACE’][‘.W’] 12916 • ‘EVEX’[‘.LEN’][‘.PREFIX’][‘.SPACE’][‘.W’] 12917 • ‘XOP’SPACE[‘.LEN’][‘.PREFIX’][‘.W’] 12918 12919 Here 12920 • LEN can be ‘LIG’, ‘128’, ‘256’, or (EVEX only) ‘512’ as 12921 well as ‘L0’ / ‘L1’ for VEX / XOP and ‘L0’...‘L3’ for 12922 EVEX 12923 • PREFIX can be ‘NP’, ‘66’, ‘F3’, or ‘F2’ 12924 • SPACE can be 12925 • ‘0f’, ‘0f38’, ‘0f3a’, or ‘M0’...‘M31’ for VEX 12926 • ‘08’...‘1f’ for XOP 12927 • ‘0f’, ‘0f38’, ‘0f3a’, or ‘M0’...‘M15’ for EVEX 12928 • W can be ‘WIG’, ‘W0’, or ‘W1’ 12929 12930 Defaults: 12931 • Omitted LEN means "infer from operand size" if there is 12932 at least one sized vector operand, or ‘LIG’ otherwise. 12933 (Obviously LEN has to be omitted when there’s EVEX 12934 rounding control specified later in the operands.) 12935 • Omitted PREFIX means ‘NP’. 12936 • Omitted SPACE (VEX/EVEX only) implies encoding space is 12937 taken from MAJOR-OPCODE. 12938 • Omitted W means "infer from GPR operand size" in 64-bit 12939 code if there is at least one GPR(-like) operand, or 12940 ‘WIG’ otherwise. 12941 12942 • MAJOR-OPCODE is an absolute expression specifying the 12943 instruction opcode. Legacy encoding prefixes altering 12944 encoding space (0x0f, 0x0f38, 0x0f3a) have to be specified as 12945 high byte(s) here. "Degenerate" ModR/M bytes, as present in 12946 e.g. certain FPU opcodes or sub-spaces like that of major 12947 opcode 0x0f01, generally want encoding as immediate operand 12948 (such opcodes wouldn’t normally have non-immediate operands); 12949 in some cases it may be possible to also encode these as low 12950 byte of the major opcode, but there are potential ambiguities. 12951 Also note that after stripping encoding prefixes, the residual 12952 has to fit in two bytes (16 bits). ‘+r’ can be suffixed to 12953 the major opcode expression to specify register-only encoding 12954 forms not using a ModR/M byte. ‘/EXTENSION’ can alternatively 12955 be suffixed to the major opcode expression to specify an 12956 extension opcode, encoded in bits 3-5 of the ModR/M byte. 12957 12958 • OPERAND is an instruction operand expressed the usual way. 12959 Register operands are primarily used to express register 12960 numbers as encoded in ModR/M byte and REX/VEX/XOP/EVEX 12961 prefixes. In certain cases the register type (really: size) 12962 is also used to derive other encoding attributes, if these 12963 aren’t specified explicitly. Note that there is no 12964 consistency checking among operands, so entirely bogus mixes 12965 of operands are possible. Note further that only operands 12966 actually encoded in the instruction should be specified. 12967 Operands like ‘%cl’ in shift/rotate instructions have to be 12968 omitted, or else they’ll be encoded as an ordinary (register) 12969 operand. Operand order may also not match that of the actual 12970 instruction (see below). 12971 12972 Encoding of operands: While for a memory operand (of which there 12973 can be only one) it is clear how to encode it in the resulting 12974 ModR/M byte, register operands are encoded strictly in this order 12975 (operand counts do not include immediate ones in the enumeration 12976 below, and if there was an extension opcode specified it counts as 12977 a register operand; VEX.vvvv is meant to cover XOP and EVEX as 12978 well): 12979 12980 • VEX.vvvv for 1-register-operand VEX/XOP/EVEX insns, 12981 • ModR/M.rm, ModR/M.reg for 2-operand insns, 12982 • ModR/M.rm, VEX.vvvv, ModR/M.reg for 3-operand insns, and 12983 • Imm{4,5}, ModR/M.rm, VEX.vvvv, ModR/M.reg for 4-operand insns, 12984 12985 obviously with the ModR/M.rm slot skipped when there is a memory 12986 operand, and obviously with the ModR/M.reg slot skipped when there 12987 is an extension opcode. For Intel syntax of course the opposite 12988 order applies. With ‘+r’ (and hence no ModR/M) there can only be a 12989 single register operand for legacy encodings. VEX and alike can 12990 have two register operands, where the second (first in Intel 12991 syntax) would go into VEX.vvvv. 12992 12993 Immediate operands (including immediate-like displacements, i.e. 12994 when not part of ModR/M addressing) are emitted in the order 12995 specified, regardless of AT&T or Intel syntax. Since it may not be 12996 possible to infer the size of such immediates, they can be suffixed 12997 by ‘{:sN}’ or ‘{:uN}’, representing signed / unsigned immediates of 12998 the given number of bits respectively. When emitting such 12999 operands, the number of bits will be rounded up to the smallest 13000 suitable of 8, 16, 32, or 64. Immediates wider than 32 bits are 13001 permitted in 64-bit code only. 13002 13003 For EVEX encoding memory operands with a displacement need to know 13004 Disp8 scaling size in order to use an 8-bit displacement. For many 13005 instructions this can be inferred from the types of other operands 13006 specified. In Intel syntax ‘DWORD PTR’ and alike can be used to 13007 specify the respective size. In AT&T syntax the memory operands 13008 can be suffixed by ‘{:dN}’ to specify the size (in bytes). This 13009 can be combined with an embedded broadcast specifier: 13010 ‘8(%eax){1to8:d8}’. 13011 13012 13013File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 13014 130159.16.3 i386 Syntactical Considerations 13016-------------------------------------- 13017 13018* Menu: 13019 13020* i386-Variations:: AT&T Syntax versus Intel Syntax 13021* i386-Chars:: Special Characters 13022 13023 13024File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 13025 130269.16.3.1 AT&T Syntax versus Intel Syntax 13027........................................ 13028 13029‘as’ now supports assembly using Intel assembler syntax. 13030‘.intel_syntax’ selects Intel mode, and ‘.att_syntax’ switches back to 13031the usual AT&T mode for compatibility with the output of ‘gcc’. Either 13032of these directives may have an optional argument, ‘prefix’, or 13033‘noprefix’ specifying whether registers require a ‘%’ prefix. AT&T 13034System V/386 assembler syntax is quite different from Intel syntax. We 13035mention these differences because almost all 80386 documents use Intel 13036syntax. Notable differences between the two syntaxes are: 13037 13038 • AT&T immediate operands are preceded by ‘$’; Intel immediate 13039 operands are undelimited (Intel ‘push 4’ is AT&T ‘pushl $4’). AT&T 13040 register operands are preceded by ‘%’; Intel register operands are 13041 undelimited. AT&T absolute (as opposed to PC relative) jump/call 13042 operands are prefixed by ‘*’; they are undelimited in Intel syntax. 13043 13044 • AT&T and Intel syntax use the opposite order for source and 13045 destination operands. Intel ‘add eax, 4’ is ‘addl $4, %eax’. The 13046 ‘source, dest’ convention is maintained for compatibility with 13047 previous Unix assemblers. Note that ‘bound’, ‘invlpga’, and 13048 instructions with 2 immediate operands, such as the ‘enter’ 13049 instruction, do _not_ have reversed order. *note i386-Bugs::. 13050 13051 • In AT&T syntax the size of memory operands is determined from the 13052 last character of the instruction mnemonic. Mnemonic suffixes of 13053 ‘b’, ‘w’, ‘l’ and ‘q’ specify byte (8-bit), word (16-bit), long 13054 (32-bit) and quadruple word (64-bit) memory references. Mnemonic 13055 suffixes of ‘x’, ‘y’ and ‘z’ specify xmm (128-bit vector), ymm 13056 (256-bit vector) and zmm (512-bit vector) memory references, only 13057 when there’s no other way to disambiguate an instruction. Intel 13058 syntax accomplishes this by prefixing memory operands (_not_ the 13059 instruction mnemonics) with ‘byte ptr’, ‘word ptr’, ‘dword ptr’, 13060 ‘qword ptr’, ‘xmmword ptr’, ‘ymmword ptr’ and ‘zmmword ptr’. Thus, 13061 Intel syntax ‘mov al, byte ptr FOO’ is ‘movb FOO, %al’ in AT&T 13062 syntax. In Intel syntax, ‘fword ptr’, ‘tbyte ptr’ and ‘oword ptr’ 13063 specify 48-bit, 80-bit and 128-bit memory references. 13064 13065 In 64-bit code, ‘movabs’ can be used to encode the ‘mov’ 13066 instruction with the 64-bit displacement or immediate operand. 13067 13068 • Immediate form long jumps and calls are ‘lcall/ljmp $SECTION, 13069 $OFFSET’ in AT&T syntax; the Intel syntax is ‘call/jmp far 13070 SECTION:OFFSET’. Also, the far return instruction is ‘lret 13071 $STACK-ADJUST’ in AT&T syntax; Intel syntax is ‘ret far 13072 STACK-ADJUST’. 13073 13074 • The AT&T assembler does not provide support for multiple section 13075 programs. Unix style systems expect all programs to be single 13076 sections. 13077 13078 13079File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 13080 130819.16.3.2 Special Characters 13082........................... 13083 13084The presence of a ‘#’ appearing anywhere on a line indicates the start 13085of a comment that extends to the end of that line. 13086 13087 If a ‘#’ appears as the first character of a line then the whole line 13088is treated as a comment, but in this case the line can also be a logical 13089line number directive (*note Comments::) or a preprocessor control 13090command (*note Preprocessing::). 13091 13092 If the ‘--divide’ command-line option has not been specified then the 13093‘/’ character appearing anywhere on a line also introduces a line 13094comment. 13095 13096 The ‘;’ character can be used to separate statements on the same 13097line. 13098 13099 13100File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 13101 131029.16.4 i386-Mnemonics 13103--------------------- 13104 131059.16.4.1 Instruction Naming 13106........................... 13107 13108Instruction mnemonics are suffixed with one character modifiers which 13109specify the size of operands. The letters ‘b’, ‘w’, ‘l’ and ‘q’ specify 13110byte, word, long and quadruple word operands. If no suffix is specified 13111by an instruction then ‘as’ tries to fill in the missing suffix based on 13112the destination register operand (the last one by convention). Thus, 13113‘mov %ax, %bx’ is equivalent to ‘movw %ax, %bx’; also, ‘mov $1, %bx’ is 13114equivalent to ‘movw $1, bx’. Note that this is incompatible with the 13115AT&T Unix assembler which assumes that a missing mnemonic suffix implies 13116long operand size. (This incompatibility does not affect compiler 13117output since compilers always explicitly specify the mnemonic suffix.) 13118 13119 When there is no sizing suffix and no (suitable) register operands to 13120deduce the size of memory operands, with a few exceptions and where long 13121operand size is possible in the first place, operand size will default 13122to long in 32- and 64-bit modes. Similarly it will default to short in 1312316-bit mode. Noteworthy exceptions are 13124 13125 • Instructions with an implicit on-stack operand as well as branches, 13126 which default to quad in 64-bit mode. 13127 13128 • Sign- and zero-extending moves, which default to byte size source 13129 operands. 13130 13131 • Floating point insns with integer operands, which default to short 13132 (for perhaps historical reasons). 13133 13134 • CRC32 with a 64-bit destination, which defaults to a quad source 13135 operand. 13136 13137 Different encoding options can be specified via pseudo prefixes: 13138 13139 • ‘{disp8}’ – prefer 8-bit displacement. 13140 13141 • ‘{disp32}’ – prefer 32-bit displacement. 13142 13143 • ‘{disp16}’ – prefer 16-bit displacement. 13144 13145 • ‘{load}’ – prefer load-form instruction. 13146 13147 • ‘{store}’ – prefer store-form instruction. 13148 13149 • ‘{vex}’ – encode with VEX prefix. 13150 13151 • ‘{vex3}’ – encode with 3-byte VEX prefix. 13152 13153 • ‘{evex}’ – encode with EVEX prefix. 13154 13155 • ‘{rex}’ – prefer REX prefix for integer and legacy vector 13156 instructions (x86-64 only). Note that this differs from the ‘rex’ 13157 prefix which generates REX prefix unconditionally. 13158 13159 • ‘{rex2}’ – prefer REX2 prefix for integer and legacy vector 13160 instructions (APX_F only). 13161 13162 • ‘{nooptimize}’ – disable instruction size optimization. 13163 13164 Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX 13165prefix by default. The pseudo ‘{vex}’ prefix can be used to encode 13166mnemonics of Intel VNNI/IFMA instructions with the VEX prefix. 13167 13168 The Intel-syntax conversion instructions 13169 13170 • ‘cbw’ — sign-extend byte in ‘%al’ to word in ‘%ax’, 13171 13172 • ‘cwde’ — sign-extend word in ‘%ax’ to long in ‘%eax’, 13173 13174 • ‘cwd’ — sign-extend word in ‘%ax’ to long in ‘%dx:%ax’, 13175 13176 • ‘cdq’ — sign-extend dword in ‘%eax’ to quad in ‘%edx:%eax’, 13177 13178 • ‘cdqe’ — sign-extend dword in ‘%eax’ to quad in ‘%rax’ (x86-64 13179 only), 13180 13181 • ‘cqo’ — sign-extend quad in ‘%rax’ to octuple in ‘%rdx:%rax’ 13182 (x86-64 only), 13183 13184are called ‘cbtw’, ‘cwtl’, ‘cwtd’, ‘cltd’, ‘cltq’, and ‘cqto’ in AT&T 13185naming. ‘as’ accepts either naming for these instructions. 13186 13187 The Intel-syntax extension instructions 13188 13189 • ‘movsx’ — sign-extend ‘reg8/mem8’ to ‘reg16’. 13190 13191 • ‘movsx’ — sign-extend ‘reg8/mem8’ to ‘reg32’. 13192 13193 • ‘movsx’ — sign-extend ‘reg8/mem8’ to ‘reg64’ (x86-64 only). 13194 13195 • ‘movsx’ — sign-extend ‘reg16/mem16’ to ‘reg32’ 13196 13197 • ‘movsx’ — sign-extend ‘reg16/mem16’ to ‘reg64’ (x86-64 only). 13198 13199 • ‘movsxd’ — sign-extend ‘reg32/mem32’ to ‘reg64’ (x86-64 only). 13200 13201 • ‘movzx’ — zero-extend ‘reg8/mem8’ to ‘reg16’. 13202 13203 • ‘movzx’ — zero-extend ‘reg8/mem8’ to ‘reg32’. 13204 13205 • ‘movzx’ — zero-extend ‘reg8/mem8’ to ‘reg64’ (x86-64 only). 13206 13207 • ‘movzx’ — zero-extend ‘reg16/mem16’ to ‘reg32’ 13208 13209 • ‘movzx’ — zero-extend ‘reg16/mem16’ to ‘reg64’ (x86-64 only). 13210 13211are called ‘movsbw/movsxb/movsx’, ‘movsbl/movsxb/movsx’, 13212‘movsbq/movsxb/movsx’, ‘movswl/movsxw’, ‘movswq/movsxw’, 13213‘movslq/movsxl’, ‘movzbw/movzxb/movzx’, ‘movzbl/movzxb/movzx’, 13214‘movzbq/movzxb/movzx’, ‘movzwl/movzxw’ and ‘movzwq/movzxw’ in AT&T 13215syntax. 13216 13217 Far call/jump instructions are ‘lcall’ and ‘ljmp’ in AT&T syntax, but 13218are ‘call far’ and ‘jump far’ in Intel convention. 13219 132209.16.4.2 AT&T Mnemonic versus Intel Mnemonic 13221............................................ 13222 13223‘as’ supports assembly using Intel mnemonic. ‘.intel_mnemonic’ selects 13224Intel mnemonic with Intel syntax, and ‘.att_mnemonic’ switches back to 13225the usual AT&T mnemonic with AT&T syntax for compatibility with the 13226output of ‘gcc’. Several x87 instructions, ‘fadd’, ‘fdiv’, ‘fdivp’, 13227‘fdivr’, ‘fdivrp’, ‘fmul’, ‘fsub’, ‘fsubp’, ‘fsubr’ and ‘fsubrp’, are 13228implemented in AT&T System V/386 assembler with different mnemonics from 13229those in Intel IA32 specification. ‘gcc’ generates those instructions 13230with AT&T mnemonic. 13231 13232 • ‘movslq’ with AT&T mnemonic only accepts 64-bit destination 13233 register. ‘movsxd’ should be used to encode 16-bit or 32-bit 13234 destination register with both AT&T and Intel mnemonics. 13235 13236 13237File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 13238 132399.16.5 Register Naming 13240---------------------- 13241 13242Register operands are always prefixed with ‘%’. The 80386 registers 13243consist of 13244 13245 • the 8 32-bit registers ‘%eax’ (the accumulator), ‘%ebx’, ‘%ecx’, 13246 ‘%edx’, ‘%edi’, ‘%esi’, ‘%ebp’ (the frame pointer), and ‘%esp’ (the 13247 stack pointer). 13248 13249 • the 8 16-bit low-ends of these: ‘%ax’, ‘%bx’, ‘%cx’, ‘%dx’, ‘%di’, 13250 ‘%si’, ‘%bp’, and ‘%sp’. 13251 13252 • the 8 8-bit registers: ‘%ah’, ‘%al’, ‘%bh’, ‘%bl’, ‘%ch’, ‘%cl’, 13253 ‘%dh’, and ‘%dl’ (These are the high-bytes and low-bytes of ‘%ax’, 13254 ‘%bx’, ‘%cx’, and ‘%dx’) 13255 13256 • the 6 section registers ‘%cs’ (code section), ‘%ds’ (data section), 13257 ‘%ss’ (stack section), ‘%es’, ‘%fs’, and ‘%gs’. 13258 13259 • the 5 processor control registers ‘%cr0’, ‘%cr2’, ‘%cr3’, ‘%cr4’, 13260 and ‘%cr8’. 13261 13262 • the 6 debug registers ‘%db0’, ‘%db1’, ‘%db2’, ‘%db3’, ‘%db6’, and 13263 ‘%db7’. 13264 13265 • the 2 test registers ‘%tr6’ and ‘%tr7’. 13266 13267 • the 8 floating point register stack ‘%st’ or equivalently ‘%st(0)’, 13268 ‘%st(1)’, ‘%st(2)’, ‘%st(3)’, ‘%st(4)’, ‘%st(5)’, ‘%st(6)’, and 13269 ‘%st(7)’. These registers are overloaded by 8 MMX registers 13270 ‘%mm0’, ‘%mm1’, ‘%mm2’, ‘%mm3’, ‘%mm4’, ‘%mm5’, ‘%mm6’ and ‘%mm7’. 13271 13272 • the 8 128-bit SSE registers registers ‘%xmm0’, ‘%xmm1’, ‘%xmm2’, 13273 ‘%xmm3’, ‘%xmm4’, ‘%xmm5’, ‘%xmm6’ and ‘%xmm7’. 13274 13275 The AMD x86-64 architecture extends the register set by: 13276 13277 • enhancing the 8 32-bit registers to 64-bit: ‘%rax’ (the 13278 accumulator), ‘%rbx’, ‘%rcx’, ‘%rdx’, ‘%rdi’, ‘%rsi’, ‘%rbp’ (the 13279 frame pointer), ‘%rsp’ (the stack pointer) 13280 13281 • the 8 extended registers ‘%r8’–‘%r15’. 13282 13283 • the 8 32-bit low ends of the extended registers: ‘%r8d’–‘%r15d’. 13284 13285 • the 8 16-bit low ends of the extended registers: ‘%r8w’–‘%r15w’. 13286 13287 • the 8 8-bit low ends of the extended registers: ‘%r8b’–‘%r15b’. 13288 13289 • the 4 8-bit registers: ‘%sil’, ‘%dil’, ‘%bpl’, ‘%spl’. 13290 13291 • the 8 debug registers: ‘%db8’–‘%db15’. 13292 13293 • the 8 128-bit SSE registers: ‘%xmm8’–‘%xmm15’. 13294 13295 With the AVX extensions more registers were made available: 13296 13297 • the 16 256-bit SSE ‘%ymm0’–‘%ymm15’ (only the first 8 available in 13298 32-bit mode). The bottom 128 bits are overlaid with the 13299 ‘xmm0’–‘xmm15’ registers. 13300 13301 The AVX512 extensions added the following registers: 13302 13303 • the 32 512-bit registers ‘%zmm0’–‘%zmm31’ (only the first 8 13304 available in 32-bit mode). The bottom 128 bits are overlaid with 13305 the ‘%xmm0’–‘%xmm31’ registers and the first 256 bits are overlaid 13306 with the ‘%ymm0’–‘%ymm31’ registers. 13307 13308 • the 8 mask registers ‘%k0’–‘%k7’. 13309 13310 13311File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 13312 133139.16.6 Instruction Prefixes 13314--------------------------- 13315 13316Instruction prefixes are used to modify the following instruction. They 13317are used to repeat string instructions, to provide section overrides, to 13318perform bus lock operations, and to change operand and address sizes. 13319(Most instructions that normally operate on 32-bit operands will use 1332016-bit operands if the instruction has an “operand size” prefix.) 13321Instruction prefixes are best written on the same line as the 13322instruction they act upon. For example, the ‘scas’ (scan string) 13323instruction is repeated with: 13324 13325 repne scas %es:(%edi),%al 13326 13327 You may also place prefixes on the lines immediately preceding the 13328instruction, but this circumvents checks that ‘as’ does with prefixes, 13329and will not work with all prefixes. 13330 13331 Here is a list of instruction prefixes: 13332 13333 • Section override prefixes ‘cs’, ‘ds’, ‘ss’, ‘es’, ‘fs’, ‘gs’. 13334 These are automatically added by specifying using the 13335 SECTION:MEMORY-OPERAND form for memory references. 13336 13337 • Operand/Address size prefixes ‘data16’ and ‘addr16’ change 32-bit 13338 operands/addresses into 16-bit operands/addresses, while ‘data32’ 13339 and ‘addr32’ change 16-bit ones (in a ‘.code16’ section) into 13340 32-bit operands/addresses. These prefixes _must_ appear on the 13341 same line of code as the instruction they modify. For example, in 13342 a 16-bit ‘.code16’ section, you might write: 13343 13344 addr32 jmpl *(%ebx) 13345 13346 • The bus lock prefix ‘lock’ inhibits interrupts during execution of 13347 the instruction it precedes. (This is only valid with certain 13348 instructions; see a 80386 manual for details). 13349 13350 • The wait for coprocessor prefix ‘wait’ waits for the coprocessor to 13351 complete the current instruction. This should never be needed for 13352 the 80386/80387 combination. 13353 13354 • The ‘rep’, ‘repe’, and ‘repne’ prefixes are added to string 13355 instructions to make them repeat ‘%ecx’ times (‘%cx’ times if the 13356 current address size is 16-bits). 13357 • The ‘rex’ family of prefixes is used by x86-64 to encode extensions 13358 to i386 instruction set. The ‘rex’ prefix has four bits — an 13359 operand size overwrite (‘64’) used to change operand size from 13360 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 13361 register set. 13362 13363 You may write the ‘rex’ prefixes directly. The ‘rex64xyz’ 13364 instruction emits ‘rex’ prefix with all the bits set. By omitting 13365 the ‘64’, ‘x’, ‘y’ or ‘z’ you may write other prefixes as well. 13366 Normally, there is no need to write the prefixes explicitly, since 13367 gas will automatically generate them based on the instruction 13368 operands. 13369 13370 13371File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 13372 133739.16.7 Memory References 13374------------------------ 13375 13376An Intel syntax indirect memory reference of the form 13377 13378 SECTION:[BASE + INDEX*SCALE + DISP] 13379 13380is translated into the AT&T syntax 13381 13382 SECTION:DISP(BASE, INDEX, SCALE) 13383 13384where BASE and INDEX are the optional 32-bit base and index registers, 13385DISP is the optional displacement, and SCALE, taking the values 1, 2, 4, 13386and 8, multiplies INDEX to calculate the address of the operand. If no 13387SCALE is specified, SCALE is taken to be 1. SECTION specifies the 13388optional section register for the memory operand, and may override the 13389default section register (see a 80386 manual for section register 13390defaults). Note that section overrides in AT&T syntax _must_ be 13391preceded by a ‘%’. If you specify a section override which coincides 13392with the default section register, ‘as’ does _not_ output any section 13393register override prefixes to assemble the given instruction. Thus, 13394section overrides can be specified to emphasize which section register 13395is used for a given memory operand. 13396 13397 Here are some examples of Intel and AT&T style memory references: 13398 13399AT&T: ‘-4(%ebp)’, Intel: ‘[ebp - 4]’ 13400 BASE is ‘%ebp’; DISP is ‘-4’. SECTION is missing, and the default 13401 section is used (‘%ss’ for addressing with ‘%ebp’ as the base 13402 register). INDEX, SCALE are both missing. 13403 13404AT&T: ‘foo(,%eax,4)’, Intel: ‘[foo + eax*4]’ 13405 INDEX is ‘%eax’ (scaled by a SCALE 4); DISP is ‘foo’. All other 13406 fields are missing. The section register here defaults to ‘%ds’. 13407 13408AT&T: ‘foo(,1)’; Intel ‘[foo]’ 13409 This uses the value pointed to by ‘foo’ as a memory operand. Note 13410 that BASE and INDEX are both missing, but there is only _one_ ‘,’. 13411 This is a syntactic exception. 13412 13413AT&T: ‘%gs:foo’; Intel ‘gs:foo’ 13414 This selects the contents of the variable ‘foo’ with section 13415 register SECTION being ‘%gs’. 13416 13417 Absolute (as opposed to PC relative) call and jump operands must be 13418prefixed with ‘*’. If no ‘*’ is specified, ‘as’ always chooses PC 13419relative addressing for jump/call labels. 13420 13421 Any instruction that has a memory operand, but no register operand, 13422_must_ specify its size (byte, word, long, or quadruple) with an 13423instruction mnemonic suffix (‘b’, ‘w’, ‘l’ or ‘q’, respectively). 13424 13425 The x86-64 architecture adds an RIP (instruction pointer relative) 13426addressing. This addressing mode is specified by using ‘rip’ as a base 13427register. Only constant offsets are valid. For example: 13428 13429AT&T: ‘1234(%rip)’, Intel: ‘[rip + 1234]’ 13430 Points to the address 1234 bytes past the end of the current 13431 instruction. 13432 13433AT&T: ‘symbol(%rip)’, Intel: ‘[rip + symbol]’ 13434 Points to the ‘symbol’ in RIP relative way, this is shorter than 13435 the default absolute addressing. 13436 13437 Other addressing modes remain unchanged in x86-64 architecture, 13438except registers used are 64-bit instead of 32-bit. 13439 13440 13441File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 13442 134439.16.8 Handling of Jump Instructions 13444------------------------------------ 13445 13446Jump instructions are always optimized to use the smallest possible 13447displacements. This is accomplished by using byte (8-bit) displacement 13448jumps whenever the target is sufficiently close. If a byte displacement 13449is insufficient a long displacement is used. We do not support word 13450(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 13451instruction with the ‘data16’ instruction prefix), since the 80386 13452insists upon masking ‘%eip’ to 16 bits after the word displacement is 13453added. (See also *note i386-Arch::) 13454 13455 Note that the ‘jcxz’, ‘jecxz’, ‘loop’, ‘loopz’, ‘loope’, ‘loopnz’ and 13456‘loopne’ instructions only come in byte displacements, so that if you 13457use these instructions (‘gcc’ does not use them) you may get an error 13458message (and incorrect code). The AT&T 80386 assembler tries to get 13459around this problem by expanding ‘jcxz foo’ to 13460 13461 jcxz cx_zero 13462 jmp cx_nonzero 13463 cx_zero: jmp foo 13464 cx_nonzero: 13465 13466 13467File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 13468 134699.16.9 Floating Point 13470--------------------- 13471 13472All 80387 floating point types except packed BCD are supported. (BCD 13473support may be added without much difficulty). These data types are 1347416-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 13475and extended (80-bit) precision floating point. Each supported type has 13476an instruction mnemonic suffix and a constructor associated with it. 13477Instruction mnemonic suffixes specify the operand’s data type. 13478Constructors build these data types into memory. 13479 13480 • Floating point constructors are ‘.float’ or ‘.single’, ‘.double’, 13481 ‘.tfloat’, ‘.hfloat’, and ‘.bfloat16’ for 32-, 64-, 80-, and 16-bit 13482 (two flavors) formats respectively. The former three correspond to 13483 instruction mnemonic suffixes ‘s’, ‘l’, and ‘t’. ‘t’ stands for 13484 80-bit (ten byte) real. The 80387 only supports this format via 13485 the ‘fldt’ (load 80-bit real to stack top) and ‘fstpt’ (store 13486 80-bit real and pop stack) instructions. 13487 13488 • Integer constructors are ‘.word’, ‘.long’ or ‘.int’, and ‘.quad’ 13489 for the 16-, 32-, and 64-bit integer formats. The corresponding 13490 instruction mnemonic suffixes are ‘s’ (short), ‘l’ (long), and ‘q’ 13491 (quad). As with the 80-bit real format, the 64-bit ‘q’ format is 13492 only present in the ‘fildq’ (load quad integer to stack top) and 13493 ‘fistpq’ (store quad integer and pop stack) instructions. 13494 13495 Register to register operations should not use instruction mnemonic 13496suffixes. ‘fstl %st, %st(1)’ will give a warning, and be assembled as 13497if you wrote ‘fst %st, %st(1)’, since all register to register 13498operations use 80-bit floating point operands. (Contrast this with 13499‘fstl %st, mem’, which converts ‘%st’ from 80-bit to 64-bit floating 13500point format, then stores the result in the 4 byte location ‘mem’) 13501 13502 13503File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 13504 135059.16.10 Intel’s MMX and AMD’s 3DNow! SIMD Operations 13506---------------------------------------------------- 13507 13508‘as’ supports Intel’s MMX instruction set (SIMD instructions for integer 13509data), available on Intel’s Pentium MMX processors and Pentium II 13510processors, AMD’s K6 and K6-2 processors, Cyrix’ M2 processor, and 13511probably others. It also supports AMD’s 3DNow! instruction set (SIMD 13512instructions for 32-bit floating point data) available on AMD’s K6-2 13513processor and possibly others in the future. 13514 13515 Currently, ‘as’ does not support Intel’s floating point SIMD, Katmai 13516(KNI). 13517 13518 The eight 64-bit MMX operands, also used by 3DNow!, are called 13519‘%mm0’, ‘%mm1’, ... ‘%mm7’. They contain eight 8-bit integers, four 1352016-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 13521floating point values. The MMX registers cannot be used at the same 13522time as the floating point stack. 13523 13524 See Intel and AMD documentation, keeping in mind that the operand 13525order in instructions is reversed from the Intel syntax. 13526 13527 13528File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent 13529 135309.16.11 AMD’s Lightweight Profiling Instructions 13531------------------------------------------------ 13532 13533‘as’ supports AMD’s Lightweight Profiling (LWP) instruction set, 13534available on AMD’s Family 15h (Orochi) processors. 13535 13536 LWP enables applications to collect and manage performance data, and 13537react to performance events. The collection of performance data 13538requires no context switches. LWP runs in the context of a thread and 13539so several counters can be used independently across multiple threads. 13540LWP can be used in both 64-bit and legacy 32-bit modes. 13541 13542 For detailed information on the LWP instruction set, see the ‘AMD 13543Lightweight Profiling Specification’ available at Lightweight Profiling 13544Specification (http://developer.amd.com/cpu/LWP). 13545 13546 13547File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent 13548 135499.16.12 Bit Manipulation Instructions 13550------------------------------------- 13551 13552‘as’ supports the Bit Manipulation (BMI) instruction set. 13553 13554 BMI instructions provide several instructions implementing individual 13555bit manipulation operations such as isolation, masking, setting, or 13556resetting. 13557 13558 13559File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent 13560 135619.16.13 AMD’s Trailing Bit Manipulation Instructions 13562---------------------------------------------------- 13563 13564‘as’ supports AMD’s Trailing Bit Manipulation (TBM) instruction set, 13565available on AMD’s BDVER2 processors (Trinity and Viperfish). 13566 13567 TBM instructions provide instructions implementing individual bit 13568manipulation operations such as isolating, masking, setting, resetting, 13569complementing, and operations on trailing zeros and ones. 13570 13571 13572File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent 13573 135749.16.14 Writing 16-bit Code 13575--------------------------- 13576 13577While ‘as’ normally writes only “pure” 32-bit i386 code or 64-bit x86-64 13578code depending on the default configuration, it also supports writing 13579code to run in real mode or in 16-bit protected mode code segments. To 13580do this, put a ‘.code16’ or ‘.code16gcc’ directive before the assembly 13581language instructions to be run in 16-bit mode. You can switch ‘as’ to 13582writing 32-bit code with the ‘.code32’ directive or 64-bit code with the 13583‘.code64’ directive. 13584 13585 ‘.code16gcc’ provides experimental support for generating 16-bit code 13586from gcc, and differs from ‘.code16’ in that ‘call’, ‘ret’, ‘enter’, 13587‘leave’, ‘push’, ‘pop’, ‘pusha’, ‘popa’, ‘pushf’, and ‘popf’ 13588instructions default to 32-bit size. This is so that the stack pointer 13589is manipulated in the same way over function calls, allowing access to 13590function parameters at the same stack offsets as in 32-bit mode. 13591‘.code16gcc’ also automatically adds address size prefixes where 13592necessary to use the 32-bit addressing modes that gcc generates. 13593 13594 The code which ‘as’ generates in 16-bit mode will not necessarily run 13595on a 16-bit pre-80386 processor. To write code that runs on such a 13596processor, you must refrain from using _any_ 32-bit constructs which 13597require ‘as’ to output address or operand size prefixes. 13598 13599 Note that writing 16-bit code instructions by explicitly specifying a 13600prefix or an instruction mnemonic suffix within a 32-bit code section 13601generates different machine instructions than those generated for a 1360216-bit code segment. In a 32-bit code section, the following code 13603generates the machine opcode bytes ‘66 6a 04’, which pushes the value 13604‘4’ onto the stack, decrementing ‘%esp’ by 2. 13605 13606 pushw $4 13607 13608 The same code in a 16-bit code section would generate the machine 13609opcode bytes ‘6a 04’ (i.e., without the operand size prefix), which is 13610correct since the processor default operand size is assumed to be 16 13611bits in a 16-bit code section. 13612 13613 13614File: as.info, Node: i386-Arch, Next: i386-ISA, Prev: i386-16bit, Up: i386-Dependent 13615 136169.16.15 Specifying CPU Architecture 13617----------------------------------- 13618 13619‘as’ may be told to assemble for a particular CPU (sub-)architecture 13620with the ‘.arch CPU_TYPE’ directive. This directive enables a warning 13621when gas detects an instruction that is not supported on the CPU 13622specified. The choices for CPU_TYPE are: 13623 13624‘default’ ‘push’ ‘pop’ 13625‘i8086’ ‘i186’ ‘i286’ ‘i386’ 13626‘i486’ ‘i586’ ‘i686’ ‘pentium’ 13627‘pentiumpro’ ‘pentiumii’ ‘pentiumiii’ ‘pentium4’ 13628‘prescott’ ‘nocona’ ‘core’ ‘core2’ 13629‘corei7’ ‘iamcu’ 13630‘k6’ ‘k6_2’ ‘athlon’ ‘k8’ 13631‘amdfam10’ ‘bdver1’ ‘bdver2’ ‘bdver3’ 13632‘bdver4’ ‘znver1’ ‘znver2’ ‘znver3’ 13633‘znver4’ ‘znver5’ ‘btver1’ ‘btver2’ 13634‘generic32’ 13635‘generic64’ ‘.cmov’ ‘.fxsr’ ‘.mmx’ 13636‘.sse’ ‘.sse2’ ‘.sse3’ ‘.sse4a’ 13637‘.ssse3’ ‘.sse4.1’ ‘.sse4.2’ ‘.sse4’ 13638‘.avx’ ‘.vmx’ ‘.smx’ ‘.ept’ 13639‘.clflush’ ‘.movbe’ ‘.xsave’ ‘.xsaveopt’ 13640‘.aes’ ‘.pclmul’ ‘.fma’ ‘.fsgsbase’ 13641‘.rdrnd’ ‘.f16c’ ‘.avx2’ ‘.bmi2’ 13642‘.lzcnt’ ‘.popcnt’ ‘.invpcid’ ‘.vmfunc’ 13643‘.monitor’ ‘.hle’ ‘.rtm’ ‘.tsx’ 13644‘.lahf_sahf’ ‘.adx’ ‘.rdseed’ ‘.prfchw’ 13645‘.smap’ ‘.mpx’ ‘.sha’ ‘.prefetchwt1’ 13646‘.clflushopt’ ‘.xsavec’ ‘.xsaves’ ‘.se1’ 13647‘.avx512f’ ‘.avx512cd’ ‘.avx512er’ ‘.avx512pf’ 13648‘.avx512vl’ ‘.avx512bw’ ‘.avx512dq’ ‘.avx512ifma’ 13649‘.avx512vbmi’ ‘.avx512_4fmaps’‘.avx512_4vnniw’ 13650‘.avx512_vpopcntdq’‘.avx512_vbmi2’‘.avx512_vnni’ 13651‘.avx512_bitalg’‘.avx512_bf16’‘.avx512_vp2intersect’ 13652‘.tdx’ ‘.avx_vnni’ ‘.avx512_fp16’ ‘.avx10.1’ 13653‘.clwb’ ‘.rdpid’ ‘.ptwrite’ ‘.ibt’ 13654‘.prefetchi’ ‘.avx_ifma’ ‘.avx_vnni_int8’ 13655‘.cmpccxadd’ ‘.wrmsrns’ ‘.msrlist’ 13656‘.avx_ne_convert’‘.rao_int’ ‘.fred’ ‘.lkgs’ 13657‘.avx_vnni_int16’‘.sha512’ ‘.sm3’ ‘.sm4’ 13658‘.pbndkb’ ‘.user_msr’ 13659‘.wbnoinvd’ ‘.pconfig’ ‘.waitpkg’ ‘.cldemote’ 13660‘.shstk’ ‘.gfni’ ‘.vaes’ ‘.vpclmulqdq’ 13661‘.movdiri’ ‘.movdir64b’ ‘.enqcmd’ ‘.tsxldtrk’ 13662‘.amx_int8’ ‘.amx_bf16’ ‘.amx_fp16’ 13663‘.amx_complex’ ‘.amx_tile’ 13664‘.kl’ ‘.widekl’ ‘.uintr’ ‘.hreset’ 13665‘.3dnow’ ‘.3dnowa’ ‘.sse4a’ ‘.sse5’ 13666‘.syscall’ ‘.rdtscp’ ‘.svme’ 13667‘.lwp’ ‘.fma4’ ‘.xop’ ‘.cx16’ 13668‘.padlock’ ‘.clzero’ ‘.mwaitx’ ‘.rdpru’ 13669‘.mcommit’ ‘.sev_es’ ‘.snp’ ‘.invlpgb’ 13670‘.tlbsync’ ‘.apx_f’ 13671 13672 Apart from the warning, there are only two other effects on ‘as’ 13673operation; Firstly, if you specify a CPU other than ‘i486’, then shift 13674by one instructions such as ‘sarl $1, %eax’ will automatically use a two 13675byte opcode sequence. The larger three byte opcode sequence is used on 13676the 486 (and when no architecture is specified) because it executes 13677faster on the 486. Note that you can explicitly request the two byte 13678opcode by writing ‘sarl %eax’. Secondly, if you specify ‘i8086’, 13679‘i186’, or ‘i286’, _and_ ‘.code16’ or ‘.code16gcc’ then byte offset 13680conditional jumps will be promoted when necessary to a two instruction 13681sequence consisting of a conditional jump of the opposite sense around 13682an unconditional jump to the target. 13683 13684 Note that the sub-architecture specifiers (starting with a dot) can 13685be prefixed with ‘no’ to revoke the respective (and any dependent) 13686functionality. Note further that ‘.avx10.<N>’ can be suffixed with a 13687vector length restriction (‘/256’ or ‘/128’, with ‘/512’ simply 13688restoring the default). Despite these otherwise being "enabling" 13689specifiers, using these suffixes will disable all insns with wider 13690vector or mask register operands. On SVR4-derived platforms, the 13691separator character ‘/’ can be replaced by ‘:’. 13692 13693 Following the CPU architecture (but not a sub-architecture, which are 13694those starting with a dot), you may specify ‘jumps’ or ‘nojumps’ to 13695control automatic promotion of conditional jumps. ‘jumps’ is the 13696default, and enables jump promotion; All external jumps will be of the 13697long variety, and file-local jumps will be promoted as necessary. 13698(*note i386-Jumps::) ‘nojumps’ leaves external conditional jumps as byte 13699offset jumps, and warns about file-local conditional jumps that ‘as’ 13700promotes. Unconditional jumps are treated as for ‘jumps’. 13701 13702 For example 13703 13704 .arch i8086,nojumps 13705 13706 13707File: as.info, Node: i386-ISA, Next: i386-Bugs, Prev: i386-Arch, Up: i386-Dependent 13708 137099.16.16 AMD64 ISA vs. Intel64 ISA 13710--------------------------------- 13711 13712There are some discrepancies between AMD64 and Intel64 ISAs. 13713 13714 • For ‘movsxd’ with 16-bit destination register, AMD64 supports 13715 32-bit source operand and Intel64 supports 16-bit source operand. 13716 13717 • For far branches (with explicit memory operand), both ISAs support 13718 32- and 16-bit operand size. Intel64 additionally supports 64-bit 13719 operand size, encoded as ‘ljmpq’ and ‘lcallq’ in AT&T syntax and 13720 with an explicit ‘tbyte ptr’ operand size specifier in Intel 13721 syntax. 13722 13723 • ‘lfs’, ‘lgs’, and ‘lss’ similarly allow for 16- and 32-bit operand 13724 size (32- and 48-bit memory operand) in both ISAs, while Intel64 13725 additionally supports 64-bit operand size (80-bit memory operands). 13726 13727 13728File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-ISA, Up: i386-Dependent 13729 137309.16.17 AT&T Syntax bugs 13731------------------------ 13732 13733The UnixWare assembler, and probably other AT&T derived ix86 Unix 13734assemblers, generate floating point instructions with reversed source 13735and destination registers in certain cases. Unfortunately, gcc and 13736possibly many other programs use this reversed syntax, so we’re stuck 13737with it. 13738 13739 For example 13740 13741 fsub %st,%st(3) 13742results in ‘%st(3)’ being updated to ‘%st - %st(3)’ rather than the 13743expected ‘%st(3) - %st’. This happens with all the non-commutative 13744arithmetic floating point operations with two register operands where 13745the source register is ‘%st’ and the destination register is ‘%st(i)’. 13746 13747 13748File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 13749 137509.16.18 Notes 13751------------- 13752 13753There is some trickery concerning the ‘mul’ and ‘imul’ instructions that 13754deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies 13755(base opcode ‘0xf6’; extension 4 for ‘mul’ and 5 for ‘imul’) can be 13756output only in the one operand form. Thus, ‘imul %ebx, %eax’ does _not_ 13757select the expanding multiply; the expanding multiply would clobber the 13758‘%edx’ register, and this would confuse ‘gcc’ output. Use ‘imul %ebx’ 13759to get the 64-bit product in ‘%edx:%eax’. 13760 13761 We have added a two operand form of ‘imul’ when the first operand is 13762an immediate mode expression and the second operand is a register. This 13763is just a shorthand, so that, multiplying ‘%eax’ by 69, for example, can 13764be done with ‘imul $69, %eax’ rather than ‘imul $69, %eax, %eax’. 13765 13766 13767File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 13768 137699.17 IA-64 Dependent Features 13770============================= 13771 13772* Menu: 13773 13774* IA-64 Options:: Options 13775* IA-64 Syntax:: Syntax 13776* IA-64 Opcodes:: Opcodes 13777 13778 13779File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 13780 137819.17.1 Options 13782-------------- 13783 13784‘-mconstant-gp’ 13785 This option instructs the assembler to mark the resulting object 13786 file as using the “constant GP” model. With this model, it is 13787 assumed that the entire program uses a single global pointer (GP) 13788 value. Note that this option does not in any fashion affect the 13789 machine code emitted by the assembler. All it does is turn on the 13790 EF_IA_64_CONS_GP flag in the ELF file header. 13791 13792‘-mauto-pic’ 13793 This option instructs the assembler to mark the resulting object 13794 file as using the “constant GP without function descriptor” data 13795 model. This model is like the “constant GP” model, except that it 13796 additionally does away with function descriptors. What this means 13797 is that the address of a function refers directly to the function’s 13798 code entry-point. Normally, such an address would refer to a 13799 function descriptor, which contains both the code entry-point and 13800 the GP-value needed by the function. Note that this option does 13801 not in any fashion affect the machine code emitted by the 13802 assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP 13803 flag in the ELF file header. 13804 13805‘-milp32’ 13806‘-milp64’ 13807‘-mlp64’ 13808‘-mp64’ 13809 These options select the data model. The assembler defaults to 13810 ‘-mlp64’ (LP64 data model). 13811 13812‘-mle’ 13813‘-mbe’ 13814 These options select the byte order. The ‘-mle’ option selects 13815 little-endian byte order (default) and ‘-mbe’ selects big-endian 13816 byte order. Note that IA-64 machine code always uses little-endian 13817 byte order. 13818 13819‘-mtune=itanium1’ 13820‘-mtune=itanium2’ 13821 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 13822 is ITANIUM2. 13823 13824‘-munwind-check=warning’ 13825‘-munwind-check=error’ 13826 These options control what the assembler will do when performing 13827 consistency checks on unwind directives. ‘-munwind-check=warning’ 13828 will make the assembler issue a warning when an unwind directive 13829 check fails. This is the default. ‘-munwind-check=error’ will 13830 make the assembler issue an error when an unwind directive check 13831 fails. 13832 13833‘-mhint.b=ok’ 13834‘-mhint.b=warning’ 13835‘-mhint.b=error’ 13836 These options control what the assembler will do when the ‘hint.b’ 13837 instruction is used. ‘-mhint.b=ok’ will make the assembler accept 13838 ‘hint.b’. ‘-mint.b=warning’ will make the assembler issue a 13839 warning when ‘hint.b’ is used. ‘-mhint.b=error’ will make the 13840 assembler treat ‘hint.b’ as an error, which is the default. 13841 13842‘-x’ 13843‘-xexplicit’ 13844 These options turn on dependency violation checking. 13845 13846‘-xauto’ 13847 This option instructs the assembler to automatically insert stop 13848 bits where necessary to remove dependency violations. This is the 13849 default mode. 13850 13851‘-xnone’ 13852 This option turns off dependency violation checking. 13853 13854‘-xdebug’ 13855 This turns on debug output intended to help tracking down bugs in 13856 the dependency violation checker. 13857 13858‘-xdebugn’ 13859 This is a shortcut for -xnone -xdebug. 13860 13861‘-xdebugx’ 13862 This is a shortcut for -xexplicit -xdebug. 13863 13864 13865File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 13866 138679.17.2 Syntax 13868------------- 13869 13870The assembler syntax closely follows the IA-64 Assembly Language 13871Reference Guide. 13872 13873* Menu: 13874 13875* IA-64-Chars:: Special Characters 13876* IA-64-Regs:: Register Names 13877* IA-64-Bits:: Bit Names 13878* IA-64-Relocs:: Relocations 13879 13880 13881File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 13882 138839.17.2.1 Special Characters 13884........................... 13885 13886‘//’ is the line comment token. 13887 13888 ‘;’ can be used instead of a newline to separate statements. 13889 13890 13891File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 13892 138939.17.2.2 Register Names 13894....................... 13895 13896The 128 integer registers are referred to as ‘rN’. The 128 13897floating-point registers are referred to as ‘fN’. The 128 application 13898registers are referred to as ‘arN’. The 128 control registers are 13899referred to as ‘crN’. The 64 one-bit predicate registers are referred 13900to as ‘pN’. The 8 branch registers are referred to as ‘bN’. In 13901addition, the assembler defines a number of aliases: ‘gp’ (‘r1’), ‘sp’ 13902(‘r12’), ‘rp’ (‘b0’), ‘ret0’ (‘r8’), ‘ret1’ (‘r9’), ‘ret2’ (‘r10’), 13903‘ret3’ (‘r9’), ‘fargN’ (‘f8+N’), and ‘fretN’ (‘f8+N’). 13904 13905 For convenience, the assembler also defines aliases for all named 13906application and control registers. For example, ‘ar.bsp’ refers to the 13907register backing store pointer (‘ar17’). Similarly, ‘cr.eoi’ refers to 13908the end-of-interrupt register (‘cr67’). 13909 13910 13911File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 13912 139139.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 13914........................................................ 13915 13916The assembler defines bit masks for each of the bits in the IA-64 13917processor status register. For example, ‘psr.ic’ corresponds to a value 13918of 0x2000. These masks are primarily intended for use with the 13919‘ssm’/‘sum’ and ‘rsm’/‘rum’ instructions, but they can be used anywhere 13920else where an integer constant is expected. 13921 13922 13923File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 13924 139259.17.2.4 Relocations 13926.................... 13927 13928In addition to the standard IA-64 relocations, the following relocations 13929are implemented by ‘as’: 13930 13931‘@slotcount(V)’ 13932 Convert the address offset V into a slot count. This pseudo 13933 function is available only on VMS. The expression V must be known 13934 at assembly time: it can’t reference undefined symbols or symbols 13935 in different sections. 13936 13937 13938File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 13939 139409.17.3 Opcodes 13941-------------- 13942 13943For detailed information on the IA-64 machine instruction set, see the 13944IA-64 Architecture Handbook 13945(http://developer.intel.com/design/itanium/arch_spec.htm). 13946 13947 13948File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 13949 139509.18 IP2K Dependent Features 13951============================ 13952 13953* Menu: 13954 13955* IP2K-Opts:: IP2K Options 13956* IP2K-Syntax:: IP2K Syntax 13957 13958 13959File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 13960 139619.18.1 IP2K Options 13962------------------- 13963 13964The Ubicom IP2K version of ‘as’ has a few machine dependent options: 13965 13966‘-mip2022ext’ 13967 ‘as’ can assemble the extended IP2022 instructions, but it will 13968 only do so if this is specifically allowed via this command line 13969 option. 13970 13971‘-mip2022’ 13972 This option restores the assembler’s default behaviour of not 13973 permitting the extended IP2022 instructions to be assembled. 13974 13975 13976File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent 13977 139789.18.2 IP2K Syntax 13979------------------ 13980 13981* Menu: 13982 13983* IP2K-Chars:: Special Characters 13984 13985 13986File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 13987 139889.18.2.1 Special Characters 13989........................... 13990 13991The presence of a ‘;’ on a line indicates the start of a comment that 13992extends to the end of the current line. 13993 13994 If a ‘#’ appears as the first character of a line, the whole line is 13995treated as a comment, but in this case the line can also be a logical 13996line number directive (*note Comments::) or a preprocessor control 13997command (*note Preprocessing::). 13998 13999 The IP2K assembler does not currently support a line separator 14000character. 14001 14002 14003File: as.info, Node: LM32-Dependent, Next: KVX-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 14004 140059.19 LM32 Dependent Features 14006============================ 14007 14008* Menu: 14009 14010* LM32 Options:: Options 14011* LM32 Syntax:: Syntax 14012* LM32 Opcodes:: Opcodes 14013 14014 14015File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 14016 140179.19.1 Options 14018-------------- 14019 14020‘-mmultiply-enabled’ 14021 Enable multiply instructions. 14022 14023‘-mdivide-enabled’ 14024 Enable divide instructions. 14025 14026‘-mbarrel-shift-enabled’ 14027 Enable barrel-shift instructions. 14028 14029‘-msign-extend-enabled’ 14030 Enable sign extend instructions. 14031 14032‘-muser-enabled’ 14033 Enable user defined instructions. 14034 14035‘-micache-enabled’ 14036 Enable instruction cache related CSRs. 14037 14038‘-mdcache-enabled’ 14039 Enable data cache related CSRs. 14040 14041‘-mbreak-enabled’ 14042 Enable break instructions. 14043 14044‘-mall-enabled’ 14045 Enable all instructions and CSRs. 14046 14047 14048File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 14049 140509.19.2 Syntax 14051------------- 14052 14053* Menu: 14054 14055* LM32-Regs:: Register Names 14056* LM32-Modifiers:: Relocatable Expression Modifiers 14057* LM32-Chars:: Special Characters 14058 14059 14060File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 14061 140629.19.2.1 Register Names 14063....................... 14064 14065LM32 has 32 x 32-bit general purpose registers ‘r0’, ‘r1’, ... ‘r31’. 14066 14067 The following aliases are defined: ‘gp’ - ‘r26’, ‘fp’ - ‘r27’, ‘sp’ - 14068‘r28’, ‘ra’ - ‘r29’, ‘ea’ - ‘r30’, ‘ba’ - ‘r31’. 14069 14070 LM32 has the following Control and Status Registers (CSRs). 14071 14072‘IE’ 14073 Interrupt enable. 14074‘IM’ 14075 Interrupt mask. 14076‘IP’ 14077 Interrupt pending. 14078‘ICC’ 14079 Instruction cache control. 14080‘DCC’ 14081 Data cache control. 14082‘CC’ 14083 Cycle counter. 14084‘CFG’ 14085 Configuration. 14086‘EBA’ 14087 Exception base address. 14088‘DC’ 14089 Debug control. 14090‘DEBA’ 14091 Debug exception base address. 14092‘JTX’ 14093 JTAG transmit. 14094‘JRX’ 14095 JTAG receive. 14096‘BP0’ 14097 Breakpoint 0. 14098‘BP1’ 14099 Breakpoint 1. 14100‘BP2’ 14101 Breakpoint 2. 14102‘BP3’ 14103 Breakpoint 3. 14104‘WP0’ 14105 Watchpoint 0. 14106‘WP1’ 14107 Watchpoint 1. 14108‘WP2’ 14109 Watchpoint 2. 14110‘WP3’ 14111 Watchpoint 3. 14112 14113 14114File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax 14115 141169.19.2.2 Relocatable Expression Modifiers 14117......................................... 14118 14119The assembler supports several modifiers when using relocatable 14120addresses in LM32 instruction operands. The general syntax is the 14121following: 14122 14123 modifier(relocatable-expression) 14124 14125‘lo’ 14126 14127 This modifier allows you to use bits 0 through 15 of an address 14128 expression as 16 bit relocatable expression. 14129 14130‘hi’ 14131 14132 This modifier allows you to use bits 16 through 23 of an address 14133 expression as 16 bit relocatable expression. 14134 14135 For example 14136 14137 ori r4, r4, lo(sym+10) 14138 orhi r4, r4, hi(sym+10) 14139 14140‘gp’ 14141 14142 This modified creates a 16-bit relocatable expression that is the 14143 offset of the symbol from the global pointer. 14144 14145 mva r4, gp(sym) 14146 14147‘got’ 14148 14149 This modifier places a symbol in the GOT and creates a 16-bit 14150 relocatable expression that is the offset into the GOT of this 14151 symbol. 14152 14153 lw r4, (gp+got(sym)) 14154 14155‘gotofflo16’ 14156 14157 This modifier allows you to use the bits 0 through 15 of an address 14158 which is an offset from the GOT. 14159 14160‘gotoffhi16’ 14161 14162 This modifier allows you to use the bits 16 through 31 of an 14163 address which is an offset from the GOT. 14164 14165 orhi r4, r4, gotoffhi16(lsym) 14166 addi r4, r4, gotofflo16(lsym) 14167 14168 14169File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 14170 141719.19.2.3 Special Characters 14172........................... 14173 14174The presence of a ‘#’ on a line indicates the start of a comment that 14175extends to the end of the current line. Note that if a line starts with 14176a ‘#’ character then it can also be a logical line number directive 14177(*note Comments::) or a preprocessor control command (*note 14178Preprocessing::). 14179 14180 A semicolon (‘;’) can be used to separate multiple statements on the 14181same line. 14182 14183 14184File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 14185 141869.19.3 Opcodes 14187-------------- 14188 14189For detailed information on the LM32 machine instruction set, see 14190<http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>. 14191 14192 ‘as’ implements all the standard LM32 opcodes. 14193 14194 14195File: as.info, Node: KVX-Dependent, Next: M32C-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 14196 141979.20 KVX Dependent Features 14198=========================== 14199 14200Labels followed by ‘::’ are extern symbols. 14201 14202* Menu: 14203 14204* KVX Options:: Options 14205* KVX Directives:: KVX Machine Directives 14206 14207 14208File: as.info, Node: KVX Options, Next: KVX Directives, Up: KVX-Dependent 14209 142109.20.1 Options 14211-------------- 14212 14213‘--dump-insn’ 14214 Dump the full list of instructions. 14215 14216‘-march=’ 14217 The assembler supports the following architectures: kv3-1, kv3-2. 14218 14219‘--check-resources’ 14220 Check that each bundle does not use more resources than available. 14221 This is the default. 14222 14223‘--no-check-resources’ 14224 Do not check that each bundle does not use more resources than 14225 available. 14226 14227‘--generate-illegal-code’ 14228 For debugging purposes only. In order to properly work, the bundle 14229 is sorted with respect to the issues it uses. If this option is 14230 turned on the assembler will not sort the bundle instructions and 14231 illegal bundles might be formed unless they were properly sorted by 14232 hand. 14233 14234‘--dump-table’ 14235 Dump the table of opcodes. 14236 14237‘--mpic | --mPIC’ 14238 Generate position independent code. 14239 14240‘--mnopic’ 14241 Generate position dependent code. 14242 14243‘-m32’ 14244 Generate 32-bits code. 14245 14246‘--all-sfr’ 14247 This switch enables the register class "system register". This 14248 register class is used when performing system validation and allows 14249 the full class of system registers to be used even on instructions 14250 that are only valid with some specific system registers. 14251 14252‘--diagnostics’ 14253 Print multi-line errors. This is the default. 14254 14255‘--no-diagnostics’ 14256 Print succinct diagnostics on one line. 14257 14258 14259File: as.info, Node: KVX Directives, Prev: KVX Options, Up: KVX-Dependent 14260 142619.20.2 KVX Machine Directives 14262----------------------------- 14263 14264‘.align ALIGNMENT’ 14265 Pad with NOPs until the next boundary with the required ALIGNMENT. 14266 14267‘.dword’ 14268 Declare a double-word-sized (8 bytes) constant. 14269 14270‘.endp [PROC]’ 14271 This directive marks the end of the procedure PROC. The name of the 14272 procedure is always ignored (it is only here as a visual 14273 indicator). 14274 14275 .proc NAME 14276 ... 14277 .endp NAME 14278 14279 is equivalent to the more traditional 14280 14281 .type NAME, @function 14282 ... 14283 .size NAME,.-NAME 14284 14285‘.file’ 14286 This directive is only supported when producing ELF files. *note 14287 ‘.file’: File. for details. 14288 14289‘.loc FILENO LINENO’ 14290 This directive is only supported when producing ELF files. *note 14291 ‘.line’: Line. for details. 14292 14293‘.proc PROC’ 14294 This directive marks the start of procedure, the name of the 14295 procedure PROC is mandatory and all ‘.proc’ directive should be 14296 matched by exactly one ‘.endp’ directive. 14297 14298‘.word’ 14299 Declare a word-sized (4 bytes) constant. 14300 14301 14302File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: KVX-Dependent, Up: Machine Dependencies 14303 143049.21 M32C Dependent Features 14305============================ 14306 14307‘as’ can assemble code for several different members of the Renesas M32C 14308family. Normally the default is to assemble code for the M16C 14309microprocessor. The ‘-m32c’ option may be used to change the default to 14310the M32C microprocessor. 14311 14312* Menu: 14313 14314* M32C-Opts:: M32C Options 14315* M32C-Syntax:: M32C Syntax 14316 14317 14318File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 14319 143209.21.1 M32C Options 14321------------------- 14322 14323The Renesas M32C version of ‘as’ has these machine-dependent options: 14324 14325‘-m32c’ 14326 Assemble M32C instructions. 14327 14328‘-m16c’ 14329 Assemble M16C instructions (default). 14330 14331‘-relax’ 14332 Enable support for link-time relaxations. 14333 14334‘-h-tick-hex’ 14335 Support H’00 style hex constants in addition to 0x00 style. 14336 14337 14338File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent 14339 143409.21.2 M32C Syntax 14341------------------ 14342 14343* Menu: 14344 14345* M32C-Modifiers:: Symbolic Operand Modifiers 14346* M32C-Chars:: Special Characters 14347 14348 14349File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax 14350 143519.21.2.1 Symbolic Operand Modifiers 14352................................... 14353 14354The assembler supports several modifiers when using symbol addresses in 14355M32C instruction operands. The general syntax is the following: 14356 14357 %modifier(symbol) 14358 14359‘%dsp8’ 14360‘%dsp16’ 14361 14362 These modifiers override the assembler’s assumptions about how big 14363 a symbol’s address is. Normally, when it sees an operand like 14364 ‘sym[a0]’ it assumes ‘sym’ may require the widest displacement 14365 field (16 bits for ‘-m16c’, 24 bits for ‘-m32c’). These modifiers 14366 tell it to assume the address will fit in an 8 or 16 bit 14367 (respectively) unsigned displacement. Note that, of course, if it 14368 doesn’t actually fit you will get linker errors. Example: 14369 14370 mov.w %dsp8(sym)[a0],r1 14371 mov.b #0,%dsp8(sym)[a0] 14372 14373‘%hi8’ 14374 14375 This modifier allows you to load bits 16 through 23 of a 24 bit 14376 address into an 8 bit register. This is useful with, for example, 14377 the M16C ‘smovf’ instruction, which expects a 20 bit address in 14378 ‘r1h’ and ‘a0’. Example: 14379 14380 mov.b #%hi8(sym),r1h 14381 mov.w #%lo16(sym),a0 14382 smovf.b 14383 14384‘%lo16’ 14385 14386 Likewise, this modifier allows you to load bits 0 through 15 of a 14387 24 bit address into a 16 bit register. 14388 14389‘%hi16’ 14390 14391 This modifier allows you to load bits 16 through 31 of a 32 bit 14392 address into a 16 bit register. While the M32C family only has 24 14393 bits of address space, it does support addresses in pairs of 16 bit 14394 registers (like ‘a1a0’ for the ‘lde’ instruction). This modifier 14395 is for loading the upper half in such cases. Example: 14396 14397 mov.w #%hi16(sym),a1 14398 mov.w #%lo16(sym),a0 14399 ... 14400 lde.w [a1a0],r1 14401 14402 14403File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 14404 144059.21.2.2 Special Characters 14406........................... 14407 14408The presence of a ‘;’ character on a line indicates the start of a 14409comment that extends to the end of that line. 14410 14411 If a ‘#’ appears as the first character of a line, the whole line is 14412treated as a comment, but in this case the line can also be a logical 14413line number directive (*note Comments::) or a preprocessor control 14414command (*note Preprocessing::). 14415 14416 The ‘|’ character can be used to separate statements on the same 14417line. 14418 14419 14420File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 14421 144229.22 M32R Dependent Features 14423============================ 14424 14425* Menu: 14426 14427* M32R-Opts:: M32R Options 14428* M32R-Directives:: M32R Directives 14429* M32R-Warnings:: M32R Warnings 14430 14431 14432File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 14433 144349.22.1 M32R Options 14435------------------- 14436 14437The Renesas M32R version of ‘as’ has a few machine dependent options: 14438 14439‘-m32rx’ 14440 ‘as’ can assemble code for several different members of the Renesas 14441 M32R family. Normally the default is to assemble code for the M32R 14442 microprocessor. This option may be used to change the default to 14443 the M32RX microprocessor, which adds some more instructions to the 14444 basic M32R instruction set, and some additional parameters to some 14445 of the original instructions. 14446 14447‘-m32r2’ 14448 This option changes the target processor to the M32R2 14449 microprocessor. 14450 14451‘-m32r’ 14452 This option can be used to restore the assembler’s default 14453 behaviour of assembling for the M32R microprocessor. This can be 14454 useful if the default has been changed by a previous command-line 14455 option. 14456 14457‘-little’ 14458 This option tells the assembler to produce little-endian code and 14459 data. The default is dependent upon how the toolchain was 14460 configured. 14461 14462‘-EL’ 14463 This is a synonym for _-little_. 14464 14465‘-big’ 14466 This option tells the assembler to produce big-endian code and 14467 data. 14468 14469‘-EB’ 14470 This is a synonym for _-big_. 14471 14472‘-KPIC’ 14473 This option specifies that the output of the assembler should be 14474 marked as position-independent code (PIC). 14475 14476‘-parallel’ 14477 This option tells the assembler to attempts to combine two 14478 sequential instructions into a single, parallel instruction, where 14479 it is legal to do so. 14480 14481‘-no-parallel’ 14482 This option disables a previously enabled _-parallel_ option. 14483 14484‘-no-bitinst’ 14485 This option disables the support for the extended bit-field 14486 instructions provided by the M32R2. If this support needs to be 14487 re-enabled the _-bitinst_ switch can be used to restore it. 14488 14489‘-O’ 14490 This option tells the assembler to attempt to optimize the 14491 instructions that it produces. This includes filling delay slots 14492 and converting sequential instructions into parallel ones. This 14493 option implies _-parallel_. 14494 14495‘-warn-explicit-parallel-conflicts’ 14496 Instructs ‘as’ to produce warning messages when questionable 14497 parallel instructions are encountered. This option is enabled by 14498 default, but ‘gcc’ disables it when it invokes ‘as’ directly. 14499 Questionable instructions are those whose behaviour would be 14500 different if they were executed sequentially. For example the code 14501 fragment ‘mv r1, r2 || mv r3, r1’ produces a different result from 14502 ‘mv r1, r2 \n mv r3, r1’ since the former moves r1 into r3 and then 14503 r2 into r1, whereas the later moves r2 into r1 and r3. 14504 14505‘-Wp’ 14506 This is a shorter synonym for the 14507 _-warn-explicit-parallel-conflicts_ option. 14508 14509‘-no-warn-explicit-parallel-conflicts’ 14510 Instructs ‘as’ not to produce warning messages when questionable 14511 parallel instructions are encountered. 14512 14513‘-Wnp’ 14514 This is a shorter synonym for the 14515 _-no-warn-explicit-parallel-conflicts_ option. 14516 14517‘-ignore-parallel-conflicts’ 14518 This option tells the assembler’s to stop checking parallel 14519 instructions for constraint violations. This ability is provided 14520 for hardware vendors testing chip designs and should not be used 14521 under normal circumstances. 14522 14523‘-no-ignore-parallel-conflicts’ 14524 This option restores the assembler’s default behaviour of checking 14525 parallel instructions to detect constraint violations. 14526 14527‘-Ip’ 14528 This is a shorter synonym for the _-ignore-parallel-conflicts_ 14529 option. 14530 14531‘-nIp’ 14532 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 14533 option. 14534 14535‘-warn-unmatched-high’ 14536 This option tells the assembler to produce a warning message if a 14537 ‘.high’ pseudo op is encountered without a matching ‘.low’ pseudo 14538 op. The presence of such an unmatched pseudo op usually indicates 14539 a programming error. 14540 14541‘-no-warn-unmatched-high’ 14542 Disables a previously enabled _-warn-unmatched-high_ option. 14543 14544‘-Wuh’ 14545 This is a shorter synonym for the _-warn-unmatched-high_ option. 14546 14547‘-Wnuh’ 14548 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 14549 14550 14551File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 14552 145539.22.2 M32R Directives 14554---------------------- 14555 14556The Renesas M32R version of ‘as’ has a few architecture specific 14557directives: 14558 14559‘low EXPRESSION’ 14560 The ‘low’ directive computes the value of its expression and places 14561 the lower 16-bits of the result into the immediate-field of the 14562 instruction. For example: 14563 14564 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 14565 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 14566 14567‘high EXPRESSION’ 14568 The ‘high’ directive computes the value of its expression and 14569 places the upper 16-bits of the result into the immediate-field of 14570 the instruction. For example: 14571 14572 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 14573 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 14574 14575‘shigh EXPRESSION’ 14576 The ‘shigh’ directive is very similar to the ‘high’ directive. It 14577 also computes the value of its expression and places the upper 14578 16-bits of the result into the immediate-field of the instruction. 14579 The difference is that ‘shigh’ also checks to see if the lower 14580 16-bits could be interpreted as a signed number, and if so it 14581 assumes that a borrow will occur from the upper-16 bits. To 14582 compensate for this the ‘shigh’ directive pre-biases the upper 16 14583 bit value by adding one to it. For example: 14584 14585 For example: 14586 14587 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 14588 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 14589 14590 In the second example the lower 16-bits are 0x8000. If these are 14591 treated as a signed value and sign extended to 32-bits then the 14592 value becomes 0xffff8000. If this value is then added to 14593 0x00010000 then the result is 0x00008000. 14594 14595 This behaviour is to allow for the different semantics of the ‘or3’ 14596 and ‘add3’ instructions. The ‘or3’ instruction treats its 16-bit 14597 immediate argument as unsigned whereas the ‘add3’ treats its 16-bit 14598 immediate as a signed value. So for example: 14599 14600 seth r0, #shigh(0x00008000) 14601 add3 r0, r0, #low(0x00008000) 14602 14603 Produces the correct result in r0, whereas: 14604 14605 seth r0, #shigh(0x00008000) 14606 or3 r0, r0, #low(0x00008000) 14607 14608 Stores 0xffff8000 into r0. 14609 14610 Note - the ‘shigh’ directive does not know where in the assembly 14611 source code the lower 16-bits of the value are going set, so it 14612 cannot check to make sure that an ‘or3’ instruction is being used 14613 rather than an ‘add3’ instruction. It is up to the programmer to 14614 make sure that correct directives are used. 14615 14616‘.m32r’ 14617 The directive performs a similar thing as the _-m32r_ command line 14618 option. It tells the assembler to only accept M32R instructions 14619 from now on. An instructions from later M32R architectures are 14620 refused. 14621 14622‘.m32rx’ 14623 The directive performs a similar thing as the _-m32rx_ command line 14624 option. It tells the assembler to start accepting the extra 14625 instructions in the M32RX ISA as well as the ordinary M32R ISA. 14626 14627‘.m32r2’ 14628 The directive performs a similar thing as the _-m32r2_ command line 14629 option. It tells the assembler to start accepting the extra 14630 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 14631 14632‘.little’ 14633 The directive performs a similar thing as the _-little_ command 14634 line option. It tells the assembler to start producing 14635 little-endian code and data. This option should be used with care 14636 as producing mixed-endian binary files is fraught with danger. 14637 14638‘.big’ 14639 The directive performs a similar thing as the _-big_ command line 14640 option. It tells the assembler to start producing big-endian code 14641 and data. This option should be used with care as producing 14642 mixed-endian binary files is fraught with danger. 14643 14644 14645File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 14646 146479.22.3 M32R Warnings 14648-------------------- 14649 14650There are several warning and error messages that can be produced by 14651‘as’ which are specific to the M32R: 14652 14653‘output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?’ 14654 This message is only produced if warnings for explicit parallel 14655 conflicts have been enabled. It indicates that the assembler has 14656 encountered a parallel instruction in which the destination 14657 register of the left hand instruction is used as an input register 14658 in the right hand instruction. For example in this code fragment 14659 ‘mv r1, r2 || neg r3, r1’ register r1 is the destination of the 14660 move instruction and the input to the neg instruction. 14661 14662‘output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?’ 14663 This message is only produced if warnings for explicit parallel 14664 conflicts have been enabled. It indicates that the assembler has 14665 encountered a parallel instruction in which the destination 14666 register of the right hand instruction is used as an input register 14667 in the left hand instruction. For example in this code fragment 14668 ‘mv r1, r2 || neg r2, r3’ register r2 is the destination of the neg 14669 instruction and the input to the move instruction. 14670 14671‘instruction ‘...’ is for the M32RX only’ 14672 This message is produced when the assembler encounters an 14673 instruction which is only supported by the M32Rx processor, and the 14674 ‘-m32rx’ command-line flag has not been specified to allow assembly 14675 of such instructions. 14676 14677‘unknown instruction ‘...’’ 14678 This message is produced when the assembler encounters an 14679 instruction which it does not recognize. 14680 14681‘only the NOP instruction can be issued in parallel on the m32r’ 14682 This message is produced when the assembler encounters a parallel 14683 instruction which does not involve a NOP instruction and the 14684 ‘-m32rx’ command-line flag has not been specified. Only the M32Rx 14685 processor is able to execute two instructions in parallel. 14686 14687‘instruction ‘...’ cannot be executed in parallel.’ 14688 This message is produced when the assembler encounters a parallel 14689 instruction which is made up of one or two instructions which 14690 cannot be executed in parallel. 14691 14692‘Instructions share the same execution pipeline’ 14693 This message is produced when the assembler encounters a parallel 14694 instruction whose components both use the same execution pipeline. 14695 14696‘Instructions write to the same destination register.’ 14697 This message is produced when the assembler encounters a parallel 14698 instruction where both components attempt to modify the same 14699 register. For example these code fragments will produce this 14700 message: ‘mv r1, r2 || neg r1, r3’ ‘jl r0 || mv r14, r1’ ‘st r2, 14701 @-r1 || mv r1, r3’ ‘mv r1, r2 || ld r0, @r1+’ ‘cmp r1, r2 || addx 14702 r3, r4’ (Both write to the condition bit) 14703 14704 14705File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 14706 147079.23 M680x0 Dependent Features 14708============================== 14709 14710* Menu: 14711 14712* M68K-Opts:: M680x0 Options 14713* M68K-Syntax:: Syntax 14714* M68K-Moto-Syntax:: Motorola Syntax 14715* M68K-Float:: Floating Point 14716* M68K-Directives:: 680x0 Machine Directives 14717* M68K-opcodes:: Opcodes 14718 14719 14720File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 14721 147229.23.1 M680x0 Options 14723--------------------- 14724 14725The Motorola 680x0 version of ‘as’ has a few machine dependent options: 14726 14727‘-march=ARCHITECTURE’ 14728 This option specifies a target architecture. The following 14729 architectures are recognized: ‘68000’, ‘68010’, ‘68020’, ‘68030’, 14730 ‘68040’, ‘68060’, ‘cpu32’, ‘isaa’, ‘isaaplus’, ‘isab’, ‘isac’ and 14731 ‘cfv4e’. 14732 14733‘-mcpu=CPU’ 14734 This option specifies a target cpu. When used in conjunction with 14735 the ‘-march’ option, the cpu must be within the specified 14736 architecture. Also, the generic features of the architecture are 14737 used for instruction generation, rather than those of the specific 14738 chip. 14739 14740‘-m[no-]68851’ 14741‘-m[no-]68881’ 14742‘-m[no-]div’ 14743‘-m[no-]usp’ 14744‘-m[no-]float’ 14745‘-m[no-]mac’ 14746‘-m[no-]emac’ 14747 14748 Enable or disable various architecture specific features. If a 14749 chip or architecture by default supports an option (for instance 14750 ‘-march=isaaplus’ includes the ‘-mdiv’ option), explicitly 14751 disabling the option will override the default. 14752 14753‘-l’ 14754 You can use the ‘-l’ option to shorten the size of references to 14755 undefined symbols. If you do not use the ‘-l’ option, references 14756 to undefined symbols are wide enough for a full ‘long’ (32 bits). 14757 (Since ‘as’ cannot know where these symbols end up, ‘as’ can only 14758 allocate space for the linker to fill in later. Since ‘as’ does 14759 not know how far away these symbols are, it allocates as much space 14760 as it can.) If you use this option, the references are only one 14761 word wide (16 bits). This may be useful if you want the object 14762 file to be as small as possible, and you know that the relevant 14763 symbols are always less than 17 bits away. 14764 14765‘--register-prefix-optional’ 14766 For some configurations, especially those where the compiler 14767 normally does not prepend an underscore to the names of user 14768 variables, the assembler requires a ‘%’ before any use of a 14769 register name. This is intended to let the assembler distinguish 14770 between C variables and functions named ‘a0’ through ‘a7’, and so 14771 on. The ‘%’ is always accepted, but is not required for certain 14772 configurations, notably ‘sun3’. The ‘--register-prefix-optional’ 14773 option may be used to permit omitting the ‘%’ even for 14774 configurations for which it is normally required. If this is done, 14775 it will generally be impossible to refer to C variables and 14776 functions with the same names as register names. 14777 14778‘--bitwise-or’ 14779 Normally the character ‘|’ is treated as a comment character, which 14780 means that it can not be used in expressions. The ‘--bitwise-or’ 14781 option turns ‘|’ into a normal character. In this mode, you must 14782 either use C style comments, or start comments with a ‘#’ character 14783 at the beginning of a line. 14784 14785‘--base-size-default-16 --base-size-default-32’ 14786 If you use an addressing mode with a base register without 14787 specifying the size, ‘as’ will normally use the full 32 bit value. 14788 For example, the addressing mode ‘%a0@(%d0)’ is equivalent to 14789 ‘%a0@(%d0:l)’. You may use the ‘--base-size-default-16’ option to 14790 tell ‘as’ to default to using the 16 bit value. In this case, 14791 ‘%a0@(%d0)’ is equivalent to ‘%a0@(%d0:w)’. You may use the 14792 ‘--base-size-default-32’ option to restore the default behaviour. 14793 14794‘--disp-size-default-16 --disp-size-default-32’ 14795 If you use an addressing mode with a displacement, and the value of 14796 the displacement is not known, ‘as’ will normally assume that the 14797 value is 32 bits. For example, if the symbol ‘disp’ has not been 14798 defined, ‘as’ will assemble the addressing mode ‘%a0@(disp,%d0)’ as 14799 though ‘disp’ is a 32 bit value. You may use the 14800 ‘--disp-size-default-16’ option to tell ‘as’ to instead assume that 14801 the displacement is 16 bits. In this case, ‘as’ will assemble 14802 ‘%a0@(disp,%d0)’ as though ‘disp’ is a 16 bit value. You may use 14803 the ‘--disp-size-default-32’ option to restore the default 14804 behaviour. 14805 14806‘--pcrel’ 14807 Always keep branches PC-relative. In the M680x0 architecture all 14808 branches are defined as PC-relative. However, on some processors 14809 they are limited to word displacements maximum. When ‘as’ needs a 14810 long branch that is not available, it normally emits an absolute 14811 jump instead. This option disables this substitution. When this 14812 option is given and no long branches are available, only word 14813 branches will be emitted. An error message will be generated if a 14814 word branch cannot reach its target. This option has no effect on 14815 68020 and other processors that have long branches. *note Branch 14816 Improvement: M68K-Branch. 14817 14818‘-m68000’ 14819 ‘as’ can assemble code for several different members of the 14820 Motorola 680x0 family. The default depends upon how ‘as’ was 14821 configured when it was built; normally, the default is to assemble 14822 code for the 68020 microprocessor. The following options may be 14823 used to change the default. These options control which 14824 instructions and addressing modes are permitted. The members of 14825 the 680x0 family are very similar. For detailed information about 14826 the differences, see the Motorola manuals. 14827 14828 ‘-m68000’ 14829 ‘-m68ec000’ 14830 ‘-m68hc000’ 14831 ‘-m68hc001’ 14832 ‘-m68008’ 14833 ‘-m68302’ 14834 ‘-m68306’ 14835 ‘-m68307’ 14836 ‘-m68322’ 14837 ‘-m68356’ 14838 Assemble for the 68000. ‘-m68008’, ‘-m68302’, and so on are 14839 synonyms for ‘-m68000’, since the chips are the same from the 14840 point of view of the assembler. 14841 14842 ‘-m68010’ 14843 Assemble for the 68010. 14844 14845 ‘-m68020’ 14846 ‘-m68ec020’ 14847 Assemble for the 68020. This is normally the default. 14848 14849 ‘-m68030’ 14850 ‘-m68ec030’ 14851 Assemble for the 68030. 14852 14853 ‘-m68040’ 14854 ‘-m68ec040’ 14855 Assemble for the 68040. 14856 14857 ‘-m68060’ 14858 ‘-m68ec060’ 14859 Assemble for the 68060. 14860 14861 ‘-mcpu32’ 14862 ‘-m68330’ 14863 ‘-m68331’ 14864 ‘-m68332’ 14865 ‘-m68333’ 14866 ‘-m68334’ 14867 ‘-m68336’ 14868 ‘-m68340’ 14869 ‘-m68341’ 14870 ‘-m68349’ 14871 ‘-m68360’ 14872 Assemble for the CPU32 family of chips. 14873 14874 ‘-m5200’ 14875 ‘-m5202’ 14876 ‘-m5204’ 14877 ‘-m5206’ 14878 ‘-m5206e’ 14879 ‘-m521x’ 14880 ‘-m5249’ 14881 ‘-m528x’ 14882 ‘-m5307’ 14883 ‘-m5407’ 14884 ‘-m547x’ 14885 ‘-m548x’ 14886 ‘-mcfv4’ 14887 ‘-mcfv4e’ 14888 Assemble for the ColdFire family of chips. 14889 14890 ‘-m68881’ 14891 ‘-m68882’ 14892 Assemble 68881 floating point instructions. This is the 14893 default for the 68020, 68030, and the CPU32. The 68040 and 14894 68060 always support floating point instructions. 14895 14896 ‘-mno-68881’ 14897 Do not assemble 68881 floating point instructions. This is 14898 the default for 68000 and the 68010. The 68040 and 68060 14899 always support floating point instructions, even if this 14900 option is used. 14901 14902 ‘-m68851’ 14903 Assemble 68851 MMU instructions. This is the default for the 14904 68020, 68030, and 68060. The 68040 accepts a somewhat 14905 different set of MMU instructions; ‘-m68851’ and ‘-m68040’ 14906 should not be used together. 14907 14908 ‘-mno-68851’ 14909 Do not assemble 68851 MMU instructions. This is the default 14910 for the 68000, 68010, and the CPU32. The 68040 accepts a 14911 somewhat different set of MMU instructions. 14912 14913 14914File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 14915 149169.23.2 Syntax 14917------------- 14918 14919This syntax for the Motorola 680x0 was developed at MIT. 14920 14921 The 680x0 version of ‘as’ uses instructions names and syntax 14922compatible with the Sun assembler. Intervening periods are ignored; for 14923example, ‘movl’ is equivalent to ‘mov.l’. 14924 14925 In the following table APC stands for any of the address registers 14926(‘%a0’ through ‘%a7’), the program counter (‘%pc’), the zero-address 14927relative to the program counter (‘%zpc’), a suppressed address register 14928(‘%za0’ through ‘%za7’), or it may be omitted entirely. The use of SIZE 14929means one of ‘w’ or ‘l’, and it may be omitted, along with the leading 14930colon, unless a scale is also specified. The use of SCALE means one of 14931‘1’, ‘2’, ‘4’, or ‘8’, and it may always be omitted along with the 14932leading colon. 14933 14934 The following addressing modes are understood: 14935“Immediate” 14936 ‘#NUMBER’ 14937 14938“Data Register” 14939 ‘%d0’ through ‘%d7’ 14940 14941“Address Register” 14942 ‘%a0’ through ‘%a7’ 14943 ‘%a7’ is also known as ‘%sp’, i.e., the Stack Pointer. ‘%a6’ is 14944 also known as ‘%fp’, the Frame Pointer. 14945 14946“Address Register Indirect” 14947 ‘%a0@’ through ‘%a7@’ 14948 14949“Address Register Postincrement” 14950 ‘%a0@+’ through ‘%a7@+’ 14951 14952“Address Register Predecrement” 14953 ‘%a0@-’ through ‘%a7@-’ 14954 14955“Indirect Plus Offset” 14956 ‘APC@(NUMBER)’ 14957 14958“Index” 14959 ‘APC@(NUMBER,REGISTER:SIZE:SCALE)’ 14960 14961 The NUMBER may be omitted. 14962 14963“Postindex” 14964 ‘APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)’ 14965 14966 The ONUMBER or the REGISTER, but not both, may be omitted. 14967 14968“Preindex” 14969 ‘APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)’ 14970 14971 The NUMBER may be omitted. Omitting the REGISTER produces the 14972 Postindex addressing mode. 14973 14974“Absolute” 14975 ‘SYMBOL’, or ‘DIGITS’, optionally followed by ‘:b’, ‘:w’, or ‘:l’. 14976 14977 14978File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 14979 149809.23.3 Motorola Syntax 14981---------------------- 14982 14983The standard Motorola syntax for this chip differs from the syntax 14984already discussed (*note Syntax: M68K-Syntax.). ‘as’ can accept 14985Motorola syntax for operands, even if MIT syntax is used for other 14986operands in the same instruction. The two kinds of syntax are fully 14987compatible. 14988 14989 In the following table APC stands for any of the address registers 14990(‘%a0’ through ‘%a7’), the program counter (‘%pc’), the zero-address 14991relative to the program counter (‘%zpc’), or a suppressed address 14992register (‘%za0’ through ‘%za7’). The use of SIZE means one of ‘w’ or 14993‘l’, and it may always be omitted along with the leading dot. The use 14994of SCALE means one of ‘1’, ‘2’, ‘4’, or ‘8’, and it may always be 14995omitted along with the leading asterisk. 14996 14997 The following additional addressing modes are understood: 14998 14999“Address Register Indirect” 15000 ‘(%a0)’ through ‘(%a7)’ 15001 ‘%a7’ is also known as ‘%sp’, i.e., the Stack Pointer. ‘%a6’ is 15002 also known as ‘%fp’, the Frame Pointer. 15003 15004“Address Register Postincrement” 15005 ‘(%a0)+’ through ‘(%a7)+’ 15006 15007“Address Register Predecrement” 15008 ‘-(%a0)’ through ‘-(%a7)’ 15009 15010“Indirect Plus Offset” 15011 ‘NUMBER(%A0)’ through ‘NUMBER(%A7)’, or ‘NUMBER(%PC)’. 15012 15013 The NUMBER may also appear within the parentheses, as in 15014 ‘(NUMBER,%A0)’. When used with the PC, the NUMBER may be omitted 15015 (with an address register, omitting the NUMBER produces Address 15016 Register Indirect mode). 15017 15018“Index” 15019 ‘NUMBER(APC,REGISTER.SIZE*SCALE)’ 15020 15021 The NUMBER may be omitted, or it may appear within the parentheses. 15022 The APC may be omitted. The REGISTER and the APC may appear in 15023 either order. If both APC and REGISTER are address registers, and 15024 the SIZE and SCALE are omitted, then the first register is taken as 15025 the base register, and the second as the index register. 15026 15027“Postindex” 15028 ‘([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)’ 15029 15030 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 15031 NUMBER or the APC may be omitted, but not both. 15032 15033“Preindex” 15034 ‘([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)’ 15035 15036 The NUMBER, or the APC, or the REGISTER, or any two of them, may be 15037 omitted. The ONUMBER may be omitted. The REGISTER and the APC may 15038 appear in either order. If both APC and REGISTER are address 15039 registers, and the SIZE and SCALE are omitted, then the first 15040 register is taken as the base register, and the second as the index 15041 register. 15042 15043 15044File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 15045 150469.23.4 Floating Point 15047--------------------- 15048 15049Packed decimal (P) format floating literals are not supported. Feel 15050free to add the code! 15051 15052 The floating point formats generated by directives are these. 15053 15054‘.float’ 15055 ‘Single’ precision floating point constants. 15056 15057‘.double’ 15058 ‘Double’ precision floating point constants. 15059 15060‘.extend’ 15061‘.ldouble’ 15062 ‘Extended’ precision (‘long double’) floating point constants. 15063 15064 15065File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 15066 150679.23.5 680x0 Machine Directives 15068------------------------------- 15069 15070In order to be compatible with the Sun assembler the 680x0 assembler 15071understands the following directives. 15072 15073‘.data1’ 15074 This directive is identical to a ‘.data 1’ directive. 15075 15076‘.data2’ 15077 This directive is identical to a ‘.data 2’ directive. 15078 15079‘.even’ 15080 This directive is a special case of the ‘.align’ directive; it 15081 aligns the output to an even byte boundary. 15082 15083‘.skip’ 15084 This directive is identical to a ‘.space’ directive. 15085 15086‘.arch NAME’ 15087 Select the target architecture and extension features. Valid 15088 values for NAME are the same as for the ‘-march’ command-line 15089 option. This directive cannot be specified after any instructions 15090 have been assembled. If it is given multiple times, or in 15091 conjunction with the ‘-march’ option, all uses must be for the same 15092 architecture and extension set. 15093 15094‘.cpu NAME’ 15095 Select the target cpu. Valid values for NAME are the same as for 15096 the ‘-mcpu’ command-line option. This directive cannot be 15097 specified after any instructions have been assembled. If it is 15098 given multiple times, or in conjunction with the ‘-mopt’ option, 15099 all uses must be for the same cpu. 15100 15101 15102File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 15103 151049.23.6 Opcodes 15105-------------- 15106 15107* Menu: 15108 15109* M68K-Branch:: Branch Improvement 15110* M68K-Chars:: Special Characters 15111 15112 15113File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 15114 151159.23.6.1 Branch Improvement 15116........................... 15117 15118Certain pseudo opcodes are permitted for branch instructions. They 15119expand to the shortest branch instruction that reach the target. 15120Generally these mnemonics are made by substituting ‘j’ for ‘b’ at the 15121start of a Motorola mnemonic. 15122 15123 The following table summarizes the pseudo-operations. A ‘*’ flags 15124cases that are more fully described after the table: 15125 15126 Displacement 15127 +------------------------------------------------------------ 15128 | 68020 68000/10, not PC-relative OK 15129 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 15130 +------------------------------------------------------------ 15131 jbsr |bsrs bsrw bsrl jsr 15132 jra |bras braw bral jmp 15133 * jXX |bXXs bXXw bXXl bNXs;jmp 15134 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 15135 fjXX | N/A fbXXw fbXXl N/A 15136 15137 XX: condition 15138 NX: negative of condition XX 15139 15140 ‘*’—see full description below 15141 ‘**’—this expansion mode is disallowed by ‘--pcrel’ 15142 15143‘jbsr’ 15144‘jra’ 15145 These are the simplest jump pseudo-operations; they always map to 15146 one particular machine instruction, depending on the displacement 15147 to the branch target. This instruction will be a byte or word 15148 branch is that is sufficient. Otherwise, a long branch will be 15149 emitted if available. If no long branches are available and the 15150 ‘--pcrel’ option is not given, an absolute long jump will be 15151 emitted instead. If no long branches are available, the ‘--pcrel’ 15152 option is given, and a word branch cannot reach the target, an 15153 error message is generated. 15154 15155 In addition to standard branch operands, ‘as’ allows these 15156 pseudo-operations to have all operands that are allowed for jsr and 15157 jmp, substituting these instructions if the operand given is not 15158 valid for a branch instruction. 15159 15160‘jXX’ 15161 Here, ‘jXX’ stands for an entire family of pseudo-operations, where 15162 XX is a conditional branch or condition-code test. The full list 15163 of pseudo-ops in this family is: 15164 jhi jls jcc jcs jne jeq jvc 15165 jvs jpl jmi jge jlt jgt jle 15166 15167 Usually, each of these pseudo-operations expands to a single branch 15168 instruction. However, if a word branch is not sufficient, no long 15169 branches are available, and the ‘--pcrel’ option is not given, ‘as’ 15170 issues a longer code fragment in terms of NX, the opposite 15171 condition to XX. For example, under these conditions: 15172 jXX foo 15173 gives 15174 bNXs oof 15175 jmp foo 15176 oof: 15177 15178‘dbXX’ 15179 The full family of pseudo-operations covered here is 15180 dbhi dbls dbcc dbcs dbne dbeq dbvc 15181 dbvs dbpl dbmi dbge dblt dbgt dble 15182 dbf dbra dbt 15183 15184 Motorola ‘dbXX’ instructions allow word displacements only. When a 15185 word displacement is sufficient, each of these pseudo-operations 15186 expands to the corresponding Motorola instruction. When a word 15187 displacement is not sufficient and long branches are available, 15188 when the source reads ‘dbXX foo’, ‘as’ emits 15189 dbXX oo1 15190 bras oo2 15191 oo1:bral foo 15192 oo2: 15193 15194 If, however, long branches are not available and the ‘--pcrel’ 15195 option is not given, ‘as’ emits 15196 dbXX oo1 15197 bras oo2 15198 oo1:jmp foo 15199 oo2: 15200 15201‘fjXX’ 15202 This family includes 15203 fjne fjeq fjge fjlt fjgt fjle fjf 15204 fjt fjgl fjgle fjnge fjngl fjngle fjngt 15205 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 15206 fjor fjseq fjsf fjsne fjst fjueq fjuge 15207 fjugt fjule fjult fjun 15208 15209 Each of these pseudo-operations always expands to a single Motorola 15210 coprocessor branch instruction, word or long. All Motorola 15211 coprocessor branch instructions allow both word and long 15212 displacements. 15213 15214 15215File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 15216 152179.23.6.2 Special Characters 15218........................... 15219 15220Line comments are introduced by the ‘|’ character appearing anywhere on 15221a line, unless the ‘--bitwise-or’ command-line option has been 15222specified. 15223 15224 An asterisk (‘*’) as the first character on a line marks the start of 15225a line comment as well. 15226 15227 A hash character (‘#’) as the first character on a line also marks 15228the start of a line comment, but in this case it could also be a logical 15229line number directive (*note Comments::) or a preprocessor control 15230command (*note Preprocessing::). If the hash character appears 15231elsewhere on a line it is used to introduce an immediate value. (This 15232is for compatibility with Sun’s assembler). 15233 15234 Multiple statements on the same line can appear if they are separated 15235by the ‘;’ character. 15236 15237 15238File: as.info, Node: M68HC11-Dependent, Next: S12Z-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 15239 152409.24 M68HC11 and M68HC12 Dependent Features 15241=========================================== 15242 15243* Menu: 15244 15245* M68HC11-Opts:: M68HC11 and M68HC12 Options 15246* M68HC11-Syntax:: Syntax 15247* M68HC11-Modifiers:: Symbolic Operand Modifiers 15248* M68HC11-Directives:: Assembler Directives 15249* M68HC11-Float:: Floating Point 15250* M68HC11-opcodes:: Opcodes 15251 15252 15253File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 15254 152559.24.1 M68HC11 and M68HC12 Options 15256---------------------------------- 15257 15258The Motorola 68HC11 and 68HC12 version of ‘as’ have a few machine 15259dependent options. 15260 15261‘-m68hc11’ 15262 This option switches the assembler into the M68HC11 mode. In this 15263 mode, the assembler only accepts 68HC11 operands and mnemonics. It 15264 produces code for the 68HC11. 15265 15266‘-m68hc12’ 15267 This option switches the assembler into the M68HC12 mode. In this 15268 mode, the assembler also accepts 68HC12 operands and mnemonics. It 15269 produces code for the 68HC12. A few 68HC11 instructions are 15270 replaced by some 68HC12 instructions as recommended by Motorola 15271 specifications. 15272 15273‘-m68hcs12’ 15274 This option switches the assembler into the M68HCS12 mode. This 15275 mode is similar to ‘-m68hc12’ but specifies to assemble for the 15276 68HCS12 series. The only difference is on the assembling of the 15277 ‘movb’ and ‘movw’ instruction when a PC-relative operand is used. 15278 15279‘-mm9s12x’ 15280 This option switches the assembler into the M9S12X mode. This mode 15281 is similar to ‘-m68hc12’ but specifies to assemble for the S12X 15282 series which is a superset of the HCS12. 15283 15284‘-mm9s12xg’ 15285 This option switches the assembler into the XGATE mode for the RISC 15286 co-processor featured on some S12X-family chips. 15287 15288‘--xgate-ramoffset’ 15289 This option instructs the linker to offset RAM addresses from S12X 15290 address space into XGATE address space. 15291 15292‘-mshort’ 15293 This option controls the ABI and indicates to use a 16-bit integer 15294 ABI. It has no effect on the assembled instructions. This is the 15295 default. 15296 15297‘-mlong’ 15298 This option controls the ABI and indicates to use a 32-bit integer 15299 ABI. 15300 15301‘-mshort-double’ 15302 This option controls the ABI and indicates to use a 32-bit float 15303 ABI. This is the default. 15304 15305‘-mlong-double’ 15306 This option controls the ABI and indicates to use a 64-bit float 15307 ABI. 15308 15309‘--strict-direct-mode’ 15310 You can use the ‘--strict-direct-mode’ option to disable the 15311 automatic translation of direct page mode addressing into extended 15312 mode when the instruction does not support direct mode. For 15313 example, the ‘clr’ instruction does not support direct page mode 15314 addressing. When it is used with the direct page mode, ‘as’ will 15315 ignore it and generate an absolute addressing. This option 15316 prevents ‘as’ from doing this, and the wrong usage of the direct 15317 page mode will raise an error. 15318 15319‘--short-branches’ 15320 The ‘--short-branches’ option turns off the translation of relative 15321 branches into absolute branches when the branch offset is out of 15322 range. By default ‘as’ transforms the relative branch (‘bsr’, 15323 ‘bgt’, ‘bge’, ‘beq’, ‘bne’, ‘ble’, ‘blt’, ‘bhi’, ‘bcc’, ‘bls’, 15324 ‘bcs’, ‘bmi’, ‘bvs’, ‘bvs’, ‘bra’) into an absolute branch when the 15325 offset is out of the -128 .. 127 range. In that case, the ‘bsr’ 15326 instruction is translated into a ‘jsr’, the ‘bra’ instruction is 15327 translated into a ‘jmp’ and the conditional branches instructions 15328 are inverted and followed by a ‘jmp’. This option disables these 15329 translations and ‘as’ will generate an error if a relative branch 15330 is out of range. This option does not affect the optimization 15331 associated to the ‘jbra’, ‘jbsr’ and ‘jbXX’ pseudo opcodes. 15332 15333‘--force-long-branches’ 15334 The ‘--force-long-branches’ option forces the translation of 15335 relative branches into absolute branches. This option does not 15336 affect the optimization associated to the ‘jbra’, ‘jbsr’ and ‘jbXX’ 15337 pseudo opcodes. 15338 15339‘--print-insn-syntax’ 15340 You can use the ‘--print-insn-syntax’ option to obtain the syntax 15341 description of the instruction when an error is detected. 15342 15343‘--print-opcodes’ 15344 The ‘--print-opcodes’ option prints the list of all the 15345 instructions with their syntax. The first item of each line 15346 represents the instruction name and the rest of the line indicates 15347 the possible operands for that instruction. The list is printed in 15348 alphabetical order. Once the list is printed ‘as’ exits. 15349 15350‘--generate-example’ 15351 The ‘--generate-example’ option is similar to ‘--print-opcodes’ but 15352 it generates an example for each instruction instead. 15353 15354 15355File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 15356 153579.24.2 Syntax 15358------------- 15359 15360In the M68HC11 syntax, the instruction name comes first and it may be 15361followed by one or several operands (up to three). Operands are 15362separated by comma (‘,’). In the normal mode, ‘as’ will complain if too 15363many operands are specified for a given instruction. In the MRI mode 15364(turned on with ‘-M’ option), it will treat them as comments. Example: 15365 15366 inx 15367 lda #23 15368 bset 2,x #4 15369 brclr *bot #8 foo 15370 15371 The presence of a ‘;’ character or a ‘!’ character anywhere on a line 15372indicates the start of a comment that extends to the end of that line. 15373 15374 A ‘*’ or a ‘#’ character at the start of a line also introduces a 15375line comment, but these characters do not work elsewhere on the line. 15376If the first character of the line is a ‘#’ then as well as starting a 15377comment, the line could also be logical line number directive (*note 15378Comments::) or a preprocessor control command (*note Preprocessing::). 15379 15380 The M68HC11 assembler does not currently support a line separator 15381character. 15382 15383 The following addressing modes are understood for 68HC11 and 68HC12: 15384“Immediate” 15385 ‘#NUMBER’ 15386 15387“Address Register” 15388 ‘NUMBER,X’, ‘NUMBER,Y’ 15389 15390 The NUMBER may be omitted in which case 0 is assumed. 15391 15392“Direct Addressing mode” 15393 ‘*SYMBOL’, or ‘*DIGITS’ 15394 15395“Absolute” 15396 ‘SYMBOL’, or ‘DIGITS’ 15397 15398 The M68HC12 has other more complex addressing modes. All of them are 15399supported and they are represented below: 15400 15401“Constant Offset Indexed Addressing Mode” 15402 ‘NUMBER,REG’ 15403 15404 The NUMBER may be omitted in which case 0 is assumed. The register 15405 can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’. The assembler will use the 15406 smaller post-byte definition according to the constant value (5-bit 15407 constant offset, 9-bit constant offset or 16-bit constant offset). 15408 If the constant is not known by the assembler it will use the 15409 16-bit constant offset post-byte and the value will be resolved at 15410 link time. 15411 15412“Offset Indexed Indirect” 15413 ‘[NUMBER,REG]’ 15414 15415 The register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’. 15416 15417“Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement” 15418 ‘NUMBER,-REG’ ‘NUMBER,+REG’ ‘NUMBER,REG-’ ‘NUMBER,REG+’ 15419 15420 The number must be in the range ‘-8’..‘+8’ and must not be 0. The 15421 register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’. 15422 15423“Accumulator Offset” 15424 ‘ACC,REG’ 15425 15426 The accumulator register can be either ‘A’, ‘B’ or ‘D’. The 15427 register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’. 15428 15429“Accumulator D offset indexed-indirect” 15430 ‘[D,REG]’ 15431 15432 The register can be either ‘X’, ‘Y’, ‘SP’ or ‘PC’. 15433 15434 For example: 15435 15436 ldab 1024,sp 15437 ldd [10,x] 15438 orab 3,+x 15439 stab -2,y- 15440 ldx a,pc 15441 sty [d,sp] 15442 15443 15444File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 15445 154469.24.3 Symbolic Operand Modifiers 15447--------------------------------- 15448 15449The assembler supports several modifiers when using symbol addresses in 1545068HC11 and 68HC12 instruction operands. The general syntax is the 15451following: 15452 15453 %modifier(symbol) 15454 15455‘%addr’ 15456 This modifier indicates to the assembler and linker to use the 15457 16-bit physical address corresponding to the symbol. This is 15458 intended to be used on memory window systems to map a symbol in the 15459 memory bank window. If the symbol is in a memory expansion part, 15460 the physical address corresponds to the symbol address within the 15461 memory bank window. If the symbol is not in a memory expansion 15462 part, this is the symbol address (using or not using the %addr 15463 modifier has no effect in that case). 15464 15465‘%page’ 15466 This modifier indicates to use the memory page number corresponding 15467 to the symbol. If the symbol is in a memory expansion part, its 15468 page number is computed by the linker as a number used to map the 15469 page containing the symbol in the memory bank window. If the 15470 symbol is not in a memory expansion part, the page number is 0. 15471 15472‘%hi’ 15473 This modifier indicates to use the 8-bit high part of the physical 15474 address of the symbol. 15475 15476‘%lo’ 15477 This modifier indicates to use the 8-bit low part of the physical 15478 address of the symbol. 15479 15480 For example a 68HC12 call to a function ‘foo_example’ stored in 15481memory expansion part could be written as follows: 15482 15483 call %addr(foo_example),%page(foo_example) 15484 15485 and this is equivalent to 15486 15487 call foo_example 15488 15489 And for 68HC11 it could be written as follows: 15490 15491 ldab #%page(foo_example) 15492 stab _page_switch 15493 jsr %addr(foo_example) 15494 15495 15496File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 15497 154989.24.4 Assembler Directives 15499--------------------------- 15500 15501The 68HC11 and 68HC12 version of ‘as’ have the following specific 15502assembler directives: 15503 15504‘.relax’ 15505 The relax directive is used by the ‘GNU Compiler’ to emit a 15506 specific relocation to mark a group of instructions for linker 15507 relaxation. The sequence of instructions within the group must be 15508 known to the linker so that relaxation can be performed. 15509 15510‘.mode [mshort|mlong|mshort-double|mlong-double]’ 15511 This directive specifies the ABI. It overrides the ‘-mshort’, 15512 ‘-mlong’, ‘-mshort-double’ and ‘-mlong-double’ options. 15513 15514‘.far SYMBOL’ 15515 This directive marks the symbol as a ‘far’ symbol meaning that it 15516 uses a ‘call/rtc’ calling convention as opposed to ‘jsr/rts’. 15517 During a final link, the linker will identify references to the 15518 ‘far’ symbol and will verify the proper calling convention. 15519 15520‘.interrupt SYMBOL’ 15521 This directive marks the symbol as an interrupt entry point. This 15522 information is then used by the debugger to correctly unwind the 15523 frame across interrupts. 15524 15525‘.xrefb SYMBOL’ 15526 This directive is defined for compatibility with the ‘Specification 15527 for Motorola 8 and 16-Bit Assembly Language Input Standard’ and is 15528 ignored. 15529 15530 15531File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 15532 155339.24.5 Floating Point 15534--------------------- 15535 15536Packed decimal (P) format floating literals are not supported. Feel 15537free to add the code! 15538 15539 The floating point formats generated by directives are these. 15540 15541‘.float’ 15542 ‘Single’ precision floating point constants. 15543 15544‘.double’ 15545 ‘Double’ precision floating point constants. 15546 15547‘.extend’ 15548‘.ldouble’ 15549 ‘Extended’ precision (‘long double’) floating point constants. 15550 15551 15552File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 15553 155549.24.6 Opcodes 15555-------------- 15556 15557* Menu: 15558 15559* M68HC11-Branch:: Branch Improvement 15560 15561 15562File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 15563 155649.24.6.1 Branch Improvement 15565........................... 15566 15567Certain pseudo opcodes are permitted for branch instructions. They 15568expand to the shortest branch instruction that reach the target. 15569Generally these mnemonics are made by prepending ‘j’ to the start of 15570Motorola mnemonic. These pseudo opcodes are not affected by the 15571‘--short-branches’ or ‘--force-long-branches’ options. 15572 15573 The following table summarizes the pseudo-operations. 15574 15575 Displacement Width 15576 +-------------------------------------------------------------+ 15577 | Options | 15578 | --short-branches --force-long-branches | 15579 +--------------------------+----------------------------------+ 15580 Op |BYTE WORD | BYTE WORD | 15581 +--------------------------+----------------------------------+ 15582 bsr | bsr <pc-rel> <error> | jsr <abs> | 15583 bra | bra <pc-rel> <error> | jmp <abs> | 15584 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 15585 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 15586 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 15587 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 15588 | jmp <abs> | | 15589 +--------------------------+----------------------------------+ 15590 XX: condition 15591 NX: negative of condition XX 15592 15593 15594‘jbsr’ 15595‘jbra’ 15596 These are the simplest jump pseudo-operations; they always map to 15597 one particular machine instruction, depending on the displacement 15598 to the branch target. 15599 15600‘jbXX’ 15601 Here, ‘jbXX’ stands for an entire family of pseudo-operations, 15602 where XX is a conditional branch or condition-code test. The full 15603 list of pseudo-ops in this family is: 15604 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 15605 jbcs jbne jblt jble jbls jbvc jbmi 15606 15607 For the cases of non-PC relative displacements and long 15608 displacements, ‘as’ issues a longer code fragment in terms of NX, 15609 the opposite condition to XX. For example, for the non-PC relative 15610 case: 15611 jbXX foo 15612 gives 15613 bNXs oof 15614 jmp foo 15615 oof: 15616 15617 15618File: as.info, Node: S12Z-Dependent, Next: Meta-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 15619 156209.25 S12Z Dependent Features 15621============================ 15622 15623The Freescale S12Z version of ‘as’ has a few machine dependent features. 15624 15625* Menu: 15626 15627* S12Z Options:: S12Z Options 15628* S12Z Syntax:: Syntax 15629 15630 15631File: as.info, Node: S12Z Options, Next: S12Z Syntax, Up: S12Z-Dependent 15632 156339.25.1 S12Z Options 15634------------------- 15635 15636The S12Z version of ‘as’ recognizes the following options: 15637 15638‘-mreg-prefix=PREFIX’ 15639 You can use the ‘-mreg-prefix=PFX’ option to indicate that the 15640 assembler should expect all register names to be prefixed with the 15641 string PFX. 15642 15643 For an explanation of what this means and why it might be needed, 15644 see *note S12Z Register Notation::. 15645 15646‘-mdollar-hex’ 15647 The ‘-mdollar-hex’ option affects the way that literal hexadecimal 15648 constants are represented. When this option is specified, the 15649 assembler will consider the ‘$’ character as the start of a 15650 hexadecimal integer constant. Without this option, the standard 15651 value of ‘0x’ is expected. 15652 15653 If you use this option, then you cannot have symbol names starting 15654 with ‘$’. ‘-mdollar-hex’ is implied if the ‘--traditional-format’ 15655 (*note traditional-format::) is used. 15656 15657 15658File: as.info, Node: S12Z Syntax, Prev: S12Z Options, Up: S12Z-Dependent 15659 156609.25.2 Syntax 15661------------- 15662 15663* Menu: 15664 15665* S12Z Syntax Overview:: General description 15666* S12Z Addressing Modes:: Operands and their semantics 15667* S12Z Register Notation:: How to refer to registers 15668 15669 15670File: as.info, Node: S12Z Syntax Overview, Next: S12Z Addressing Modes, Up: S12Z Syntax 15671 156729.25.2.1 Overview 15673................. 15674 15675In the S12Z syntax, the instruction name comes first and it may be 15676followed by one, or by several operands. In most cases the maximum 15677number of operands is three. Operands are separated by a comma (‘,’). 15678A comma however does not act as a separator if it appears within 15679parentheses (‘()’) or within square brackets (‘[]’). ‘as’ will complain 15680if too many, too few or inappropriate operands are specified for a given 15681instruction. 15682 15683 Some instructions accept and (in certain situations require) a suffix 15684indicating the size of the operand. The suffix is separated from the 15685instruction name by a period (‘.’) and may be one of ‘b’, ‘w’, ‘p’ or 15686‘l’ indicating ‘byte’ (a single byte), ‘word’ (2 bytes), ‘pointer’ (3 15687bytes) or ‘long’ (4 bytes) respectively. 15688 15689 Example: 15690 15691 bset.b 0xA98, #5 15692 mov.b #6, 0x2409 15693 ld d0, #4 15694 mov.l (d0, x), 0x2409 15695 inc d0 15696 cmp d0, #12 15697 blt *-4 15698 lea x, 0x2409 15699 st y, (1, x) 15700 15701 The presence of a ‘;’ character anywhere on a line indicates the 15702start of a comment that extends to the end of that line. 15703 15704 A ‘*’ or a ‘#’ character at the start of a line also introduces a 15705line comment, but these characters do not work elsewhere on the line. 15706If the first character of the line is a ‘#’ then as well as starting a 15707comment, the line could also be logical line number directive (*note 15708Comments::) or a preprocessor control command (*note Preprocessing::). 15709 15710 The S12Z assembler does not currently support a line separator 15711character. 15712 15713 15714File: as.info, Node: S12Z Addressing Modes, Next: S12Z Register Notation, Prev: S12Z Syntax Overview, Up: S12Z Syntax 15715 157169.25.2.2 Addressing Modes 15717......................... 15718 15719The following addressing modes are understood for the S12Z. 15720“Immediate” 15721 ‘#NUMBER’ 15722 15723“Immediate Bit Field” 15724 ‘#WIDTH:OFFSET’ 15725 15726 Bit field instructions in the immediate mode require the width and 15727 offset to be specified. The WIDTH parameter specifies the number 15728 of bits in the field. It should be a number in the range [1,32]. 15729 OFFSET determines the position within the field where the operation 15730 should start. It should be a number in the range [0,31]. 15731 15732“Relative” 15733 ‘*SYMBOL’, or ‘*[+-]DIGITS’ 15734 15735 Program counter relative addresses have a width of 15 bits. Thus, 15736 they must be within the range [-32768, 32767]. 15737 15738“Register” 15739 ‘REG’ 15740 15741 Some instructions accept a register as an operand. In general, REG 15742 may be a data register (‘D0’, ‘D1’ ... ‘D7’), the ‘X’ register or 15743 the ‘Y’ register. 15744 15745 A few instructions accept as an argument the stack pointer register 15746 (‘S’), and/or the program counter (‘P’). 15747 15748 Some very special instructions accept arguments which refer to the 15749 condition code register. For these arguments the syntax is ‘CCR’, 15750 ‘CCH’ or ‘CCL’ which refer to the complete condition code register, 15751 the condition code register high byte and the condition code 15752 register low byte respectively. 15753 15754“Absolute Direct” 15755 ‘SYMBOL’, or ‘DIGITS’ 15756 15757“Absolute Indirect” 15758 ‘[SYMBOL’, or ‘DIGITS]’ 15759 15760“Constant Offset Indexed” 15761 ‘(NUMBER,REG)’ 15762 15763 REG may be either ‘X’, ‘Y’, ‘S’ or ‘P’ or one of the data registers 15764 ‘D0’, ‘D1’ ... ‘D7’. If any of the registers ‘D2’ ... ‘D5’ are 15765 specified, then the register value is treated as a signed value. 15766 Otherwise it is treated as unsigned. NUMBER may be any integer in 15767 the range [-8388608,8388607]. 15768 15769“Offset Indexed Indirect” 15770 ‘[NUMBER,REG]’ 15771 15772 REG may be either ‘X’, ‘Y’, ‘S’ or ‘P’. NUMBER may be any integer 15773 in the range [-8388608,8388607]. 15774 15775“Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement” 15776 ‘-REG’, ‘+REG’, ‘REG-’ or ‘REG+’ 15777 15778 This addressing mode is typically used to access a value at an 15779 address, and simultaneously to increment/decrement the register 15780 pointing to that address. Thus REG may be any of the 24 bit 15781 registers ‘X’, ‘Y’, or ‘S’. Pre-increment and post-decrement are 15782 not available for register ‘S’ (only post-increment and 15783 pre-decrement are available). 15784 15785“Register Offset Direct” 15786 ‘(DATA-REG,REG)’ 15787 15788 REG can be either ‘X’, ‘Y’, or ‘S’. DATA-REG must be one of the 15789 data registers ‘D0’, ‘D1’ ... ‘D7’. If any of the registers ‘D2’ 15790 ... ‘D5’ are specified, then the register value is treated as a 15791 signed value. Otherwise it is treated as unsigned. 15792 15793“Register Offset Indirect” 15794 ‘[DATA-REG,REG]’ 15795 15796 REG can be either ‘X’ or ‘Y’. DATA-REG must be one of the data 15797 registers ‘D0’, ‘D1’ ... ‘D7’. If any of the registers ‘D2’ ... 15798 ‘D5’ are specified, then the register value is treated as a signed 15799 value. Otherwise it is treated as unsigned. 15800 15801 For example: 15802 15803 trap #197 ;; Immediate mode 15804 bra *+49 ;; Relative mode 15805 bra .L0 ;; ditto 15806 jmp 0xFE0034 ;; Absolute direct mode 15807 jmp [0xFD0012] ;; Absolute indirect mode 15808 inc.b (4,x) ;; Constant offset indexed mode 15809 jsr (45, d0) ;; ditto 15810 dec.w [4,y] ;; Constant offset indexed indirect mode 15811 clr.p (-s) ;; Pre-decrement mode 15812 neg.l (d0, s) ;; Register offset direct mode 15813 com.b [d1, x] ;; Register offset indirect mode 15814 psh cch ;; Register mode 15815 15816 15817File: as.info, Node: S12Z Register Notation, Prev: S12Z Addressing Modes, Up: S12Z Syntax 15818 158199.25.2.3 Register Notation 15820.......................... 15821 15822Without a register prefix (*note S12Z Options::), S12Z assembler code is 15823expected in the traditional format like this: 15824 lea s, (-2,s) 15825 st d2, (0,s) 15826 ld x, symbol 15827 tfr d2, d6 15828 cmp d6, #1532 15829 15830However, if ‘as’ is started with (for example) ‘-mreg-prefix=%’ then all 15831register names must be prefixed with ‘%’ as follows: 15832 lea %s, (-2,%s) 15833 st %d2, (0,%s) 15834 ld %x, symbol 15835 tfr %d2, %d6 15836 cmp %d6, #1532 15837 15838 The register prefix feature is intended to be used by compilers to 15839avoid ambiguity between symbols and register names. Consider the 15840following assembler instruction: 15841 st d0, d1 15842The destination operand of this instruction could either refer to the 15843register ‘D1’, or it could refer to the symbol named “d1”. If the 15844latter is intended then ‘as’ must be invoked with ‘-mreg-prefix=PFX’ and 15845the code written as 15846 st PFXd0, d1 15847where PFX is the chosen register prefix. For this reason, compiler 15848back-ends should choose a register prefix which cannot be confused with 15849a symbol name. 15850 15851 15852File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: S12Z-Dependent, Up: Machine Dependencies 15853 158549.26 Meta Dependent Features 15855============================ 15856 15857* Menu: 15858 15859* Meta Options:: Options 15860* Meta Syntax:: Meta Assembler Syntax 15861 15862 15863File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent 15864 158659.26.1 Options 15866-------------- 15867 15868The Imagination Technologies Meta architecture is implemented in a 15869number of versions, with each new version adding new features such as 15870instructions and registers. For precise details of what instructions 15871each core supports, please see the chip’s technical reference manual. 15872 15873 The following table lists all available Meta options. 15874 15875‘-mcpu=metac11’ 15876 Generate code for Meta 1.1. 15877 15878‘-mcpu=metac12’ 15879 Generate code for Meta 1.2. 15880 15881‘-mcpu=metac21’ 15882 Generate code for Meta 2.1. 15883 15884‘-mfpu=metac21’ 15885 Allow code to use FPU hardware of Meta 2.1. 15886 15887 15888File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent 15889 158909.26.2 Syntax 15891------------- 15892 15893* Menu: 15894 15895* Meta-Chars:: Special Characters 15896* Meta-Regs:: Register Names 15897 15898 15899File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax 15900 159019.26.2.1 Special Characters 15902........................... 15903 15904‘!’ is the line comment character. 15905 15906 You can use ‘;’ instead of a newline to separate statements. 15907 15908 Since ‘$’ has no special meaning, you may use it in symbol names. 15909 15910 15911File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax 15912 159139.26.2.2 Register Names 15914....................... 15915 15916Registers can be specified either using their mnemonic names, such as 15917‘D0Re0’, or using the unit plus register number separated by a ‘.’, such 15918as ‘D0.0’. 15919 15920 15921File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies 15922 159239.27 MicroBlaze Dependent Features 15924================================== 15925 15926The Xilinx MicroBlaze processor family includes several variants, all 15927using the same core instruction set. This chapter covers features of 15928the GNU assembler that are specific to the MicroBlaze architecture. For 15929details about the MicroBlaze instruction set, please see the ‘MicroBlaze 15930Processor Reference Guide (UG081)’ available at www.xilinx.com. 15931 15932* Menu: 15933 15934* MicroBlaze Directives:: Directives for MicroBlaze Processors. 15935* MicroBlaze Syntax:: Syntax for the MicroBlaze 15936* MicroBlaze Options:: Options for MicroBlaze Processors. 15937 15938 15939File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent 15940 159419.27.1 Directives 15942----------------- 15943 15944A number of assembler directives are available for MicroBlaze. 15945 15946‘.data8 EXPRESSION,...’ 15947 This directive is an alias for ‘.byte’. Each expression is 15948 assembled into an eight-bit value. 15949 15950‘.data16 EXPRESSION,...’ 15951 This directive is an alias for ‘.hword’. Each expression is 15952 assembled into an 16-bit value. 15953 15954‘.data32 EXPRESSION,...’ 15955 This directive is an alias for ‘.word’. Each expression is 15956 assembled into an 32-bit value. 15957 15958‘.ent NAME[,LABEL]’ 15959 This directive is an alias for ‘.func’ denoting the start of 15960 function NAME at (optional) LABEL. 15961 15962‘.end NAME[,LABEL]’ 15963 This directive is an alias for ‘.endfunc’ denoting the end of 15964 function NAME. 15965 15966‘.gpword LABEL,...’ 15967 This directive is an alias for ‘.rva’. The resolved address of 15968 LABEL is stored in the data section. 15969 15970‘.weakext LABEL’ 15971 Declare that LABEL is a weak external symbol. 15972 15973‘.rodata’ 15974 Switch to .rodata section. Equivalent to ‘.section .rodata’ 15975 15976‘.sdata2’ 15977 Switch to .sdata2 section. Equivalent to ‘.section .sdata2’ 15978 15979‘.sdata’ 15980 Switch to .sdata section. Equivalent to ‘.section .sdata’ 15981 15982‘.bss’ 15983 Switch to .bss section. Equivalent to ‘.section .bss’ 15984 15985‘.sbss’ 15986 Switch to .sbss section. Equivalent to ‘.section .sbss’ 15987 15988 15989File: as.info, Node: MicroBlaze Syntax, Next: MicroBlaze Options, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent 15990 159919.27.2 Syntax for the MicroBlaze 15992-------------------------------- 15993 15994* Menu: 15995 15996* MicroBlaze-Chars:: Special Characters 15997 15998 15999File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 16000 160019.27.2.1 Special Characters 16002........................... 16003 16004The presence of a ‘#’ on a line indicates the start of a comment that 16005extends to the end of the current line. 16006 16007 If a ‘#’ appears as the first character of a line, the whole line is 16008treated as a comment, but in this case the line can also be a logical 16009line number directive (*note Comments::) or a preprocessor control 16010command (*note Preprocessing::). 16011 16012 The ‘;’ character can be used to separate statements on the same 16013line. 16014 16015 16016File: as.info, Node: MicroBlaze Options, Prev: MicroBlaze Syntax, Up: MicroBlaze-Dependent 16017 160189.27.3 Options 16019-------------- 16020 16021MicroBlaze processors support the following options: 16022 16023‘-mbig-endian’ 16024 Build for MicroBlaze in Big Endian configuration. 16025 16026‘-mlittle-endian’ 16027 Build for MicroBlaze in Little Endian configuration. 16028 16029 16030File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 16031 160329.28 MIPS Dependent Features 16033============================ 16034 16035GNU ‘as’ for MIPS architectures supports several different MIPS 16036processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 16037information about the MIPS instruction set, see ‘MIPS RISC 16038Architecture’, by Kane and Heindrich (Prentice-Hall). For an overview 16039of MIPS assembly conventions, see “Appendix D: Assembly Language 16040Programming” in the same work. 16041 16042* Menu: 16043 16044* MIPS Options:: Assembler options 16045* MIPS Macros:: High-level assembly macros 16046* MIPS Symbol Sizes:: Directives to override the size of symbols 16047* MIPS Small Data:: Controlling the use of small data accesses 16048* MIPS ISA:: Directives to override the ISA level 16049* MIPS assembly options:: Directives to control code generation 16050* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 16051* MIPS insn:: Directive to mark data as an instruction 16052* MIPS FP ABIs:: Marking which FP ABI is in use 16053* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 16054* MIPS Option Stack:: Directives to save and restore options 16055* MIPS ASE Instruction Generation Overrides:: Directives to control 16056 generation of MIPS ASE instructions 16057* MIPS Floating-Point:: Directives to override floating-point options 16058* MIPS Syntax:: MIPS specific syntactical considerations 16059 16060 16061File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent 16062 160639.28.1 Assembler options 16064------------------------ 16065 16066The MIPS configurations of GNU ‘as’ support these special options: 16067 16068‘-G NUM’ 16069 Set the “small data” limit to N bytes. The default limit is 8 16070 bytes. *Note Controlling the use of small data accesses: MIPS 16071 Small Data. 16072 16073‘-EB’ 16074‘-EL’ 16075 Any MIPS configuration of ‘as’ can select big-endian or 16076 little-endian output at run time (unlike the other GNU development 16077 tools, which must be configured for one or the other). Use ‘-EB’ 16078 to select big-endian output, and ‘-EL’ for little-endian. 16079 16080‘-KPIC’ 16081 Generate SVR4-style PIC. This option tells the assembler to 16082 generate SVR4-style position-independent macro expansions. It also 16083 tells the assembler to mark the output file as PIC. 16084 16085‘-mvxworks-pic’ 16086 Generate VxWorks PIC. This option tells the assembler to generate 16087 VxWorks-style position-independent macro expansions. 16088 16089‘-mips1’ 16090‘-mips2’ 16091‘-mips3’ 16092‘-mips4’ 16093‘-mips5’ 16094‘-mips32’ 16095‘-mips32r2’ 16096‘-mips32r3’ 16097‘-mips32r5’ 16098‘-mips32r6’ 16099‘-mips64’ 16100‘-mips64r2’ 16101‘-mips64r3’ 16102‘-mips64r5’ 16103‘-mips64r6’ 16104 Generate code for a particular MIPS Instruction Set Architecture 16105 level. ‘-mips1’ corresponds to the R2000 and R3000 processors, 16106 ‘-mips2’ to the R6000 processor, ‘-mips3’ to the R4000 processor, 16107 and ‘-mips4’ to the R8000 and R10000 processors. ‘-mips5’, 16108 ‘-mips32’, ‘-mips32r2’, ‘-mips32r3’, ‘-mips32r5’, ‘-mips32r6’, 16109 ‘-mips64’, ‘-mips64r2’, ‘-mips64r3’, ‘-mips64r5’, and ‘-mips64r6’ 16110 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 16111 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 16112 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 16113 ISA processors, respectively. You can also switch instruction sets 16114 during the assembly; see *note Directives to override the ISA 16115 level: MIPS ISA. 16116 16117‘-mgp32’ 16118‘-mfp32’ 16119 Some macros have different expansions for 32-bit and 64-bit 16120 registers. The register sizes are normally inferred from the ISA 16121 and ABI, but these flags force a certain group of registers to be 16122 treated as 32 bits wide at all times. ‘-mgp32’ controls the size 16123 of general-purpose registers and ‘-mfp32’ controls the size of 16124 floating-point registers. 16125 16126 The ‘.set gp=32’ and ‘.set fp=32’ directives allow the size of 16127 registers to be changed for parts of an object. The default value 16128 is restored by ‘.set gp=default’ and ‘.set fp=default’. 16129 16130 On some MIPS variants there is a 32-bit mode flag; when this flag 16131 is set, 64-bit instructions generate a trap. Also, some 32-bit 16132 OSes only save the 32-bit registers on a context switch, so it is 16133 essential never to use the 64-bit registers. 16134 16135‘-mgp64’ 16136‘-mfp64’ 16137 Assume that 64-bit registers are available. This is provided in 16138 the interests of symmetry with ‘-mgp32’ and ‘-mfp32’. 16139 16140 The ‘.set gp=64’ and ‘.set fp=64’ directives allow the size of 16141 registers to be changed for parts of an object. The default value 16142 is restored by ‘.set gp=default’ and ‘.set fp=default’. 16143 16144‘-mfpxx’ 16145 Make no assumptions about whether 32-bit or 64-bit floating-point 16146 registers are available. This is provided to support having 16147 modules compatible with either ‘-mfp32’ or ‘-mfp64’. This option 16148 can only be used with MIPS II and above. 16149 16150 The ‘.set fp=xx’ directive allows a part of an object to be marked 16151 as not making assumptions about 32-bit or 64-bit FP registers. The 16152 default value is restored by ‘.set fp=default’. 16153 16154‘-modd-spreg’ 16155‘-mno-odd-spreg’ 16156 Enable use of floating-point operations on odd-numbered 16157 single-precision registers when supported by the ISA. ‘-mfpxx’ 16158 implies ‘-mno-odd-spreg’, otherwise the default is ‘-modd-spreg’ 16159 16160‘-mips16’ 16161‘-no-mips16’ 16162 Generate code for the MIPS 16 processor. This is equivalent to 16163 putting ‘.module mips16’ at the start of the assembly file. 16164 ‘-no-mips16’ turns off this option. 16165 16166‘-mmips16e2’ 16167‘-mno-mips16e2’ 16168 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is 16169 equivalent to putting ‘.module mips16e2’ at the start of the 16170 assembly file. ‘-mno-mips16e2’ turns off this option. 16171 16172‘-mmicromips’ 16173‘-mno-micromips’ 16174 Generate code for the microMIPS processor. This is equivalent to 16175 putting ‘.module micromips’ at the start of the assembly file. 16176 ‘-mno-micromips’ turns off this option. This is equivalent to 16177 putting ‘.module nomicromips’ at the start of the assembly file. 16178 16179‘-msmartmips’ 16180‘-mno-smartmips’ 16181 Enables the SmartMIPS extensions to the MIPS32 instruction set, 16182 which provides a number of new instructions which target smartcard 16183 and cryptographic applications. This is equivalent to putting 16184 ‘.module smartmips’ at the start of the assembly file. 16185 ‘-mno-smartmips’ turns off this option. 16186 16187‘-mips3d’ 16188‘-no-mips3d’ 16189 Generate code for the MIPS-3D Application Specific Extension. This 16190 tells the assembler to accept MIPS-3D instructions. ‘-no-mips3d’ 16191 turns off this option. 16192 16193‘-mdmx’ 16194‘-no-mdmx’ 16195 Generate code for the MDMX Application Specific Extension. This 16196 tells the assembler to accept MDMX instructions. ‘-no-mdmx’ turns 16197 off this option. 16198 16199‘-mdsp’ 16200‘-mno-dsp’ 16201 Generate code for the DSP Release 1 Application Specific Extension. 16202 This tells the assembler to accept DSP Release 1 instructions. 16203 ‘-mno-dsp’ turns off this option. 16204 16205‘-mdspr2’ 16206‘-mno-dspr2’ 16207 Generate code for the DSP Release 2 Application Specific Extension. 16208 This option implies ‘-mdsp’. This tells the assembler to accept 16209 DSP Release 2 instructions. ‘-mno-dspr2’ turns off this option. 16210 16211‘-mdspr3’ 16212‘-mno-dspr3’ 16213 Generate code for the DSP Release 3 Application Specific Extension. 16214 This option implies ‘-mdsp’ and ‘-mdspr2’. This tells the 16215 assembler to accept DSP Release 3 instructions. ‘-mno-dspr3’ turns 16216 off this option. 16217 16218‘-mmt’ 16219‘-mno-mt’ 16220 Generate code for the MT Application Specific Extension. This 16221 tells the assembler to accept MT instructions. ‘-mno-mt’ turns off 16222 this option. 16223 16224‘-mmcu’ 16225‘-mno-mcu’ 16226 Generate code for the MCU Application Specific Extension. This 16227 tells the assembler to accept MCU instructions. ‘-mno-mcu’ turns 16228 off this option. 16229 16230‘-mmsa’ 16231‘-mno-msa’ 16232 Generate code for the MIPS SIMD Architecture Extension. This tells 16233 the assembler to accept MSA instructions. ‘-mno-msa’ turns off 16234 this option. 16235 16236‘-mxpa’ 16237‘-mno-xpa’ 16238 Generate code for the MIPS eXtended Physical Address (XPA) 16239 Extension. This tells the assembler to accept XPA instructions. 16240 ‘-mno-xpa’ turns off this option. 16241 16242‘-mvirt’ 16243‘-mno-virt’ 16244 Generate code for the Virtualization Application Specific 16245 Extension. This tells the assembler to accept Virtualization 16246 instructions. ‘-mno-virt’ turns off this option. 16247 16248‘-mcrc’ 16249‘-mno-crc’ 16250 Generate code for the cyclic redundancy check (CRC) Application 16251 Specific Extension. This tells the assembler to accept CRC 16252 instructions. ‘-mno-crc’ turns off this option. 16253 16254‘-mginv’ 16255‘-mno-ginv’ 16256 Generate code for the Global INValidate (GINV) Application Specific 16257 Extension. This tells the assembler to accept GINV instructions. 16258 ‘-mno-ginv’ turns off this option. 16259 16260‘-mloongson-mmi’ 16261‘-mno-loongson-mmi’ 16262 Generate code for the Loongson MultiMedia extensions Instructions 16263 (MMI) Application Specific Extension. This tells the assembler to 16264 accept MMI instructions. ‘-mno-loongson-mmi’ turns off this 16265 option. 16266 16267‘-mloongson-cam’ 16268‘-mno-loongson-cam’ 16269 Generate code for the Loongson Content Address Memory (CAM) 16270 Application Specific Extension. This tells the assembler to accept 16271 CAM instructions. ‘-mno-loongson-cam’ turns off this option. 16272 16273‘-mloongson-ext’ 16274‘-mno-loongson-ext’ 16275 Generate code for the Loongson EXTensions (EXT) instructions 16276 Application Specific Extension. This tells the assembler to accept 16277 EXT instructions. ‘-mno-loongson-ext’ turns off this option. 16278 16279‘-mloongson-ext2’ 16280‘-mno-loongson-ext2’ 16281 Generate code for the Loongson EXTensions R2 (EXT2) instructions 16282 Application Specific Extension. This tells the assembler to accept 16283 EXT2 instructions. ‘-mno-loongson-ext2’ turns off this option. 16284 16285‘-minsn32’ 16286‘-mno-insn32’ 16287 Only use 32-bit instruction encodings when generating code for the 16288 microMIPS processor. This option inhibits the use of any 16-bit 16289 instructions. This is equivalent to putting ‘.set insn32’ at the 16290 start of the assembly file. ‘-mno-insn32’ turns off this option. 16291 This is equivalent to putting ‘.set noinsn32’ at the start of the 16292 assembly file. By default ‘-mno-insn32’ is selected, allowing all 16293 instructions to be used. 16294 16295‘-mfix7000’ 16296‘-mno-fix7000’ 16297 Cause nops to be inserted if the read of the destination register 16298 of an mfhi or mflo instruction occurs in the following two 16299 instructions. 16300 16301‘-mfix-rm7000’ 16302‘-mno-fix-rm7000’ 16303 Cause nops to be inserted if a dmult or dmultu instruction is 16304 followed by a load instruction. 16305 16306‘-mfix-loongson2f-jump’ 16307‘-mno-fix-loongson2f-jump’ 16308 Eliminate instruction fetch from outside 256M region to work around 16309 the Loongson2F ‘jump’ instructions. Without it, under extreme 16310 cases, the kernel may crash. The issue has been solved in latest 16311 processor batches, but this fix has no side effect to them. 16312 16313‘-mfix-loongson2f-nop’ 16314‘-mno-fix-loongson2f-nop’ 16315 Replace nops by ‘or at,at,zero’ to work around the Loongson2F ‘nop’ 16316 errata. Without it, under extreme cases, the CPU might deadlock. 16317 The issue has been solved in later Loongson2F batches, but this fix 16318 has no side effect to them. 16319 16320‘-mfix-loongson3-llsc’ 16321‘-mno-fix-loongson3-llsc’ 16322 Insert ‘sync’ before ‘ll’ and ‘lld’ to work around Loongson3 LLSC 16323 errata. Without it, under extrame cases, the CPU might deadlock. 16324 The default can be controlled by the 16325 ‘--enable-mips-fix-loongson3-llsc=[yes|no]’ configure option. 16326 16327‘-mfix-vr4120’ 16328‘-mno-fix-vr4120’ 16329 Insert nops to work around certain VR4120 errata. This option is 16330 intended to be used on GCC-generated code: it is not designed to 16331 catch all problems in hand-written assembler code. 16332 16333‘-mfix-vr4130’ 16334‘-mno-fix-vr4130’ 16335 Insert nops to work around the VR4130 ‘mflo’/‘mfhi’ errata. 16336 16337‘-mfix-24k’ 16338‘-mno-fix-24k’ 16339 Insert nops to work around the 24K ‘eret’/‘deret’ errata. 16340 16341‘-mfix-cn63xxp1’ 16342‘-mno-fix-cn63xxp1’ 16343 Replace ‘pref’ hints 0 - 4 and 6 - 24 with hint 28 to work around 16344 certain CN63XXP1 errata. 16345 16346‘-mfix-r5900’ 16347‘-mno-fix-r5900’ 16348 Do not attempt to schedule the preceding instruction into the delay 16349 slot of a branch instruction placed at the end of a short loop of 16350 six instructions or fewer and always schedule a ‘nop’ instruction 16351 there instead. The short loop bug under certain conditions causes 16352 loops to execute only once or twice, due to a hardware bug in the 16353 R5900 chip. 16354 16355‘-m4010’ 16356‘-no-m4010’ 16357 Generate code for the LSI R4010 chip. This tells the assembler to 16358 accept the R4010-specific instructions (‘addciu’, ‘ffc’, etc.), and 16359 to not schedule ‘nop’ instructions around accesses to the ‘HI’ and 16360 ‘LO’ registers. ‘-no-m4010’ turns off this option. 16361 16362‘-m4650’ 16363‘-no-m4650’ 16364 Generate code for the MIPS R4650 chip. This tells the assembler to 16365 accept the ‘mad’ and ‘madu’ instruction, and to not schedule ‘nop’ 16366 instructions around accesses to the ‘HI’ and ‘LO’ registers. 16367 ‘-no-m4650’ turns off this option. 16368 16369‘-m3900’ 16370‘-no-m3900’ 16371‘-m4100’ 16372‘-no-m4100’ 16373 For each option ‘-mNNNN’, generate code for the MIPS RNNNN chip. 16374 This tells the assembler to accept instructions specific to that 16375 chip, and to schedule for that chip’s hazards. 16376 16377‘-march=CPU’ 16378 Generate code for a particular MIPS CPU. It is exactly equivalent 16379 to ‘-mCPU’, except that there are more value of CPU understood. 16380 Valid CPU value are: 16381 16382 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 16383 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 16384 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 16385 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 16386 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 16387 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 16388 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 16389 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 16390 interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf, 16391 20kc, 25kf, sb1, sb1a, i6400, i6500, p6600, loongson2e, 16392 loongson2f, gs464, gs464e, gs264e, octeon, octeon+, octeon2, 16393 octeon3, xlr, xlp 16394 16395 For compatibility reasons, ‘Nx’ and ‘Bfx’ are accepted as synonyms 16396 for ‘Nf1_1’. These values are deprecated. 16397 16398 In addition the special name ‘from-abi’ can be used, in which case 16399 the assembler will select an architecture suitable for whichever 16400 ABI has been selected, either via the ‘-mabi=’ command line option 16401 or the built in default. 16402 16403‘-mtune=CPU’ 16404 Schedule and tune for a particular MIPS CPU. Valid CPU values are 16405 identical to ‘-march=CPU’. 16406 16407‘-mabi=ABI’ 16408 Record which ABI the source code uses. The recognized arguments 16409 are: ‘32’, ‘n32’, ‘o64’, ‘64’ and ‘eabi’. 16410 16411‘-msym32’ 16412‘-mno-sym32’ 16413 Equivalent to adding ‘.set sym32’ or ‘.set nosym32’ to the 16414 beginning of the assembler input. *Note MIPS Symbol Sizes::. 16415 16416‘-nocpp’ 16417 This option is ignored. It is accepted for command-line 16418 compatibility with other assemblers, which use it to turn off C 16419 style preprocessing. With GNU ‘as’, there is no need for ‘-nocpp’, 16420 because the GNU assembler itself never runs the C preprocessor. 16421 16422‘-msoft-float’ 16423‘-mhard-float’ 16424 Disable or enable floating-point instructions. Note that by 16425 default floating-point instructions are always allowed even with 16426 CPU targets that don’t have support for these instructions. 16427 16428‘-msingle-float’ 16429‘-mdouble-float’ 16430 Disable or enable double-precision floating-point operations. Note 16431 that by default double-precision floating-point operations are 16432 always allowed even with CPU targets that don’t have support for 16433 these operations. 16434 16435‘--construct-floats’ 16436‘--no-construct-floats’ 16437 The ‘--no-construct-floats’ option disables the construction of 16438 double width floating point constants by loading the two halves of 16439 the value into the two single width floating point registers that 16440 make up the double width register. This feature is useful if the 16441 processor support the FR bit in its status register, and this bit 16442 is known (by the programmer) to be set. This bit prevents the 16443 aliasing of the double width register by the single width 16444 registers. 16445 16446 By default ‘--construct-floats’ is selected, allowing construction 16447 of these floating point constants. 16448 16449‘--relax-branch’ 16450‘--no-relax-branch’ 16451 The ‘--relax-branch’ option enables the relaxation of out-of-range 16452 branches. Any branches whose target cannot be reached directly are 16453 converted to a small instruction sequence including an 16454 inverse-condition branch to the physically next instruction, and a 16455 jump to the original target is inserted between the two 16456 instructions. In PIC code the jump will involve further 16457 instructions for address calculation. 16458 16459 The ‘BC1ANY2F’, ‘BC1ANY2T’, ‘BC1ANY4F’, ‘BC1ANY4T’, ‘BPOSGE32’ and 16460 ‘BPOSGE64’ instructions are excluded from relaxation, because they 16461 have no complementing counterparts. They could be relaxed with the 16462 use of a longer sequence involving another branch, however this has 16463 not been implemented and if their target turns out of reach, they 16464 produce an error even if branch relaxation is enabled. 16465 16466 Also no MIPS16 branches are ever relaxed. 16467 16468 By default ‘--no-relax-branch’ is selected, causing any 16469 out-of-range branches to produce an error. 16470 16471‘-mignore-branch-isa’ 16472‘-mno-ignore-branch-isa’ 16473 Ignore branch checks for invalid transitions between ISA modes. 16474 16475 The semantics of branches does not provide for an ISA mode switch, 16476 so in most cases the ISA mode a branch has been encoded for has to 16477 be the same as the ISA mode of the branch’s target label. If the 16478 ISA modes do not match, then such a branch, if taken, will cause 16479 the ISA mode to remain unchanged and instructions that follow will 16480 be executed in the wrong ISA mode causing the program to misbehave 16481 or crash. 16482 16483 In the case of the ‘BAL’ instruction it may be possible to relax it 16484 to an equivalent ‘JALX’ instruction so that the ISA mode is 16485 switched at the run time as required. For other branches no 16486 relaxation is possible and therefore GAS has checks implemented 16487 that verify in branch assembly that the two ISA modes match, and 16488 report an error otherwise so that the problem with code can be 16489 diagnosed at the assembly time rather than at the run time. 16490 16491 However some assembly code, including generated code produced by 16492 some versions of GCC, may incorrectly include branches to data 16493 labels, which appear to require a mode switch but are either dead 16494 or immediately followed by valid instructions encoded for the same 16495 ISA the branch has been encoded for. While not strictly correct at 16496 the source level such code will execute as intended, so to help 16497 with these cases ‘-mignore-branch-isa’ is supported which disables 16498 ISA mode checks for branches. 16499 16500 By default ‘-mno-ignore-branch-isa’ is selected, causing any 16501 invalid branch requiring a transition between ISA modes to produce 16502 an error. 16503 16504‘-mnan=ENCODING’ 16505 This option indicates whether the source code uses the IEEE 2008 16506 NaN encoding (‘-mnan=2008’) or the original MIPS encoding 16507 (‘-mnan=legacy’). It is equivalent to adding a ‘.nan’ directive to 16508 the beginning of the source file. *Note MIPS NaN Encodings::. 16509 16510 ‘-mnan=legacy’ is the default if no ‘-mnan’ option or ‘.nan’ 16511 directive is used. 16512 16513‘--trap’ 16514‘--no-break’ 16515 ‘as’ automatically macro expands certain division and 16516 multiplication instructions to check for overflow and division by 16517 zero. This option causes ‘as’ to generate code to take a trap 16518 exception rather than a break exception when an error is detected. 16519 The trap instructions are only supported at Instruction Set 16520 Architecture level 2 and higher. 16521 16522‘--break’ 16523‘--no-trap’ 16524 Generate code to take a break exception rather than a trap 16525 exception when an error is detected. This is the default. 16526 16527‘-mpdr’ 16528‘-mno-pdr’ 16529 Control generation of ‘.pdr’ sections. Off by default on IRIX, on 16530 elsewhere. 16531 16532‘-mshared’ 16533‘-mno-shared’ 16534 When generating code using the Unix calling conventions (selected 16535 by ‘-KPIC’ or ‘-mcall_shared’), gas will normally generate code 16536 which can go into a shared library. The ‘-mno-shared’ option tells 16537 gas to generate code which uses the calling convention, but can not 16538 go into a shared library. The resulting code is slightly more 16539 efficient. This option only affects the handling of the ‘.cpload’ 16540 and ‘.cpsetup’ pseudo-ops. 16541 16542 16543File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent 16544 165459.28.2 High-level assembly macros 16546--------------------------------- 16547 16548MIPS assemblers have traditionally provided a wider range of 16549instructions than the MIPS architecture itself. These extra 16550instructions are usually referred to as “macro” instructions (1). 16551 16552 Some MIPS macro instructions extend an underlying architectural 16553instruction while others are entirely new. An example of the former 16554type is ‘and’, which allows the third operand to be either a register or 16555an arbitrary immediate value. Examples of the latter type include 16556‘bgt’, which branches to the third operand when the first operand is 16557greater than the second operand, and ‘ulh’, which implements an 16558unaligned 2-byte load. 16559 16560 One of the most common extensions provided by macros is to expand 16561memory offsets to the full address range (32 or 64 bits) and to allow 16562symbolic offsets such as ‘my_data + 4’ to be used in place of integer 16563constants. For example, the architectural instruction ‘lbu’ allows only 16564a signed 16-bit offset, whereas the macro ‘lbu’ allows code such as ‘lbu 16565$4,array+32769($5)’. The implementation of these symbolic offsets 16566depends on several factors, such as whether the assembler is generating 16567SVR4-style PIC (selected by ‘-KPIC’, *note Assembler options: MIPS 16568Options.), the size of symbols (*note Directives to override the size of 16569symbols: MIPS Symbol Sizes.), and the small data limit (*note 16570Controlling the use of small data accesses: MIPS Small Data.). 16571 16572 Sometimes it is undesirable to have one assembly instruction expand 16573to several machine instructions. The directive ‘.set nomacro’ tells the 16574assembler to warn when this happens. ‘.set macro’ restores the default 16575behavior. 16576 16577 Some macro instructions need a temporary register to store 16578intermediate results. This register is usually ‘$1’, also known as 16579‘$at’, but it can be changed to any core register REG using ‘.set 16580at=REG’. Note that ‘$at’ always refers to ‘$1’ regardless of which 16581register is being used as the temporary register. 16582 16583 Implicit uses of the temporary register in macros could interfere 16584with explicit uses in the assembly code. The assembler therefore warns 16585whenever it sees an explicit use of the temporary register. The 16586directive ‘.set noat’ silences this warning while ‘.set at’ restores the 16587default behavior. It is safe to use ‘.set noat’ while ‘.set nomacro’ is 16588in effect since single-instruction macros never need a temporary 16589register. 16590 16591 Note that while the GNU assembler provides these macros for 16592compatibility, it does not make any attempt to optimize them with the 16593surrounding code. 16594 16595 ---------- Footnotes ---------- 16596 16597 (1) The term “macro” is somewhat overloaded here, since these macros 16598have no relation to those defined by ‘.macro’, *note ‘.macro’: Macro. 16599 16600 16601File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent 16602 166039.28.3 Directives to override the size of symbols 16604------------------------------------------------- 16605 16606The n64 ABI allows symbols to have any 64-bit value. Although this 16607provides a great deal of flexibility, it means that some macros have 16608much longer expansions than their 32-bit counterparts. For example, the 16609non-PIC expansion of ‘dla $4,sym’ is usually: 16610 16611 lui $4,%highest(sym) 16612 lui $1,%hi(sym) 16613 daddiu $4,$4,%higher(sym) 16614 daddiu $1,$1,%lo(sym) 16615 dsll32 $4,$4,0 16616 daddu $4,$4,$1 16617 16618 whereas the 32-bit expansion is simply: 16619 16620 lui $4,%hi(sym) 16621 daddiu $4,$4,%lo(sym) 16622 16623 n64 code is sometimes constructed in such a way that all symbolic 16624constants are known to have 32-bit values, and in such cases, it’s 16625preferable to use the 32-bit expansion instead of the 64-bit expansion. 16626 16627 You can use the ‘.set sym32’ directive to tell the assembler that, 16628from this point on, all expressions of the form ‘SYMBOL’ or ‘SYMBOL + 16629OFFSET’ have 32-bit values. For example: 16630 16631 .set sym32 16632 dla $4,sym 16633 lw $4,sym+16 16634 sw $4,sym+0x8000($4) 16635 16636 will cause the assembler to treat ‘sym’, ‘sym+16’ and ‘sym+0x8000’ as 1663732-bit values. The handling of non-symbolic addresses is not affected. 16638 16639 The directive ‘.set nosym32’ ends a ‘.set sym32’ block and reverts to 16640the normal behavior. It is also possible to change the symbol size 16641using the command-line options ‘-msym32’ and ‘-mno-sym32’. 16642 16643 These options and directives are always accepted, but at present, 16644they have no effect for anything other than n64. 16645 16646 16647File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent 16648 166499.28.4 Controlling the use of small data accesses 16650------------------------------------------------- 16651 16652It often takes several instructions to load the address of a symbol. 16653For example, when ‘addr’ is a 32-bit symbol, the non-PIC expansion of 16654‘dla $4,addr’ is usually: 16655 16656 lui $4,%hi(addr) 16657 daddiu $4,$4,%lo(addr) 16658 16659 The sequence is much longer when ‘addr’ is a 64-bit symbol. *Note 16660Directives to override the size of symbols: MIPS Symbol Sizes. 16661 16662 In order to cut down on this overhead, most embedded MIPS systems set 16663aside a 64-kilobyte “small data” area and guarantee that all data of 16664size N and smaller will be placed in that area. The limit N is passed 16665to both the assembler and the linker using the command-line option ‘-G 16666N’, *note Assembler options: MIPS Options. Note that the same value of 16667N must be used when linking and when assembling all input files to the 16668link; any inconsistency could cause a relocation overflow error. 16669 16670 The size of an object in the ‘.bss’ section is set by the ‘.comm’ or 16671‘.lcomm’ directive that defines it. The size of an external object may 16672be set with the ‘.extern’ directive. For example, ‘.extern sym,4’ 16673declares that the object at ‘sym’ is 4 bytes in length, while leaving 16674‘sym’ otherwise undefined. 16675 16676 When no ‘-G’ option is given, the default limit is 8 bytes. The 16677option ‘-G 0’ prevents any data from being automatically classified as 16678small. 16679 16680 It is also possible to mark specific objects as small by putting them 16681in the special sections ‘.sdata’ and ‘.sbss’, which are “small” 16682counterparts of ‘.data’ and ‘.bss’ respectively. The toolchain will 16683treat such data as small regardless of the ‘-G’ setting. 16684 16685 On startup, systems that support a small data area are expected to 16686initialize register ‘$28’, also known as ‘$gp’, in such a way that small 16687data can be accessed using a 16-bit offset from that register. For 16688example, when ‘addr’ is small data, the ‘dla $4,addr’ instruction above 16689is equivalent to: 16690 16691 daddiu $4,$28,%gp_rel(addr) 16692 16693 Small data is not supported for SVR4-style PIC. 16694 16695 16696File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent 16697 166989.28.5 Directives to override the ISA level 16699------------------------------------------- 16700 16701GNU ‘as’ supports an additional directive to change the MIPS Instruction 16702Set Architecture level on the fly: ‘.set mipsN’. N should be a number 16703from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 1670464r6. The values other than 0 make the assembler accept instructions 16705for the corresponding ISA level, from that point on in the assembly. 16706‘.set mipsN’ affects not only which instructions are permitted, but also 16707how certain macros are expanded. ‘.set mips0’ restores the ISA level to 16708its original level: either the level you selected with command-line 16709options, or the default for your configuration. You can use this 16710feature to permit specific MIPS III instructions while assembling in 32 16711bit mode. Use this directive with care! 16712 16713 The ‘.set arch=CPU’ directive provides even finer control. It 16714changes the effective CPU target and allows the assembler to use 16715instructions specific to a particular CPU. All CPUs supported by the 16716‘-march’ command-line option are also selectable by this directive. The 16717original value is restored by ‘.set arch=default’. 16718 16719 The directive ‘.set mips16’ puts the assembler into MIPS 16 mode, in 16720which it will assemble instructions for the MIPS 16 processor. Use 16721‘.set nomips16’ to return to normal 32 bit mode. 16722 16723 Traditional MIPS assemblers do not support this directive. 16724 16725 The directive ‘.set micromips’ puts the assembler into microMIPS 16726mode, in which it will assemble instructions for the microMIPS 16727processor. Use ‘.set nomicromips’ to return to normal 32 bit mode. 16728 16729 Traditional MIPS assemblers do not support this directive. 16730 16731 16732File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 16733 167349.28.6 Directives to control code generation 16735-------------------------------------------- 16736 16737The ‘.module’ directive allows command-line options to be set directly 16738from assembly. The format of the directive matches the ‘.set’ directive 16739but only those options which are relevant to a whole module are 16740supported. The effect of a ‘.module’ directive is the same as the 16741corresponding command-line option. Where ‘.set’ directives support 16742returning to a default then the ‘.module’ directives do not as they 16743define the defaults. 16744 16745 These module-level directives must appear first in assembly. 16746 16747 Traditional MIPS assemblers do not support this directive. 16748 16749 The directive ‘.set insn32’ makes the assembler only use 32-bit 16750instruction encodings when generating code for the microMIPS processor. 16751This directive inhibits the use of any 16-bit instructions from that 16752point on in the assembly. The ‘.set noinsn32’ directive allows 16-bit 16753instructions to be accepted. 16754 16755 Traditional MIPS assemblers do not support this directive. 16756 16757 16758File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent 16759 167609.28.7 Directives for extending MIPS 16 bit instructions 16761-------------------------------------------------------- 16762 16763By default, MIPS 16 instructions are automatically extended to 32 bits 16764when necessary. The directive ‘.set noautoextend’ will turn this off. 16765When ‘.set noautoextend’ is in effect, any 32 bit instruction must be 16766explicitly extended with the ‘.e’ modifier (e.g., ‘li.e $4,1000’). The 16767directive ‘.set autoextend’ may be used to once again automatically 16768extend instructions when necessary. 16769 16770 This directive is only meaningful when in MIPS 16 mode. Traditional 16771MIPS assemblers do not support this directive. 16772 16773 16774File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent 16775 167769.28.8 Directive to mark data as an instruction 16777----------------------------------------------- 16778 16779The ‘.insn’ directive tells ‘as’ that the following data is actually 16780instructions. This makes a difference in MIPS 16 and microMIPS modes: 16781when loading the address of a label which precedes instructions, ‘as’ 16782automatically adds 1 to the value, so that jumping to the loaded address 16783will do the right thing. 16784 16785 The ‘.global’ and ‘.globl’ directives supported by ‘as’ will by 16786default mark the symbol as pointing to a region of data not code. This 16787means that, for example, any instructions following such a symbol will 16788not be disassembled by ‘objdump’ as it will regard them as data. To 16789change this behavior an optional section name can be placed after the 16790symbol name in the ‘.global’ directive. If this section exists and is 16791known to be a code section, then the symbol will be marked as pointing 16792at code not data. Ie the syntax for the directive is: 16793 16794 ‘.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...’, 16795 16796 Here is a short example: 16797 16798 .global foo .text, bar, baz .data 16799 foo: 16800 nop 16801 bar: 16802 .word 0x0 16803 baz: 16804 .word 0x1 16805 16806 16807 16808File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent 16809 168109.28.9 Directives to control the FP ABI 16811--------------------------------------- 16812 16813* Menu: 16814 16815* MIPS FP ABI History:: History of FP ABIs 16816* MIPS FP ABI Variants:: Supported FP ABIs 16817* MIPS FP ABI Selection:: Automatic selection of FP ABI 16818* MIPS FP ABI Compatibility:: Linking different FP ABI variants 16819 16820 16821File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs 16822 168239.28.9.1 History of FP ABIs 16824........................... 16825 16826The MIPS ABIs support a variety of different floating-point extensions 16827where calling-convention and register sizes vary for floating-point 16828data. The extensions exist to support a wide variety of optional 16829architecture features. The resulting ABI variants are generally 16830incompatible with each other and must be tracked carefully. 16831 16832 Traditionally the use of an explicit ‘.gnu_attribute 4, N’ directive 16833is used to indicate which ABI is in use by a specific module. It was 16834then left to the user to ensure that command-line options and the 16835selected ABI were compatible with some potential for inconsistencies. 16836 16837 16838File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs 16839 168409.28.9.2 Supported FP ABIs 16841.......................... 16842 16843The supported floating-point ABI variants are: 16844 16845‘0 - No floating-point’ 16846 This variant is used to indicate that floating-point is not used 16847 within the module at all and therefore has no impact on the ABI. 16848 This is the default. 16849 16850‘1 - Double-precision’ 16851 This variant indicates that double-precision support is used. For 16852 64-bit ABIs this means that 64-bit wide floating-point registers 16853 are required. For 32-bit ABIs this means that 32-bit wide 16854 floating-point registers are required and double-precision 16855 operations use pairs of registers. 16856 16857‘2 - Single-precision’ 16858 This variant indicates that single-precision support is used. 16859 Double precision operations will be supported via soft-float 16860 routines. 16861 16862‘3 - Soft-float’ 16863 This variant indicates that although floating-point support is used 16864 all operations are emulated in software. This means the ABI is 16865 modified to pass all floating-point data in general-purpose 16866 registers. 16867 16868‘4 - Deprecated’ 16869 This variant existed as an initial attempt at supporting 64-bit 16870 wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This 16871 has been superseded by 5, 6 and 7. 16872 16873‘5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU’ 16874 This variant is used by 32-bit ABIs to indicate that the 16875 floating-point code in the module has been designed to operate 16876 correctly with either 32-bit wide or 64-bit wide floating-point 16877 registers. Double-precision support is used. Only O32 currently 16878 supports this variant and requires a minimum architecture of MIPS 16879 II. 16880 16881‘6 - Double-precision 32-bit FPU, 64-bit FPU’ 16882 This variant is used by 32-bit ABIs to indicate that the 16883 floating-point code in the module requires 64-bit wide 16884 floating-point registers. Double-precision support is used. Only 16885 O32 currently supports this variant and requires a minimum 16886 architecture of MIPS32r2. 16887 16888‘7 - Double-precision compat 32-bit FPU, 64-bit FPU’ 16889 This variant is used by 32-bit ABIs to indicate that the 16890 floating-point code in the module requires 64-bit wide 16891 floating-point registers. Double-precision support is used. This 16892 differs from the previous ABI as it restricts use of odd-numbered 16893 single-precision registers. Only O32 currently supports this 16894 variant and requires a minimum architecture of MIPS32r2. 16895 16896 16897File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs 16898 168999.28.9.3 Automatic selection of FP ABI 16900...................................... 16901 16902In order to simplify and add safety to the process of selecting the 16903correct floating-point ABI, the assembler will automatically infer the 16904correct ‘.gnu_attribute 4, N’ directive based on command-line options 16905and ‘.module’ overrides. Where an explicit ‘.gnu_attribute 4, N’ 16906directive has been seen then a warning will be raised if it does not 16907match an inferred setting. 16908 16909 The floating-point ABI is inferred as follows. If ‘-msoft-float’ has 16910been used the module will be marked as soft-float. If ‘-msingle-float’ 16911has been used then the module will be marked as single-precision. The 16912remaining ABIs are then selected based on the FP register width. 16913Double-precision is selected if the width of GP and FP registers match 16914and the special double-precision variants for 32-bit ABIs are then 16915selected depending on ‘-mfpxx’, ‘-mfp64’ and ‘-mno-odd-spreg’. 16916 16917 16918File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs 16919 169209.28.9.4 Linking different FP ABI variants 16921.......................................... 16922 16923Modules using the default FP ABI (no floating-point) can be linked with 16924any other (singular) FP ABI variant. 16925 16926 Special compatibility support exists for O32 with the four 16927double-precision FP ABI variants. The ‘-mfpxx’ FP ABI is specifically 16928designed to be compatible with the standard double-precision ABI and the 16929‘-mfp64’ FP ABIs. This makes it desirable for O32 modules to be built 16930as ‘-mfpxx’ to ensure the maximum compatibility with other modules 16931produced for more specific needs. The only FP ABIs which cannot be 16932linked together are the standard double-precision ABI and the full 16933‘-mfp64’ ABI with ‘-modd-spreg’. 16934 16935 16936File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent 16937 169389.28.10 Directives to record which NaN encoding is being used 16939------------------------------------------------------------- 16940 16941The IEEE 754 floating-point standard defines two types of not-a-number 16942(NaN) data: “signalling” NaNs and “quiet” NaNs. The original version of 16943the standard did not specify how these two types should be 16944distinguished. Most implementations followed the i387 model, in which 16945the first bit of the significand is set for quiet NaNs and clear for 16946signalling NaNs. However, the original MIPS implementation assigned the 16947opposite meaning to the bit, so that it was set for signalling NaNs and 16948clear for quiet NaNs. 16949 16950 The 2008 revision of the standard formally suggested the i387 choice 16951and as from Sep 2012 the current release of the MIPS architecture 16952therefore optionally supports that form. Code that uses one NaN 16953encoding would usually be incompatible with code that uses the other NaN 16954encoding, so MIPS ELF objects have a flag (‘EF_MIPS_NAN2008’) to record 16955which encoding is being used. 16956 16957 Assembly files can use the ‘.nan’ directive to select between the two 16958encodings. ‘.nan 2008’ says that the assembly file uses the IEEE 16959754-2008 encoding while ‘.nan legacy’ says that the file uses the 16960original MIPS encoding. If several ‘.nan’ directives are given, the 16961final setting is the one that is used. 16962 16963 The command-line options ‘-mnan=legacy’ and ‘-mnan=2008’ can be used 16964instead of ‘.nan legacy’ and ‘.nan 2008’ respectively. However, any 16965‘.nan’ directive overrides the command-line setting. 16966 16967 ‘.nan legacy’ is the default if no ‘.nan’ directive or ‘-mnan’ option 16968is given. 16969 16970 Note that GNU ‘as’ does not produce NaNs itself and therefore these 16971directives do not affect code generation. They simply control the 16972setting of the ‘EF_MIPS_NAN2008’ flag. 16973 16974 Traditional MIPS assemblers do not support these directives. 16975 16976 16977File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent 16978 169799.28.11 Directives to save and restore options 16980---------------------------------------------- 16981 16982The directives ‘.set push’ and ‘.set pop’ may be used to save and 16983restore the current settings for all the options which are controlled by 16984‘.set’. The ‘.set push’ directive saves the current settings on a 16985stack. The ‘.set pop’ directive pops the stack and restores the 16986settings. 16987 16988 These directives can be useful inside an macro which must change an 16989option such as the ISA level or instruction reordering but does not want 16990to change the state of the code which invoked the macro. 16991 16992 Traditional MIPS assemblers do not support these directives. 16993 16994 16995File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent 16996 169979.28.12 Directives to control generation of MIPS ASE instructions 16998----------------------------------------------------------------- 16999 17000The directive ‘.set mips3d’ makes the assembler accept instructions from 17001the MIPS-3D Application Specific Extension from that point on in the 17002assembly. The ‘.set nomips3d’ directive prevents MIPS-3D instructions 17003from being accepted. 17004 17005 The directive ‘.set smartmips’ makes the assembler accept 17006instructions from the SmartMIPS Application Specific Extension to the 17007MIPS32 ISA from that point on in the assembly. The ‘.set nosmartmips’ 17008directive prevents SmartMIPS instructions from being accepted. 17009 17010 The directive ‘.set mdmx’ makes the assembler accept instructions 17011from the MDMX Application Specific Extension from that point on in the 17012assembly. The ‘.set nomdmx’ directive prevents MDMX instructions from 17013being accepted. 17014 17015 The directive ‘.set dsp’ makes the assembler accept instructions from 17016the DSP Release 1 Application Specific Extension from that point on in 17017the assembly. The ‘.set nodsp’ directive prevents DSP Release 1 17018instructions from being accepted. 17019 17020 The directive ‘.set dspr2’ makes the assembler accept instructions 17021from the DSP Release 2 Application Specific Extension from that point on 17022in the assembly. This directive implies ‘.set dsp’. The ‘.set nodspr2’ 17023directive prevents DSP Release 2 instructions from being accepted. 17024 17025 The directive ‘.set dspr3’ makes the assembler accept instructions 17026from the DSP Release 3 Application Specific Extension from that point on 17027in the assembly. This directive implies ‘.set dsp’ and ‘.set dspr2’. 17028The ‘.set nodspr3’ directive prevents DSP Release 3 instructions from 17029being accepted. 17030 17031 The directive ‘.set mt’ makes the assembler accept instructions from 17032the MT Application Specific Extension from that point on in the 17033assembly. The ‘.set nomt’ directive prevents MT instructions from being 17034accepted. 17035 17036 The directive ‘.set mcu’ makes the assembler accept instructions from 17037the MCU Application Specific Extension from that point on in the 17038assembly. The ‘.set nomcu’ directive prevents MCU instructions from 17039being accepted. 17040 17041 The directive ‘.set msa’ makes the assembler accept instructions from 17042the MIPS SIMD Architecture Extension from that point on in the assembly. 17043The ‘.set nomsa’ directive prevents MSA instructions from being 17044accepted. 17045 17046 The directive ‘.set virt’ makes the assembler accept instructions 17047from the Virtualization Application Specific Extension from that point 17048on in the assembly. The ‘.set novirt’ directive prevents Virtualization 17049instructions from being accepted. 17050 17051 The directive ‘.set xpa’ makes the assembler accept instructions from 17052the XPA Extension from that point on in the assembly. The ‘.set noxpa’ 17053directive prevents XPA instructions from being accepted. 17054 17055 The directive ‘.set mips16e2’ makes the assembler accept instructions 17056from the MIPS16e2 Application Specific Extension from that point on in 17057the assembly, whenever in MIPS16 mode. The ‘.set nomips16e2’ directive 17058prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. 17059Neither directive affects the state of MIPS16 mode being active itself 17060which has separate controls. 17061 17062 The directive ‘.set crc’ makes the assembler accept instructions from 17063the CRC Extension from that point on in the assembly. The ‘.set nocrc’ 17064directive prevents CRC instructions from being accepted. 17065 17066 The directive ‘.set ginv’ makes the assembler accept instructions 17067from the GINV Extension from that point on in the assembly. The ‘.set 17068noginv’ directive prevents GINV instructions from being accepted. 17069 17070 The directive ‘.set loongson-mmi’ makes the assembler accept 17071instructions from the MMI Extension from that point on in the assembly. 17072The ‘.set noloongson-mmi’ directive prevents MMI instructions from being 17073accepted. 17074 17075 The directive ‘.set loongson-cam’ makes the assembler accept 17076instructions from the Loongson CAM from that point on in the assembly. 17077The ‘.set noloongson-cam’ directive prevents Loongson CAM instructions 17078from being accepted. 17079 17080 The directive ‘.set loongson-ext’ makes the assembler accept 17081instructions from the Loongson EXT from that point on in the assembly. 17082The ‘.set noloongson-ext’ directive prevents Loongson EXT instructions 17083from being accepted. 17084 17085 The directive ‘.set loongson-ext2’ makes the assembler accept 17086instructions from the Loongson EXT2 from that point on in the assembly. 17087This directive implies ‘.set loognson-ext’. The ‘.set noloongson-ext2’ 17088directive prevents Loongson EXT2 instructions from being accepted. 17089 17090 Traditional MIPS assemblers do not support these directives. 17091 17092 17093File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent 17094 170959.28.13 Directives to override floating-point options 17096----------------------------------------------------- 17097 17098The directives ‘.set softfloat’ and ‘.set hardfloat’ provide finer 17099control of disabling and enabling float-point instructions. These 17100directives always override the default (that hard-float instructions are 17101accepted) or the command-line options (‘-msoft-float’ and 17102‘-mhard-float’). 17103 17104 The directives ‘.set singlefloat’ and ‘.set doublefloat’ provide 17105finer control of disabling and enabling double-precision float-point 17106operations. These directives always override the default (that 17107double-precision operations are accepted) or the command-line options 17108(‘-msingle-float’ and ‘-mdouble-float’). 17109 17110 Traditional MIPS assemblers do not support these directives. 17111 17112 17113File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent 17114 171159.28.14 Syntactical considerations for the MIPS assembler 17116--------------------------------------------------------- 17117 17118* Menu: 17119 17120* MIPS-Chars:: Special Characters 17121 17122 17123File: as.info, Node: MIPS-Chars, Up: MIPS Syntax 17124 171259.28.14.1 Special Characters 17126............................ 17127 17128The presence of a ‘#’ on a line indicates the start of a comment that 17129extends to the end of the current line. 17130 17131 If a ‘#’ appears as the first character of a line, the whole line is 17132treated as a comment, but in this case the line can also be a logical 17133line number directive (*note Comments::) or a preprocessor control 17134command (*note Preprocessing::). 17135 17136 The ‘;’ character can be used to separate statements on the same 17137line. 17138 17139 17140File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 17141 171429.29 MMIX Dependent Features 17143============================ 17144 17145* Menu: 17146 17147* MMIX-Opts:: Command-line Options 17148* MMIX-Expand:: Instruction expansion 17149* MMIX-Syntax:: Syntax 17150* MMIX-mmixal:: Differences to ‘mmixal’ syntax and semantics 17151 17152 17153File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 17154 171559.29.1 Command-line Options 17156--------------------------- 17157 17158The MMIX version of ‘as’ has some machine-dependent options. 17159 17160 When ‘--fixed-special-register-names’ is specified, only the register 17161names specified in *note MMIX-Regs:: are recognized in the instructions 17162‘PUT’ and ‘GET’. 17163 17164 You can use the ‘--globalize-symbols’ to make all symbols global. 17165This option is useful when splitting up a ‘mmixal’ program into several 17166files. 17167 17168 The ‘--gnu-syntax’ turns off most syntax compatibility with ‘mmixal’. 17169Its usability is currently doubtful. 17170 17171 The ‘--relax’ option is not fully supported, but will eventually make 17172the object file prepared for linker relaxation. 17173 17174 If you want to avoid inadvertently calling a predefined symbol and 17175would rather get an error, for example when using ‘as’ with a compiler 17176or other machine-generated code, specify ‘--no-predefined-syms’. This 17177turns off built-in predefined definitions of all such symbols, including 17178rounding-mode symbols, segment symbols, ‘BIT’ symbols, and ‘TRAP’ 17179symbols used in ‘mmix’ “system calls”. It also turns off predefined 17180special-register names, except when used in ‘PUT’ and ‘GET’ 17181instructions. 17182 17183 By default, some instructions are expanded to fit the size of the 17184operand or an external symbol (*note MMIX-Expand::). By passing 17185‘--no-expand’, no such expansion will be done, instead causing errors at 17186link time if the operand does not fit. 17187 17188 The ‘mmixal’ documentation (*note mmixsite::) specifies that global 17189registers allocated with the ‘GREG’ directive (*note MMIX-greg::) and 17190initialized to the same non-zero value, will refer to the same global 17191register. This isn’t strictly enforceable in ‘as’ since the final 17192addresses aren’t known until link-time, but it will do an effort unless 17193the ‘--no-merge-gregs’ option is specified. (Register merging isn’t yet 17194implemented in ‘ld’.) 17195 17196 ‘as’ will warn every time it expands an instruction to fit an operand 17197unless the option ‘-x’ is specified. It is believed that this behaviour 17198is more useful than just mimicking ‘mmixal’’s behaviour, in which 17199instructions are only expanded if the ‘-x’ option is specified, and 17200assembly fails otherwise, when an instruction needs to be expanded. It 17201needs to be kept in mind that ‘mmixal’ is both an assembler and linker, 17202while ‘as’ will expand instructions that at link stage can be 17203contracted. (Though linker relaxation isn’t yet implemented in ‘ld’.) 17204The option ‘-x’ also implies ‘--linker-allocated-gregs’. 17205 17206 If instruction expansion is enabled, ‘as’ can expand a ‘PUSHJ’ 17207instruction into a series of instructions. The shortest expansion is to 17208not expand it, but just mark the call as redirectable to a stub, which 17209‘ld’ creates at link-time, but only if the original ‘PUSHJ’ instruction 17210is found not to reach the target. The stub consists of the necessary 17211instructions to form a jump to the target. This happens if ‘as’ can 17212assert that the ‘PUSHJ’ instruction can reach such a stub. The option 17213‘--no-pushj-stubs’ disables this shorter expansion, and the longer 17214series of instructions is then created at assembly-time. The option 17215‘--no-stubs’ is a synonym, intended for compatibility with future 17216releases, where generation of stubs for other instructions may be 17217implemented. 17218 17219 Usually a two-operand-expression (*note GREG-base::) without a 17220matching ‘GREG’ directive is treated as an error by ‘as’. When the 17221option ‘--linker-allocated-gregs’ is in effect, they are instead passed 17222through to the linker, which will allocate as many global registers as 17223is needed. 17224 17225 17226File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 17227 172289.29.2 Instruction expansion 17229---------------------------- 17230 17231When ‘as’ encounters an instruction with an operand that is either not 17232known or does not fit the operand size of the instruction, ‘as’ (and 17233‘ld’) will expand the instruction into a sequence of instructions 17234semantically equivalent to the operand fitting the instruction. 17235Expansion will take place for the following instructions: 17236 17237‘GETA’ 17238 Expands to a sequence of four instructions: ‘SETL’, ‘INCML’, 17239 ‘INCMH’ and ‘INCH’. The operand must be a multiple of four. 17240Conditional branches 17241 A branch instruction is turned into a branch with the complemented 17242 condition and prediction bit over five instructions; four 17243 instructions setting ‘$255’ to the operand value, which like with 17244 ‘GETA’ must be a multiple of four, and a final ‘GO $255,$255,0’. 17245‘PUSHJ’ 17246 Similar to expansion for conditional branches; four instructions 17247 set ‘$255’ to the operand value, followed by a ‘PUSHGO 17248 $255,$255,0’. 17249‘JMP’ 17250 Similar to conditional branches and ‘PUSHJ’. The final instruction 17251 is ‘GO $255,$255,0’. 17252 17253 The linker ‘ld’ is expected to shrink these expansions for code 17254assembled with ‘--relax’ (though not currently implemented). 17255 17256 17257File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 17258 172599.29.3 Syntax 17260------------- 17261 17262The assembly syntax is supposed to be upward compatible with that 17263described in Sections 1.3 and 1.4 of ‘The Art of Computer Programming, 17264Volume 1’. Draft versions of those chapters as well as other MMIX 17265information is located at 17266<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code 17267examples from the mmixal package located there should work unmodified 17268when assembled and linked as single files, with a few noteworthy 17269exceptions (*note MMIX-mmixal::). 17270 17271 Before an instruction is emitted, the current location is aligned to 17272the next four-byte boundary. If a label is defined at the beginning of 17273the line, its value will be the aligned value. 17274 17275 In addition to the traditional hex-prefix ‘0x’, a hexadecimal number 17276can also be specified by the prefix character ‘#’. 17277 17278 After all operands to an MMIX instruction or directive have been 17279specified, the rest of the line is ignored, treated as a comment. 17280 17281* Menu: 17282 17283* MMIX-Chars:: Special Characters 17284* MMIX-Symbols:: Symbols 17285* MMIX-Regs:: Register Names 17286* MMIX-Pseudos:: Assembler Directives 17287 17288 17289File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 17290 172919.29.3.1 Special Characters 17292........................... 17293 17294The characters ‘*’ and ‘#’ are line comment characters; each start a 17295comment at the beginning of a line, but only at the beginning of a line. 17296A ‘#’ prefixes a hexadecimal number if found elsewhere on a line. If a 17297‘#’ appears at the start of a line the whole line is treated as a 17298comment, but the line can also act as a logical line number directive 17299(*note Comments::) or a preprocessor control command (*note 17300Preprocessing::). 17301 17302 Two other characters, ‘%’ and ‘!’, each start a comment anywhere on 17303the line. Thus you can’t use the ‘modulus’ and ‘not’ operators in 17304expressions normally associated with these two characters. 17305 17306 A ‘;’ is a line separator, treated as a new-line, so separate 17307instructions can be specified on a single line. 17308 17309 17310File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 17311 173129.29.3.2 Symbols 17313................ 17314 17315The character ‘:’ is permitted in identifiers. There are two exceptions 17316to it being treated as any other symbol character: if a symbol begins 17317with ‘:’, it means that the symbol is in the global namespace and that 17318the current prefix should not be prepended to that symbol (*note 17319MMIX-prefix::). The ‘:’ is then not considered part of the symbol. For 17320a symbol in the label position (first on a line), a ‘:’ at the end of a 17321symbol is silently stripped off. A label is permitted, but not 17322required, to be followed by a ‘:’, as with many other assembly formats. 17323 17324 The character ‘@’ in an expression, is a synonym for ‘.’, the current 17325location. 17326 17327 In addition to the common forward and backward local symbol formats 17328(*note Symbol Names::), they can be specified with upper-case ‘B’ and 17329‘F’, as in ‘8B’ and ‘9F’. A local label defined for the current 17330position is written with a ‘H’ appended to the number: 17331 3H LDB $0,$1,2 17332 This and traditional local-label formats cannot be mixed: a label 17333must be defined and referred to using the same format. 17334 17335 There’s a minor caveat: just as for the ordinary local symbols, the 17336local symbols are translated into ordinary symbols using control 17337characters are to hide the ordinal number of the symbol. Unfortunately, 17338these symbols are not translated back in error messages. Thus you may 17339see confusing error messages when local symbols are used. Control 17340characters ‘\003’ (control-C) and ‘\004’ (control-D) are used for the 17341MMIX-specific local-symbol syntax. 17342 17343 The symbol ‘Main’ is handled specially; it is always global. 17344 17345 By defining the symbols ‘__.MMIX.start..text’ and 17346‘__.MMIX.start..data’, the address of respectively the ‘.text’ and 17347‘.data’ segments of the final program can be defined, though when 17348linking more than one object file, the code or data in the object file 17349containing the symbol is not guaranteed to be start at that position; 17350just the final executable. *Note MMIX-loc::. 17351 17352 17353File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 17354 173559.29.3.3 Register names 17356....................... 17357 17358Local and global registers are specified as ‘$0’ to ‘$255’. The 17359recognized special register names are ‘rJ’, ‘rA’, ‘rB’, ‘rC’, ‘rD’, 17360‘rE’, ‘rF’, ‘rG’, ‘rH’, ‘rI’, ‘rK’, ‘rL’, ‘rM’, ‘rN’, ‘rO’, ‘rP’, ‘rQ’, 17361‘rR’, ‘rS’, ‘rT’, ‘rU’, ‘rV’, ‘rW’, ‘rX’, ‘rY’, ‘rZ’, ‘rBB’, ‘rTT’, 17362‘rWW’, ‘rXX’, ‘rYY’ and ‘rZZ’. A leading ‘:’ is optional for special 17363register names. 17364 17365 Local and global symbols can be equated to register names and used in 17366place of ordinary registers. 17367 17368 Similarly for special registers, local and global symbols can be 17369used. Also, symbols equated from numbers and constant expressions are 17370allowed in place of a special register, except when either of the 17371options ‘--no-predefined-syms’ and ‘--fixed-special-register-names’ are 17372specified. Then only the special register names above are allowed for 17373the instructions having a special register operand; ‘GET’ and ‘PUT’. 17374 17375 17376File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 17377 173789.29.3.4 Assembler Directives 17379............................. 17380 17381‘LOC’ 17382 17383 The ‘LOC’ directive sets the current location to the value of the 17384 operand field, which may include changing sections. If the operand 17385 is a constant, the section is set to either ‘.data’ if the value is 17386 ‘0x2000000000000000’ or larger, else it is set to ‘.text’. Within 17387 a section, the current location may only be changed to 17388 monotonically higher addresses. A LOC expression must be a 17389 previously defined symbol or a “pure” constant. 17390 17391 An example, which sets the label PREV to the current location, and 17392 updates the current location to eight bytes forward: 17393 prev LOC @+8 17394 17395 When a LOC has a constant as its operand, a symbol 17396 ‘__.MMIX.start..text’ or ‘__.MMIX.start..data’ is defined depending 17397 on the address as mentioned above. Each such symbol is interpreted 17398 as special by the linker, locating the section at that address. 17399 Note that if multiple files are linked, the first object file with 17400 that section will be mapped to that address (not necessarily the 17401 file with the LOC definition). 17402 17403‘LOCAL’ 17404 17405 Example: 17406 LOCAL external_symbol 17407 LOCAL 42 17408 .local asymbol 17409 17410 This directive-operation generates a link-time assertion that the 17411 operand does not correspond to a global register. The operand is 17412 an expression that at link-time resolves to a register symbol or a 17413 number. A number is treated as the register having that number. 17414 There is one restriction on the use of this directive: the 17415 pseudo-directive must be placed in a section with contents, code or 17416 data. 17417 17418‘IS’ 17419 17420 The ‘IS’ directive: 17421 asymbol IS an_expression 17422 sets the symbol ‘asymbol’ to ‘an_expression’. A symbol may not be 17423 set more than once using this directive. Local labels may be set 17424 using this directive, for example: 17425 5H IS @+4 17426 17427‘GREG’ 17428 17429 This directive reserves a global register, gives it an initial 17430 value and optionally gives it a symbolic name. Some examples: 17431 17432 areg GREG 17433 breg GREG data_value 17434 GREG data_buffer 17435 .greg creg, another_data_value 17436 17437 The symbolic register name can be used in place of a (non-special) 17438 register. If a value isn’t provided, it defaults to zero. Unless 17439 the option ‘--no-merge-gregs’ is specified, non-zero registers 17440 allocated with this directive may be eliminated by ‘as’; another 17441 register with the same value used in its place. Any of the 17442 instructions ‘CSWAP’, ‘GO’, ‘LDA’, ‘LDBU’, ‘LDB’, ‘LDHT’, ‘LDOU’, 17443 ‘LDO’, ‘LDSF’, ‘LDTU’, ‘LDT’, ‘LDUNC’, ‘LDVTS’, ‘LDWU’, ‘LDW’, 17444 ‘PREGO’, ‘PRELD’, ‘PREST’, ‘PUSHGO’, ‘STBU’, ‘STB’, ‘STCO’, ‘STHT’, 17445 ‘STOU’, ‘STSF’, ‘STTU’, ‘STT’, ‘STUNC’, ‘SYNCD’, ‘SYNCID’, can have 17446 a value nearby an initial value in place of its second and third 17447 operands. Here, “nearby” is defined as within the range 0...255 17448 from the initial value of such an allocated register. 17449 17450 buffer1 BYTE 0,0,0,0,0 17451 buffer2 BYTE 0,0,0,0,0 17452 ... 17453 GREG buffer1 17454 LDOU $42,buffer2 17455 In the example above, the ‘Y’ field of the ‘LDOUI’ instruction 17456 (LDOU with a constant Z) will be replaced with the global register 17457 allocated for ‘buffer1’, and the ‘Z’ field will have the value 5, 17458 the offset from ‘buffer1’ to ‘buffer2’. The result is equivalent 17459 to this code: 17460 buffer1 BYTE 0,0,0,0,0 17461 buffer2 BYTE 0,0,0,0,0 17462 ... 17463 tmpreg GREG buffer1 17464 LDOU $42,tmpreg,(buffer2-buffer1) 17465 17466 Global registers allocated with this directive are allocated in 17467 order higher-to-lower within a file. Other than that, the exact 17468 order of register allocation and elimination is undefined. For 17469 example, the order is undefined when more than one file with such 17470 directives are linked together. With the options ‘-x’ and 17471 ‘--linker-allocated-gregs’, ‘GREG’ directives for two-operand cases 17472 like the one mentioned above can be omitted. Sufficient global 17473 registers will then be allocated by the linker. 17474 17475‘BYTE’ 17476 17477 The ‘BYTE’ directive takes a series of operands separated by a 17478 comma. If an operand is a string (*note Strings::), each character 17479 of that string is emitted as a byte. Other operands must be 17480 constant expressions without forward references, in the range 17481 0...255. If you need operands having expressions with forward 17482 references, use ‘.byte’ (*note Byte::). An operand can be omitted, 17483 defaulting to a zero value. 17484 17485‘WYDE’ 17486‘TETRA’ 17487‘OCTA’ 17488 17489 The directives ‘WYDE’, ‘TETRA’ and ‘OCTA’ emit constants of two, 17490 four and eight bytes size respectively. Before anything else 17491 happens for the directive, the current location is aligned to the 17492 respective constant-size boundary. If a label is defined at the 17493 beginning of the line, its value will be that after the alignment. 17494 A single operand can be omitted, defaulting to a zero value emitted 17495 for the directive. Operands can be expressed as strings (*note 17496 Strings::), in which case each character in the string is emitted 17497 as a separate constant of the size indicated by the directive. 17498 17499‘PREFIX’ 17500 17501 The ‘PREFIX’ directive sets a symbol name prefix to be prepended to 17502 all symbols (except local symbols, *note MMIX-Symbols::), that are 17503 not prefixed with ‘:’, until the next ‘PREFIX’ directive. Such 17504 prefixes accumulate. For example, 17505 PREFIX a 17506 PREFIX b 17507 c IS 0 17508 defines a symbol ‘abc’ with the value 0. 17509 17510‘BSPEC’ 17511‘ESPEC’ 17512 17513 A pair of ‘BSPEC’ and ‘ESPEC’ directives delimit a section of 17514 special contents (without specified semantics). Example: 17515 BSPEC 42 17516 TETRA 1,2,3 17517 ESPEC 17518 The single operand to ‘BSPEC’ must be number in the range 0...255. 17519 The ‘BSPEC’ number 80 is used by the GNU binutils implementation. 17520 17521 17522File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 17523 175249.29.4 Differences to ‘mmixal’ 17525------------------------------ 17526 17527The binutils ‘as’ and ‘ld’ combination has a few differences in function 17528compared to ‘mmixal’ (*note mmixsite::). 17529 17530 The replacement of a symbol with a GREG-allocated register (*note 17531GREG-base::) is not handled the exactly same way in ‘as’ as in ‘mmixal’. 17532This is apparent in the ‘mmixal’ example file ‘inout.mms’, where 17533different registers with different offsets, eventually yielding the same 17534address, are used in the first instruction. This type of difference 17535should however not affect the function of any program unless it has 17536specific assumptions about the allocated register number. 17537 17538 Line numbers (in the ‘mmo’ object format) are currently not 17539supported. 17540 17541 Expression operator precedence is not that of mmixal: operator 17542precedence is that of the C programming language. It’s recommended to 17543use parentheses to explicitly specify wanted operator precedence 17544whenever more than one type of operators are used. 17545 17546 The serialize unary operator ‘&’, the fractional division operator 17547‘//’, the logical not operator ‘!’ and the modulus operator ‘%’ are not 17548available. 17549 17550 Symbols are not global by default, unless the option 17551‘--globalize-symbols’ is passed. Use the ‘.global’ directive to 17552globalize symbols (*note Global::). 17553 17554 Operand syntax is a bit stricter with ‘as’ than ‘mmixal’. For 17555example, you can’t say ‘addu 1,2,3’, instead you must write ‘addu 17556$1,$2,3’. 17557 17558 You can’t LOC to a lower address than those already visited (i.e., 17559“backwards”). 17560 17561 A LOC directive must come before any emitted code. 17562 17563 Predefined symbols are visible as file-local symbols after use. (In 17564the ELF file, that is—the linked mmo file has no notion of a file-local 17565symbol.) 17566 17567 Some mapping of constant expressions to sections in LOC expressions 17568is attempted, but that functionality is easily confused and should be 17569avoided unless compatibility with ‘mmixal’ is required. A LOC 17570expression to ‘0x2000000000000000’ or higher, maps to the ‘.data’ 17571section and lower addresses map to the ‘.text’ section (*note 17572MMIX-loc::). 17573 17574 The code and data areas are each contiguous. Sparse programs with 17575far-away LOC directives will take up the same amount of space as a 17576contiguous program with zeros filled in the gaps between the LOC 17577directives. If you need sparse programs, you might try and get the 17578wanted effect with a linker script and splitting up the code parts into 17579sections (*note Section::). Assembly code for this, to be compatible 17580with ‘mmixal’, would look something like: 17581 .if 0 17582 LOC away_expression 17583 .else 17584 .section away,"ax" 17585 .fi 17586 ‘as’ will not execute the LOC directive and ‘mmixal’ ignores the 17587lines with ‘.’. This construct can be used generally to help 17588compatibility. 17589 17590 Symbols can’t be defined twice–not even to the same value. 17591 17592 Instruction mnemonics are recognized case-insensitive, though the 17593‘IS’ and ‘GREG’ pseudo-operations must be specified in upper-case 17594characters. 17595 17596 There’s no unicode support. 17597 17598 The following is a list of programs in ‘mmix.tar.gz’, available at 17599<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked 17600with the version dated 2001-08-25 (md5sum 17601c393470cfc86fac040487d22d2bf0172) that assemble with ‘mmixal’ but do not 17602assemble with ‘as’: 17603 17604‘silly.mms’ 17605 LOC to a previous address. 17606‘sim.mms’ 17607 Redefines symbol ‘Done’. 17608‘test.mms’ 17609 Uses the serial operator ‘&’. 17610 17611 17612File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 17613 176149.30 MSP 430 Dependent Features 17615=============================== 17616 17617* Menu: 17618 17619* MSP430 Options:: Options 17620* MSP430 Syntax:: Syntax 17621* MSP430 Floating Point:: Floating Point 17622* MSP430 Directives:: MSP 430 Machine Directives 17623* MSP430 Opcodes:: Opcodes 17624* MSP430 Profiling Capability:: Profiling Capability 17625 17626 17627File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 17628 176299.30.1 Options 17630-------------- 17631 17632‘-mmcu’ 17633 selects the mcu architecture. If the architecture is 430Xv2 then 17634 this also enables NOP generation unless the ‘-mN’ is also 17635 specified. 17636 17637‘-mcpu’ 17638 selects the cpu architecture. If the architecture is 430Xv2 then 17639 this also enables NOP generation unless the ‘-mN’ is also 17640 specified. 17641 17642‘-msilicon-errata=NAME[,NAME...]’ 17643 Implements a fixup for named silicon errata. Multiple silicon 17644 errata can be specified by multiple uses of the ‘-msilicon-errata’ 17645 option and/or by including the errata names, separated by commas, 17646 on an individual ‘-msilicon-errata’ option. Errata names currently 17647 recognised by the assembler are: 17648 17649 ‘cpu4’ 17650 ‘PUSH #4’ and ‘PUSH #8’ need longer encodings on the MSP430. 17651 This option is enabled by default, and cannot be disabled. 17652 ‘cpu8’ 17653 Do not set the ‘SP’ to an odd value. 17654 ‘cpu11’ 17655 Do not update the ‘SR’ and the ‘PC’ in the same instruction. 17656 ‘cpu12’ 17657 Do not use the ‘PC’ in a ‘CMP’ or ‘BIT’ instruction. 17658 ‘cpu13’ 17659 Do not use an arithmetic instruction to modify the ‘SR’. 17660 ‘cpu19’ 17661 Insert ‘NOP’ after ‘CPUOFF’. 17662 17663‘-msilicon-errata-warn=NAME[,NAME...]’ 17664 Like the ‘-msilicon-errata’ option except that instead of fixing 17665 the specified errata, a warning message is issued instead. This 17666 option can be used alongside ‘-msilicon-errata’ to generate 17667 messages whenever a problem is fixed, or on its own in order to 17668 inspect code for potential problems. 17669 17670‘-mP’ 17671 enables polymorph instructions handler. 17672 17673‘-mQ’ 17674 enables relaxation at assembly time. DANGEROUS! 17675 17676‘-ml’ 17677 indicates that the input uses the large code model. 17678 17679‘-mn’ 17680 enables the generation of a NOP instruction following any 17681 instruction that might change the interrupts enabled/disabled 17682 state. The pipelined nature of the MSP430 core means that any 17683 instruction that changes the interrupt state (‘EINT’, ‘DINT’, ‘BIC 17684 #8, SR’, ‘BIS #8, SR’ or ‘MOV.W <>, SR’) must be followed by a NOP 17685 instruction in order to ensure the correct processing of 17686 interrupts. By default it is up to the programmer to supply these 17687 NOP instructions, but this command-line option enables the 17688 automatic insertion by the assembler, if they are missing. 17689 17690‘-mN’ 17691 disables the generation of a NOP instruction following any 17692 instruction that might change the interrupts enabled/disabled 17693 state. This is the default behaviour. 17694 17695‘-my’ 17696 tells the assembler to generate a warning message if a NOP does not 17697 immediately follow an instruction that enables or disables 17698 interrupts. This is the default. 17699 17700 Note that this option can be stacked with the ‘-mn’ option so that 17701 the assembler will both warn about missing NOP instructions and 17702 then insert them automatically. 17703 17704‘-mY’ 17705 disables warnings about missing NOP instructions. 17706 17707‘-md’ 17708 mark the object file as one that requires data to copied from ROM 17709 to RAM at execution startup. Disabled by default. 17710 17711‘-mdata-region=REGION’ 17712 Select the region data will be placed in. Region placement is 17713 performed by the compiler and linker. The only effect this option 17714 will have on the assembler is that if UPPER or EITHER is selected, 17715 then the symbols to initialise high data and bss will be defined. 17716 Valid REGION values are: 17717 ‘none’ 17718 ‘lower’ 17719 ‘upper’ 17720 ‘either’ 17721 17722 17723File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 17724 177259.30.2 Syntax 17726------------- 17727 17728* Menu: 17729 17730* MSP430-Macros:: Macros 17731* MSP430-Chars:: Special Characters 17732* MSP430-Regs:: Register Names 17733* MSP430-Ext:: Assembler Extensions 17734 17735 17736File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 17737 177389.30.2.1 Macros 17739............... 17740 17741The macro syntax used on the MSP 430 is like that described in the MSP 17742430 Family Assembler Specification. Normal ‘as’ macros should still 17743work. 17744 17745 Additional built-in macros are: 17746 17747‘llo(exp)’ 17748 Extracts least significant word from 32-bit expression ’exp’. 17749 17750‘lhi(exp)’ 17751 Extracts most significant word from 32-bit expression ’exp’. 17752 17753‘hlo(exp)’ 17754 Extracts 3rd word from 64-bit expression ’exp’. 17755 17756‘hhi(exp)’ 17757 Extracts 4th word from 64-bit expression ’exp’. 17758 17759 They normally being used as an immediate source operand. 17760 mov #llo(1), r10 ; == mov #1, r10 17761 mov #lhi(1), r10 ; == mov #0, r10 17762 17763 17764File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 17765 177669.30.2.2 Special Characters 17767........................... 17768 17769A semicolon (‘;’) appearing anywhere on a line starts a comment that 17770extends to the end of that line. 17771 17772 If a ‘#’ appears as the first character of a line then the whole line 17773is treated as a comment, but it can also be a logical line number 17774directive (*note Comments::) or a preprocessor control command (*note 17775Preprocessing::). 17776 17777 Multiple statements can appear on the same line provided that they 17778are separated by the ‘{’ character. 17779 17780 The character ‘$’ in jump instructions indicates current location and 17781implemented only for TI syntax compatibility. 17782 17783 17784File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 17785 177869.30.2.3 Register Names 17787....................... 17788 17789General-purpose registers are represented by predefined symbols of the 17790form ‘rN’ (for global registers), where N represents a number between 17791‘0’ and ‘15’. The leading letters may be in either upper or lower case; 17792for example, ‘r13’ and ‘R7’ are both valid register names. 17793 17794 Register names ‘PC’, ‘SP’ and ‘SR’ cannot be used as register names 17795and will be treated as variables. Use ‘r0’, ‘r1’, and ‘r2’ instead. 17796 17797 17798File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 17799 178009.30.2.4 Assembler Extensions 17801............................. 17802 17803‘@rN’ 17804 As destination operand being treated as ‘0(rn)’ 17805 17806‘0(rN)’ 17807 As source operand being treated as ‘@rn’ 17808 17809‘jCOND +N’ 17810 Skips next N bytes followed by jump instruction and equivalent to 17811 ‘jCOND $+N+2’ 17812 17813 Also, there are some instructions, which cannot be found in other 17814assemblers. These are branch instructions, which has different opcodes 17815upon jump distance. They all got PC relative addressing mode. 17816 17817‘beq label’ 17818 A polymorph instruction which is ‘jeq label’ in case if jump 17819 distance within allowed range for cpu’s jump instruction. If not, 17820 this unrolls into a sequence of 17821 jne $+6 17822 br label 17823 17824‘bne label’ 17825 A polymorph instruction which is ‘jne label’ or ‘jeq +4; br label’ 17826 17827‘blt label’ 17828 A polymorph instruction which is ‘jl label’ or ‘jge +4; br label’ 17829 17830‘bltn label’ 17831 A polymorph instruction which is ‘jn label’ or ‘jn +2; jmp +4; br 17832 label’ 17833 17834‘bltu label’ 17835 A polymorph instruction which is ‘jlo label’ or ‘jhs +2; br label’ 17836 17837‘bge label’ 17838 A polymorph instruction which is ‘jge label’ or ‘jl +4; br label’ 17839 17840‘bgeu label’ 17841 A polymorph instruction which is ‘jhs label’ or ‘jlo +4; br label’ 17842 17843‘bgt label’ 17844 A polymorph instruction which is ‘jeq +2; jge label’ or ‘jeq +6; jl 17845 +4; br label’ 17846 17847‘bgtu label’ 17848 A polymorph instruction which is ‘jeq +2; jhs label’ or ‘jeq +6; 17849 jlo +4; br label’ 17850 17851‘bleu label’ 17852 A polymorph instruction which is ‘jeq label; jlo label’ or ‘jeq +2; 17853 jhs +4; br label’ 17854 17855‘ble label’ 17856 A polymorph instruction which is ‘jeq label; jl label’ or ‘jeq +2; 17857 jge +4; br label’ 17858 17859‘jump label’ 17860 A polymorph instruction which is ‘jmp label’ or ‘br label’ 17861 17862 17863File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 17864 178659.30.3 Floating Point 17866--------------------- 17867 17868The MSP 430 family uses IEEE 32-bit floating-point numbers. 17869 17870 17871File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 17872 178739.30.4 MSP 430 Machine Directives 17874--------------------------------- 17875 17876‘.file’ 17877 This directive is ignored; it is accepted for compatibility with 17878 other MSP 430 assemblers. 17879 17880 _Warning:_ in other versions of the GNU assembler, ‘.file’ is 17881 used for the directive called ‘.app-file’ in the MSP 430 17882 support. 17883 17884‘.line’ 17885 This directive is ignored; it is accepted for compatibility with 17886 other MSP 430 assemblers. 17887 17888‘.arch’ 17889 Sets the target microcontroller in the same way as the ‘-mmcu’ 17890 command-line option. 17891 17892‘.cpu’ 17893 Sets the target architecture in the same way as the ‘-mcpu’ 17894 command-line option. 17895 17896‘.profiler’ 17897 This directive instructs assembler to add new profile entry to the 17898 object file. 17899 17900‘.refsym’ 17901 This directive instructs assembler to add an undefined reference to 17902 the symbol following the directive. The maximum symbol name length 17903 is 1023 characters. No relocation is created for this symbol; it 17904 will exist purely for pulling in object files from archives. Note 17905 that this reloc is not sufficient to prevent garbage collection; 17906 use a KEEP() directive in the linker file to preserve such objects. 17907 17908‘.mspabi_attribute’ 17909 This directive tells the assembler what the MSPABI build attributes 17910 for this file are. This is used for validating the command line 17911 options passed to the assembler against the options the original 17912 source file was compiled with. The expected format is: 17913 ‘.mspabi_attribute tag_name, tag_value’ For example, to set the tag 17914 ‘OFBA_MSPABI_Tag_ISA’ to ‘MSP430X’: ‘.mspabi_attribute 4, 2’ 17915 17916 See the ‘MSP430 EABI, document slaa534’ for the details on tag 17917 names and values. 17918 17919 17920File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 17921 179229.30.5 Opcodes 17923-------------- 17924 17925‘as’ implements all the standard MSP 430 opcodes. No additional 17926pseudo-instructions are needed on this family. 17927 17928 For information on the 430 machine instruction set, see ‘MSP430 17929User’s Manual, document slau049d’, Texas Instrument, Inc. 17930 17931 17932File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 17933 179349.30.6 Profiling Capability 17935--------------------------- 17936 17937It is a performance hit to use gcc’s profiling approach for this tiny 17938target. Even more – jtag hardware facility does not perform any 17939profiling functions. However we’ve got gdb’s built-in simulator where 17940we can do anything. 17941 17942 We define new section ‘.profiler’ which holds all profiling 17943information. We define new pseudo operation ‘.profiler’ which will 17944instruct assembler to add new profile entry to the object file. Profile 17945should take place at the present address. 17946 17947 Pseudo operation format: 17948 17949 ‘.profiler flags,function_to_profile [, cycle_corrector, extra]’ 17950 17951 where: 17952 17953 ‘flags’ is a combination of the following characters: 17954 17955 ‘s’ 17956 function entry 17957 ‘x’ 17958 function exit 17959 ‘i’ 17960 function is in init section 17961 ‘f’ 17962 function is in fini section 17963 ‘l’ 17964 library call 17965 ‘c’ 17966 libc standard call 17967 ‘d’ 17968 stack value demand 17969 ‘I’ 17970 interrupt service routine 17971 ‘P’ 17972 prologue start 17973 ‘p’ 17974 prologue end 17975 ‘E’ 17976 epilogue start 17977 ‘e’ 17978 epilogue end 17979 ‘j’ 17980 long jump / sjlj unwind 17981 ‘a’ 17982 an arbitrary code fragment 17983 ‘t’ 17984 extra parameter saved (a constant value like frame size) 17985 17986‘function_to_profile’ 17987 a function address 17988‘cycle_corrector’ 17989 a value which should be added to the cycle counter, zero if 17990 omitted. 17991‘extra’ 17992 any extra parameter, zero if omitted. 17993 17994 For example: 17995 .global fxx 17996 .type fxx,@function 17997 fxx: 17998 .LFrameOffset_fxx=0x08 17999 .profiler "scdP", fxx ; function entry. 18000 ; we also demand stack value to be saved 18001 push r11 18002 push r10 18003 push r9 18004 push r8 18005 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 18006 ; (this is a prologue end) 18007 ; note, that spare var filled with 18008 ; the farme size 18009 mov r15,r8 18010 ... 18011 .profiler cdE,fxx ; check stack 18012 pop r8 18013 pop r9 18014 pop r10 18015 pop r11 18016 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 18017 ret ; cause 'ret' insn takes 3 cycles 18018 18019 18020File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 18021 180229.31 NDS32 Dependent Features 18023============================= 18024 18025The NDS32 processors family includes high-performance and low-power 1802632-bit processors for high-end to low-end. GNU ‘as’ for NDS32 18027architectures supports NDS32 ISA version 3. For detail about NDS32 18028instruction set, please see the AndeStar ISA User Manual which is 18029available at http://www.andestech.com/en/index/index.htm 18030 18031* Menu: 18032 18033* NDS32 Options:: Assembler options 18034* NDS32 Syntax:: High-level assembly macros 18035 18036 18037File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent 18038 180399.31.1 NDS32 Options 18040-------------------- 18041 18042The NDS32 configurations of GNU ‘as’ support these special options: 18043 18044‘-O1’ 18045 Optimize for performance. 18046 18047‘-Os’ 18048 Optimize for space. 18049 18050‘-EL’ 18051 Produce little endian data output. 18052 18053‘-EB’ 18054 Produce little endian data output. 18055 18056‘-mpic’ 18057 Generate PIC. 18058 18059‘-mno-fp-as-gp-relax’ 18060 Suppress fp-as-gp relaxation for this file. 18061 18062‘-mb2bb-relax’ 18063 Back-to-back branch optimization. 18064 18065‘-mno-all-relax’ 18066 Suppress all relaxation for this file. 18067 18068‘-march=<arch name>’ 18069 Assemble for architecture <arch name> which could be v3, v3j, v3m, 18070 v3f, v3s, v2, v2j, v2f, v2s. 18071 18072‘-mbaseline=<baseline>’ 18073 Assemble for baseline <baseline> which could be v2, v3, v3m. 18074 18075‘-mfpu-freg=FREG’ 18076 Specify a FPU configuration. 18077 ‘0 8 SP / 4 DP registers’ 18078 ‘1 16 SP / 8 DP registers’ 18079 ‘2 32 SP / 16 DP registers’ 18080 ‘3 32 SP / 32 DP registers’ 18081 18082‘-mabi=ABI’ 18083 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. 18084 18085‘-m[no-]mac’ 18086 Enable/Disable Multiply instructions support. 18087 18088‘-m[no-]div’ 18089 Enable/Disable Divide instructions support. 18090 18091‘-m[no-]16bit-ext’ 18092 Enable/Disable 16-bit extension 18093 18094‘-m[no-]dx-regs’ 18095 Enable/Disable d0/d1 registers 18096 18097‘-m[no-]perf-ext’ 18098 Enable/Disable Performance extension 18099 18100‘-m[no-]perf2-ext’ 18101 Enable/Disable Performance extension 2 18102 18103‘-m[no-]string-ext’ 18104 Enable/Disable String extension 18105 18106‘-m[no-]reduced-regs’ 18107 Enable/Disable Reduced Register configuration (GPR16) option 18108 18109‘-m[no-]audio-isa-ext’ 18110 Enable/Disable AUDIO ISA extension 18111 18112‘-m[no-]fpu-sp-ext’ 18113 Enable/Disable FPU SP extension 18114 18115‘-m[no-]fpu-dp-ext’ 18116 Enable/Disable FPU DP extension 18117 18118‘-m[no-]fpu-fma’ 18119 Enable/Disable FPU fused-multiply-add instructions 18120 18121‘-mall-ext’ 18122 Turn on all extensions and instructions support 18123 18124 18125File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent 18126 181279.31.2 Syntax 18128------------- 18129 18130* Menu: 18131 18132* NDS32-Chars:: Special Characters 18133* NDS32-Regs:: Register Names 18134* NDS32-Ops:: Pseudo Instructions 18135 18136 18137File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax 18138 181399.31.2.1 Special Characters 18140........................... 18141 18142Use ‘#’ at column 1 and ‘!’ anywhere in the line except inside quotes. 18143 18144 Multiple instructions in a line are allowed though not recommended 18145and should be separated by ‘;’. 18146 18147 Assembler is not case-sensitive in general except user defined label. 18148For example, ‘jral F1’ is different from ‘jral f1’ while it is the same 18149as ‘JRAL F1’. 18150 18151 18152File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax 18153 181549.31.2.2 Register Names 18155....................... 18156 18157‘General purpose registers (GPR)’ 18158 There are 32 32-bit general purpose registers $r0 to $r31. 18159 18160‘Accumulators d0 and d1’ 18161 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. 18162 18163‘Assembler reserved register $ta’ 18164 Register $ta ($r15) is reserved for assembler using. 18165 18166‘Operating system reserved registers $p0 and $p1’ 18167 Registers $p0 ($r26) and $p1 ($r27) are used by operating system as 18168 scratch registers. 18169 18170‘Frame pointer $fp’ 18171 Register $r28 is regarded as the frame pointer. 18172 18173‘Global pointer’ 18174 Register $r29 is regarded as the global pointer. 18175 18176‘Link pointer’ 18177 Register $r30 is regarded as the link pointer. 18178 18179‘Stack pointer’ 18180 Register $r31 is regarded as the stack pointer. 18181 18182 18183File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax 18184 181859.31.2.3 Pseudo Instructions 18186............................ 18187 18188‘li rt5,imm32’ 18189 load 32-bit integer into register rt5. ‘sethi rt5,hi20(imm32)’ and 18190 then ‘ori rt5,reg,lo12(imm32)’. 18191 18192‘la rt5,var’ 18193 Load 32-bit address of var into register rt5. ‘sethi 18194 rt5,hi20(var)’ and then ‘ori reg,rt5,lo12(var)’ 18195 18196‘l.[bhw] rt5,var’ 18197 Load value of var into register rt5. ‘sethi $ta,hi20(var)’ and 18198 then ‘l[bhw]i rt5,[$ta+lo12(var)]’ 18199 18200‘l.[bh]s rt5,var’ 18201 Load value of var into register rt5. ‘sethi $ta,hi20(var)’ and 18202 then ‘l[bh]si rt5,[$ta+lo12(var)]’ 18203 18204‘l.[bhw]p rt5,var,inc’ 18205 Load value of var into register rt5 and increment $ta by amount 18206 inc. ‘la $ta,var’ and then ‘l[bhw]i.bi rt5,[$ta],inc’ 18207 18208‘l.[bhw]pc rt5,inc’ 18209 Continue loading value of var into register rt5 and increment $ta 18210 by amount inc. ‘l[bhw]i.bi rt5,[$ta],inc.’ 18211 18212‘l.[bh]sp rt5,var,inc’ 18213 Load value of var into register rt5 and increment $ta by amount 18214 inc. ‘la $ta,var’ and then ‘l[bh]si.bi rt5,[$ta],inc’ 18215 18216‘l.[bh]spc rt5,inc’ 18217 Continue loading value of var into register rt5 and increment $ta 18218 by amount inc. ‘l[bh]si.bi rt5,[$ta],inc.’ 18219 18220‘s.[bhw] rt5,var’ 18221 Store register rt5 to var. ‘sethi $ta,hi20(var)’ and then ‘s[bhw]i 18222 rt5,[$ta+lo12(var)]’ 18223 18224‘s.[bhw]p rt5,var,inc’ 18225 Store register rt5 to var and increment $ta by amount inc. ‘la 18226 $ta,var’ and then ‘s[bhw]i.bi rt5,[$ta],inc’ 18227 18228‘s.[bhw]pc rt5,inc’ 18229 Continue storing register rt5 to var and increment $ta by amount 18230 inc. ‘s[bhw]i.bi rt5,[$ta],inc.’ 18231 18232‘not rt5,ra5’ 18233 Alias of ‘nor rt5,ra5,ra5’. 18234 18235‘neg rt5,ra5’ 18236 Alias of ‘subri rt5,ra5,0’. 18237 18238‘br rb5’ 18239 Depending on how it is assembled, it is translated into ‘r5 rb5’ or 18240 ‘jr rb5’. 18241 18242‘b label’ 18243 Branch to label depending on how it is assembled, it is translated 18244 into ‘j8 label’, ‘j label’, or "‘la $ta,label’ ‘br $ta’". 18245 18246‘bral rb5’ 18247 Alias of jral br5 depending on how it is assembled, it is 18248 translated into ‘jral5 rb5’ or ‘jral rb5’. 18249 18250‘bal fname’ 18251 Alias of jal fname depending on how it is assembled, it is 18252 translated into ‘jal fname’ or "‘la $ta,fname’ ‘bral $ta’". 18253 18254‘call fname’ 18255 Call function fname same as ‘jal fname’. 18256 18257‘move rt5,ra5’ 18258 For 16-bit, this is ‘mov55 rt5,ra5’. For no 16-bit, this is ‘ori 18259 rt5,ra5,0’. 18260 18261‘move rt5,var’ 18262 This is the same as ‘l.w rt5,var’. 18263 18264‘move rt5,imm32’ 18265 This is the same as ‘li rt5,imm32’. 18266 18267‘pushm ra5,rb5’ 18268 Push contents of registers from ra5 to rb5 into stack. 18269 18270‘push ra5’ 18271 Push content of register ra5 into stack. (same ‘pushm ra5,ra5’). 18272 18273‘push.d var’ 18274 Push value of double-word variable var into stack. 18275 18276‘push.w var’ 18277 Push value of word variable var into stack. 18278 18279‘push.h var’ 18280 Push value of half-word variable var into stack. 18281 18282‘push.b var’ 18283 Push value of byte variable var into stack. 18284 18285‘pusha var’ 18286 Push 32-bit address of variable var into stack. 18287 18288‘pushi imm32’ 18289 Push 32-bit immediate value into stack. 18290 18291‘popm ra5,rb5’ 18292 Pop top of stack values into registers ra5 to rb5. 18293 18294‘pop rt5’ 18295 Pop top of stack value into register. (same as ‘popm rt5,rt5’.) 18296 18297‘pop.d var,ra5’ 18298 Pop value of double-word variable var from stack using register ra5 18299 as 2nd scratch register. (1st is $ta) 18300 18301‘pop.w var,ra5’ 18302 Pop value of word variable var from stack using register ra5. 18303 18304‘pop.h var,ra5’ 18305 Pop value of half-word variable var from stack using register ra5. 18306 18307‘pop.b var,ra5’ 18308 Pop value of byte variable var from stack using register ra5. 18309 18310 18311File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies 18312 183139.32 Nios II Dependent Features 18314=============================== 18315 18316* Menu: 18317 18318* Nios II Options:: Options 18319* Nios II Syntax:: Syntax 18320* Nios II Relocations:: Relocations 18321* Nios II Directives:: Nios II Machine Directives 18322* Nios II Opcodes:: Opcodes 18323 18324 18325File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent 18326 183279.32.1 Options 18328-------------- 18329 18330‘-relax-section’ 18331 Replace identified out-of-range branches with PC-relative ‘jmp’ 18332 sequences when possible. The generated code sequences are suitable 18333 for use in position-independent code, but there is a practical 18334 limit on the extended branch range because of the length of the 18335 sequences. This option is the default. 18336 18337‘-relax-all’ 18338 Replace branch instructions not determinable to be in range and all 18339 call instructions with ‘jmp’ and ‘callr’ sequences (respectively). 18340 This option generates absolute relocations against the target 18341 symbols and is not appropriate for position-independent code. 18342 18343‘-no-relax’ 18344 Do not replace any branches or calls. 18345 18346‘-EB’ 18347 Generate big-endian output. 18348 18349‘-EL’ 18350 Generate little-endian output. This is the default. 18351 18352‘-march=ARCHITECTURE’ 18353 This option specifies the target architecture. The assembler 18354 issues an error message if an attempt is made to assemble an 18355 instruction which will not execute on the target architecture. The 18356 following architecture names are recognized: ‘r1’, ‘r2’. The 18357 default is ‘r1’. 18358 18359 18360File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent 18361 183629.32.2 Syntax 18363------------- 18364 18365* Menu: 18366 18367* Nios II Chars:: Special Characters 18368 18369 18370File: as.info, Node: Nios II Chars, Up: Nios II Syntax 18371 183729.32.2.1 Special Characters 18373........................... 18374 18375‘#’ is the line comment character. ‘;’ is the line separator character. 18376 18377 18378File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent 18379 183809.32.3 Nios II Machine Relocations 18381---------------------------------- 18382 18383‘%hiadj(EXPRESSION)’ 18384 Extract the upper 16 bits of EXPRESSION and add one if the 15th bit 18385 is set. 18386 18387 The value of ‘%hiadj(EXPRESSION)’ is: 18388 ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01) 18389 18390 The ‘%hiadj’ relocation is intended to be used with the ‘addi’, 18391 ‘ld’ or ‘st’ instructions along with a ‘%lo’, in order to load a 18392 32-bit constant. 18393 18394 movhi r2, %hiadj(symbol) 18395 addi r2, r2, %lo(symbol) 18396 18397‘%hi(EXPRESSION)’ 18398 Extract the upper 16 bits of EXPRESSION. 18399 18400‘%lo(EXPRESSION)’ 18401 Extract the lower 16 bits of EXPRESSION. 18402 18403‘%gprel(EXPRESSION)’ 18404 Subtract the value of the symbol ‘_gp’ from EXPRESSION. 18405 18406 The intention of the ‘%gprel’ relocation is to have a fast small 18407 area of memory which only takes a 16-bit immediate to access. 18408 18409 .section .sdata 18410 fastint: 18411 .int 123 18412 .section .text 18413 ldw r4, %gprel(fastint)(gp) 18414 18415‘%call(EXPRESSION)’ 18416‘%call_lo(EXPRESSION)’ 18417‘%call_hiadj(EXPRESSION)’ 18418‘%got(EXPRESSION)’ 18419‘%got_lo(EXPRESSION)’ 18420‘%got_hiadj(EXPRESSION)’ 18421‘%gotoff(EXPRESSION)’ 18422‘%gotoff_lo(EXPRESSION)’ 18423‘%gotoff_hiadj(EXPRESSION)’ 18424‘%tls_gd(EXPRESSION)’ 18425‘%tls_ie(EXPRESSION)’ 18426‘%tls_le(EXPRESSION)’ 18427‘%tls_ldm(EXPRESSION)’ 18428‘%tls_ldo(EXPRESSION)’ 18429 18430 These relocations support the ABI for Linux Systems documented in 18431 the ‘Nios II Processor Reference Handbook’. 18432 18433 18434File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent 18435 184369.32.4 Nios II Machine Directives 18437--------------------------------- 18438 18439‘.align EXPRESSION [, EXPRESSION]’ 18440 This is the generic ‘.align’ directive, however this aligns to a 18441 power of two. 18442 18443‘.half EXPRESSION’ 18444 Create an aligned constant 2 bytes in size. 18445 18446‘.word EXPRESSION’ 18447 Create an aligned constant 4 bytes in size. 18448 18449‘.dword EXPRESSION’ 18450 Create an aligned constant 8 bytes in size. 18451 18452‘.2byte EXPRESSION’ 18453 Create an unaligned constant 2 bytes in size. 18454 18455‘.4byte EXPRESSION’ 18456 Create an unaligned constant 4 bytes in size. 18457 18458‘.8byte EXPRESSION’ 18459 Create an unaligned constant 8 bytes in size. 18460 18461‘.16byte EXPRESSION’ 18462 Create an unaligned constant 16 bytes in size. 18463 18464‘.set noat’ 18465 Allows assembly code to use ‘at’ register without warning. Macro 18466 or relaxation expansions generate warnings. 18467 18468‘.set at’ 18469 Assembly code using ‘at’ register generates warnings, and macro 18470 expansion and relaxation are enabled. 18471 18472‘.set nobreak’ 18473 Allows assembly code to use ‘ba’ and ‘bt’ registers without 18474 warning. 18475 18476‘.set break’ 18477 Turns warnings back on for using ‘ba’ and ‘bt’ registers. 18478 18479‘.set norelax’ 18480 Do not replace any branches or calls. 18481 18482‘.set relaxsection’ 18483 Replace identified out-of-range branches with ‘jmp’ sequences 18484 (default). 18485 18486‘.set relaxsection’ 18487 Replace all branch and call instructions with ‘jmp’ and ‘callr’ 18488 sequences. 18489 18490‘.set ...’ 18491 All other ‘.set’ are the normal use. 18492 18493 18494File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent 18495 184969.32.5 Opcodes 18497-------------- 18498 18499‘as’ implements all the standard Nios II opcodes documented in the ‘Nios 18500II Processor Reference Handbook’, including the assembler 18501pseudo-instructions. 18502 18503 18504File: as.info, Node: NS32K-Dependent, Next: OpenRISC-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies 18505 185069.33 NS32K Dependent Features 18507============================= 18508 18509* Menu: 18510 18511* NS32K Syntax:: Syntax 18512 18513 18514File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent 18515 185169.33.1 Syntax 18517------------- 18518 18519* Menu: 18520 18521* NS32K-Chars:: Special Characters 18522 18523 18524File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 18525 185269.33.1.1 Special Characters 18527........................... 18528 18529The presence of a ‘#’ appearing anywhere on a line indicates the start 18530of a comment that extends to the end of that line. 18531 18532 If a ‘#’ appears as the first character of a line then the whole line 18533is treated as a comment, but in this case the line can also be a logical 18534line number directive (*note Comments::) or a preprocessor control 18535command (*note Preprocessing::). 18536 18537 If Sequent compatibility has been configured into the assembler then 18538the ‘|’ character appearing as the first character on a line will also 18539indicate the start of a line comment. 18540 18541 The ‘;’ character can be used to separate statements on the same 18542line. 18543 18544 18545File: as.info, Node: OpenRISC-Dependent, Next: PDP-11-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 18546 185479.34 OPENRISC Dependent Features 18548================================ 18549 18550* Menu: 18551 18552* OpenRISC-Syntax:: Syntax 18553* OpenRISC-Float:: Floating Point 18554* OpenRISC-Directives:: OpenRISC Machine Directives 18555* OpenRISC-Opcodes:: Opcodes 18556 18557 18558File: as.info, Node: OpenRISC-Syntax, Next: OpenRISC-Float, Up: OpenRISC-Dependent 18559 185609.34.1 OpenRISC Syntax 18561---------------------- 18562 18563The assembler syntax follows the OpenRISC 1000 Architecture Manual. 18564 18565* Menu: 18566 18567* OpenRISC-Chars:: Special Characters 18568* OpenRISC-Regs:: Register Names 18569* OpenRISC-Relocs:: Relocations 18570 18571 18572File: as.info, Node: OpenRISC-Chars, Next: OpenRISC-Regs, Up: OpenRISC-Syntax 18573 185749.34.1.1 Special Characters 18575........................... 18576 18577A ‘#’ character appearing anywhere on a line indicates the start of a 18578comment that extends to the end of that line. 18579 18580 ‘;’ can be used instead of a newline to separate statements. 18581 18582 18583File: as.info, Node: OpenRISC-Regs, Next: OpenRISC-Relocs, Prev: OpenRISC-Chars, Up: OpenRISC-Syntax 18584 185859.34.1.2 Register Names 18586....................... 18587 18588The OpenRISC register file contains 32 general purpose registers. 18589 18590 • The 32 general purpose registers are referred to as ‘rN’. 18591 18592 • The stack pointer register ‘r1’ can be referenced using the alias 18593 ‘sp’. 18594 18595 • The frame pointer register ‘r2’ can be referenced using the alias 18596 ‘fp’. 18597 18598 • The link register ‘r9’ can be referenced using the alias ‘lr’. 18599 18600 Floating point operations use the same general purpose registers. 18601The instructions ‘lf.itof.s’ (single precision) and ‘lf.itof.d’ (double 18602precision) can be used to convert integer values to floating point. 18603Likewise, instructions ‘lf.ftoi.s’ (single precision) and ‘lf.ftoi.d’ 18604(double precision) can be used to convert floating point to integer. 18605 18606 OpenRISC also contains privileged special purpose registers (SPRs). 18607The SPRs are accessed using the ‘l.mfspr’ and ‘l.mtspr’ instructions. 18608 18609 18610File: as.info, Node: OpenRISC-Relocs, Prev: OpenRISC-Regs, Up: OpenRISC-Syntax 18611 186129.34.1.3 Relocations 18613.................... 18614 18615ELF relocations are available as defined in the OpenRISC architecture 18616specification. 18617 18618 ‘R_OR1K_HI_16_IN_INSN’ is obtained using ‘hi’ and 18619‘R_OR1K_LO_16_IN_INSN’ and ‘R_OR1K_SLO16’ are obtained using ‘lo’. For 18620signed offsets ‘R_OR1K_AHI16’ is obtained from ‘ha’. For example: 18621 18622 l.movhi r5, hi(symbol) 18623 l.ori r5, r5, lo(symbol) 18624 18625 l.movhi r5, ha(symbol) 18626 l.addi r5, r5, lo(symbol) 18627 18628 These “high” mnemonics extract bits 31:16 of their operand, and the 18629“low” mnemonics extract bits 15:0 of their operand. 18630 18631 The PC relative relocation ‘R_OR1K_GOTPC_HI16’ can be obtained by 18632enclosing an operand inside of ‘gotpchi’. Likewise, the 18633‘R_OR1K_GOTPC_LO16’ relocation can be obtained using ‘gotpclo’. These 18634are mostly used when assembling PIC code. For example, the standard PIC 18635sequence on OpenRISC to get the base of the global offset table, PC 18636relative, into a register, can be performed as: 18637 18638 l.jal 0x8 18639 l.movhi r17, gotpchi(_GLOBAL_OFFSET_TABLE_-4) 18640 l.ori r17, r17, gotpclo(_GLOBAL_OFFSET_TABLE_+0) 18641 l.add r17, r17, r9 18642 18643 Several relocations exist to allow the link editor to perform GOT 18644data references. The ‘R_OR1K_GOT16’ relocation can obtained by 18645enclosing an operand inside of ‘got’. For example, assuming the GOT 18646base is in register ‘r17’. 18647 18648 l.lwz r19, got(a)(r17) 18649 l.lwz r21, 0(r19) 18650 18651 Also, several relocations exist for local GOT references. The 18652‘R_OR1K_GOTOFF_AHI16’ relocation can obtained by enclosing an operand 18653inside of ‘gotoffha’. Likewise, ‘R_OR1K_GOTOFF_LO16’ and 18654‘R_OR1K_GOTOFF_SLO16’ can be obtained by enclosing an operand inside of 18655‘gotofflo’. For example, assuming the GOT base is in register ‘rl7’: 18656 18657 l.movhi r19, gotoffha(symbol) 18658 l.add r19, r19, r17 18659 l.lwz r19, gotofflo(symbol)(r19) 18660 18661 The above PC relative relocations use a ‘l.jal’ (jump) instruction 18662and reading of the link register to load the PC. OpenRISC also supports 18663page offset PC relative locations without a jump instruction using the 18664‘l.adrp’ instruction. By default the ‘l.adrp’ instruction will create 18665an ‘R_OR1K_PCREL_PG21’ relocation. Likewise, ‘BFD_RELOC_OR1K_LO13’ and 18666‘BFD_RELOC_OR1K_SLO13’ can be obtained by enclosing an operand inside of 18667‘po’. For example: 18668 18669 l.adrp r3, symbol 18670 l.ori r4, r3, po(symbol) 18671 l.lbz r5, po(symbol)(r3) 18672 l.sb po(symbol)(r3), r6 18673 18674 Likewise the page offset relocations can be used with GOT references. 18675The relocation ‘R_OR1K_GOT_PG21’ can be obtained by enclosing an 18676‘l.adrp’ immediate operand inside of ‘got’. Likewise, ‘R_OR1K_GOT_LO13’ 18677can be obtained by enclosing an operand inside of ‘gotpo’. For example 18678to load the value of a GOT symbol into register ‘r5’ we can do: 18679 18680 l.adrp r17, got(_GLOBAL_OFFSET_TABLE_) 18681 l.lwz r5, gotpo(symbol)(r17) 18682 18683 There are many relocations that can be requested for access to thread 18684local storage variables. All of the OpenRISC TLS mnemonics are 18685supported: 18686 18687 • ‘R_OR1K_TLS_GD_HI16’ is requested using ‘tlsgdhi’. 18688 • ‘R_OR1K_TLS_GD_LO16’ is requested using ‘tlsgdlo’. 18689 • ‘R_OR1K_TLS_GD_PG21’ is requested using ‘tldgd’. 18690 • ‘R_OR1K_TLS_GD_LO13’ is requested using ‘tlsgdpo’. 18691 18692 • ‘R_OR1K_TLS_LDM_HI16’ is requested using ‘tlsldmhi’. 18693 • ‘R_OR1K_TLS_LDM_LO16’ is requested using ‘tlsldmlo’. 18694 • ‘R_OR1K_TLS_LDM_PG21’ is requested using ‘tldldm’. 18695 • ‘R_OR1K_TLS_LDM_LO13’ is requested using ‘tlsldmpo’. 18696 18697 • ‘R_OR1K_TLS_LDO_HI16’ is requested using ‘dtpoffhi’. 18698 • ‘R_OR1K_TLS_LDO_LO16’ is requested using ‘dtpofflo’. 18699 18700 • ‘R_OR1K_TLS_IE_HI16’ is requested using ‘gottpoffhi’. 18701 • ‘R_OR1K_TLS_IE_AHI16’ is requested using ‘gottpoffha’. 18702 • ‘R_OR1K_TLS_IE_LO16’ is requested using ‘gottpofflo’. 18703 • ‘R_OR1K_TLS_IE_PG21’ is requested using ‘gottp’. 18704 • ‘R_OR1K_TLS_IE_LO13’ is requested using ‘gottppo’. 18705 18706 • ‘R_OR1K_TLS_LE_HI16’ is requested using ‘tpoffhi’. 18707 • ‘R_OR1K_TLS_LE_AHI16’ is requested using ‘tpoffha’. 18708 • ‘R_OR1K_TLS_LE_LO16’ is requested using ‘tpofflo’. 18709 • ‘R_OR1K_TLS_LE_SLO16’ also is requested using ‘tpofflo’ depending 18710 on the instruction format. 18711 18712 Here are some example TLS model sequences. 18713 18714 First, General Dynamic: 18715 18716 l.movhi r17, tlsgdhi(symbol) 18717 l.ori r17, r17, tlsgdlo(symbol) 18718 l.add r17, r17, r16 18719 l.or r3, r17, r17 18720 l.jal plt(__tls_get_addr) 18721 l.nop 18722 18723 Initial Exec: 18724 18725 l.movhi r17, gottpoffhi(symbol) 18726 l.add r17, r17, r16 18727 l.lwz r17, gottpofflo(symbol)(r17) 18728 l.add r17, r17, r10 18729 l.lbs r17, 0(r17) 18730 18731 And finally, Local Exec: 18732 18733 l.movhi r17, tpoffha(symbol) 18734 l.add r17, r17, r10 18735 l.addi r17, r17, tpofflo(symbol) 18736 l.lbs r17, 0(r17) 18737 18738 18739File: as.info, Node: OpenRISC-Float, Next: OpenRISC-Directives, Prev: OpenRISC-Syntax, Up: OpenRISC-Dependent 18740 187419.34.2 Floating Point 18742--------------------- 18743 18744OpenRISC uses IEEE floating-point numbers. 18745 18746 18747File: as.info, Node: OpenRISC-Directives, Next: OpenRISC-Opcodes, Prev: OpenRISC-Float, Up: OpenRISC-Dependent 18748 187499.34.3 OpenRISC Machine Directives 18750---------------------------------- 18751 18752The OpenRISC version of ‘as’ supports the following additional machine 18753directives: 18754 18755‘.align’ 18756 This must be followed by the desired alignment in bytes. 18757 18758‘.word’ 18759 On the OpenRISC, the ‘.word’ directive produces a 32 bit value. 18760 18761‘.nodelay’ 18762 On the OpenRISC, the ‘.nodelay’ directive sets a flag in elf 18763 binaries indicating that the binary is generated catering for no 18764 delay slots. 18765 18766‘.proc’ 18767 This directive is ignored. Any text following it on the same line 18768 is also ignored. 18769 18770‘.endproc’ 18771 This directive is ignored. Any text following it on the same line 18772 is also ignored. 18773 18774 18775File: as.info, Node: OpenRISC-Opcodes, Prev: OpenRISC-Directives, Up: OpenRISC-Dependent 18776 187779.34.4 Opcodes 18778-------------- 18779 18780For detailed information on the OpenRISC machine instruction set, see 18781<http://www.openrisc.io/architecture/>. 18782 18783 ‘as’ implements all the standard OpenRISC opcodes. 18784 18785 18786File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: OpenRISC-Dependent, Up: Machine Dependencies 18787 187889.35 PDP-11 Dependent Features 18789============================== 18790 18791* Menu: 18792 18793* PDP-11-Options:: Options 18794* PDP-11-Pseudos:: Assembler Directives 18795* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 18796* PDP-11-Mnemonics:: Instruction Naming 18797* PDP-11-Synthetic:: Synthetic Instructions 18798 18799 18800File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 18801 188029.35.1 Options 18803-------------- 18804 18805The PDP-11 version of ‘as’ has a rich set of machine dependent options. 18806 188079.35.1.1 Code Generation Options 18808................................ 18809 18810‘-mpic | -mno-pic’ 18811 Generate position-independent (or position-dependent) code. 18812 18813 The default is to generate position-independent code. 18814 188159.35.1.2 Instruction Set Extension Options 18816.......................................... 18817 18818These options enables or disables the use of extensions over the base 18819line instruction set as introduced by the first PDP-11 CPU: the KA11. 18820Most options come in two variants: a ‘-m’EXTENSION that enables 18821EXTENSION, and a ‘-mno-’EXTENSION that disables EXTENSION. 18822 18823 The default is to enable all extensions. 18824 18825‘-mall | -mall-extensions’ 18826 Enable all instruction set extensions. 18827 18828‘-mno-extensions’ 18829 Disable all instruction set extensions. 18830 18831‘-mcis | -mno-cis’ 18832 Enable (or disable) the use of the commercial instruction set, 18833 which consists of these instructions: ‘ADDNI’, ‘ADDN’, ‘ADDPI’, 18834 ‘ADDP’, ‘ASHNI’, ‘ASHN’, ‘ASHPI’, ‘ASHP’, ‘CMPCI’, ‘CMPC’, ‘CMPNI’, 18835 ‘CMPN’, ‘CMPPI’, ‘CMPP’, ‘CVTLNI’, ‘CVTLN’, ‘CVTLPI’, ‘CVTLP’, 18836 ‘CVTNLI’, ‘CVTNL’, ‘CVTNPI’, ‘CVTNP’, ‘CVTPLI’, ‘CVTPL’, ‘CVTPNI’, 18837 ‘CVTPN’, ‘DIVPI’, ‘DIVP’, ‘L2DR’, ‘L3DR’, ‘LOCCI’, ‘LOCC’, ‘MATCI’, 18838 ‘MATC’, ‘MOVCI’, ‘MOVC’, ‘MOVRCI’, ‘MOVRC’, ‘MOVTCI’, ‘MOVTC’, 18839 ‘MULPI’, ‘MULP’, ‘SCANCI’, ‘SCANC’, ‘SKPCI’, ‘SKPC’, ‘SPANCI’, 18840 ‘SPANC’, ‘SUBNI’, ‘SUBN’, ‘SUBPI’, and ‘SUBP’. 18841 18842‘-mcsm | -mno-csm’ 18843 Enable (or disable) the use of the ‘CSM’ instruction. 18844 18845‘-meis | -mno-eis’ 18846 Enable (or disable) the use of the extended instruction set, which 18847 consists of these instructions: ‘ASHC’, ‘ASH’, ‘DIV’, ‘MARK’, 18848 ‘MUL’, ‘RTT’, ‘SOB’ ‘SXT’, and ‘XOR’. 18849 18850‘-mfis | -mkev11’ 18851‘-mno-fis | -mno-kev11’ 18852 Enable (or disable) the use of the KEV11 floating-point 18853 instructions: ‘FADD’, ‘FDIV’, ‘FMUL’, and ‘FSUB’. 18854 18855‘-mfpp | -mfpu | -mfp-11’ 18856‘-mno-fpp | -mno-fpu | -mno-fp-11’ 18857 Enable (or disable) the use of FP-11 floating-point instructions: 18858 ‘ABSF’, ‘ADDF’, ‘CFCC’, ‘CLRF’, ‘CMPF’, ‘DIVF’, ‘LDCFF’, ‘LDCIF’, 18859 ‘LDEXP’, ‘LDF’, ‘LDFPS’, ‘MODF’, ‘MULF’, ‘NEGF’, ‘SETD’, ‘SETF’, 18860 ‘SETI’, ‘SETL’, ‘STCFF’, ‘STCFI’, ‘STEXP’, ‘STF’, ‘STFPS’, ‘STST’, 18861 ‘SUBF’, and ‘TSTF’. 18862 18863‘-mlimited-eis | -mno-limited-eis’ 18864 Enable (or disable) the use of the limited extended instruction 18865 set: ‘MARK’, ‘RTT’, ‘SOB’, ‘SXT’, and ‘XOR’. 18866 18867 The -mno-limited-eis options also implies -mno-eis. 18868 18869‘-mmfpt | -mno-mfpt’ 18870 Enable (or disable) the use of the ‘MFPT’ instruction. 18871 18872‘-mmultiproc | -mno-multiproc’ 18873 Enable (or disable) the use of multiprocessor instructions: 18874 ‘TSTSET’ and ‘WRTLCK’. 18875 18876‘-mmxps | -mno-mxps’ 18877 Enable (or disable) the use of the ‘MFPS’ and ‘MTPS’ instructions. 18878 18879‘-mspl | -mno-spl’ 18880 Enable (or disable) the use of the ‘SPL’ instruction. 18881 18882 Enable (or disable) the use of the microcode instructions: ‘LDUB’, 18883 ‘MED’, and ‘XFC’. 18884 188859.35.1.3 CPU Model Options 18886.......................... 18887 18888These options enable the instruction set extensions supported by a 18889particular CPU, and disables all other extensions. 18890 18891‘-mka11’ 18892 KA11 CPU. Base line instruction set only. 18893 18894‘-mkb11’ 18895 KB11 CPU. Enable extended instruction set and ‘SPL’. 18896 18897‘-mkd11a’ 18898 KD11-A CPU. Enable limited extended instruction set. 18899 18900‘-mkd11b’ 18901 KD11-B CPU. Base line instruction set only. 18902 18903‘-mkd11d’ 18904 KD11-D CPU. Base line instruction set only. 18905 18906‘-mkd11e’ 18907 KD11-E CPU. Enable extended instruction set, ‘MFPS’, and ‘MTPS’. 18908 18909‘-mkd11f | -mkd11h | -mkd11q’ 18910 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction 18911 set, ‘MFPS’, and ‘MTPS’. 18912 18913‘-mkd11k’ 18914 KD11-K CPU. Enable extended instruction set, ‘LDUB’, ‘MED’, ‘MFPS’, 18915 ‘MFPT’, ‘MTPS’, and ‘XFC’. 18916 18917‘-mkd11z’ 18918 KD11-Z CPU. Enable extended instruction set, ‘CSM’, ‘MFPS’, ‘MFPT’, 18919 ‘MTPS’, and ‘SPL’. 18920 18921‘-mf11’ 18922 F11 CPU. Enable extended instruction set, ‘MFPS’, ‘MFPT’, and 18923 ‘MTPS’. 18924 18925‘-mj11’ 18926 J11 CPU. Enable extended instruction set, ‘CSM’, ‘MFPS’, ‘MFPT’, 18927 ‘MTPS’, ‘SPL’, ‘TSTSET’, and ‘WRTLCK’. 18928 18929‘-mt11’ 18930 T11 CPU. Enable limited extended instruction set, ‘MFPS’, and 18931 ‘MTPS’. 18932 189339.35.1.4 Machine Model Options 18934.............................. 18935 18936These options enable the instruction set extensions supported by a 18937particular machine model, and disables all other extensions. 18938 18939‘-m11/03’ 18940 Same as ‘-mkd11f’. 18941 18942‘-m11/04’ 18943 Same as ‘-mkd11d’. 18944 18945‘-m11/05 | -m11/10’ 18946 Same as ‘-mkd11b’. 18947 18948‘-m11/15 | -m11/20’ 18949 Same as ‘-mka11’. 18950 18951‘-m11/21’ 18952 Same as ‘-mt11’. 18953 18954‘-m11/23 | -m11/24’ 18955 Same as ‘-mf11’. 18956 18957‘-m11/34’ 18958 Same as ‘-mkd11e’. 18959 18960‘-m11/34a’ 18961 Ame as ‘-mkd11e’ ‘-mfpp’. 18962 18963‘-m11/35 | -m11/40’ 18964 Same as ‘-mkd11a’. 18965 18966‘-m11/44’ 18967 Same as ‘-mkd11z’. 18968 18969‘-m11/45 | -m11/50 | -m11/55 | -m11/70’ 18970 Same as ‘-mkb11’. 18971 18972‘-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94’ 18973 Same as ‘-mj11’. 18974 18975‘-m11/60’ 18976 Same as ‘-mkd11k’. 18977 18978 18979File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 18980 189819.35.2 Assembler Directives 18982--------------------------- 18983 18984The PDP-11 version of ‘as’ has a few machine dependent assembler 18985directives. 18986 18987‘.bss’ 18988 Switch to the ‘bss’ section. 18989 18990‘.even’ 18991 Align the location counter to an even number. 18992 18993 18994File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 18995 189969.35.3 PDP-11 Assembly Language Syntax 18997-------------------------------------- 18998 18999‘as’ supports both DEC syntax and BSD syntax. The only difference is 19000that in DEC syntax, a ‘#’ character is used to denote an immediate 19001constants, while in BSD syntax the character for this purpose is ‘$’. 19002 19003 general-purpose registers are named ‘r0’ through ‘r7’. Mnemonic 19004alternatives for ‘r6’ and ‘r7’ are ‘sp’ and ‘pc’, respectively. 19005 19006 Floating-point registers are named ‘ac0’ through ‘ac3’, or 19007alternatively ‘fr0’ through ‘fr3’. 19008 19009 Comments are started with a ‘#’ or a ‘/’ character, and extend to the 19010end of the line. (FIXME: clash with immediates?) 19011 19012 Multiple statements on the same line can be separated by the ‘;’ 19013character. 19014 19015 19016File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 19017 190189.35.4 Instruction Naming 19019------------------------- 19020 19021Some instructions have alternative names. 19022 19023‘BCC’ 19024 ‘BHIS’ 19025 19026‘BCS’ 19027 ‘BLO’ 19028 19029‘L2DR’ 19030 ‘L2D’ 19031 19032‘L3DR’ 19033 ‘L3D’ 19034 19035‘SYS’ 19036 ‘TRAP’ 19037 19038 19039File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 19040 190419.35.5 Synthetic Instructions 19042----------------------------- 19043 19044The ‘JBR’ and ‘J’CC synthetic instructions are not supported yet. 19045 19046 19047File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 19048 190499.36 picoJava Dependent Features 19050================================ 19051 19052* Menu: 19053 19054* PJ Options:: Options 19055* PJ Syntax:: PJ Syntax 19056 19057 19058File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 19059 190609.36.1 Options 19061-------------- 19062 19063‘as’ has two additional command-line options for the picoJava 19064architecture. 19065‘-ml’ 19066 This option selects little endian data output. 19067 19068‘-mb’ 19069 This option selects big endian data output. 19070 19071 19072File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent 19073 190749.36.2 PJ Syntax 19075---------------- 19076 19077* Menu: 19078 19079* PJ-Chars:: Special Characters 19080 19081 19082File: as.info, Node: PJ-Chars, Up: PJ Syntax 19083 190849.36.2.1 Special Characters 19085........................... 19086 19087The presence of a ‘!’ or ‘/’ on a line indicates the start of a comment 19088that extends to the end of the current line. 19089 19090 If a ‘#’ appears as the first character of a line then the whole line 19091is treated as a comment, but in this case the line could also be a 19092logical line number directive (*note Comments::) or a preprocessor 19093control command (*note Preprocessing::). 19094 19095 The ‘;’ character can be used to separate statements on the same 19096line. 19097 19098 19099File: as.info, Node: PPC-Dependent, Next: PRU-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 19100 191019.37 PowerPC Dependent Features 19102=============================== 19103 19104* Menu: 19105 19106* PowerPC-Opts:: Options 19107* PowerPC-Pseudo:: PowerPC Assembler Directives 19108* PowerPC-Syntax:: PowerPC Syntax 19109 19110 19111File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 19112 191139.37.1 Options 19114-------------- 19115 19116The PowerPC chip family includes several successive levels, using the 19117same core instruction set, but including a few additional instructions 19118at each level. There are exceptions to this however. For details on 19119what instructions each variant supports, please see the chip’s 19120architecture reference manual. 19121 19122 The following table lists all available PowerPC options. 19123 19124‘-a32’ 19125 Generate ELF32 or XCOFF32. 19126 19127‘-a64’ 19128 Generate ELF64 or XCOFF64. 19129 19130‘-K PIC’ 19131 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 19132 19133‘-mpwrx | -mpwr2’ 19134 Generate code for POWER/2 (RIOS2). 19135 19136‘-mpwr’ 19137 Generate code for POWER (RIOS1) 19138 19139‘-m601’ 19140 Generate code for PowerPC 601. 19141 19142‘-mppc, -mppc32, -m603, -m604’ 19143 Generate code for PowerPC 603/604. 19144 19145‘-m403, -m405’ 19146 Generate code for PowerPC 403/405. 19147 19148‘-m440’ 19149 Generate code for PowerPC 440. BookE and some 405 instructions. 19150 19151‘-m464’ 19152 Generate code for PowerPC 464. 19153 19154‘-m476’ 19155 Generate code for PowerPC 476. 19156 19157‘-m7400, -m7410, -m7450, -m7455’ 19158 Generate code for PowerPC 7400/7410/7450/7455. 19159 19160‘-m750cl, -mgekko, -mbroadway’ 19161 Generate code for PowerPC 750CL/Gekko/Broadway. 19162 19163‘-m821, -m850, -m860’ 19164 Generate code for PowerPC 821/850/860. 19165 19166‘-mppc64, -m620’ 19167 Generate code for PowerPC 620/625/630. 19168 19169‘-me200z2, -me200z4’ 19170 Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE. 19171 19172‘-me300’ 19173 Generate code for PowerPC e300 family. 19174 19175‘-me500, -me500x2’ 19176 Generate code for Motorola e500 core complex. 19177 19178‘-me500mc’ 19179 Generate code for Freescale e500mc core complex. 19180 19181‘-me500mc64’ 19182 Generate code for Freescale e500mc64 core complex. 19183 19184‘-me5500’ 19185 Generate code for Freescale e5500 core complex. 19186 19187‘-me6500’ 19188 Generate code for Freescale e6500 core complex. 19189 19190‘-mlsp’ 19191 Enable LSP instructions. (Disables SPE and SPE2.) 19192 19193‘-mspe’ 19194 Generate code for Motorola SPE instructions. (Disables LSP.) 19195 19196‘-mspe2’ 19197 Generate code for Freescale SPE2 instructions. (Disables LSP.) 19198 19199‘-mtitan’ 19200 Generate code for AppliedMicro Titan core complex. 19201 19202‘-mppc64bridge’ 19203 Generate code for PowerPC 64, including bridge insns. 19204 19205‘-mbooke’ 19206 Generate code for 32-bit BookE. 19207 19208‘-ma2’ 19209 Generate code for A2 architecture. 19210 19211‘-maltivec’ 19212 Generate code for processors with AltiVec instructions. 19213 19214‘-mvle’ 19215 Generate code for Freescale PowerPC VLE instructions. 19216 19217‘-mvsx’ 19218 Generate code for processors with Vector-Scalar (VSX) instructions. 19219 19220‘-mhtm’ 19221 Generate code for processors with Hardware Transactional Memory 19222 instructions. 19223 19224‘-mpower4, -mpwr4’ 19225 Generate code for Power4 architecture. 19226 19227‘-mpower5, -mpwr5, -mpwr5x’ 19228 Generate code for Power5 architecture. 19229 19230‘-mpower6, -mpwr6’ 19231 Generate code for Power6 architecture. 19232 19233‘-mpower7, -mpwr7’ 19234 Generate code for Power7 architecture. 19235 19236‘-mpower8, -mpwr8’ 19237 Generate code for Power8 architecture. 19238 19239‘-mpower9, -mpwr9’ 19240 Generate code for Power9 architecture. 19241 19242‘-mpower10, -mpwr10’ 19243 Generate code for Power10 architecture. 19244 19245‘-mfuture’ 19246 Generate code for ’future’ architecture. 19247 19248‘-mcell’ 19249‘-mcell’ 19250 Generate code for Cell Broadband Engine architecture. 19251 19252‘-mcom’ 19253 Generate code Power/PowerPC common instructions. 19254 19255‘-many’ 19256 Generate code for any architecture (PWR/PWRX/PPC). 19257 19258‘-mregnames’ 19259 Allow symbolic names for registers. 19260 19261‘-mno-regnames’ 19262 Do not allow symbolic names for registers. 19263 19264‘-mrelocatable’ 19265 Support for GCC’s -mrelocatable option. 19266 19267‘-mrelocatable-lib’ 19268 Support for GCC’s -mrelocatable-lib option. 19269 19270‘-memb’ 19271 Set PPC_EMB bit in ELF flags. 19272 19273‘-mlittle, -mlittle-endian, -le’ 19274 Generate code for a little endian machine. 19275 19276‘-mbig, -mbig-endian, -be’ 19277 Generate code for a big endian machine. 19278 19279‘-msolaris’ 19280 Generate code for Solaris. 19281 19282‘-mno-solaris’ 19283 Do not generate code for Solaris. 19284 19285‘-nops=COUNT’ 19286 If an alignment directive inserts more than COUNT nops, put a 19287 branch at the beginning to skip execution of the nops. 19288 19289 19290File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent 19291 192929.37.2 PowerPC Assembler Directives 19293----------------------------------- 19294 19295A number of assembler directives are available for PowerPC. The 19296following table is far from complete. 19297 19298‘.machine "string"’ 19299 This directive allows you to change the machine for which code is 19300 generated. ‘"string"’ may be any of the -m cpu selection options 19301 (without the -m) enclosed in double quotes, ‘"push"’, or ‘"pop"’. 19302 ‘.machine "push"’ saves the currently selected cpu, which may be 19303 restored with ‘.machine "pop"’. 19304 19305 19306File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent 19307 193089.37.3 PowerPC Syntax 19309--------------------- 19310 19311* Menu: 19312 19313* PowerPC-Chars:: Special Characters 19314 19315 19316File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 19317 193189.37.3.1 Special Characters 19319........................... 19320 19321The presence of a ‘#’ on a line indicates the start of a comment that 19322extends to the end of the current line. 19323 19324 If a ‘#’ appears as the first character of a line then the whole line 19325is treated as a comment, but in this case the line could also be a 19326logical line number directive (*note Comments::) or a preprocessor 19327control command (*note Preprocessing::). 19328 19329 If the assembler has been configured for the ppc-*-solaris* target 19330then the ‘!’ character also acts as a line comment character. This can 19331be disabled via the ‘-mno-solaris’ command-line option. 19332 19333 The ‘;’ character can be used to separate statements on the same 19334line. 19335 19336 19337File: as.info, Node: PRU-Dependent, Next: RISC-V-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 19338 193399.38 PRU Dependent Features 19340=========================== 19341 19342* Menu: 19343 19344* PRU Options:: Options 19345* PRU Syntax:: Syntax 19346* PRU Relocations:: Relocations 19347* PRU Directives:: PRU Machine Directives 19348* PRU Opcodes:: Opcodes 19349 19350 19351File: as.info, Node: PRU Options, Next: PRU Syntax, Up: PRU-Dependent 19352 193539.38.1 Options 19354-------------- 19355 19356‘-mlink-relax’ 19357 Assume that LD would optimize LDI32 instructions by checking the 19358 upper 16 bits of the EXPRESSION. If they are all zeros, then LD 19359 would shorten the LDI32 instruction to a single LDI. In such case 19360 ‘as’ will output DIFF relocations for diff expressions. 19361 19362‘-mno-link-relax’ 19363 Assume that LD would not optimize LDI32 instructions. As a 19364 consequence, DIFF relocations will not be emitted. 19365 19366‘-mno-warn-regname-label’ 19367 Do not warn if a label name matches a register name. Usually 19368 assembler programmers will want this warning to be emitted. C 19369 compilers may want to turn this off. 19370 19371 19372File: as.info, Node: PRU Syntax, Next: PRU Relocations, Prev: PRU Options, Up: PRU-Dependent 19373 193749.38.2 Syntax 19375------------- 19376 19377* Menu: 19378 19379* PRU Chars:: Special Characters 19380 19381 19382File: as.info, Node: PRU Chars, Up: PRU Syntax 19383 193849.38.2.1 Special Characters 19385........................... 19386 19387‘#’ and ‘;’ are the line comment characters. 19388 19389 19390File: as.info, Node: PRU Relocations, Next: PRU Directives, Prev: PRU Syntax, Up: PRU-Dependent 19391 193929.38.3 PRU Machine Relocations 19393------------------------------ 19394 19395‘%pmem(EXPRESSION)’ 19396 Convert EXPRESSION from byte-address to a word-address. In other 19397 words, shift right by two. 19398 19399‘%label(EXPRESSION)’ 19400 Mark the given operand as a label. This is useful if you need to 19401 jump to a label that matches a register name. 19402 19403 r1: 19404 jmp r1 ; Will jump to register R1 19405 jmp %label(r1) ; Will jump to label r1 19406 19407 19408File: as.info, Node: PRU Directives, Next: PRU Opcodes, Prev: PRU Relocations, Up: PRU-Dependent 19409 194109.38.4 PRU Machine Directives 19411----------------------------- 19412 19413‘.align EXPRESSION [, EXPRESSION]’ 19414 This is the generic ‘.align’ directive, however this aligns to a 19415 power of two. 19416 19417‘.word EXPRESSION’ 19418 Create an aligned constant 4 bytes in size. 19419 19420‘.dword EXPRESSION’ 19421 Create an aligned constant 8 bytes in size. 19422 19423‘.2byte EXPRESSION’ 19424 Create an unaligned constant 2 bytes in size. 19425 19426‘.4byte EXPRESSION’ 19427 Create an unaligned constant 4 bytes in size. 19428 19429‘.8byte EXPRESSION’ 19430 Create an unaligned constant 8 bytes in size. 19431 19432‘.16byte EXPRESSION’ 19433 Create an unaligned constant 16 bytes in size. 19434 19435‘.set no_warn_regname_label’ 19436 Do not output warnings when a label name matches a register name. 19437 Equivalent to passing the ‘-mno-warn-regname-label’ command-line 19438 option. 19439 19440 19441File: as.info, Node: PRU Opcodes, Prev: PRU Directives, Up: PRU-Dependent 19442 194439.38.5 Opcodes 19444-------------- 19445 19446‘as’ implements all the standard PRU core V3 opcodes in the original 19447pasm assembler. Older cores are not supported by ‘as’. 19448 19449 GAS also implements the LDI32 pseudo instruction for loading a 32-bit 19450immediate value into a register. 19451 19452 ldi32 sp, __stack_top 19453 ldi32 r14, 0x12345678 19454 19455 19456File: as.info, Node: RISC-V-Dependent, Next: RL78-Dependent, Prev: PRU-Dependent, Up: Machine Dependencies 19457 194589.39 RISC-V Dependent Features 19459============================== 19460 19461* Menu: 19462 19463* RISC-V-Options:: RISC-V Options 19464* RISC-V-Directives:: RISC-V Directives 19465* RISC-V-Modifiers:: RISC-V Assembler Modifiers 19466* RISC-V-Floating-Point:: RISC-V Floating Point 19467* RISC-V-Formats:: RISC-V Instruction Formats 19468* RISC-V-ATTRIBUTE:: RISC-V Object Attribute 19469* RISC-V-CustomExts:: RISC-V Custom (Vendor-Defined) Extensions 19470 19471 19472File: as.info, Node: RISC-V-Options, Next: RISC-V-Directives, Up: RISC-V-Dependent 19473 194749.39.1 RISC-V Options 19475--------------------- 19476 19477The following table lists all available RISC-V specific options. 19478 19479‘-fpic’ 19480‘-fPIC’ 19481 Generate position-independent code 19482 19483‘-fno-pic’ 19484 Don’t generate position-independent code (default) 19485 19486‘-march=ISA’ 19487 Select the base isa, as specified by ISA. For example 19488 -march=rv32ima. If this option and the architecture attributes 19489 aren’t set, then assembler will check the default configure setting 19490 –with-arch=ISA. 19491 19492‘-misa-spec=ISAspec’ 19493 Select the default isa spec version. If the version of ISA isn’t 19494 set by -march, then assembler helps to set the version according to 19495 the default chosen spec. If this option isn’t set, then assembler 19496 will check the default configure setting –with-isa-spec=ISAspec. 19497 19498‘-mpriv-spec=PRIVspec’ 19499 Select the privileged spec version. We can decide whether the CSR 19500 is valid or not according to the chosen spec. If this option and 19501 the privilege attributes aren’t set, then assembler will check the 19502 default configure setting –with-priv-spec=PRIVspec. 19503 19504‘-mabi=ABI’ 19505 Selects the ABI, which is either "ilp32" or "lp64", optionally 19506 followed by "f", "d", or "q" to indicate single-precision, 19507 double-precision, or quad-precision floating-point calling 19508 convention, or none or "e" to indicate the soft-float calling 19509 convention ("e" indicates a soft-float RVE ABI). 19510 19511‘-mrelax’ 19512 Take advantage of linker relaxations to reduce the number of 19513 instructions required to materialize symbol addresses. (default) 19514 19515‘-mno-relax’ 19516 Don’t do linker relaxations. 19517 19518‘-march-attr’ 19519 Generate the default contents for the riscv elf attribute section 19520 if the .attribute directives are not set. This section is used to 19521 record the information that a linker or runtime loader needs to 19522 check compatibility. This information includes ISA string, stack 19523 alignment requirement, unaligned memory accesses, and the major, 19524 minor and revision version of privileged specification. 19525 19526‘-mno-arch-attr’ 19527 Don’t generate the default riscv elf attribute section if the 19528 .attribute directives are not set. 19529 19530‘-mcsr-check’ 19531 Enable the CSR checking for the ISA-dependent CRS and the read-only 19532 CSR. The ISA-dependent CSR are only valid when the specific ISA is 19533 set. The read-only CSR can not be written by the CSR instructions. 19534 19535‘-mno-csr-check’ 19536 Don’t do CSR checking. 19537 19538‘-mlittle-endian’ 19539 Generate code for a little endian machine. 19540 19541‘-mbig-endian’ 19542 Generate code for a big endian machine. 19543 19544 19545File: as.info, Node: RISC-V-Directives, Next: RISC-V-Modifiers, Prev: RISC-V-Options, Up: RISC-V-Dependent 19546 195479.39.2 RISC-V Directives 19548------------------------ 19549 19550The following table lists all available RISC-V specific directives. 19551 19552‘.align SIZE-LOG-2’ 19553 Align to the given boundary, with the size given as log2 the number 19554 of bytes to align to. 19555 19556‘.half VALUE’ 19557‘.word VALUE’ 19558‘.dword VALUE’ 19559 Emits a half-word, word, or double-word value at the current 19560 position. 19561 19562‘.dtprelword VALUE’ 19563‘.dtpreldword VALUE’ 19564 Emits a DTP-relative word (or double-word) at the current position. 19565 This is meant to be used by the compiler in shared libraries for 19566 DWARF debug info for thread local variables. 19567 19568‘.uleb128 VALUE’ 19569‘.sleb128 VALUE’ 19570 Emits a signed or unsigned LEB128 value at the current position. 19571 This only accepts constant expressions, because symbol addresses 19572 can change with relaxation, and we don’t support relocations to 19573 modify LEB128 values at link time. 19574 19575‘.option ARGUMENT’ 19576 Modifies RISC-V specific assembler options inline with the assembly 19577 code. This is used when particular instruction sequences must be 19578 assembled with a specific set of options. For example, since we 19579 relax addressing sequences to shorter GP-relative sequences when 19580 possible the initial load of GP must not be relaxed and should be 19581 emitted as something like 19582 19583 .option push 19584 .option norelax 19585 la gp, __global_pointer$ 19586 .option pop 19587 19588 in order to produce after linker relaxation the expected 19589 19590 auipc gp, %pcrel_hi(__global_pointer$) 19591 addi gp, gp, %pcrel_lo(__global_pointer$) 19592 19593 instead of just 19594 19595 addi gp, gp, 0 19596 19597 It’s not expected that options are changed in this manner during 19598 regular use, but there are a handful of esoteric cases like the one 19599 above where users need to disable particular features of the 19600 assembler for particular code sequences. The complete list of 19601 option arguments is shown below: 19602 19603 ‘push’ 19604 ‘pop’ 19605 Pushes or pops the current option stack. These should be used 19606 whenever changing an option in line with assembly code in 19607 order to ensure the user’s command-line options are respected 19608 for the bulk of the file being assembled. 19609 19610 ‘rvc’ 19611 ‘norvc’ 19612 Enables or disables the generation of compressed instructions. 19613 Instructions are opportunistically compressed by the RISC-V 19614 assembler when possible, but sometimes this behavior is not 19615 desirable, especially when handling alignments. 19616 19617 ‘pic’ 19618 ‘nopic’ 19619 Enables or disables position-independent code generation. 19620 Unless you really know what you’re doing, this should only be 19621 at the top of a file. 19622 19623 ‘relax’ 19624 ‘norelax’ 19625 Enables or disables relaxation. The RISC-V assembler and 19626 linker opportunistically relax some code sequences, but 19627 sometimes this behavior is not desirable. 19628 19629 ‘csr-check’ 19630 ‘no-csr-check’ 19631 Enables or disables the CSR checking. 19632 19633 ‘arch, +EXTENSION[VERSION] [,...,+EXTENSION_N[VERSION_N]]’ 19634 ‘arch, -EXTENSION [,...,-EXTENSION_N]’ 19635 ‘arch, =ISA’ 19636 Enables or disables the extensions for specific code region. 19637 For example, ‘.option arch, +m2p0’ means add m extension with 19638 version 2.0, and ‘.option arch, -f, -d’ means remove 19639 extensions, f and d, from the architecture string. Note that, 19640 ‘.option arch, +c, -c’ have the same behavior as ‘.option rvc, 19641 norvc’. However, they are also undesirable sometimes. 19642 Besides, ‘.option arch, -i’ is illegal, since we cannot remove 19643 the base i extension anytime. If you want to reset the whole 19644 ISA string, you can also use ‘.option arch, =rv32imac’ to 19645 overwrite the previous settings. 19646 19647‘.insn TYPE, OPERAND [,...,OPERAND_N]’ 19648‘.insn INSN_LENGTH, VALUE’ 19649‘.insn VALUE’ 19650 This directive permits the numeric representation of an 19651 instructions and makes the assembler insert the operands according 19652 to one of the instruction formats for ‘.insn’ (*note 19653 RISC-V-Formats::). For example, the instruction ‘add a0, a1, a2’ 19654 could be written as ‘.insn r 0x33, 0, 0, a0, a1, a2’. But in fact, 19655 the instruction formats are difficult to use for some users, so 19656 most of them are using ‘.word’ to encode the instruction directly, 19657 rather than using ‘.insn’. It is fine for now, but will be wrong 19658 when the mapping symbols are supported, since ‘.word’ will not be 19659 shown as an instruction, it should be shown as data. Therefore, we 19660 also support two more formats of the ‘.insn’, the instruction ‘add 19661 a0, a1, a2’ could also be written as ‘.insn 0x4, 0xc58533’ or 19662 ‘.insn 0xc58533’. When the INSN_LENGTH is set, then assembler will 19663 check if the VALUE is a valid INSN_LENGTH bytes instruction. 19664 19665‘.attribute TAG, VALUE’ 19666 Set the object attribute TAG to VALUE. 19667 19668 The TAG is either an attribute number, or one of the following: 19669 ‘Tag_RISCV_arch’, ‘Tag_RISCV_stack_align’, 19670 ‘Tag_RISCV_unaligned_access’, ‘Tag_RISCV_priv_spec’, 19671 ‘Tag_RISCV_priv_spec_minor’, ‘Tag_RISCV_priv_spec_revision’. 19672 19673 19674File: as.info, Node: RISC-V-Modifiers, Next: RISC-V-Floating-Point, Prev: RISC-V-Directives, Up: RISC-V-Dependent 19675 196769.39.3 RISC-V Assembler Modifiers 19677--------------------------------- 19678 19679The RISC-V assembler supports following modifiers for relocatable 19680addresses used in RISC-V instruction operands. However, we also support 19681some pseudo instructions that are easier to use than these modifiers. 19682 19683‘%lo(SYMBOL)’ 19684 The low 12 bits of absolute address for SYMBOL. 19685 19686‘%hi(SYMBOL)’ 19687 The high 20 bits of absolute address for SYMBOL. This is usually 19688 used with the %lo modifier to represent a 32-bit absolute address. 19689 19690 lui a0, %hi(SYMBOL) // R_RISCV_HI20 19691 addi a0, a0, %lo(SYMBOL) // R_RISCV_LO12_I 19692 19693 lui a0, %hi(SYMBOL) // R_RISCV_HI20 19694 load/store a0, %lo(SYMBOL)(a0) // R_RISCV_LO12_I/S 19695 19696‘%pcrel_lo(LABEL)’ 19697 The low 12 bits of relative address between pc and SYMBOL. The 19698 SYMBOL is related to the high part instruction which is marked by 19699 LABEL. 19700 19701‘%pcrel_hi(SYMBOL)’ 19702 The high 20 bits of relative address between pc and SYMBOL. This 19703 is usually used with the %pcrel_lo modifier to represent a +/-2GB 19704 pc-relative range. 19705 19706 LABEL: 19707 auipc a0, %pcrel_hi(SYMBOL) // R_RISCV_PCREL_HI20 19708 addi a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I 19709 19710 LABEL: 19711 auipc a0, %pcrel_hi(SYMBOL) // R_RISCV_PCREL_HI20 19712 load/store a0, %pcrel_lo(LABEL)(a0) // R_RISCV_PCREL_LO12_I/S 19713 19714 Or you can use the pseudo lla/lw/sw/... instruction to do this. 19715 19716 lla a0, SYMBOL 19717 19718‘%got_pcrel_hi(SYMBOL)’ 19719 The high 20 bits of relative address between pc and the GOT entry 19720 of SYMBOL. This is usually used with the %pcrel_lo modifier to 19721 access the GOT entry. 19722 19723 LABEL: 19724 auipc a0, %got_pcrel_hi(SYMBOL) // R_RISCV_GOT_HI20 19725 addi a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I 19726 19727 LABEL: 19728 auipc a0, %got_pcrel_hi(SYMBOL) // R_RISCV_GOT_HI20 19729 load/store a0, %pcrel_lo(LABEL)(a0) // R_RISCV_PCREL_LO12_I/S 19730 19731 Also, the pseudo la instruction with PIC has similar behavior. 19732 19733‘%tprel_add(SYMBOL)’ 19734 This is used purely to associate the R_RISCV_TPREL_ADD relocation 19735 for TLS relaxation. This one is only valid as the fourth operand 19736 to the normally 3 operand add instruction. 19737 19738‘%tprel_lo(SYMBOL)’ 19739 The low 12 bits of relative address between tp and SYMBOL. 19740 19741‘%tprel_hi(SYMBOL)’ 19742 The high 20 bits of relative address between tp and SYMBOL. This 19743 is usually used with the %tprel_lo and %tprel_add modifiers to 19744 access the thread local variable SYMBOL in TLS Local Exec. 19745 19746 lui a5, %tprel_hi(SYMBOL) // R_RISCV_TPREL_HI20 19747 add a5, a5, tp, %tprel_add(SYMBOL) // R_RISCV_TPREL_ADD 19748 load/store t0, %tprel_lo(SYMBOL)(a5) // R_RISCV_TPREL_LO12_I/S 19749 19750‘%tls_ie_pcrel_hi(SYMBOL)’ 19751 The high 20 bits of relative address between pc and GOT entry. It 19752 is usually used with the %pcrel_lo modifier to access the thread 19753 local variable SYMBOL in TLS Initial Exec. 19754 19755 la.tls.ie a5, SYMBOL 19756 add a5, a5, tp 19757 load/store t0, 0(a5) 19758 19759 The pseudo la.tls.ie instruction can be expended to 19760 19761 LABEL: 19762 auipc a5, %tls_ie_pcrel_hi(SYMBOL) // R_RISCV_TLS_GOT_HI20 19763 load a5, %pcrel_lo(LABEL)(a5) // R_RISCV_PCREL_LO12_I 19764 19765‘%tls_gd_pcrel_hi(SYMBOL)’ 19766 The high 20 bits of relative address between pc and GOT entry. It 19767 is usually used with the %pcrel_lo modifier to access the thread 19768 local variable SYMBOL in TLS Global Dynamic. 19769 19770 la.tls.gd a0, SYMBOL 19771 call __tls_get_addr@plt 19772 mv a5, a0 19773 load/store t0, 0(a5) 19774 19775 The pseudo la.tls.gd instruction can be expended to 19776 19777 LABEL: 19778 auipc a0, %tls_gd_pcrel_hi(SYMBOL) // R_RISCV_TLS_GD_HI20 19779 addi a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I 19780 19781 19782File: as.info, Node: RISC-V-Floating-Point, Next: RISC-V-Formats, Prev: RISC-V-Modifiers, Up: RISC-V-Dependent 19783 197849.39.4 RISC-V Floating Point 19785---------------------------- 19786 19787The RISC-V architecture uses IEEE floating-point numbers. 19788 19789 The RISC-V Zfa extension includes a load-immediate instruction for 19790floating-point registers, which allows specifying the immediate (from a 19791pool of 32 predefined values defined in the specification) as operand. 19792E.g. to load the value ‘0.0625’ as single-precision FP value into the 19793FP register ‘ft1’ one of the following instructions can be used: 19794 19795 fli.s ft1, 0.0625 # dec floating-point literal fli.s ft1, 0x1p-4 # 19796hex floating-point literal fli.s ft1, 0x0.8p-3 fli.s ft1, 0x1.0p-4 fli.s 19797ft1, 0x2p-5 fli.s ft1, 0x4p-6 ... 19798 19799 As can be seen, many valid ways exist to express a floating-point 19800value. This is realized by parsing the value operand using strtof() and 19801comparing the parsed value against built-in float-constants that are 19802written as hex floating-point literals. 19803 19804 This approach works on all machines that use IEEE 754. However, 19805there is a chance that this fails on other machines with the following 19806error message: 19807 19808 Error: improper fli value operand Error: illegal operands ‘fli.s 19809ft1,0.0625 19810 19811 The error indicates that parsing ‘0x1p-4’ and ‘0.0625’ to 19812single-precision floating point numbers will not result in two equal 19813values on that machine. 19814 19815 If you encounter this problem, then please report it. 19816 19817 19818File: as.info, Node: RISC-V-Formats, Next: RISC-V-ATTRIBUTE, Prev: RISC-V-Floating-Point, Up: RISC-V-Dependent 19819 198209.39.5 RISC-V Instruction Formats 19821--------------------------------- 19822 19823The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15 19824instruction formats where some of the formats have multiple variants. 19825For the ‘.insn’ pseudo directive the assembler recognizes some of the 19826formats. Typically, the most general variant of the instruction format 19827is used by the ‘.insn’ directive. 19828 19829 The following table lists the abbreviations used in the table of 19830instruction formats: 19831 19832 opcode Unsigned immediate or opcode name for 7-bits opcode. 19833 opcode2 Unsigned immediate or opcode name for 2-bits opcode. 19834 func7 Unsigned immediate for 7-bits function code. 19835 func6 Unsigned immediate for 6-bits function code. 19836 func4 Unsigned immediate for 4-bits function code. 19837 func3 Unsigned immediate for 3-bits function code. 19838 func2 Unsigned immediate for 2-bits function code. 19839 rd Destination register number for operand x, can be GPR or FPR. 19840 rd’ Destination register number for operand x, 19841 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 19842 rs1 First source register number for operand x, can be GPR or FPR. 19843 rs1’ First source register number for operand x, 19844 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 19845 rs2 Second source register number for operand x, can be GPR or FPR. 19846 rs2’ Second source register number for operand x, 19847 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 19848 simm12 Sign-extended 12-bit immediate for operand x. 19849 simm20 Sign-extended 20-bit immediate for operand x. 19850 simm6 Sign-extended 6-bit immediate for operand x. 19851 uimm5 Unsigned 5-bit immediate for operand x. 19852 uimm6 Unsigned 6-bit immediate for operand x. 19853 uimm8 Unsigned 8-bit immediate for operand x. 19854 symbol Symbol or label reference for operand x. 19855 19856 The following table lists all available opcode name: 19857 19858‘C0’ 19859‘C1’ 19860‘C2’ 19861 Opcode space for compressed instructions. 19862 19863‘LOAD’ 19864 Opcode space for load instructions. 19865 19866‘LOAD_FP’ 19867 Opcode space for floating-point load instructions. 19868 19869‘STORE’ 19870 Opcode space for store instructions. 19871 19872‘STORE_FP’ 19873 Opcode space for floating-point store instructions. 19874 19875‘AUIPC’ 19876 Opcode space for auipc instruction. 19877 19878‘LUI’ 19879 Opcode space for lui instruction. 19880 19881‘BRANCH’ 19882 Opcode space for branch instructions. 19883 19884‘JAL’ 19885 Opcode space for jal instruction. 19886 19887‘JALR’ 19888 Opcode space for jalr instruction. 19889 19890‘OP’ 19891 Opcode space for ALU instructions. 19892 19893‘OP_32’ 19894 Opcode space for 32-bits ALU instructions. 19895 19896‘OP_IMM’ 19897 Opcode space for ALU with immediate instructions. 19898 19899‘OP_IMM_32’ 19900 Opcode space for 32-bits ALU with immediate instructions. 19901 19902‘OP_FP’ 19903 Opcode space for floating-point operation instructions. 19904 19905‘MADD’ 19906 Opcode space for madd instruction. 19907 19908‘MSUB’ 19909 Opcode space for msub instruction. 19910 19911‘NMADD’ 19912 Opcode space for nmadd instruction. 19913 19914‘NMSUB’ 19915 Opcode space for msub instruction. 19916 19917‘AMO’ 19918 Opcode space for atomic memory operation instructions. 19919 19920‘MISC_MEM’ 19921 Opcode space for misc instructions. 19922 19923‘SYSTEM’ 19924 Opcode space for system instructions. 19925 19926‘CUSTOM_0’ 19927‘CUSTOM_1’ 19928‘CUSTOM_2’ 19929‘CUSTOM_3’ 19930 Opcode space for customize instructions. 19931 19932 An instruction is two or four bytes in length and must be aligned on 19933a 2 byte boundary. The first two bits of the instruction specify the 19934length of the instruction, 00, 01 and 10 indicates a two byte 19935instruction, 11 indicates a four byte instruction. 19936 19937 The following table lists the RISC-V instruction formats that are 19938available with the ‘.insn’ pseudo directive: 19939 19940‘R type: .insn r opcode6, func3, func7, rd, rs1, rs2’ 19941 +-------+-----+-----+-------+----+---------+ 19942 | func7 | rs2 | rs1 | func3 | rd | opcode6 | 19943 +-------+-----+-----+-------+----+---------+ 19944 31 25 20 15 12 7 0 19945 19946‘R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3’ 19947‘R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3’ 19948 +-----+-------+-----+-----+-------+----+---------+ 19949 | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 | 19950 +-----+-------+-----+-----+-------+----+---------+ 19951 31 27 25 20 15 12 7 0 19952 19953‘I type: .insn i opcode6, func3, rd, rs1, simm12’ 19954‘I type: .insn i opcode6, func3, rd, simm12(rs1)’ 19955 +--------------+-----+-------+----+---------+ 19956 | simm12[11:0] | rs1 | func3 | rd | opcode6 | 19957 +--------------+-----+-------+----+---------+ 19958 31 20 15 12 7 0 19959 19960‘S type: .insn s opcode6, func3, rs2, simm12(rs1)’ 19961 +--------------+-----+-----+-------+-------------+---------+ 19962 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 | 19963 +--------------+-----+-----+-------+-------------+---------+ 19964 31 25 20 15 12 7 0 19965 19966‘B type: .insn s opcode6, func3, rs1, rs2, symbol’ 19967‘SB type: .insn sb opcode6, func3, rs1, rs2, symbol’ 19968 +-----------------+-----+-----+-------+----------------+---------+ 19969 | simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 | 19970 +-----------------+-----+-----+-------+----------------+---------+ 19971 31 25 20 15 12 7 0 19972 19973‘U type: .insn u opcode6, rd, simm20’ 19974 +--------------------------+----+---------+ 19975 | simm20[20|10:1|11|19:12] | rd | opcode6 | 19976 +--------------------------+----+---------+ 19977 31 12 7 0 19978 19979‘J type: .insn j opcode6, rd, symbol’ 19980‘UJ type: .insn uj opcode6, rd, symbol’ 19981 +------------+--------------+------------+---------------+----+---------+ 19982 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 | 19983 +------------+--------------+------------+---------------+----+---------+ 19984 31 30 21 20 12 7 0 19985 19986‘CR type: .insn cr opcode2, func4, rd, rs2’ 19987 +-------+--------+-----+---------+ 19988 | func4 | rd/rs1 | rs2 | opcode2 | 19989 +-------+--------+-----+---------+ 19990 15 12 7 2 0 19991 19992‘CI type: .insn ci opcode2, func3, rd, simm6’ 19993 +-------+----------+--------+------------+---------+ 19994 | func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 | 19995 +-------+----------+--------+------------+---------+ 19996 15 13 12 7 2 0 19997 19998‘CIW type: .insn ciw opcode2, func3, rd', uimm8’ 19999 +-------+------------+-----+---------+ 20000 | func3 | uimm8[7:0] | rd' | opcode2 | 20001 +-------+-------- ---+-----+---------+ 20002 15 13 5 2 0 20003 20004‘CSS type: .insn css opcode2, func3, rd, uimm6’ 20005 +-------+------------+----+---------+ 20006 | func3 | uimm6[5:0] | rd | opcode2 | 20007 +-------+------------+----+---------+ 20008 15 13 7 2 0 20009 20010‘CL type: .insn cl opcode2, func3, rd', uimm5(rs1')’ 20011 +-------+------------+------+------------+------+---------+ 20012 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 | 20013 +-------+------------+------+------------+------+---------+ 20014 15 13 10 7 5 2 0 20015 20016‘CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')’ 20017 +-------+------------+------+------------+------+---------+ 20018 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 | 20019 +-------+------------+------+------------+------+---------+ 20020 15 13 10 7 5 2 0 20021 20022‘CA type: .insn ca opcode2, func6, func2, rd', rs2'’ 20023 +-- ----+----------+-------+------+---------+ 20024 | func6 | rd'/rs1' | func2 | rs2' | opcode2 | 20025 +-------+----------+-------+------+---------+ 20026 15 10 7 5 2 0 20027 20028‘CB type: .insn cb opcode2, func3, rs1', symbol’ 20029 +-------+--------------+------+------------------+---------+ 20030 | func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 | 20031 +-------+--------------+------+------------------+---------+ 20032 15 13 10 7 2 0 20033 20034‘CJ type: .insn cj opcode2, symbol’ 20035 +-------+-------------------------------+---------+ 20036 | func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 | 20037 +-------+-------------------------------+---------+ 20038 15 13 2 0 20039 20040 For the complete list of all instruction format variants see The 20041RISC-V Instruction Set Manual Volume I: User-Level ISA. 20042 20043 20044File: as.info, Node: RISC-V-ATTRIBUTE, Next: RISC-V-CustomExts, Prev: RISC-V-Formats, Up: RISC-V-Dependent 20045 200469.39.6 RISC-V Object Attribute 20047------------------------------ 20048 20049RISC-V attributes have a string value if the tag number is odd and an 20050integer value if the tag number is even. 20051 20052Tag_RISCV_stack_align (4) 20053 Tag_RISCV_strict_align records the N-byte stack alignment for this 20054 object. The default value is 16 for RV32I or RV64I, and 4 for 20055 RV32E. 20056 20057 The smallest value will be used if object files with different 20058 Tag_RISCV_stack_align values are merged. 20059 20060Tag_RISCV_arch (5) 20061 Tag_RISCV_arch contains a string for the target architecture taken 20062 from the option ‘-march’. Different architectures will be 20063 integrated into a superset when object files are merged. 20064 20065 Note that the version information of the target architecture must 20066 be presented explicitly in the attribute and abbreviations must be 20067 expanded. The version information, if not given by ‘-march’, must 20068 be in accordance with the default specified by the tool. For 20069 example, the architecture ‘RV32I’ has to be recorded in the 20070 attribute as ‘RV32I2P0’ in which ‘2P0’ stands for the default 20071 version of its base ISA. On the other hand, the architecture 20072 ‘RV32G’ has to be presented as ‘RV32I2P0_M2P0_A2P0_F2P0_D2P0’ in 20073 which the abbreviation ‘G’ is expanded to the ‘IMAFD’ combination 20074 with default versions of the standard extensions. 20075 20076Tag_RISCV_unaligned_access (6) 20077 Tag_RISCV_unaligned_access is 0 for files that do not allow any 20078 unaligned memory accesses, and 1 for files that do allow unaligned 20079 memory accesses. 20080 20081Tag_RISCV_priv_spec (8) 20082Tag_RISCV_priv_spec_minor (10) 20083Tag_RISCV_priv_spec_revision (12) 20084 Tag_RISCV_priv_spec contains the major/minor/revision version 20085 information of the privileged specification. It will report errors 20086 if object files of different privileged specification versions are 20087 merged. 20088 20089 20090File: as.info, Node: RISC-V-CustomExts, Prev: RISC-V-ATTRIBUTE, Up: RISC-V-Dependent 20091 200929.39.7 RISC-V Custom (Vendor-Defined) Extensions 20093------------------------------------------------ 20094 20095The following table lists the custom (vendor-defined) RISC-V extensions 20096supported and provides the location of their publicly-released 20097documentation: 20098 20099Xcvmac 20100 The Xcvmac extension provides instructions for multiply-accumulate 20101 operations. 20102 20103 It is documented in 20104 <https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html> 20105 20106Xcvalu 20107 The Xcvalu extension provides instructions for general ALU 20108 operations. 20109 20110 It is documented in 20111 <https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html> 20112 20113XTheadBa 20114 The XTheadBa extension provides instructions for address 20115 calculations. 20116 20117 It is documented in 20118 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20119 20120XTheadBb 20121 The XTheadBb extension provides instructions for basic 20122 bit-manipulation 20123 20124 It is documented in 20125 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20126 20127XTheadBs 20128 The XTheadBs extension provides single-bit instructions. 20129 20130 It is documented in 20131 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20132 20133XTheadCmo 20134 The XTheadCmo extension provides instructions for cache management. 20135 20136 It is documented in 20137 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20138 20139XTheadCondMov 20140 The XTheadCondMov extension provides instructions for conditional 20141 moves. 20142 20143 It is documented in 20144 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20145 20146XTheadFMemIdx 20147 The XTheadFMemIdx extension provides floating-point memory 20148 operations. 20149 20150 It is documented in 20151 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20152 20153XTheadFmv 20154 The XTheadFmv extension provides access to the upper 32 bits of a 20155 doulbe-precision floating point register. 20156 20157 It is documented in 20158 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf>. 20159 20160XTheadInt 20161 The XTheadInt extension provides access to ISR stack management 20162 instructions. 20163 20164 It is documented in 20165 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf>. 20166 20167XTheadMac 20168 The XTheadMac extension provides multiply-accumulate instructions. 20169 20170 It is documented in 20171 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20172 20173XTheadMemIdx 20174 The XTheadMemIdx extension provides GPR memory operations. 20175 20176 It is documented in 20177 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20178 20179XTheadMemPair 20180 The XTheadMemPair extension provides two-GP-register memory 20181 operations. 20182 20183 It is documented in 20184 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20185 20186XTheadSync 20187 The XTheadSync extension provides instructions for multi-processor 20188 synchronization. 20189 20190 It is documented in 20191 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf>. 20192 20193XTheadVector 20194 The XTheadVector extension provides instructions for thead vector. 20195 20196 It is documented in 20197 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf>. 20198 20199XTheadZvamo 20200 The XTheadZvamo extension is a subextension of the XTheadVector 20201 extension, and it provides AMO instructions for the T-Head VECTOR 20202 vendor extension. 20203 20204 It is documented in 20205 <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf>. 20206 20207XVentanaCondOps 20208 XVentanaCondOps extension provides instructions for branchless 20209 sequences that perform conditional arithmetic, conditional 20210 bitwise-logic, and conditional select operations. 20211 20212 It is documented in 20213 <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>. 20214 20215XSfVcp 20216 The XSfVcp (VCIX) extension provides flexible instructions for 20217 extending vector coprocessor. To accelerate performance, system 20218 designers may use VCIX as a low-latency, high-throughput interface 20219 to a coprocessor. 20220 20221 It is documented in 20222 <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>. 20223 20224 20225File: as.info, Node: RL78-Dependent, Next: RX-Dependent, Prev: RISC-V-Dependent, Up: Machine Dependencies 20226 202279.40 RL78 Dependent Features 20228============================ 20229 20230* Menu: 20231 20232* RL78-Opts:: RL78 Assembler Command-line Options 20233* RL78-Modifiers:: Symbolic Operand Modifiers 20234* RL78-Directives:: Assembler Directives 20235* RL78-Syntax:: Syntax 20236 20237 20238File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent 20239 202409.40.1 RL78 Options 20241------------------- 20242 20243‘relax’ 20244 Enable support for link-time relaxation. 20245 20246‘norelax’ 20247 Disable support for link-time relaxation (default). 20248 20249‘mg10’ 20250 Mark the generated binary as targeting the G10 variant of the RL78 20251 architecture. 20252 20253‘mg13’ 20254 Mark the generated binary as targeting the G13 variant of the RL78 20255 architecture. 20256 20257‘mg14’ 20258‘mrl78’ 20259 Mark the generated binary as targeting the G14 variant of the RL78 20260 architecture. This is the default. 20261 20262‘m32bit-doubles’ 20263 Mark the generated binary as one that uses 32-bits to hold the 20264 ‘double’ floating point type. This is the default. 20265 20266‘m64bit-doubles’ 20267 Mark the generated binary as one that uses 64-bits to hold the 20268 ‘double’ floating point type. 20269 20270 20271File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent 20272 202739.40.2 Symbolic Operand Modifiers 20274--------------------------------- 20275 20276The RL78 has three modifiers that adjust the relocations used by the 20277linker: 20278 20279‘%lo16()’ 20280 20281 When loading a 20-bit (or wider) address into registers, this 20282 modifier selects the 16 least significant bits. 20283 20284 movw ax,#%lo16(_sym) 20285 20286‘%hi16()’ 20287 20288 When loading a 20-bit (or wider) address into registers, this 20289 modifier selects the 16 most significant bits. 20290 20291 movw ax,#%hi16(_sym) 20292 20293‘%hi8()’ 20294 20295 When loading a 20-bit (or wider) address into registers, this 20296 modifier selects the 8 bits that would go into CS or ES (i.e. bits 20297 23..16). 20298 20299 mov es, #%hi8(_sym) 20300 20301 20302File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent 20303 203049.40.3 Assembler Directives 20305--------------------------- 20306 20307In addition to the common directives, the RL78 adds these: 20308 20309‘.double’ 20310 Output a constant in “double” format, which is either a 32-bit or a 20311 64-bit floating point value, depending upon the setting of the 20312 ‘-m32bit-doubles’|‘-m64bit-doubles’ command-line option. 20313 20314‘.bss’ 20315 Select the BSS section. 20316 20317‘.3byte’ 20318 Output a constant value in a three byte format. 20319 20320‘.int’ 20321‘.word’ 20322 Output a constant value in a four byte format. 20323 20324 20325File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent 20326 203279.40.4 Syntax for the RL78 20328-------------------------- 20329 20330* Menu: 20331 20332* RL78-Chars:: Special Characters 20333 20334 20335File: as.info, Node: RL78-Chars, Up: RL78-Syntax 20336 203379.40.4.1 Special Characters 20338........................... 20339 20340The presence of a ‘;’ appearing anywhere on a line indicates the start 20341of a comment that extends to the end of that line. 20342 20343 If a ‘#’ appears as the first character of a line then the whole line 20344is treated as a comment, but in this case the line can also be a logical 20345line number directive (*note Comments::) or a preprocessor control 20346command (*note Preprocessing::). 20347 20348 The ‘|’ character can be used to separate statements on the same 20349line. 20350 20351 20352File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies 20353 203549.41 RX Dependent Features 20355========================== 20356 20357* Menu: 20358 20359* RX-Opts:: RX Assembler Command-line Options 20360* RX-Modifiers:: Symbolic Operand Modifiers 20361* RX-Directives:: Assembler Directives 20362* RX-Float:: Floating Point 20363* RX-Syntax:: Syntax 20364 20365 20366File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 20367 203689.41.1 RX Options 20369----------------- 20370 20371The Renesas RX port of ‘as’ has a few target specific command-line 20372options: 20373 20374‘-m32bit-doubles’ 20375 This option controls the ABI and indicates to use a 32-bit float 20376 ABI. It has no effect on the assembled instructions, but it does 20377 influence the behaviour of the ‘.double’ pseudo-op. This is the 20378 default. 20379 20380‘-m64bit-doubles’ 20381 This option controls the ABI and indicates to use a 64-bit float 20382 ABI. It has no effect on the assembled instructions, but it does 20383 influence the behaviour of the ‘.double’ pseudo-op. 20384 20385‘-mbig-endian’ 20386 This option controls the ABI and indicates to use a big-endian data 20387 ABI. It has no effect on the assembled instructions, but it does 20388 influence the behaviour of the ‘.short’, ‘.hword’, ‘.int’, ‘.word’, 20389 ‘.long’, ‘.quad’ and ‘.octa’ pseudo-ops. 20390 20391‘-mlittle-endian’ 20392 This option controls the ABI and indicates to use a little-endian 20393 data ABI. It has no effect on the assembled instructions, but it 20394 does influence the behaviour of the ‘.short’, ‘.hword’, ‘.int’, 20395 ‘.word’, ‘.long’, ‘.quad’ and ‘.octa’ pseudo-ops. This is the 20396 default. 20397 20398‘-muse-conventional-section-names’ 20399 This option controls the default names given to the code (.text), 20400 initialised data (.data) and uninitialised data sections (.bss). 20401 20402‘-muse-renesas-section-names’ 20403 This option controls the default names given to the code (P), 20404 initialised data (D_1) and uninitialised data sections (B_1). This 20405 is the default. 20406 20407‘-msmall-data-limit’ 20408 This option tells the assembler that the small data limit feature 20409 of the RX port of GCC is being used. This results in the assembler 20410 generating an undefined reference to a symbol called ‘__gp’ for use 20411 by the relocations that are needed to support the small data limit 20412 feature. This option is not enabled by default as it would 20413 otherwise pollute the symbol table. 20414 20415‘-mpid’ 20416 This option tells the assembler that the position independent data 20417 of the RX port of GCC is being used. This results in the assembler 20418 generating an undefined reference to a symbol called ‘__pid_base’, 20419 and also setting the RX_PID flag bit in the e_flags field of the 20420 ELF header of the object file. 20421 20422‘-mint-register=NUM’ 20423 This option tells the assembler how many registers have been 20424 reserved for use by interrupt handlers. This is needed in order to 20425 compute the correct values for the ‘%gpreg’ and ‘%pidreg’ meta 20426 registers. 20427 20428‘-mgcc-abi’ 20429 This option tells the assembler that the old GCC ABI is being used 20430 by the assembled code. With this version of the ABI function 20431 arguments that are passed on the stack are aligned to a 32-bit 20432 boundary. 20433 20434‘-mrx-abi’ 20435 This option tells the assembler that the official RX ABI is being 20436 used by the assembled code. With this version of the ABI function 20437 arguments that are passed on the stack are aligned to their natural 20438 alignments. This option is the default. 20439 20440‘-mcpu=NAME’ 20441 This option tells the assembler the target CPU type. Currently the 20442 ‘rx100’, ‘rx200’, ‘rx600’, ‘rx610’, ‘rxv2’, ‘rxv3’ and ‘rxv3-dfpu’ 20443 are recognised as valid cpu names. Attempting to assemble an 20444 instructionnot supported by the indicated cpu type will result in 20445 an error message being generated. 20446 20447‘-mno-allow-string-insns’ 20448 This option tells the assembler to mark the object file that it is 20449 building as one that does not use the string instructions ‘SMOVF’, 20450 ‘SCMPU’, ‘SMOVB’, ‘SMOVU’, ‘SUNTIL’ ‘SWHILE’ or the ‘RMPA’ 20451 instruction. In addition the mark tells the linker to complain if 20452 an attempt is made to link the binary with another one that does 20453 use any of these instructions. 20454 20455 Note - the inverse of this option, ‘-mallow-string-insns’, is not 20456 needed. The assembler automatically detects the use of the the 20457 instructions in the source code and labels the resulting object 20458 file appropriately. If no string instructions are detected then 20459 the object file is labelled as being one that can be linked with 20460 either string-using or string-banned object files. 20461 20462 20463File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 20464 204659.41.2 Symbolic Operand Modifiers 20466--------------------------------- 20467 20468The assembler supports one modifier when using symbol addresses in RX 20469instruction operands. The general syntax is the following: 20470 20471 %gp(symbol) 20472 20473 The modifier returns the offset from the __GP symbol to the specified 20474symbol as a 16-bit value. The intent is that this offset should be used 20475in a register+offset move instruction when generating references to 20476small data. Ie, like this: 20477 20478 mov.W %gp(_foo)[%gpreg], r1 20479 20480 The assembler also supports two meta register names which can be used 20481to refer to registers whose values may not be known to the programmer. 20482These meta register names are: 20483 20484‘%gpreg’ 20485 The small data address register. 20486 20487‘%pidreg’ 20488 The PID base address register. 20489 20490 Both registers normally have the value r13, but this can change if 20491some registers have been reserved for use by interrupt handlers or if 20492both the small data limit and position independent data features are 20493being used at the same time. 20494 20495 20496File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 20497 204989.41.3 Assembler Directives 20499--------------------------- 20500 20501The RX version of ‘as’ has the following specific assembler directives: 20502 20503‘.3byte’ 20504 Inserts a 3-byte value into the output file at the current 20505 location. 20506 20507‘.fetchalign’ 20508 If the next opcode following this directive spans a fetch line 20509 boundary (8 byte boundary), the opcode is aligned to that boundary. 20510 If the next opcode does not span a fetch line, this directive has 20511 no effect. Note that one or more labels may be between this 20512 directive and the opcode; those labels are aligned as well. Any 20513 inserted bytes due to alignment will form a NOP opcode. 20514 20515 20516File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent 20517 205189.41.4 Floating Point 20519--------------------- 20520 20521The floating point formats generated by directives are these. 20522 20523‘.float’ 20524 ‘Single’ precision (32-bit) floating point constants. 20525 20526‘.double’ 20527 If the ‘-m64bit-doubles’ command-line option has been specified 20528 then then ‘double’ directive generates ‘double’ precision (64-bit) 20529 floating point constants, otherwise it generates ‘single’ precision 20530 (32-bit) floating point constants. To force the generation of 20531 64-bit floating point constants used the ‘dc.d’ directive instead. 20532 20533 20534File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent 20535 205369.41.5 Syntax for the RX 20537------------------------ 20538 20539* Menu: 20540 20541* RX-Chars:: Special Characters 20542 20543 20544File: as.info, Node: RX-Chars, Up: RX-Syntax 20545 205469.41.5.1 Special Characters 20547........................... 20548 20549The presence of a ‘;’ appearing anywhere on a line indicates the start 20550of a comment that extends to the end of that line. 20551 20552 If a ‘#’ appears as the first character of a line then the whole line 20553is treated as a comment, but in this case the line can also be a logical 20554line number directive (*note Comments::) or a preprocessor control 20555command (*note Preprocessing::). 20556 20557 The ‘!’ character can be used to separate statements on the same 20558line. 20559 20560 20561File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 20562 205639.42 IBM S/390 Dependent Features 20564================================= 20565 20566The s390 version of ‘as’ supports two architectures modes and eleven 20567chip levels. The architecture modes are the Enterprise System 20568Architecture (ESA) and the newer z/Architecture mode. The chip levels 20569are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec 20570(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or 20571arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14). 20572 20573* Menu: 20574 20575* s390 Options:: Command-line Options. 20576* s390 Characters:: Special Characters. 20577* s390 Syntax:: Assembler Instruction syntax. 20578* s390 Directives:: Assembler Directives. 20579* s390 Floating Point:: Floating Point. 20580 20581 20582File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 20583 205849.42.1 Options 20585-------------- 20586 20587The following table lists all available s390 specific options: 20588 20589‘-m31 | -m64’ 20590 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 20591 20592 These options are only available with the ELF object file format, 20593 and require that the necessary BFD support has been included (on a 20594 31-bit platform you must add –enable-64-bit-bfd on the call to the 20595 configure script to enable 64-bit usage and use s390x as target 20596 platform). 20597 20598‘-mesa | -mzarch’ 20599 Select the architecture mode, either the Enterprise System 20600 Architecture (esa) mode or the z/Architecture mode (zarch). 20601 20602 The 64-bit instructions are only available with the z/Architecture 20603 mode. The combination of ‘-m64’ and ‘-mesa’ results in a warning 20604 message. 20605 20606‘-march=CPU’ 20607 This option specifies the target processor. The following 20608 processor names are recognized: ‘g5’ (or ‘arch3’), ‘g6’, ‘z900’ (or 20609 ‘arch5’), ‘z990’ (or ‘arch6’), ‘z9-109’, ‘z9-ec’ (or ‘arch7’), 20610 ‘z10’ (or ‘arch8’), ‘z196’ (or ‘arch9’), ‘zEC12’ (or ‘arch10’), 20611 ‘z13’ (or ‘arch11’), ‘z14’ (or ‘arch12’), ‘z15’ (or ‘arch13’), and 20612 ‘z16’ (or ‘arch14’). 20613 20614 Assembling an instruction that is not supported on the target 20615 processor results in an error message. 20616 20617 The processor names starting with ‘arch’ refer to the edition 20618 number in the Principle of Operations manual. They can be used as 20619 alternate processor names and have been added for compatibility 20620 with the IBM XL compiler. 20621 20622 ‘arch3’, ‘g5’ and ‘g6’ cannot be used with the ‘-mzarch’ option 20623 since the z/Architecture mode is not supported on these processor 20624 levels. 20625 20626 There is no ‘arch4’ option supported. ‘arch4’ matches 20627 ‘-march=arch5 -mesa’. 20628 20629‘-mregnames’ 20630 Allow symbolic names for registers. 20631 20632‘-mno-regnames’ 20633 Do not allow symbolic names for registers. 20634 20635‘-mwarn-areg-zero’ 20636 Warn whenever the operand for a base or index register has been 20637 specified but evaluates to zero. This can indicate the misuse of 20638 general purpose register 0 as an address register. 20639 20640 20641File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 20642 206439.42.2 Special Characters 20644------------------------- 20645 20646‘#’ is the line comment character. 20647 20648 If a ‘#’ appears as the first character of a line then the whole line 20649is treated as a comment, but in this case the line could also be a 20650logical line number directive (*note Comments::) or a preprocessor 20651control command (*note Preprocessing::). 20652 20653 The ‘;’ character can be used instead of a newline to separate 20654statements. 20655 20656 20657File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 20658 206599.42.3 Instruction syntax 20660------------------------- 20661 20662The assembler syntax closely follows the syntax outlined in Enterprise 20663Systems Architecture/390 Principles of Operation (SA22-7201) and the 20664z/Architecture Principles of Operation (SA22-7832). 20665 20666 Each instruction has two major parts, the instruction mnemonic and 20667the instruction operands. The instruction format varies. 20668 20669* Menu: 20670 20671* s390 Register:: Register Naming 20672* s390 Mnemonics:: Instruction Mnemonics 20673* s390 Operands:: Instruction Operands 20674* s390 Formats:: Instruction Formats 20675* s390 Aliases:: Instruction Aliases 20676* s390 Operand Modifier:: Instruction Operand Modifier 20677* s390 Instruction Marker:: Instruction Marker 20678* s390 Literal Pool Entries:: Literal Pool Entries 20679 20680 20681File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 20682 206839.42.3.1 Register naming 20684........................ 20685 20686The ‘as’ recognizes a number of predefined symbols for the various 20687processor registers. A register specification in one of the instruction 20688formats is an unsigned integer between 0 and 15. The specific 20689instruction and the position of the register in the instruction format 20690denotes the type of the register. The register symbols are prefixed 20691with ‘%’: 20692 20693 %rN the 16 general purpose registers, 0 <= N <= 15 20694 %fN the 16 floating point registers, 0 <= N <= 15 20695 %aN the 16 access registers, 0 <= N <= 15 20696 %cN the 16 control registers, 0 <= N <= 15 20697 %lit an alias for the general purpose register %r13 20698 %sp an alias for the general purpose register %r15 20699 20700 20701File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 20702 207039.42.3.2 Instruction Mnemonics 20704.............................. 20705 20706All instructions documented in the Principles of Operation are supported 20707with the mnemonic and order of operands as described. The instruction 20708mnemonic identifies the instruction format (*note s390 Formats::) and 20709the specific operation code for the instruction. For example, the ‘lr’ 20710mnemonic denotes the instruction format ‘RR’ with the operation code 20711‘0x18’. 20712 20713 The definition of the various mnemonics follows a scheme, where the 20714first character usually hint at the type of the instruction: 20715 20716 a add instruction, for example ‘al’ for add logical 32-bit 20717 b branch instruction, for example ‘bc’ for branch on condition 20718 c compare or convert instruction, for example ‘cr’ for compare 20719 register 32-bit 20720 d divide instruction, for example ‘dlr’ divide logical register 20721 64-bit to 32-bit 20722 i insert instruction, for example ‘ic’ insert character 20723 l load instruction, for example ‘ltr’ load and test register 20724 mv move instruction, for example ‘mvc’ move character 20725 m multiply instruction, for example ‘mh’ multiply halfword 20726 n and instruction, for example ‘ni’ and immediate 20727 o or instruction, for example ‘oc’ or character 20728 sla, sll shift left single instruction 20729 sra, srl shift right single instruction 20730 st store instruction, for example ‘stm’ store multiple 20731 s subtract instruction, for example ‘slr’ subtract 20732 logical 32-bit 20733 t test or translate instruction, of example ‘tm’ test under mask 20734 x exclusive or instruction, for example ‘xc’ exclusive or 20735 character 20736 20737 Certain characters at the end of the mnemonic may describe a property 20738of the instruction: 20739 20740 c the instruction uses a 8-bit character operand 20741 f the instruction extends a 32-bit operand to 64 bit 20742 g the operands are treated as 64-bit values 20743 h the operand uses a 16-bit halfword operand 20744 i the instruction uses an immediate operand 20745 l the instruction uses unsigned, logical operands 20746 m the instruction uses a mask or operates on multiple values 20747 r if r is the last character, the instruction operates on registers 20748 y the instruction uses 20-bit displacements 20749 20750 There are many exceptions to the scheme outlined in the above lists, 20751in particular for the privileged instructions. For non-privileged 20752instruction it works quite well, for example the instruction ‘clgfr’ c: 20753compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 2075464-bit extension, r: register operands. The instruction compares an 2075564-bit value in a register with the zero extended 32-bit value from a 20756second register. For a complete list of all mnemonics see appendix B in 20757the Principles of Operation. 20758 20759 20760File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 20761 207629.42.3.3 Instruction Operands 20763............................. 20764 20765Instruction operands can be grouped into three classes, operands located 20766in registers, immediate operands, and operands in storage. 20767 20768 A register operand can be located in general, floating-point, access, 20769or control register. The register is identified by a four-bit field. 20770The field containing the register operand is called the R field. 20771 20772 Immediate operands are contained within the instruction and can have 207738, 16 or 32 bits. The field containing the immediate operand is called 20774the I field. Dependent on the instruction the I field is either signed 20775or unsigned. 20776 20777 A storage operand consists of an address and a length. The address 20778of a storage operands can be specified in any of these ways: 20779 20780 • The content of a single general R 20781 • The sum of the content of a general register called the base 20782 register B plus the content of a displacement field D 20783 • The sum of the contents of two general registers called the index 20784 register X and the base register B plus the content of a 20785 displacement field 20786 • The sum of the current instruction address and a 32-bit signed 20787 immediate field multiplied by two. 20788 20789 The length of a storage operand can be: 20790 20791 • Implied by the instruction 20792 • Specified by a bitmask 20793 • Specified by a four-bit or eight-bit length field L 20794 • Specified by the content of a general register 20795 20796 The notation for storage operand addresses formed from multiple 20797fields is as follows: 20798 20799‘Dn(Bn)’ 20800 the address for operand number n is formed from the content of 20801 general register Bn called the base register and the displacement 20802 field Dn. 20803‘Dn(Xn,Bn)’ 20804 the address for operand number n is formed from the content of 20805 general register Xn called the index register, general register Bn 20806 called the base register and the displacement field Dn. 20807‘Dn(Ln,Bn)’ 20808 the address for operand number n is formed from the content of 20809 general register Bn called the base register and the displacement 20810 field Dn. The length of the operand n is specified by the field 20811 Ln. 20812 20813 The base registers Bn and the index registers Xn of a storage operand 20814can be skipped. If Bn and Xn are skipped, a zero will be stored to the 20815operand field. The notation changes as follows: 20816 20817 full notation short notation 20818 ---------------------------------------------- 20819 Dn(0,Bn) Dn(Bn) 20820 Dn(0,0) Dn 20821 Dn(0) Dn 20822 Dn(Ln,0) Dn(Ln) 20823 20824 20825File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 20826 208279.42.3.4 Instruction Formats 20828............................ 20829 20830The Principles of Operation manuals lists 35 instruction formats where 20831some of the formats have multiple variants. For the ‘.insn’ pseudo 20832directive the assembler recognizes some of the formats. Typically, the 20833most general variant of the instruction format is used by the ‘.insn’ 20834directive. 20835 20836 The following table lists the abbreviations used in the table of 20837instruction formats: 20838 20839 OpCode / OpCd Part of the op code. 20840 Bx Base register number for operand x. 20841 Dx Displacement for operand x. 20842 DLx Displacement lower 12 bits for operand x. 20843 DHx Displacement higher 8-bits for operand x. 20844 Rx Register number for operand x. 20845 Xx Index register number for operand x. 20846 Ix Signed immediate for operand x. 20847 Ux Unsigned immediate for operand x. 20848 20849 An instruction is two, four, or six bytes in length and must be 20850aligned on a 2 byte boundary. The first two bits of the instruction 20851specify the length of the instruction, 00 indicates a two byte 20852instruction, 01 and 10 indicates a four byte instruction, and 11 20853indicates a six byte instruction. 20854 20855 The following table lists the s390 instruction formats that are 20856available with the ‘.insn’ pseudo directive: 20857 20858‘E format’ 20859 +-------------+ 20860 | OpCode | 20861 +-------------+ 20862 0 15 20863 20864‘RI format: <insn> R1,I2’ 20865 +--------+----+----+------------------+ 20866 | OpCode | R1 |OpCd| I2 | 20867 +--------+----+----+------------------+ 20868 0 8 12 16 31 20869 20870‘RIE format: <insn> R1,R3,I2’ 20871 +--------+----+----+------------------+--------+--------+ 20872 | OpCode | R1 | R3 | I2 |////////| OpCode | 20873 +--------+----+----+------------------+--------+--------+ 20874 0 8 12 16 32 40 47 20875 20876‘RIL format: <insn> R1,I2’ 20877 +--------+----+----+------------------------------------+ 20878 | OpCode | R1 |OpCd| I2 | 20879 +--------+----+----+------------------------------------+ 20880 0 8 12 16 47 20881 20882‘RILU format: <insn> R1,U2’ 20883 +--------+----+----+------------------------------------+ 20884 | OpCode | R1 |OpCd| U2 | 20885 +--------+----+----+------------------------------------+ 20886 0 8 12 16 47 20887 20888‘RIS format: <insn> R1,I2,M3,D4(B4)’ 20889 +--------+----+----+----+-------------+--------+--------+ 20890 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 20891 +--------+----+----+----+-------------+--------+--------+ 20892 0 8 12 16 20 32 36 47 20893 20894‘RR format: <insn> R1,R2’ 20895 +--------+----+----+ 20896 | OpCode | R1 | R2 | 20897 +--------+----+----+ 20898 0 8 12 15 20899 20900‘RRE format: <insn> R1,R2’ 20901 +------------------+--------+----+----+ 20902 | OpCode |////////| R1 | R2 | 20903 +------------------+--------+----+----+ 20904 0 16 24 28 31 20905 20906‘RRF format: <insn> R1,R2,R3,M4’ 20907 +------------------+----+----+----+----+ 20908 | OpCode | R3 | M4 | R1 | R2 | 20909 +------------------+----+----+----+----+ 20910 0 16 20 24 28 31 20911 20912‘RRS format: <insn> R1,R2,M3,D4(B4)’ 20913 +--------+----+----+----+-------------+----+----+--------+ 20914 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 20915 +--------+----+----+----+-------------+----+----+--------+ 20916 0 8 12 16 20 32 36 40 47 20917 20918‘RS format: <insn> R1,R3,D2(B2)’ 20919 +--------+----+----+----+-------------+ 20920 | OpCode | R1 | R3 | B2 | D2 | 20921 +--------+----+----+----+-------------+ 20922 0 8 12 16 20 31 20923 20924‘RSE format: <insn> R1,R3,D2(B2)’ 20925 +--------+----+----+----+-------------+--------+--------+ 20926 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 20927 +--------+----+----+----+-------------+--------+--------+ 20928 0 8 12 16 20 32 40 47 20929 20930‘RSI format: <insn> R1,R3,I2’ 20931 +--------+----+----+------------------------------------+ 20932 | OpCode | R1 | R3 | I2 | 20933 +--------+----+----+------------------------------------+ 20934 0 8 12 16 47 20935 20936‘RSY format: <insn> R1,R3,D2(B2)’ 20937 +--------+----+----+----+-------------+--------+--------+ 20938 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 20939 +--------+----+----+----+-------------+--------+--------+ 20940 0 8 12 16 20 32 40 47 20941 20942‘RX format: <insn> R1,D2(X2,B2)’ 20943 +--------+----+----+----+-------------+ 20944 | OpCode | R1 | X2 | B2 | D2 | 20945 +--------+----+----+----+-------------+ 20946 0 8 12 16 20 31 20947 20948‘RXE format: <insn> R1,D2(X2,B2)’ 20949 +--------+----+----+----+-------------+--------+--------+ 20950 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 20951 +--------+----+----+----+-------------+--------+--------+ 20952 0 8 12 16 20 32 40 47 20953 20954‘RXF format: <insn> R1,R3,D2(X2,B2)’ 20955 +--------+----+----+----+-------------+----+---+--------+ 20956 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 20957 +--------+----+----+----+-------------+----+---+--------+ 20958 0 8 12 16 20 32 36 40 47 20959 20960‘RXY format: <insn> R1,D2(X2,B2)’ 20961 +--------+----+----+----+-------------+--------+--------+ 20962 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 20963 +--------+----+----+----+-------------+--------+--------+ 20964 0 8 12 16 20 32 36 40 47 20965 20966‘S format: <insn> D2(B2)’ 20967 +------------------+----+-------------+ 20968 | OpCode | B2 | D2 | 20969 +------------------+----+-------------+ 20970 0 16 20 31 20971 20972‘SI format: <insn> D1(B1),I2’ 20973 +--------+---------+----+-------------+ 20974 | OpCode | I2 | B1 | D1 | 20975 +--------+---------+----+-------------+ 20976 0 8 16 20 31 20977 20978‘SIY format: <insn> D1(B1),U2’ 20979 +--------+---------+----+-------------+--------+--------+ 20980 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 20981 +--------+---------+----+-------------+--------+--------+ 20982 0 8 16 20 32 36 40 47 20983 20984‘SIL format: <insn> D1(B1),I2’ 20985 +------------------+----+-------------+-----------------+ 20986 | OpCode | B1 | D1 | I2 | 20987 +------------------+----+-------------+-----------------+ 20988 0 16 20 32 47 20989 20990‘SS format: <insn> D1(R1,B1),D2(B3),R3’ 20991 +--------+----+----+----+-------------+----+------------+ 20992 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 20993 +--------+----+----+----+-------------+----+------------+ 20994 0 8 12 16 20 32 36 47 20995 20996‘SSE format: <insn> D1(B1),D2(B2)’ 20997 +------------------+----+-------------+----+------------+ 20998 | OpCode | B1 | D1 | B2 | D2 | 20999 +------------------+----+-------------+----+------------+ 21000 0 8 12 16 20 32 36 47 21001 21002‘SSF format: <insn> D1(B1),D2(B2),R3’ 21003 +--------+----+----+----+-------------+----+------------+ 21004 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 21005 +--------+----+----+----+-------------+----+------------+ 21006 0 8 12 16 20 32 36 47 21007 21008‘VRV format: <insn> V1,D2(V2,B2),M3’ 21009 +--------+----+----+----+-------------+----+------------+ 21010 | OpCode | V1 | V2 | B2 | D2 | M3 | Opcode | 21011 +--------+----+----+----+-------------+----+------------+ 21012 0 8 12 16 20 32 36 47 21013 21014‘VRI format: <insn> V1,V2,I3,M4,M5’ 21015 +--------+----+----+-------------+----+----+------------+ 21016 | OpCode | V1 | V2 | I3 | M5 | M4 | Opcode | 21017 +--------+----+----+-------------+----+----+------------+ 21018 0 8 12 16 28 32 36 47 21019 21020‘VRX format: <insn> V1,D2(R2,B2),M3’ 21021 +--------+----+----+----+-------------+----+------------+ 21022 | OpCode | V1 | R2 | B2 | D2 | M3 | Opcode | 21023 +--------+----+----+----+-------------+----+------------+ 21024 0 8 12 16 20 32 36 47 21025 21026‘VRS format: <insn> R1,V3,D2(B2),M4’ 21027 +--------+----+----+----+-------------+----+------------+ 21028 | OpCode | R1 | V3 | B2 | D2 | M4 | Opcode | 21029 +--------+----+----+----+-------------+----+------------+ 21030 0 8 12 16 20 32 36 47 21031 21032‘VRR format: <insn> V1,V2,V3,M4,M5,M6’ 21033 +--------+----+----+----+---+----+----+----+------------+ 21034 | OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode | 21035 +--------+----+----+----+---+----+----+----+------------+ 21036 0 8 12 16 24 28 32 36 47 21037 21038‘VSI format: <insn> V1,D2(B2),I3’ 21039 +--------+---------+----+-------------+----+------------+ 21040 | OpCode | I3 | B2 | D2 | V1 | Opcode | 21041 +--------+---------+----+-------------+----+------------+ 21042 0 8 16 20 32 36 47 21043 21044 For the complete list of all instruction format variants see the 21045Principles of Operation manuals. 21046 21047 21048File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 21049 210509.42.3.5 Instruction Aliases 21051............................ 21052 21053A specific bit pattern can have multiple mnemonics, for example the bit 21054pattern ‘0xa7000000’ has the mnemonics ‘tmh’ and ‘tmlh’. In addition, 21055there are a number of mnemonics recognized by ‘as’ that are not present 21056in the Principles of Operation. These are the short forms of the branch 21057instructions, where the condition code mask operand is encoded in the 21058mnemonic. This is relevant for the branch instructions, the compare and 21059branch instructions, and the compare and trap instructions. 21060 21061 For the branch instructions there are 20 condition code strings that 21062can be used as part of the mnemonic in place of a mask operand in the 21063instruction format: 21064 21065 instruction short form 21066 ---------------------------------------------- 21067 bcr M1,R2 b<m>r R2 21068 bc M1,D2(X2,B2) b<m> D2(X2,B2) 21069 brc M1,I2 j<m> I2 21070 brcl M1,I2 jg<m> I2 21071 21072 In the mnemonic for a branch instruction the condition code string 21073<m> can be any of the following: 21074 21075 o jump on overflow / if ones 21076 h jump on A high 21077 p jump on plus 21078 nle jump on not low or equal 21079 l jump on A low 21080 m jump on minus 21081 nhe jump on not high or equal 21082 lh jump on low or high 21083 ne jump on A not equal B 21084 nz jump on not zero / if not zeros 21085 e jump on A equal B 21086 z jump on zero / if zeroes 21087 nlh jump on not low or high 21088 he jump on high or equal 21089 nl jump on A not low 21090 nm jump on not minus / if not mixed 21091 le jump on low or equal 21092 nh jump on A not high 21093 np jump on not plus 21094 no jump on not overflow / if not ones 21095 21096 For the compare and branch, and compare and trap instructions there 21097are 12 condition code strings that can be used as part of the mnemonic 21098in place of a mask operand in the instruction format: 21099 21100 instruction short form 21101 ------------------------------------------------------------ 21102 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 21103 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 21104 crj R1,R2,M3,I4 crj<m> R1,R2,I4 21105 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 21106 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 21107 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 21108 cij R1,I2,M3,I4 cij<m> R1,I2,I4 21109 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 21110 crt R1,R2,M3 crt<m> R1,R2 21111 cgrt R1,R2,M3 cgrt<m> R1,R2 21112 cit R1,I2,M3 cit<m> R1,I2 21113 cgit R1,I2,M3 cgit<m> R1,I2 21114 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 21115 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 21116 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 21117 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 21118 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 21119 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 21120 clij R1,I2,M3,I4 clij<m> R1,I2,I4 21121 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 21122 clrt R1,R2,M3 clrt<m> R1,R2 21123 clgrt R1,R2,M3 clgrt<m> R1,R2 21124 clfit R1,I2,M3 clfit<m> R1,I2 21125 clgit R1,I2,M3 clgit<m> R1,I2 21126 21127 In the mnemonic for a compare and branch and compare and trap 21128instruction the condition code string <m> can be any of the following: 21129 21130 h jump on A high 21131 nle jump on not low or equal 21132 l jump on A low 21133 nhe jump on not high or equal 21134 ne jump on A not equal B 21135 lh jump on low or high 21136 e jump on A equal B 21137 nlh jump on not low or high 21138 nl jump on A not low 21139 he jump on high or equal 21140 nh jump on A not high 21141 le jump on low or equal 21142 21143 21144File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 21145 211469.42.3.6 Instruction Operand Modifier 21147..................................... 21148 21149If a symbol modifier is attached to a symbol in an expression for an 21150instruction operand field, the symbol term is replaced with a reference 21151to an object in the global offset table (GOT) or the procedure linkage 21152table (PLT). The following expressions are allowed: ‘symbol@modifier + 21153constant’, ‘symbol@modifier + label + constant’, and ‘symbol@modifier - 21154label + constant’. The term ‘symbol’ is the symbol that will be entered 21155into the GOT or PLT, ‘label’ is a local label, and ‘constant’ is an 21156arbitrary expression that the assembler can evaluate to a constant 21157value. 21158 21159 The term ‘(symbol + constant1)@modifier +/- label + constant2’ is 21160also accepted but a warning message is printed and the term is converted 21161to ‘symbol@modifier +/- label + constant1 + constant2’. 21162 21163‘@got’ 21164‘@got12’ 21165 The @got modifier can be used for displacement fields, 16-bit 21166 immediate fields and 32-bit pc-relative immediate fields. The 21167 @got12 modifier is synonym to @got. The symbol is added to the 21168 GOT. For displacement fields and 16-bit immediate fields the symbol 21169 term is replaced with the offset from the start of the GOT to the 21170 GOT slot for the symbol. For a 32-bit pc-relative field the 21171 pc-relative offset to the GOT slot from the current instruction 21172 address is used. 21173‘@gotent’ 21174 The @gotent modifier can be used for 32-bit pc-relative immediate 21175 fields. The symbol is added to the GOT and the symbol term is 21176 replaced with the pc-relative offset from the current instruction 21177 to the GOT slot for the symbol. 21178‘@gotoff’ 21179 The @gotoff modifier can be used for 16-bit immediate fields. The 21180 symbol term is replaced with the offset from the start of the GOT 21181 to the address of the symbol. 21182‘@gotplt’ 21183 The @gotplt modifier can be used for displacement fields, 16-bit 21184 immediate fields, and 32-bit pc-relative immediate fields. A 21185 procedure linkage table entry is generated for the symbol and a 21186 jump slot for the symbol is added to the GOT. For displacement 21187 fields and 16-bit immediate fields the symbol term is replaced with 21188 the offset from the start of the GOT to the jump slot for the 21189 symbol. For a 32-bit pc-relative field the pc-relative offset to 21190 the jump slot from the current instruction address is used. 21191‘@plt’ 21192 The @plt modifier can be used for 16-bit and 32-bit pc-relative 21193 immediate fields. A procedure linkage table entry is generated for 21194 the symbol. The symbol term is replaced with the relative offset 21195 from the current instruction to the PLT entry for the symbol. 21196‘@pltoff’ 21197 The @pltoff modifier can be used for 16-bit immediate fields. The 21198 symbol term is replaced with the offset from the start of the PLT 21199 to the address of the symbol. 21200‘@gotntpoff’ 21201 The @gotntpoff modifier can be used for displacement fields. The 21202 symbol is added to the static TLS block and the negated offset to 21203 the symbol in the static TLS block is added to the GOT. The symbol 21204 term is replaced with the offset to the GOT slot from the start of 21205 the GOT. 21206‘@indntpoff’ 21207 The @indntpoff modifier can be used for 32-bit pc-relative 21208 immediate fields. The symbol is added to the static TLS block and 21209 the negated offset to the symbol in the static TLS block is added 21210 to the GOT. The symbol term is replaced with the pc-relative offset 21211 to the GOT slot from the current instruction address. 21212 21213 For more information about the thread local storage modifiers 21214‘gotntpoff’ and ‘indntpoff’ see the ELF extension documentation ‘ELF 21215Handling For Thread-Local Storage’. 21216 21217 21218File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 21219 212209.42.3.7 Instruction Marker 21221........................... 21222 21223The thread local storage instruction markers are used by the linker to 21224perform code optimization. 21225 21226‘:tls_load’ 21227 The :tls_load marker is used to flag the load instruction in the 21228 initial exec TLS model that retrieves the offset from the thread 21229 pointer to a thread local storage variable from the GOT. 21230‘:tls_gdcall’ 21231 The :tls_gdcall marker is used to flag the branch-and-save 21232 instruction to the __tls_get_offset function in the global dynamic 21233 TLS model. 21234‘:tls_ldcall’ 21235 The :tls_ldcall marker is used to flag the branch-and-save 21236 instruction to the __tls_get_offset function in the local dynamic 21237 TLS model. 21238 21239 For more information about the thread local storage instruction 21240marker and the linker optimizations see the ELF extension documentation 21241‘ELF Handling For Thread-Local Storage’. 21242 21243 21244File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 21245 212469.42.3.8 Literal Pool Entries 21247............................. 21248 21249A literal pool is a collection of values. To access the values a 21250pointer to the literal pool is loaded to a register, the literal pool 21251register. Usually, register %r13 is used as the literal pool register 21252(*note s390 Register::). Literal pool entries are created by adding the 21253suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 21254instruction operand. The expression is added to the literal pool and 21255the operand is replaced with the offset to the literal in the literal 21256pool. 21257 21258‘:lit1’ 21259 The literal pool entry is created as an 8-bit value. An operand 21260 modifier must not be used for the original expression. 21261‘:lit2’ 21262 The literal pool entry is created as a 16 bit value. The operand 21263 modifier @got may be used in the original expression. The term 21264 ‘x@got:lit2’ will put the got offset for the global symbol x to the 21265 literal pool as 16 bit value. 21266‘:lit4’ 21267 The literal pool entry is created as a 32-bit value. The operand 21268 modifier @got and @plt may be used in the original expression. The 21269 term ‘x@got:lit4’ will put the got offset for the global symbol x 21270 to the literal pool as a 32-bit value. The term ‘x@plt:lit4’ will 21271 put the plt offset for the global symbol x to the literal pool as a 21272 32-bit value. 21273‘:lit8’ 21274 The literal pool entry is created as a 64-bit value. The operand 21275 modifier @got and @plt may be used in the original expression. The 21276 term ‘x@got:lit8’ will put the got offset for the global symbol x 21277 to the literal pool as a 64-bit value. The term ‘x@plt:lit8’ will 21278 put the plt offset for the global symbol x to the literal pool as a 21279 64-bit value. 21280 21281 The assembler directive ‘.ltorg’ is used to emit all literal pool 21282entries to the current position. 21283 21284 21285File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 21286 212879.42.4 Assembler Directives 21288--------------------------- 21289 21290‘as’ for s390 supports all of the standard ELF assembler directives as 21291outlined in the main part of this document. Some directives have been 21292extended and there are some additional directives, which are only 21293available for the s390 ‘as’. 21294 21295‘.insn’ 21296 This directive permits the numeric representation of an 21297 instructions and makes the assembler insert the operands according 21298 to one of the instructions formats for ‘.insn’ (*note s390 21299 Formats::). For example, the instruction ‘l %r1,24(%r15)’ could be 21300 written as ‘.insn rx,0x58000000,%r1,24(%r15)’. 21301‘.short’ 21302‘.long’ 21303‘.quad’ 21304 This directive places one or more 16-bit (.short), 32-bit (.long), 21305 or 64-bit (.quad) values into the current section. If an ELF or 21306 TLS modifier is used only the following expressions are allowed: 21307 ‘symbol@modifier + constant’, ‘symbol@modifier + label + constant’, 21308 and ‘symbol@modifier - label + constant’. The following modifiers 21309 are available: 21310 ‘@got’ 21311 ‘@got12’ 21312 The @got modifier can be used for .short, .long and .quad. 21313 The @got12 modifier is synonym to @got. The symbol is added 21314 to the GOT. The symbol term is replaced with offset from the 21315 start of the GOT to the GOT slot for the symbol. 21316 ‘@gotoff’ 21317 The @gotoff modifier can be used for .short, .long and .quad. 21318 The symbol term is replaced with the offset from the start of 21319 the GOT to the address of the symbol. 21320 ‘@gotplt’ 21321 The @gotplt modifier can be used for .long and .quad. A 21322 procedure linkage table entry is generated for the symbol and 21323 a jump slot for the symbol is added to the GOT. The symbol 21324 term is replaced with the offset from the start of the GOT to 21325 the jump slot for the symbol. 21326 ‘@plt’ 21327 The @plt modifier can be used for .long and .quad. A 21328 procedure linkage table entry us generated for the symbol. 21329 The symbol term is replaced with the address of the PLT entry 21330 for the symbol. 21331 ‘@pltoff’ 21332 The @pltoff modifier can be used for .short, .long and .quad. 21333 The symbol term is replaced with the offset from the start of 21334 the PLT to the address of the symbol. 21335 ‘@tlsgd’ 21336 ‘@tlsldm’ 21337 The @tlsgd and @tlsldm modifier can be used for .long and 21338 .quad. A tls_index structure for the symbol is added to the 21339 GOT. The symbol term is replaced with the offset from the 21340 start of the GOT to the tls_index structure. 21341 ‘@gotntpoff’ 21342 ‘@indntpoff’ 21343 The @gotntpoff and @indntpoff modifier can be used for .long 21344 and .quad. The symbol is added to the static TLS block and 21345 the negated offset to the symbol in the static TLS block is 21346 added to the GOT. For @gotntpoff the symbol term is replaced 21347 with the offset from the start of the GOT to the GOT slot, for 21348 @indntpoff the symbol term is replaced with the address of the 21349 GOT slot. 21350 ‘@dtpoff’ 21351 The @dtpoff modifier can be used for .long and .quad. The 21352 symbol term is replaced with the offset of the symbol relative 21353 to the start of the TLS block it is contained in. 21354 ‘@ntpoff’ 21355 The @ntpoff modifier can be used for .long and .quad. The 21356 symbol term is replaced with the offset of the symbol relative 21357 to the TCB pointer. 21358 21359 For more information about the thread local storage modifiers see 21360 the ELF extension documentation ‘ELF Handling For Thread-Local 21361 Storage’. 21362 21363‘.ltorg’ 21364 This directive causes the current contents of the literal pool to 21365 be dumped to the current location (*note s390 Literal Pool 21366 Entries::). 21367 21368‘.machine STRING[+EXTENSION]...’ 21369 21370 This directive allows changing the machine for which code is 21371 generated. ‘string’ may be any of the ‘-march=’ selection options, 21372 or ‘push’, or ‘pop’. ‘.machine push’ saves the currently selected 21373 cpu, which may be restored with ‘.machine pop’. Be aware that the 21374 cpu string has to be put into double quotes in case it contains 21375 characters not appropriate for identifiers. So you have to write 21376 ‘"z9-109"’ instead of just ‘z9-109’. Extensions can be specified 21377 after the cpu name, separated by plus characters. Valid extensions 21378 are: ‘htm’, ‘nohtm’, ‘vx’, ‘novx’. They extend the basic 21379 instruction set with features from a higher cpu level, or remove 21380 support for a feature from the given cpu level. 21381 21382 Example: ‘z13+nohtm’ allows all instructions of the z13 cpu except 21383 instructions from the HTM facility. 21384 21385‘.machinemode string’ 21386 This directive allows one to change the architecture mode for which 21387 code is being generated. ‘string’ may be ‘esa’, ‘zarch’, 21388 ‘zarch_nohighgprs’, ‘push’, or ‘pop’. ‘.machinemode 21389 zarch_nohighgprs’ can be used to prevent the ‘highgprs’ flag from 21390 being set in the ELF header of the output file. This is useful in 21391 situations where the code is gated with a runtime check which makes 21392 sure that the code is only executed on kernels providing the 21393 ‘highgprs’ feature. ‘.machinemode push’ saves the currently 21394 selected mode, which may be restored with ‘.machinemode pop’. 21395 21396 21397File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 21398 213999.42.5 Floating Point 21400--------------------- 21401 21402The assembler recognizes both the IEEE floating-point instruction and 21403the hexadecimal floating-point instructions. The floating-point 21404constructors ‘.float’, ‘.single’, and ‘.double’ always emit the IEEE 21405format. To assemble hexadecimal floating-point constants the ‘.long’ 21406and ‘.quad’ directives must be used. 21407 21408 21409File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 21410 214119.43 SCORE Dependent Features 21412============================= 21413 21414* Menu: 21415 21416* SCORE-Opts:: Assembler options 21417* SCORE-Pseudo:: SCORE Assembler Directives 21418* SCORE-Syntax:: Syntax 21419 21420 21421File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 21422 214239.43.1 Options 21424-------------- 21425 21426The following table lists all available SCORE options. 21427 21428‘-G NUM’ 21429 This option sets the largest size of an object that can be 21430 referenced implicitly with the ‘gp’ register. The default value is 21431 8. 21432 21433‘-EB’ 21434 Assemble code for a big-endian cpu 21435 21436‘-EL’ 21437 Assemble code for a little-endian cpu 21438 21439‘-FIXDD’ 21440 Assemble code for fix data dependency 21441 21442‘-NWARN’ 21443 Assemble code for no warning message for fix data dependency 21444 21445‘-SCORE5’ 21446 Assemble code for target is SCORE5 21447 21448‘-SCORE5U’ 21449 Assemble code for target is SCORE5U 21450 21451‘-SCORE7’ 21452 Assemble code for target is SCORE7, this is default setting 21453 21454‘-SCORE3’ 21455 Assemble code for target is SCORE3 21456 21457‘-march=score7’ 21458 Assemble code for target is SCORE7, this is default setting 21459 21460‘-march=score3’ 21461 Assemble code for target is SCORE3 21462 21463‘-USE_R1’ 21464 Assemble code for no warning message when using temp register r1 21465 21466‘-KPIC’ 21467 Generate code for PIC. This option tells the assembler to generate 21468 score position-independent macro expansions. It also tells the 21469 assembler to mark the output file as PIC. 21470 21471‘-O0’ 21472 Assembler will not perform any optimizations 21473 21474‘-V’ 21475 Sunplus release version 21476 21477 21478File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 21479 214809.43.2 SCORE Assembler Directives 21481--------------------------------- 21482 21483A number of assembler directives are available for SCORE. The following 21484table is far from complete. 21485 21486‘.set nwarn’ 21487 Let the assembler not to generate warnings if the source machine 21488 language instructions happen data dependency. 21489 21490‘.set fixdd’ 21491 Let the assembler to insert bubbles (32 bit nop instruction / 16 21492 bit nop! Instruction) if the source machine language instructions 21493 happen data dependency. 21494 21495‘.set nofixdd’ 21496 Let the assembler to generate warnings if the source machine 21497 language instructions happen data dependency. (Default) 21498 21499‘.set r1’ 21500 Let the assembler not to generate warnings if the source program 21501 uses r1. allow user to use r1 21502 21503‘set nor1’ 21504 Let the assembler to generate warnings if the source program uses 21505 r1. (Default) 21506 21507‘.sdata’ 21508 Tell the assembler to add subsequent data into the sdata section 21509 21510‘.rdata’ 21511 Tell the assembler to add subsequent data into the rdata section 21512 21513‘.frame "frame-register", "offset", "return-pc-register"’ 21514 Describe a stack frame. "frame-register" is the frame register, 21515 "offset" is the distance from the frame register to the virtual 21516 frame pointer, "return-pc-register" is the return program register. 21517 You must use ".ent" before ".frame" and only one ".frame" can be 21518 used per ".ent". 21519 21520‘.mask "bitmask", "frameoffset"’ 21521 Indicate which of the integer registers are saved in the current 21522 function’s stack frame, this is for the debugger to explain the 21523 frame chain. 21524 21525‘.ent "proc-name"’ 21526 Set the beginning of the procedure "proc_name". Use this directive 21527 when you want to generate information for the debugger. 21528 21529‘.end proc-name’ 21530 Set the end of a procedure. Use this directive to generate 21531 information for the debugger. 21532 21533‘.bss’ 21534 Switch the destination of following statements into the bss 21535 section, which is used for data that is uninitialized anywhere. 21536 21537 21538File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent 21539 215409.43.3 SCORE Syntax 21541------------------- 21542 21543* Menu: 21544 21545* SCORE-Chars:: Special Characters 21546 21547 21548File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 21549 215509.43.3.1 Special Characters 21551........................... 21552 21553The presence of a ‘#’ appearing anywhere on a line indicates the start 21554of a comment that extends to the end of that line. 21555 21556 If a ‘#’ appears as the first character of a line then the whole line 21557is treated as a comment, but in this case the line can also be a logical 21558line number directive (*note Comments::) or a preprocessor control 21559command (*note Preprocessing::). 21560 21561 The ‘;’ character can be used to separate statements on the same 21562line. 21563 21564 21565File: as.info, Node: SH-Dependent, Next: Sparc-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 21566 215679.44 Renesas / SuperH SH Dependent Features 21568=========================================== 21569 21570* Menu: 21571 21572* SH Options:: Options 21573* SH Syntax:: Syntax 21574* SH Floating Point:: Floating Point 21575* SH Directives:: SH Machine Directives 21576* SH Opcodes:: Opcodes 21577 21578 21579File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 21580 215819.44.1 Options 21582-------------- 21583 21584‘as’ has following command-line options for the Renesas (formerly 21585Hitachi) / SuperH SH family. 21586 21587‘--little’ 21588 Generate little endian code. 21589 21590‘--big’ 21591 Generate big endian code. 21592 21593‘--relax’ 21594 Alter jump instructions for long displacements. 21595 21596‘--small’ 21597 Align sections to 4 byte boundaries, not 16. 21598 21599‘--dsp’ 21600 Enable sh-dsp insns, and disable sh3e / sh4 insns. 21601 21602‘--renesas’ 21603 Disable optimization with section symbol for compatibility with 21604 Renesas assembler. 21605 21606‘--allow-reg-prefix’ 21607 Allow ’$’ as a register name prefix. 21608 21609‘--fdpic’ 21610 Generate an FDPIC object file. 21611 21612‘--isa=sh4 | sh4a’ 21613 Specify the sh4 or sh4a instruction set. 21614‘--isa=dsp’ 21615 Enable sh-dsp insns, and disable sh3e / sh4 insns. 21616‘--isa=fp’ 21617 Enable sh2e, sh3e, sh4, and sh4a insn sets. 21618‘--isa=all’ 21619 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 21620 21621‘-h-tick-hex’ 21622 Support H’00 style hex constants in addition to 0x00 style. 21623 21624 21625File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 21626 216279.44.2 Syntax 21628------------- 21629 21630* Menu: 21631 21632* SH-Chars:: Special Characters 21633* SH-Regs:: Register Names 21634* SH-Addressing:: Addressing Modes 21635 21636 21637File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 21638 216399.44.2.1 Special Characters 21640........................... 21641 21642‘!’ is the line comment character. 21643 21644 You can use ‘;’ instead of a newline to separate statements. 21645 21646 If a ‘#’ appears as the first character of a line then the whole line 21647is treated as a comment, but in this case the line could also be a 21648logical line number directive (*note Comments::) or a preprocessor 21649control command (*note Preprocessing::). 21650 21651 Since ‘$’ has no special meaning, you may use it in symbol names. 21652 21653 21654File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 21655 216569.44.2.2 Register Names 21657....................... 21658 21659You can use the predefined symbols ‘r0’, ‘r1’, ‘r2’, ‘r3’, ‘r4’, ‘r5’, 21660‘r6’, ‘r7’, ‘r8’, ‘r9’, ‘r10’, ‘r11’, ‘r12’, ‘r13’, ‘r14’, and ‘r15’ to 21661refer to the SH registers. 21662 21663 The SH also has these control registers: 21664 21665‘pr’ 21666 procedure register (holds return address) 21667 21668‘pc’ 21669 program counter 21670 21671‘mach’ 21672‘macl’ 21673 high and low multiply accumulator registers 21674 21675‘sr’ 21676 status register 21677 21678‘gbr’ 21679 global base register 21680 21681‘vbr’ 21682 vector base register (for interrupt vectors) 21683 21684 21685File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 21686 216879.44.2.3 Addressing Modes 21688......................... 21689 21690‘as’ understands the following addressing modes for the SH. ‘RN’ in the 21691following refers to any of the numbered registers, but _not_ the control 21692registers. 21693 21694‘RN’ 21695 Register direct 21696 21697‘@RN’ 21698 Register indirect 21699 21700‘@-RN’ 21701 Register indirect with pre-decrement 21702 21703‘@RN+’ 21704 Register indirect with post-increment 21705 21706‘@(DISP, RN)’ 21707 Register indirect with displacement 21708 21709‘@(R0, RN)’ 21710 Register indexed 21711 21712‘@(DISP, GBR)’ 21713 ‘GBR’ offset 21714 21715‘@(R0, GBR)’ 21716 GBR indexed 21717 21718‘ADDR’ 21719‘@(DISP, PC)’ 21720 PC relative address (for branch or for addressing memory). The 21721 ‘as’ implementation allows you to use the simpler form ADDR 21722 anywhere a PC relative address is called for; the alternate form is 21723 supported for compatibility with other assemblers. 21724 21725‘#IMM’ 21726 Immediate data 21727 21728 21729File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 21730 217319.44.3 Floating Point 21732--------------------- 21733 21734SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 21735SH groups can use ‘.float’ directive to generate IEEE floating-point 21736numbers. 21737 21738 SH2E and SH3E support single-precision floating point calculations as 21739well as entirely PCAPI compatible emulation of double-precision floating 21740point calculations. SH2E and SH3E instructions are a subset of the 21741floating point calculations conforming to the IEEE754 standard. 21742 21743 In addition to single-precision and double-precision floating-point 21744operation capability, the on-chip FPU of SH4 has a 128-bit graphic 21745engine that enables 32-bit floating-point data to be processed 128 bits 21746at a time. It also supports 4 * 4 array operations and inner product 21747operations. Also, a superscalar architecture is employed that enables 21748simultaneous execution of two instructions (including FPU instructions), 21749providing performance of up to twice that of conventional architectures 21750at the same frequency. 21751 21752 21753File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 21754 217559.44.4 SH Machine Directives 21756---------------------------- 21757 21758‘uaword’ 21759‘ualong’ 21760‘uaquad’ 21761 ‘as’ will issue a warning when a misaligned ‘.word’, ‘.long’, or 21762 ‘.quad’ directive is used. You may use ‘.uaword’, ‘.ualong’, or 21763 ‘.uaquad’ to indicate that the value is intentionally misaligned. 21764 21765 21766File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 21767 217689.44.5 Opcodes 21769-------------- 21770 21771For detailed information on the SH machine instruction set, see 21772‘SH-Microcomputer User’s Manual’ (Renesas) or ‘SH-4 32-bit CPU Core 21773Architecture’ (SuperH) and ‘SuperH (SH) 64-Bit RISC Series’ (SuperH). 21774 21775 ‘as’ implements all the standard SH opcodes. No additional 21776pseudo-instructions are needed on this family. Note, however, that 21777because ‘as’ supports a simpler form of PC-relative addressing, you may 21778simply write (for example) 21779 21780 mov.l bar,r0 21781 21782where other assemblers might require an explicit displacement to ‘bar’ 21783from the program counter: 21784 21785 mov.l @(DISP, PC) 21786 21787 Here is a summary of SH opcodes: 21788 21789 Legend: 21790 Rn a numbered register 21791 Rm another numbered register 21792 #imm immediate data 21793 disp displacement 21794 disp8 8-bit displacement 21795 disp12 12-bit displacement 21796 21797 add #imm,Rn lds.l @Rn+,PR 21798 add Rm,Rn mac.w @Rm+,@Rn+ 21799 addc Rm,Rn mov #imm,Rn 21800 addv Rm,Rn mov Rm,Rn 21801 and #imm,R0 mov.b Rm,@(R0,Rn) 21802 and Rm,Rn mov.b Rm,@-Rn 21803 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 21804 bf disp8 mov.b @(disp,Rm),R0 21805 bra disp12 mov.b @(disp,GBR),R0 21806 bsr disp12 mov.b @(R0,Rm),Rn 21807 bt disp8 mov.b @Rm+,Rn 21808 clrmac mov.b @Rm,Rn 21809 clrt mov.b R0,@(disp,Rm) 21810 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 21811 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 21812 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 21813 cmp/gt Rm,Rn mov.l Rm,@-Rn 21814 cmp/hi Rm,Rn mov.l Rm,@Rn 21815 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 21816 cmp/pl Rn mov.l @(disp,GBR),R0 21817 cmp/pz Rn mov.l @(disp,PC),Rn 21818 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 21819 div0s Rm,Rn mov.l @Rm+,Rn 21820 div0u mov.l @Rm,Rn 21821 div1 Rm,Rn mov.l R0,@(disp,GBR) 21822 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 21823 exts.w Rm,Rn mov.w Rm,@-Rn 21824 extu.b Rm,Rn mov.w Rm,@Rn 21825 extu.w Rm,Rn mov.w @(disp,Rm),R0 21826 jmp @Rn mov.w @(disp,GBR),R0 21827 jsr @Rn mov.w @(disp,PC),Rn 21828 ldc Rn,GBR mov.w @(R0,Rm),Rn 21829 ldc Rn,SR mov.w @Rm+,Rn 21830 ldc Rn,VBR mov.w @Rm,Rn 21831 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 21832 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 21833 ldc.l @Rn+,VBR mova @(disp,PC),R0 21834 lds Rn,MACH movt Rn 21835 lds Rn,MACL muls Rm,Rn 21836 lds Rn,PR mulu Rm,Rn 21837 lds.l @Rn+,MACH neg Rm,Rn 21838 lds.l @Rn+,MACL negc Rm,Rn 21839 nop stc VBR,Rn 21840 not Rm,Rn stc.l GBR,@-Rn 21841 or #imm,R0 stc.l SR,@-Rn 21842 or Rm,Rn stc.l VBR,@-Rn 21843 or.b #imm,@(R0,GBR) sts MACH,Rn 21844 rotcl Rn sts MACL,Rn 21845 rotcr Rn sts PR,Rn 21846 rotl Rn sts.l MACH,@-Rn 21847 rotr Rn sts.l MACL,@-Rn 21848 rte sts.l PR,@-Rn 21849 rts sub Rm,Rn 21850 sett subc Rm,Rn 21851 shal Rn subv Rm,Rn 21852 shar Rn swap.b Rm,Rn 21853 shll Rn swap.w Rm,Rn 21854 shll16 Rn tas.b @Rn 21855 shll2 Rn trapa #imm 21856 shll8 Rn tst #imm,R0 21857 shlr Rn tst Rm,Rn 21858 shlr16 Rn tst.b #imm,@(R0,GBR) 21859 shlr2 Rn xor #imm,R0 21860 shlr8 Rn xor Rm,Rn 21861 sleep xor.b #imm,@(R0,GBR) 21862 stc GBR,Rn xtrct Rm,Rn 21863 stc SR,Rn 21864 21865 21866File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 21867 218689.45 SPARC Dependent Features 21869============================= 21870 21871* Menu: 21872 21873* Sparc-Opts:: Options 21874* Sparc-Aligned-Data:: Option to enforce aligned data 21875* Sparc-Syntax:: Syntax 21876* Sparc-Float:: Floating Point 21877* Sparc-Directives:: Sparc Machine Directives 21878 21879 21880File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 21881 218829.45.1 Options 21883-------------- 21884 21885The SPARC chip family includes several successive versions, using the 21886same core instruction set, but including a few additional instructions 21887at each version. There are exceptions to this however. For details on 21888what instructions each variant supports, please see the chip’s 21889architecture reference manual. 21890 21891 By default, ‘as’ assumes the core instruction set (SPARC v6), but 21892“bumps” the architecture level as needed: it switches to successively 21893higher architectures as it encounters instructions that only exist in 21894the higher levels. 21895 21896 If not configured for SPARC v9 (‘sparc64-*-*’) GAS will not bump past 21897sparclite by default, an option must be passed to enable the v9 21898instructions. 21899 21900 GAS treats sparclite as being compatible with v8, unless an 21901architecture is explicitly requested. SPARC v9 is always incompatible 21902with sparclite. 21903 21904‘-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite’ 21905‘-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |’ 21906‘-Av8plusv | -Av8plusm | -Av8plusm8’ 21907‘-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8’ 21908‘-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima’ 21909‘-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6’ 21910 Use one of the ‘-A’ options to select one of the SPARC 21911 architectures explicitly. If you select an architecture 21912 explicitly, ‘as’ reports a fatal error if it encounters an 21913 instruction or feature requiring an incompatible or higher level. 21914 21915 ‘-Av8plus’, ‘-Av8plusa’, ‘-Av8plusb’, ‘-Av8plusc’, ‘-Av8plusd’, and 21916 ‘-Av8plusv’ select a 32 bit environment. 21917 21918 ‘-Av9’, ‘-Av9a’, ‘-Av9b’, ‘-Av9c’, ‘-Av9d’, ‘-Av9e’, ‘-Av9v’ and 21919 ‘-Av9m’ select a 64 bit environment and are not available unless 21920 GAS is explicitly configured with 64 bit environment support. 21921 21922 ‘-Av8plusa’ and ‘-Av9a’ enable the SPARC V9 instruction set with 21923 UltraSPARC VIS 1.0 extensions. 21924 21925 ‘-Av8plusb’ and ‘-Av9b’ enable the UltraSPARC VIS 2.0 instructions, 21926 as well as the instructions enabled by ‘-Av8plusa’ and ‘-Av9a’. 21927 21928 ‘-Av8plusc’ and ‘-Av9c’ enable the UltraSPARC Niagara instructions, 21929 as well as the instructions enabled by ‘-Av8plusb’ and ‘-Av9b’. 21930 21931 ‘-Av8plusd’ and ‘-Av9d’ enable the floating point fused 21932 multiply-add, VIS 3.0, and HPC extension instructions, as well as 21933 the instructions enabled by ‘-Av8plusc’ and ‘-Av9c’. 21934 21935 ‘-Av8pluse’ and ‘-Av9e’ enable the cryptographic instructions, as 21936 well as the instructions enabled by ‘-Av8plusd’ and ‘-Av9d’. 21937 21938 ‘-Av8plusv’ and ‘-Av9v’ enable floating point unfused multiply-add, 21939 and integer multiply-add, as well as the instructions enabled by 21940 ‘-Av8pluse’ and ‘-Av9e’. 21941 21942 ‘-Av8plusm’ and ‘-Av9m’ enable the VIS 4.0, subtract extended, 21943 xmpmul, xmontmul and xmontsqr instructions, as well as the 21944 instructions enabled by ‘-Av8plusv’ and ‘-Av9v’. 21945 21946 ‘-Av8plusm8’ and ‘-Av9m8’ enable the instructions introduced in the 21947 Oracle SPARC Architecture 2017 and the M8 processor, as well as the 21948 instructions enabled by ‘-Av8plusm’ and ‘-Av9m’. 21949 21950 ‘-Asparc’ specifies a v9 environment. It is equivalent to ‘-Av9’ 21951 if the word size is 64-bit, and ‘-Av8plus’ otherwise. 21952 21953 ‘-Asparcvis’ specifies a v9a environment. It is equivalent to 21954 ‘-Av9a’ if the word size is 64-bit, and ‘-Av8plusa’ otherwise. 21955 21956 ‘-Asparcvis2’ specifies a v9b environment. It is equivalent to 21957 ‘-Av9b’ if the word size is 64-bit, and ‘-Av8plusb’ otherwise. 21958 21959 ‘-Asparcfmaf’ specifies a v9b environment with the floating point 21960 fused multiply-add instructions enabled. 21961 21962 ‘-Asparcima’ specifies a v9b environment with the integer 21963 multiply-add instructions enabled. 21964 21965 ‘-Asparcvis3’ specifies a v9b environment with the VIS 3.0, HPC , 21966 and floating point fused multiply-add instructions enabled. 21967 21968 ‘-Asparcvis3r’ specifies a v9b environment with the VIS 3.0, HPC, 21969 and floating point unfused multiply-add instructions enabled. 21970 21971 ‘-Asparc5’ is equivalent to ‘-Av9m’. 21972 21973 ‘-Asparc6’ is equivalent to ‘-Av9m8’. 21974 21975‘-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc’ 21976‘-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |’ 21977‘-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b’ 21978‘-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v’ 21979‘-xarch=v9m | -xarch=v9m8’ 21980‘-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2’ 21981‘-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3’ 21982‘-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6’ 21983 For compatibility with the SunOS v9 assembler. These options are 21984 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, 21985 -Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, 21986 -Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2, 21987 -Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and 21988 -Asparc6 respectively. 21989 21990‘-bump’ 21991 Warn whenever it is necessary to switch to another level. If an 21992 architecture level is explicitly requested, GAS will not issue 21993 warnings until that level is reached, and will then bump the level 21994 as required (except between incompatible levels). 21995 21996‘-32 | -64’ 21997 Select the word size, either 32 bits or 64 bits. These options are 21998 only available with the ELF object file format, and require that 21999 the necessary BFD support has been included. 22000 22001‘--dcti-couples-detect’ 22002 Warn if a DCTI (delayed control transfer instruction) couple is 22003 found when generating code for a variant of the SPARC architecture 22004 in which the execution of the couple is unpredictable, or very 22005 slow. This is disabled by default. 22006 22007 22008File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 22009 220109.45.2 Enforcing aligned data 22011----------------------------- 22012 22013SPARC GAS normally permits data to be misaligned. For example, it 22014permits the ‘.long’ pseudo-op to be used on a byte boundary. However, 22015the native SunOS assemblers issue an error when they see misaligned 22016data. 22017 22018 You can use the ‘--enforce-aligned-data’ option to make SPARC GAS 22019also issue an error about misaligned data, just as the SunOS assemblers 22020do. 22021 22022 The ‘--enforce-aligned-data’ option is not the default because gcc 22023issues misaligned data pseudo-ops when it initializes certain packed 22024data structures (structures defined using the ‘packed’ attribute). You 22025may have to assemble with GAS in order to initialize packed data 22026structures in your own code. 22027 22028 22029File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 22030 220319.45.3 Sparc Syntax 22032------------------- 22033 22034The assembler syntax closely follows The Sparc Architecture Manual, 22035versions 8 and 9, as well as most extensions defined by Sun for their 22036UltraSPARC and Niagara line of processors. 22037 22038* Menu: 22039 22040* Sparc-Chars:: Special Characters 22041* Sparc-Regs:: Register Names 22042* Sparc-Constants:: Constant Names 22043* Sparc-Relocs:: Relocations 22044* Sparc-Size-Translations:: Size Translations 22045 22046 22047File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 22048 220499.45.3.1 Special Characters 22050........................... 22051 22052A ‘!’ character appearing anywhere on a line indicates the start of a 22053comment that extends to the end of that line. 22054 22055 If a ‘#’ appears as the first character of a line then the whole line 22056is treated as a comment, but in this case the line could also be a 22057logical line number directive (*note Comments::) or a preprocessor 22058control command (*note Preprocessing::). 22059 22060 ‘;’ can be used instead of a newline to separate statements. 22061 22062 22063File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 22064 220659.45.3.2 Register Names 22066....................... 22067 22068The Sparc integer register file is broken down into global, outgoing, 22069local, and incoming. 22070 22071 • The 8 global registers are referred to as ‘%gN’. 22072 22073 • The 8 outgoing registers are referred to as ‘%oN’. 22074 22075 • The 8 local registers are referred to as ‘%lN’. 22076 22077 • The 8 incoming registers are referred to as ‘%iN’. 22078 22079 • The frame pointer register ‘%i6’ can be referenced using the alias 22080 ‘%fp’. 22081 22082 • The stack pointer register ‘%o6’ can be referenced using the alias 22083 ‘%sp’. 22084 22085 Floating point registers are simply referred to as ‘%fN’. When 22086assembling for pre-V9, only 32 floating point registers are available. 22087For V9 and later there are 64, but there are restrictions when 22088referencing the upper 32 registers. They can only be accessed as double 22089or quad, and thus only even or quad numbered accesses are allowed. For 22090example, ‘%f34’ is a legal floating point register, but ‘%f35’ is not. 22091 22092 Floating point registers accessed as double can also be referred 22093using the ‘%dN’ notation, where N is even. Similarly, floating point 22094registers accessed as quad can be referred using the ‘%qN’ notation, 22095where N is a multiple of 4. For example, ‘%f4’ can be denoted as both 22096‘%d4’ and ‘%q4’. On the other hand, ‘%f2’ can be denoted as ‘%d2’ but 22097not as ‘%q2’. 22098 22099 Certain V9 instructions allow access to ancillary state registers. 22100Most simply they can be referred to as ‘%asrN’ where N can be from 16 to 2210131. However, there are some aliases defined to reference ASR registers 22102defined for various UltraSPARC processors: 22103 22104 • The tick compare register is referred to as ‘%tick_cmpr’. 22105 22106 • The system tick register is referred to as ‘%stick’. An alias, 22107 ‘%sys_tick’, exists but is deprecated and should not be used by new 22108 software. 22109 22110 • The system tick compare register is referred to as ‘%stick_cmpr’. 22111 An alias, ‘%sys_tick_cmpr’, exists but is deprecated and should not 22112 be used by new software. 22113 22114 • The software interrupt register is referred to as ‘%softint’. 22115 22116 • The set software interrupt register is referred to as 22117 ‘%set_softint’. The mnemonic ‘%softint_set’ is provided as an 22118 alias. 22119 22120 • The clear software interrupt register is referred to as 22121 ‘%clear_softint’. The mnemonic ‘%softint_clear’ is provided as an 22122 alias. 22123 22124 • The performance instrumentation counters register is referred to as 22125 ‘%pic’. 22126 22127 • The performance control register is referred to as ‘%pcr’. 22128 22129 • The graphics status register is referred to as ‘%gsr’. 22130 22131 • The V9 dispatch control register is referred to as ‘%dcr’. 22132 22133 Various V9 branch and conditional move instructions allow 22134specification of which set of integer condition codes to test. These 22135are referred to as ‘%xcc’ and ‘%icc’. 22136 22137 Additionally, GAS supports the so-called “natural” condition codes; 22138these are referred to as ‘%ncc’ and reference to ‘%icc’ if the word size 22139is 32, ‘%xcc’ if the word size is 64. 22140 22141 In V9, there are 4 sets of floating point condition codes which are 22142referred to as ‘%fccN’. 22143 22144 Several special privileged and non-privileged registers exist: 22145 22146 • The V9 address space identifier register is referred to as ‘%asi’. 22147 22148 • The V9 restorable windows register is referred to as ‘%canrestore’. 22149 22150 • The V9 saveable windows register is referred to as ‘%cansave’. 22151 22152 • The V9 clean windows register is referred to as ‘%cleanwin’. 22153 22154 • The V9 current window pointer register is referred to as ‘%cwp’. 22155 22156 • The floating-point queue register is referred to as ‘%fq’. 22157 22158 • The V8 co-processor queue register is referred to as ‘%cq’. 22159 22160 • The floating point status register is referred to as ‘%fsr’. 22161 22162 • The other windows register is referred to as ‘%otherwin’. 22163 22164 • The V9 program counter register is referred to as ‘%pc’. 22165 22166 • The V9 next program counter register is referred to as ‘%npc’. 22167 22168 • The V9 processor interrupt level register is referred to as ‘%pil’. 22169 22170 • The V9 processor state register is referred to as ‘%pstate’. 22171 22172 • The trap base address register is referred to as ‘%tba’. 22173 22174 • The V9 tick register is referred to as ‘%tick’. 22175 22176 • The V9 trap level is referred to as ‘%tl’. 22177 22178 • The V9 trap program counter is referred to as ‘%tpc’. 22179 22180 • The V9 trap next program counter is referred to as ‘%tnpc’. 22181 22182 • The V9 trap state is referred to as ‘%tstate’. 22183 22184 • The V9 trap type is referred to as ‘%tt’. 22185 22186 • The V9 condition codes is referred to as ‘%ccr’. 22187 22188 • The V9 floating-point registers state is referred to as ‘%fprs’. 22189 22190 • The V9 version register is referred to as ‘%ver’. 22191 22192 • The V9 window state register is referred to as ‘%wstate’. 22193 22194 • The Y register is referred to as ‘%y’. 22195 22196 • The V8 window invalid mask register is referred to as ‘%wim’. 22197 22198 • The V8 processor state register is referred to as ‘%psr’. 22199 22200 • The V9 global register level register is referred to as ‘%gl’. 22201 22202 Several special register names exist for hypervisor mode code: 22203 22204 • The hyperprivileged processor state register is referred to as 22205 ‘%hpstate’. 22206 22207 • The hyperprivileged trap state register is referred to as 22208 ‘%htstate’. 22209 22210 • The hyperprivileged interrupt pending register is referred to as 22211 ‘%hintp’. 22212 22213 • The hyperprivileged trap base address register is referred to as 22214 ‘%htba’. 22215 22216 • The hyperprivileged implementation version register is referred to 22217 as ‘%hver’. 22218 22219 • The hyperprivileged system tick offset register is referred to as 22220 ‘%hstick_offset’. Note that there is no ‘%hstick’ register, the 22221 normal ‘%stick’ is used. 22222 22223 • The hyperprivileged system tick enable register is referred to as 22224 ‘%hstick_enable’. 22225 22226 • The hyperprivileged system tick compare register is referred to as 22227 ‘%hstick_cmpr’. 22228 22229 22230File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 22231 222329.45.3.3 Constants 22233.................. 22234 22235Several Sparc instructions take an immediate operand field for which 22236mnemonic names exist. Two such examples are ‘membar’ and ‘prefetch’. 22237Another example are the set of V9 memory access instruction that allow 22238specification of an address space identifier. 22239 22240 The ‘membar’ instruction specifies a memory barrier that is the 22241defined by the operand which is a bitmask. The supported mask mnemonics 22242are: 22243 22244 • ‘#Sync’ requests that all operations (including nonmemory reference 22245 operations) appearing prior to the ‘membar’ must have been 22246 performed and the effects of any exceptions become visible before 22247 any instructions after the ‘membar’ may be initiated. This 22248 corresponds to ‘membar’ cmask field bit 2. 22249 22250 • ‘#MemIssue’ requests that all memory reference operations appearing 22251 prior to the ‘membar’ must have been performed before any memory 22252 operation after the ‘membar’ may be initiated. This corresponds to 22253 ‘membar’ cmask field bit 1. 22254 22255 • ‘#Lookaside’ requests that a store appearing prior to the ‘membar’ 22256 must complete before any load following the ‘membar’ referencing 22257 the same address can be initiated. This corresponds to ‘membar’ 22258 cmask field bit 0. 22259 22260 • ‘#StoreStore’ defines that the effects of all stores appearing 22261 prior to the ‘membar’ instruction must be visible to all processors 22262 before the effect of any stores following the ‘membar’. Equivalent 22263 to the deprecated ‘stbar’ instruction. This corresponds to 22264 ‘membar’ mmask field bit 3. 22265 22266 • ‘#LoadStore’ defines all loads appearing prior to the ‘membar’ 22267 instruction must have been performed before the effect of any 22268 stores following the ‘membar’ is visible to any other processor. 22269 This corresponds to ‘membar’ mmask field bit 2. 22270 22271 • ‘#StoreLoad’ defines that the effects of all stores appearing prior 22272 to the ‘membar’ instruction must be visible to all processors 22273 before loads following the ‘membar’ may be performed. This 22274 corresponds to ‘membar’ mmask field bit 1. 22275 22276 • ‘#LoadLoad’ defines that all loads appearing prior to the ‘membar’ 22277 instruction must have been performed before any loads following the 22278 ‘membar’ may be performed. This corresponds to ‘membar’ mmask 22279 field bit 0. 22280 22281 These values can be ored together, for example: 22282 22283 membar #Sync 22284 membar #StoreLoad | #LoadLoad 22285 membar #StoreLoad | #StoreStore 22286 22287 The ‘prefetch’ and ‘prefetcha’ instructions take a prefetch function 22288code. The following prefetch function code constant mnemonics are 22289available: 22290 22291 • ‘#n_reads’ requests a prefetch for several reads, and corresponds 22292 to a prefetch function code of 0. 22293 22294 ‘#one_read’ requests a prefetch for one read, and corresponds to a 22295 prefetch function code of 1. 22296 22297 ‘#n_writes’ requests a prefetch for several writes (and possibly 22298 reads), and corresponds to a prefetch function code of 2. 22299 22300 ‘#one_write’ requests a prefetch for one write, and corresponds to 22301 a prefetch function code of 3. 22302 22303 ‘#page’ requests a prefetch page, and corresponds to a prefetch 22304 function code of 4. 22305 22306 ‘#invalidate’ requests a prefetch invalidate, and corresponds to a 22307 prefetch function code of 16. 22308 22309 ‘#unified’ requests a prefetch to the nearest unified cache, and 22310 corresponds to a prefetch function code of 17. 22311 22312 ‘#n_reads_strong’ requests a strong prefetch for several reads, and 22313 corresponds to a prefetch function code of 20. 22314 22315 ‘#one_read_strong’ requests a strong prefetch for one read, and 22316 corresponds to a prefetch function code of 21. 22317 22318 ‘#n_writes_strong’ requests a strong prefetch for several writes, 22319 and corresponds to a prefetch function code of 22. 22320 22321 ‘#one_write_strong’ requests a strong prefetch for one write, and 22322 corresponds to a prefetch function code of 23. 22323 22324 Onle one prefetch code may be specified. Here are some examples: 22325 22326 prefetch [%l0 + %l2], #one_read 22327 prefetch [%g2 + 8], #n_writes 22328 prefetcha [%g1] 0x8, #unified 22329 prefetcha [%o0 + 0x10] %asi, #n_reads 22330 22331 The actual behavior of a given prefetch function code is processor 22332 specific. If a processor does not implement a given prefetch 22333 function code, it will treat the prefetch instruction as a nop. 22334 22335 For instructions that accept an immediate address space identifier, 22336 ‘as’ provides many mnemonics corresponding to V9 defined as well as 22337 UltraSPARC and Niagara extended values. For example, ‘#ASI_P’ and 22338 ‘#ASI_BLK_INIT_QUAD_LDD_AIUS’. See the V9 and processor specific 22339 manuals for details. 22340 22341 22342File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 22343 223449.45.3.4 Relocations 22345.................... 22346 22347ELF relocations are available as defined in the 32-bit and 64-bit Sparc 22348ELF specifications. 22349 22350 ‘R_SPARC_HI22’ is obtained using ‘%hi’ and ‘R_SPARC_LO10’ is obtained 22351using ‘%lo’. Likewise ‘R_SPARC_HIX22’ is obtained from ‘%hix’ and 22352‘R_SPARC_LOX10’ is obtained using ‘%lox’. For example: 22353 22354 sethi %hi(symbol), %g1 22355 or %g1, %lo(symbol), %g1 22356 22357 sethi %hix(symbol), %g1 22358 xor %g1, %lox(symbol), %g1 22359 22360 These “high” mnemonics extract bits 31:10 of their operand, and the 22361“low” mnemonics extract bits 9:0 of their operand. 22362 22363 V9 code model relocations can be requested as follows: 22364 22365 • ‘R_SPARC_HH22’ is requested using ‘%hh’. It can also be generated 22366 using ‘%uhi’. 22367 • ‘R_SPARC_HM10’ is requested using ‘%hm’. It can also be generated 22368 using ‘%ulo’. 22369 • ‘R_SPARC_LM22’ is requested using ‘%lm’. 22370 22371 • ‘R_SPARC_H44’ is requested using ‘%h44’. 22372 • ‘R_SPARC_M44’ is requested using ‘%m44’. 22373 • ‘R_SPARC_L44’ is requested using ‘%l44’ or ‘%l34’. 22374 • ‘R_SPARC_H34’ is requested using ‘%h34’. 22375 22376 The ‘%l34’ generates a ‘R_SPARC_L44’ relocation because it calculates 22377the necessary value, and therefore no explicit ‘R_SPARC_L34’ relocation 22378needed to be created for this purpose. 22379 22380 The ‘%h34’ and ‘%l34’ relocations are used for the abs34 code model. 22381Here is an example abs34 address generation sequence: 22382 22383 sethi %h34(symbol), %g1 22384 sllx %g1, 2, %g1 22385 or %g1, %l34(symbol), %g1 22386 22387 The PC relative relocation ‘R_SPARC_PC22’ can be obtained by 22388enclosing an operand inside of ‘%pc22’. Likewise, the ‘R_SPARC_PC10’ 22389relocation can be obtained using ‘%pc10’. These are mostly used when 22390assembling PIC code. For example, the standard PIC sequence on Sparc to 22391get the base of the global offset table, PC relative, into a register, 22392can be performed as: 22393 22394 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 22395 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 22396 22397 Several relocations exist to allow the link editor to potentially 22398optimize GOT data references. The ‘R_SPARC_GOTDATA_OP_HIX22’ relocation 22399can obtained by enclosing an operand inside of ‘%gdop_hix22’. The 22400‘R_SPARC_GOTDATA_OP_LOX10’ relocation can obtained by enclosing an 22401operand inside of ‘%gdop_lox10’. Likewise, ‘R_SPARC_GOTDATA_OP’ can be 22402obtained by enclosing an operand inside of ‘%gdop’. For example, 22403assuming the GOT base is in register ‘%l7’: 22404 22405 sethi %gdop_hix22(symbol), %l1 22406 xor %l1, %gdop_lox10(symbol), %l1 22407 ld [%l7 + %l1], %l2, %gdop(symbol) 22408 22409 There are many relocations that can be requested for access to thread 22410local storage variables. All of the Sparc TLS mnemonics are supported: 22411 22412 • ‘R_SPARC_TLS_GD_HI22’ is requested using ‘%tgd_hi22’. 22413 • ‘R_SPARC_TLS_GD_LO10’ is requested using ‘%tgd_lo10’. 22414 • ‘R_SPARC_TLS_GD_ADD’ is requested using ‘%tgd_add’. 22415 • ‘R_SPARC_TLS_GD_CALL’ is requested using ‘%tgd_call’. 22416 22417 • ‘R_SPARC_TLS_LDM_HI22’ is requested using ‘%tldm_hi22’. 22418 • ‘R_SPARC_TLS_LDM_LO10’ is requested using ‘%tldm_lo10’. 22419 • ‘R_SPARC_TLS_LDM_ADD’ is requested using ‘%tldm_add’. 22420 • ‘R_SPARC_TLS_LDM_CALL’ is requested using ‘%tldm_call’. 22421 22422 • ‘R_SPARC_TLS_LDO_HIX22’ is requested using ‘%tldo_hix22’. 22423 • ‘R_SPARC_TLS_LDO_LOX10’ is requested using ‘%tldo_lox10’. 22424 • ‘R_SPARC_TLS_LDO_ADD’ is requested using ‘%tldo_add’. 22425 22426 • ‘R_SPARC_TLS_IE_HI22’ is requested using ‘%tie_hi22’. 22427 • ‘R_SPARC_TLS_IE_LO10’ is requested using ‘%tie_lo10’. 22428 • ‘R_SPARC_TLS_IE_LD’ is requested using ‘%tie_ld’. 22429 • ‘R_SPARC_TLS_IE_LDX’ is requested using ‘%tie_ldx’. 22430 • ‘R_SPARC_TLS_IE_ADD’ is requested using ‘%tie_add’. 22431 22432 • ‘R_SPARC_TLS_LE_HIX22’ is requested using ‘%tle_hix22’. 22433 • ‘R_SPARC_TLS_LE_LOX10’ is requested using ‘%tle_lox10’. 22434 22435 Here are some example TLS model sequences. 22436 22437 First, General Dynamic: 22438 22439 sethi %tgd_hi22(symbol), %l1 22440 add %l1, %tgd_lo10(symbol), %l1 22441 add %l7, %l1, %o0, %tgd_add(symbol) 22442 call __tls_get_addr, %tgd_call(symbol) 22443 nop 22444 22445 Local Dynamic: 22446 22447 sethi %tldm_hi22(symbol), %l1 22448 add %l1, %tldm_lo10(symbol), %l1 22449 add %l7, %l1, %o0, %tldm_add(symbol) 22450 call __tls_get_addr, %tldm_call(symbol) 22451 nop 22452 22453 sethi %tldo_hix22(symbol), %l1 22454 xor %l1, %tldo_lox10(symbol), %l1 22455 add %o0, %l1, %l1, %tldo_add(symbol) 22456 22457 Initial Exec: 22458 22459 sethi %tie_hi22(symbol), %l1 22460 add %l1, %tie_lo10(symbol), %l1 22461 ld [%l7 + %l1], %o0, %tie_ld(symbol) 22462 add %g7, %o0, %o0, %tie_add(symbol) 22463 22464 sethi %tie_hi22(symbol), %l1 22465 add %l1, %tie_lo10(symbol), %l1 22466 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 22467 add %g7, %o0, %o0, %tie_add(symbol) 22468 22469 And finally, Local Exec: 22470 22471 sethi %tle_hix22(symbol), %l1 22472 add %l1, %tle_lox10(symbol), %l1 22473 add %g7, %l1, %l1 22474 22475 When assembling for 64-bit, and a secondary constant addend is 22476specified in an address expression that would normally generate an 22477‘R_SPARC_LO10’ relocation, the assembler will emit an ‘R_SPARC_OLO10’ 22478instead. 22479 22480 22481File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 22482 224839.45.3.5 Size Translations 22484.......................... 22485 22486Often it is desirable to write code in an operand size agnostic manner. 22487‘as’ provides support for this via operand size opcode translations. 22488Translations are supported for loads, stores, shifts, compare-and-swap 22489atomics, and the ‘clr’ synthetic instruction. 22490 22491 If generating 32-bit code, ‘as’ will generate the 32-bit opcode. 22492Whereas if 64-bit code is being generated, the 64-bit opcode will be 22493emitted. For example ‘ldn’ will be transformed into ‘ld’ for 32-bit 22494code and ‘ldx’ for 64-bit code. 22495 22496 Here is an example meant to demonstrate all the supported opcode 22497translations: 22498 22499 ldn [%o0], %o1 22500 ldna [%o0] %asi, %o2 22501 stn %o1, [%o0] 22502 stna %o2, [%o0] %asi 22503 slln %o3, 3, %o3 22504 srln %o4, 8, %o4 22505 sran %o5, 12, %o5 22506 casn [%o0], %o1, %o2 22507 casna [%o0] %asi, %o1, %o2 22508 clrn %g1 22509 22510 In 32-bit mode ‘as’ will emit: 22511 22512 ld [%o0], %o1 22513 lda [%o0] %asi, %o2 22514 st %o1, [%o0] 22515 sta %o2, [%o0] %asi 22516 sll %o3, 3, %o3 22517 srl %o4, 8, %o4 22518 sra %o5, 12, %o5 22519 cas [%o0], %o1, %o2 22520 casa [%o0] %asi, %o1, %o2 22521 clr %g1 22522 22523 And in 64-bit mode ‘as’ will emit: 22524 22525 ldx [%o0], %o1 22526 ldxa [%o0] %asi, %o2 22527 stx %o1, [%o0] 22528 stxa %o2, [%o0] %asi 22529 sllx %o3, 3, %o3 22530 srlx %o4, 8, %o4 22531 srax %o5, 12, %o5 22532 casx [%o0], %o1, %o2 22533 casxa [%o0] %asi, %o1, %o2 22534 clrx %g1 22535 22536 Finally, the ‘.nword’ translating directive is supported as well. It 22537is documented in the section on Sparc machine directives. 22538 22539 22540File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 22541 225429.45.4 Floating Point 22543--------------------- 22544 22545The Sparc uses IEEE floating-point numbers. 22546 22547 22548File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 22549 225509.45.5 Sparc Machine Directives 22551------------------------------- 22552 22553The Sparc version of ‘as’ supports the following additional machine 22554directives: 22555 22556‘.align’ 22557 This must be followed by the desired alignment in bytes. 22558 22559‘.common’ 22560 This must be followed by a symbol name, a positive number, and 22561 ‘"bss"’. This behaves somewhat like ‘.comm’, but the syntax is 22562 different. 22563 22564‘.half’ 22565 This is functionally identical to ‘.short’. 22566 22567‘.nword’ 22568 On the Sparc, the ‘.nword’ directive produces native word sized 22569 value, ie. if assembling with -32 it is equivalent to ‘.word’, if 22570 assembling with -64 it is equivalent to ‘.xword’. 22571 22572‘.proc’ 22573 This directive is ignored. Any text following it on the same line 22574 is also ignored. 22575 22576‘.register’ 22577 This directive declares use of a global application or system 22578 register. It must be followed by a register name %g2, %g3, %g6 or 22579 %g7, comma and the symbol name for that register. If symbol name 22580 is ‘#scratch’, it is a scratch register, if it is ‘#ignore’, it 22581 just suppresses any errors about using undeclared global register, 22582 but does not emit any information about it into the object file. 22583 This can be useful e.g. if you save the register before use and 22584 restore it after. 22585 22586‘.reserve’ 22587 This must be followed by a symbol name, a positive number, and 22588 ‘"bss"’. This behaves somewhat like ‘.lcomm’, but the syntax is 22589 different. 22590 22591‘.seg’ 22592 This must be followed by ‘"text"’, ‘"data"’, or ‘"data1"’. It 22593 behaves like ‘.text’, ‘.data’, or ‘.data 1’. 22594 22595‘.skip’ 22596 This is functionally identical to the ‘.space’ directive. 22597 22598‘.word’ 22599 On the Sparc, the ‘.word’ directive produces 32 bit values, instead 22600 of the 16 bit values it produces on many other machines. 22601 22602‘.xword’ 22603 On the Sparc V9 processor, the ‘.xword’ directive produces 64 bit 22604 values. 22605 22606 22607File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 22608 226099.46 TIC54X Dependent Features 22610============================== 22611 22612* Menu: 22613 22614* TIC54X-Opts:: Command-line Options 22615* TIC54X-Block:: Blocking 22616* TIC54X-Env:: Environment Settings 22617* TIC54X-Constants:: Constants Syntax 22618* TIC54X-Subsyms:: String Substitution 22619* TIC54X-Locals:: Local Label Syntax 22620* TIC54X-Builtins:: Builtin Assembler Math Functions 22621* TIC54X-Ext:: Extended Addressing Support 22622* TIC54X-Directives:: Directives 22623* TIC54X-Macros:: Macro Features 22624* TIC54X-MMRegs:: Memory-mapped Registers 22625* TIC54X-Syntax:: Syntax 22626 22627 22628File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 22629 226309.46.1 Options 22631-------------- 22632 22633The TMS320C54X version of ‘as’ has a few machine-dependent options. 22634 22635 You can use the ‘-mfar-mode’ option to enable extended addressing 22636mode. All addresses will be assumed to be > 16 bits, and the 22637appropriate relocation types will be used. This option is equivalent to 22638using the ‘.far_mode’ directive in the assembly code. If you do not use 22639the ‘-mfar-mode’ option, all references will be assumed to be 16 bits. 22640This option may be abbreviated to ‘-mf’. 22641 22642 You can use the ‘-mcpu’ option to specify a particular CPU. This 22643option is equivalent to using the ‘.version’ directive in the assembly 22644code. For recognized CPU codes, see *Note ‘.version’: 22645TIC54X-Directives. The default CPU version is ‘542’. 22646 22647 You can use the ‘-merrors-to-file’ option to redirect error output to 22648a file (this provided for those deficient environments which don’t 22649provide adequate output redirection). This option may be abbreviated to 22650‘-me’. 22651 22652 22653File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 22654 226559.46.2 Blocking 22656--------------- 22657 22658A blocked section or memory block is guaranteed not to cross the 22659blocking boundary (usually a page, or 128 words) if it is smaller than 22660the blocking size, or to start on a page boundary if it is larger than 22661the blocking size. 22662 22663 22664File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 22665 226669.46.3 Environment Settings 22667--------------------------- 22668 22669‘C54XDSP_DIR’ and ‘A_DIR’ are semicolon-separated paths which are added 22670to the list of directories normally searched for source and include 22671files. ‘C54XDSP_DIR’ will override ‘A_DIR’. 22672 22673 22674File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 22675 226769.46.4 Constants Syntax 22677----------------------- 22678 22679The TIC54X version of ‘as’ allows the following additional constant 22680formats, using a suffix to indicate the radix: 22681 22682 Binary 000000B, 011000b 22683 Octal 10Q, 224q 22684 Hexadecimal 45h, 0FH 22685 22686 22687 22688File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 22689 226909.46.5 String Substitution 22691-------------------------- 22692 22693A subset of allowable symbols (which we’ll call subsyms) may be assigned 22694arbitrary string values. This is roughly equivalent to C preprocessor 22695#define macros. When ‘as’ encounters one of these symbols, the symbol 22696is replaced in the input stream by its string value. Subsym names 22697*must* begin with a letter. 22698 22699 Subsyms may be defined using the ‘.asg’ and ‘.eval’ directives (*Note 22700‘.asg’: TIC54X-Directives, *Note ‘.eval’: TIC54X-Directives. 22701 22702 Expansion is recursive until a previously encountered symbol is seen, 22703at which point substitution stops. 22704 22705 In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, 22706and SYM1 is replaced with x. At this point, x has already been 22707encountered and the substitution stops. 22708 22709 .asg "x",SYM1 22710 .asg "SYM1",SYM2 22711 .asg "SYM2",x 22712 add x,a ; final code assembled is "add x, a" 22713 22714 Macro parameters are converted to subsyms; a side effect of this is 22715the normal ‘as’ ’\ARG’ dereferencing syntax is unnecessary. Subsyms 22716defined within a macro will have global scope, unless the ‘.var’ 22717directive is used to identify the subsym as a local macro variable *note 22718‘.var’: TIC54X-Directives. 22719 22720 Substitution may be forced in situations where replacement might be 22721ambiguous by placing colons on either side of the subsym. The following 22722code: 22723 22724 .eval "10",x 22725 LAB:X: add #x, a 22726 22727 When assembled becomes: 22728 22729 LAB10 add #10, a 22730 22731 Smaller parts of the string assigned to a subsym may be accessed with 22732the following syntax: 22733 22734‘:SYMBOL(CHAR_INDEX):’ 22735 Evaluates to a single-character string, the character at 22736 CHAR_INDEX. 22737‘:SYMBOL(START,LENGTH):’ 22738 Evaluates to a substring of SYMBOL beginning at START with length 22739 LENGTH. 22740 22741 22742File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 22743 227449.46.6 Local Labels 22745------------------- 22746 22747Local labels may be defined in two ways: 22748 22749 • $N, where N is a decimal number between 0 and 9 22750 • LABEL?, where LABEL is any legal symbol name. 22751 22752 Local labels thus defined may be redefined or automatically 22753generated. The scope of a local label is based on when it may be 22754undefined or reset. This happens when one of the following situations 22755is encountered: 22756 22757 • .newblock directive *note ‘.newblock’: TIC54X-Directives. 22758 • The current section is changed (.sect, .text, or .data) 22759 • Entering or leaving an included file 22760 • The macro scope where the label was defined is exited 22761 22762 22763File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 22764 227659.46.7 Math Builtins 22766-------------------- 22767 22768The following built-in functions may be used to generate a 22769floating-point value. All return a floating-point value except ‘$cvi’, 22770‘$int’, and ‘$sgn’, which return an integer value. 22771 22772‘$acos(EXPR)’ 22773 Returns the floating point arccosine of EXPR. 22774 22775‘$asin(EXPR)’ 22776 Returns the floating point arcsine of EXPR. 22777 22778‘$atan(EXPR)’ 22779 Returns the floating point arctangent of EXPR. 22780 22781‘$atan2(EXPR1,EXPR2)’ 22782 Returns the floating point arctangent of EXPR1 / EXPR2. 22783 22784‘$ceil(EXPR)’ 22785 Returns the smallest integer not less than EXPR as floating point. 22786 22787‘$cosh(EXPR)’ 22788 Returns the floating point hyperbolic cosine of EXPR. 22789 22790‘$cos(EXPR)’ 22791 Returns the floating point cosine of EXPR. 22792 22793‘$cvf(EXPR)’ 22794 Returns the integer value EXPR converted to floating-point. 22795 22796‘$cvi(EXPR)’ 22797 Returns the floating point value EXPR converted to integer. 22798 22799‘$exp(EXPR)’ 22800 Returns the floating point value e ^ EXPR. 22801 22802‘$fabs(EXPR)’ 22803 Returns the floating point absolute value of EXPR. 22804 22805‘$floor(EXPR)’ 22806 Returns the largest integer that is not greater than EXPR as 22807 floating point. 22808 22809‘$fmod(EXPR1,EXPR2)’ 22810 Returns the floating point remainder of EXPR1 / EXPR2. 22811 22812‘$int(EXPR)’ 22813 Returns 1 if EXPR evaluates to an integer, zero otherwise. 22814 22815‘$ldexp(EXPR1,EXPR2)’ 22816 Returns the floating point value EXPR1 * 2 ^ EXPR2. 22817 22818‘$log10(EXPR)’ 22819 Returns the base 10 logarithm of EXPR. 22820 22821‘$log(EXPR)’ 22822 Returns the natural logarithm of EXPR. 22823 22824‘$max(EXPR1,EXPR2)’ 22825 Returns the floating point maximum of EXPR1 and EXPR2. 22826 22827‘$min(EXPR1,EXPR2)’ 22828 Returns the floating point minimum of EXPR1 and EXPR2. 22829 22830‘$pow(EXPR1,EXPR2)’ 22831 Returns the floating point value EXPR1 ^ EXPR2. 22832 22833‘$round(EXPR)’ 22834 Returns the nearest integer to EXPR as a floating point number. 22835 22836‘$sgn(EXPR)’ 22837 Returns -1, 0, or 1 based on the sign of EXPR. 22838 22839‘$sin(EXPR)’ 22840 Returns the floating point sine of EXPR. 22841 22842‘$sinh(EXPR)’ 22843 Returns the floating point hyperbolic sine of EXPR. 22844 22845‘$sqrt(EXPR)’ 22846 Returns the floating point square root of EXPR. 22847 22848‘$tan(EXPR)’ 22849 Returns the floating point tangent of EXPR. 22850 22851‘$tanh(EXPR)’ 22852 Returns the floating point hyperbolic tangent of EXPR. 22853 22854‘$trunc(EXPR)’ 22855 Returns the integer value of EXPR truncated towards zero as 22856 floating point. 22857 22858 22859File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 22860 228619.46.8 Extended Addressing 22862-------------------------- 22863 22864The ‘LDX’ pseudo-op is provided for loading the extended addressing bits 22865of a label or address. For example, if an address ‘_label’ resides in 22866extended program memory, the value of ‘_label’ may be loaded as follows: 22867 ldx #_label,16,a ; loads extended bits of _label 22868 or #_label,a ; loads lower 16 bits of _label 22869 bacc a ; full address is in accumulator A 22870 22871 22872File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 22873 228749.46.9 Directives 22875----------------- 22876 22877‘.align [SIZE]’ 22878‘.even’ 22879 Align the section program counter on the next boundary, based on 22880 SIZE. SIZE may be any power of 2. ‘.even’ is equivalent to 22881 ‘.align’ with a SIZE of 2. 22882 ‘1’ 22883 Align SPC to word boundary 22884 ‘2’ 22885 Align SPC to longword boundary (same as .even) 22886 ‘128’ 22887 Align SPC to page boundary 22888 22889‘.asg STRING, NAME’ 22890 Assign NAME the string STRING. String replacement is performed on 22891 STRING before assignment. 22892 22893‘.eval STRING, NAME’ 22894 Evaluate the contents of string STRING and assign the result as a 22895 string to the subsym NAME. String replacement is performed on 22896 STRING before assignment. 22897 22898‘.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]’ 22899 Reserve space for SYMBOL in the .bss section. SIZE is in words. 22900 If present, BLOCKING_FLAG indicates the allocated space should be 22901 aligned on a page boundary if it would otherwise cross a page 22902 boundary. If present, ALIGNMENT_FLAG causes the assembler to 22903 allocate SIZE on a long word boundary. 22904 22905‘.byte VALUE [,...,VALUE_N]’ 22906‘.ubyte VALUE [,...,VALUE_N]’ 22907‘.char VALUE [,...,VALUE_N]’ 22908‘.uchar VALUE [,...,VALUE_N]’ 22909 Place one or more bytes into consecutive words of the current 22910 section. The upper 8 bits of each word is zero-filled. If a label 22911 is used, it points to the word allocated for the first byte 22912 encountered. 22913 22914‘.clink ["SECTION_NAME"]’ 22915 Set STYP_CLINK flag for this section, which indicates to the linker 22916 that if no symbols from this section are referenced, the section 22917 should not be included in the link. If SECTION_NAME is omitted, 22918 the current section is used. 22919 22920‘.c_mode’ 22921 TBD. 22922 22923‘.copy "FILENAME" | FILENAME’ 22924‘.include "FILENAME" | FILENAME’ 22925 Read source statements from FILENAME. The normal include search 22926 path is used. Normally .copy will cause statements from the 22927 included file to be printed in the assembly listing and .include 22928 will not, but this distinction is not currently implemented. 22929 22930‘.data’ 22931 Begin assembling code into the .data section. 22932 22933‘.double VALUE [,...,VALUE_N]’ 22934‘.ldouble VALUE [,...,VALUE_N]’ 22935‘.float VALUE [,...,VALUE_N]’ 22936‘.xfloat VALUE [,...,VALUE_N]’ 22937 Place an IEEE single-precision floating-point representation of one 22938 or more floating-point values into the current section. All but 22939 ‘.xfloat’ align the result on a longword boundary. Values are 22940 stored most-significant word first. 22941 22942‘.drlist’ 22943‘.drnolist’ 22944 Control printing of directives to the listing file. Ignored. 22945 22946‘.emsg STRING’ 22947‘.mmsg STRING’ 22948‘.wmsg STRING’ 22949 Emit a user-defined error, message, or warning, respectively. 22950 22951‘.far_mode’ 22952 Use extended addressing when assembling statements. This should 22953 appear only once per file, and is equivalent to the -mfar-mode 22954 option *note ‘-mfar-mode’: TIC54X-Opts. 22955 22956‘.fclist’ 22957‘.fcnolist’ 22958 Control printing of false conditional blocks to the listing file. 22959 22960‘.field VALUE [,SIZE]’ 22961 Initialize a bitfield of SIZE bits in the current section. If 22962 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 22963 bits. If VALUE does not fit into SIZE bits, the value will be 22964 truncated. Successive ‘.field’ directives will pack starting at 22965 the current word, filling the most significant bits first, and 22966 aligning to the start of the next word if the field size does not 22967 fit into the space remaining in the current word. A ‘.align’ 22968 directive with an operand of 1 will force the next ‘.field’ 22969 directive to begin packing into a new word. If a label is used, it 22970 points to the word that contains the specified field. 22971 22972‘.global SYMBOL [,...,SYMBOL_N]’ 22973‘.def SYMBOL [,...,SYMBOL_N]’ 22974‘.ref SYMBOL [,...,SYMBOL_N]’ 22975 ‘.def’ nominally identifies a symbol defined in the current file 22976 and available to other files. ‘.ref’ identifies a symbol used in 22977 the current file but defined elsewhere. Both map to the standard 22978 ‘.global’ directive. 22979 22980‘.half VALUE [,...,VALUE_N]’ 22981‘.uhalf VALUE [,...,VALUE_N]’ 22982‘.short VALUE [,...,VALUE_N]’ 22983‘.ushort VALUE [,...,VALUE_N]’ 22984‘.int VALUE [,...,VALUE_N]’ 22985‘.uint VALUE [,...,VALUE_N]’ 22986‘.word VALUE [,...,VALUE_N]’ 22987‘.uword VALUE [,...,VALUE_N]’ 22988 Place one or more values into consecutive words of the current 22989 section. If a label is used, it points to the word allocated for 22990 the first value encountered. 22991 22992‘.label SYMBOL’ 22993 Define a special SYMBOL to refer to the load time address of the 22994 current section program counter. 22995 22996‘.length’ 22997‘.width’ 22998 Set the page length and width of the output listing file. Ignored. 22999 23000‘.list’ 23001‘.nolist’ 23002 Control whether the source listing is printed. Ignored. 23003 23004‘.long VALUE [,...,VALUE_N]’ 23005‘.ulong VALUE [,...,VALUE_N]’ 23006‘.xlong VALUE [,...,VALUE_N]’ 23007 Place one or more 32-bit values into consecutive words in the 23008 current section. The most significant word is stored first. 23009 ‘.long’ and ‘.ulong’ align the result on a longword boundary; 23010 ‘xlong’ does not. 23011 23012‘.loop [COUNT]’ 23013‘.break [CONDITION]’ 23014‘.endloop’ 23015 Repeatedly assemble a block of code. ‘.loop’ begins the block, and 23016 ‘.endloop’ marks its termination. COUNT defaults to 1024, and 23017 indicates the number of times the block should be repeated. 23018 ‘.break’ terminates the loop so that assembly begins after the 23019 ‘.endloop’ directive. The optional CONDITION will cause the loop 23020 to terminate only if it evaluates to zero. 23021 23022‘MACRO_NAME .macro [PARAM1][,...PARAM_N]’ 23023‘[.mexit]’ 23024‘.endm’ 23025 See the section on macros for more explanation (*Note 23026 TIC54X-Macros::. 23027 23028‘.mlib "FILENAME" | FILENAME’ 23029 Load the macro library FILENAME. FILENAME must be an archived 23030 library (BFD ar-compatible) of text files, expected to contain only 23031 macro definitions. The standard include search path is used. 23032 23033‘.mlist’ 23034‘.mnolist’ 23035 Control whether to include macro and loop block expansions in the 23036 listing output. Ignored. 23037 23038‘.mmregs’ 23039 Define global symbolic names for the ’c54x registers. Supposedly 23040 equivalent to executing ‘.set’ directives for each register with 23041 its memory-mapped value, but in reality is provided only for 23042 compatibility and does nothing. 23043 23044‘.newblock’ 23045 This directive resets any TIC54X local labels currently defined. 23046 Normal ‘as’ local labels are unaffected. 23047 23048‘.option OPTION_LIST’ 23049 Set listing options. Ignored. 23050 23051‘.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]’ 23052 Designate SECTION_NAME for blocking. Blocking guarantees that a 23053 section will start on a page boundary (128 words) if it would 23054 otherwise cross a page boundary. Only initialized sections may be 23055 designated with this directive. See also *Note TIC54X-Block::. 23056 23057‘.sect "SECTION_NAME"’ 23058 Define a named initialized section and make it the current section. 23059 23060‘SYMBOL .set "VALUE"’ 23061‘SYMBOL .equ "VALUE"’ 23062 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 23063 table. SYMBOL may not be previously defined. 23064 23065‘.space SIZE_IN_BITS’ 23066‘.bes SIZE_IN_BITS’ 23067 Reserve the given number of bits in the current section and 23068 zero-fill them. If a label is used with ‘.space’, it points to the 23069 *first* word reserved. With ‘.bes’, the label points to the *last* 23070 word reserved. 23071 23072‘.sslist’ 23073‘.ssnolist’ 23074 Controls the inclusion of subsym replacement in the listing output. 23075 Ignored. 23076 23077‘.string "STRING" [,...,"STRING_N"]’ 23078‘.pstring "STRING" [,...,"STRING_N"]’ 23079 Place 8-bit characters from STRING into the current section. 23080 ‘.string’ zero-fills the upper 8 bits of each word, while 23081 ‘.pstring’ puts two characters into each word, filling the 23082 most-significant bits first. Unused space is zero-filled. If a 23083 label is used, it points to the first word initialized. 23084 23085‘[STAG] .struct [OFFSET]’ 23086‘[NAME_1] element [COUNT_1]’ 23087‘[NAME_2] element [COUNT_2]’ 23088‘[TNAME] .tag STAGX [TCOUNT]’ 23089‘...’ 23090‘[NAME_N] element [COUNT_N]’ 23091‘[SSIZE] .endstruct’ 23092‘LABEL .tag [STAG]’ 23093 Assign symbolic offsets to the elements of a structure. STAG 23094 defines a symbol to use to reference the structure. OFFSET 23095 indicates a starting value to use for the first element 23096 encountered; otherwise it defaults to zero. Each element can have 23097 a named offset, NAME, which is a symbol assigned the value of the 23098 element’s offset into the structure. If STAG is missing, these 23099 become global symbols. COUNT adjusts the offset that many times, 23100 as if ‘element’ were an array. ‘element’ may be one of ‘.byte’, 23101 ‘.word’, ‘.long’, ‘.float’, or any equivalent of those, and the 23102 structure offset is adjusted accordingly. ‘.field’ and ‘.string’ 23103 are also allowed; the size of ‘.field’ is one bit, and ‘.string’ is 23104 considered to be one word in size. Only element descriptors, 23105 structure/union tags, ‘.align’ and conditional assembly directives 23106 are allowed within ‘.struct’/‘.endstruct’. ‘.align’ aligns member 23107 offsets to word boundaries only. SSIZE, if provided, will always 23108 be assigned the size of the structure. 23109 23110 The ‘.tag’ directive, in addition to being used to define a 23111 structure/union element within a structure, may be used to apply a 23112 structure to a symbol. Once applied to LABEL, the individual 23113 structure elements may be applied to LABEL to produce the desired 23114 offsets using LABEL as the structure base. 23115 23116‘.tab’ 23117 Set the tab size in the output listing. Ignored. 23118 23119‘[UTAG] .union’ 23120‘[NAME_1] element [COUNT_1]’ 23121‘[NAME_2] element [COUNT_2]’ 23122‘[TNAME] .tag UTAGX[,TCOUNT]’ 23123‘...’ 23124‘[NAME_N] element [COUNT_N]’ 23125‘[USIZE] .endstruct’ 23126‘LABEL .tag [UTAG]’ 23127 Similar to ‘.struct’, but the offset after each element is reset to 23128 zero, and the USIZE is set to the maximum of all defined elements. 23129 Starting offset for the union is always zero. 23130 23131‘[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]’ 23132 Reserve space for variables in a named, uninitialized section 23133 (similar to .bss). ‘.usect’ allows definitions sections 23134 independent of .bss. SYMBOL points to the first location reserved 23135 by this allocation. The symbol may be used as a variable name. 23136 SIZE is the allocated size in words. BLOCKING_FLAG indicates 23137 whether to block this section on a page boundary (128 words) (*note 23138 TIC54X-Block::). ALIGNMENT FLAG indicates whether the section 23139 should be longword-aligned. 23140 23141‘.var SYM[,..., SYM_N]’ 23142 Define a subsym to be a local variable within a macro. See *Note 23143 TIC54X-Macros::. 23144 23145‘.version VERSION’ 23146 Set which processor to build instructions for. Though the 23147 following values are accepted, the op is ignored. 23148 ‘541’ 23149 ‘542’ 23150 ‘543’ 23151 ‘545’ 23152 ‘545LP’ 23153 ‘546LP’ 23154 ‘548’ 23155 ‘549’ 23156 23157 23158File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 23159 231609.46.10 Macros 23161-------------- 23162 23163Macros do not require explicit dereferencing of arguments (i.e., \ARG). 23164 23165 During macro expansion, the macro parameters are converted to 23166subsyms. If the number of arguments passed the macro invocation exceeds 23167the number of parameters defined, the last parameter is assigned the 23168string equivalent of all remaining arguments. If fewer arguments are 23169given than parameters, the missing parameters are assigned empty 23170strings. To include a comma in an argument, you must enclose the 23171argument in quotes. 23172 23173 The following built-in subsym functions allow examination of the 23174string value of subsyms (or ordinary strings). The arguments are 23175strings unless otherwise indicated (subsyms passed as args will be 23176replaced by the strings they represent). 23177‘$symlen(STR)’ 23178 Returns the length of STR. 23179 23180‘$symcmp(STR1,STR2)’ 23181 Returns 0 if STR1 == STR2, non-zero otherwise. 23182 23183‘$firstch(STR,CH)’ 23184 Returns index of the first occurrence of character constant CH in 23185 STR. 23186 23187‘$lastch(STR,CH)’ 23188 Returns index of the last occurrence of character constant CH in 23189 STR. 23190 23191‘$isdefed(SYMBOL)’ 23192 Returns zero if the symbol SYMBOL is not in the symbol table, 23193 non-zero otherwise. 23194 23195‘$ismember(SYMBOL,LIST)’ 23196 Assign the first member of comma-separated string LIST to SYMBOL; 23197 LIST is reassigned the remainder of the list. Returns zero if LIST 23198 is a null string. Both arguments must be subsyms. 23199 23200‘$iscons(EXPR)’ 23201 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4 23202 if a character, 5 if decimal, and zero if not an integer. 23203 23204‘$isname(NAME)’ 23205 Returns 1 if NAME is a valid symbol name, zero otherwise. 23206 23207‘$isreg(REG)’ 23208 Returns 1 if REG is a valid predefined register name (AR0-AR7 23209 only). 23210 23211‘$structsz(STAG)’ 23212 Returns the size of the structure or union represented by STAG. 23213 23214‘$structacc(STAG)’ 23215 Returns the reference point of the structure or union represented 23216 by STAG. Always returns zero. 23217 23218 23219File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent 23220 232219.46.11 Memory-mapped Registers 23222------------------------------- 23223 23224The following symbols are recognized as memory-mapped registers: 23225 23226 23227File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent 23228 232299.46.12 TIC54X Syntax 23230--------------------- 23231 23232* Menu: 23233 23234* TIC54X-Chars:: Special Characters 23235 23236 23237File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 23238 232399.46.12.1 Special Characters 23240............................ 23241 23242The presence of a ‘;’ appearing anywhere on a line indicates the start 23243of a comment that extends to the end of that line. 23244 23245 If a ‘#’ appears as the first character of a line then the whole line 23246is treated as a comment, but in this case the line can also be a logical 23247line number directive (*note Comments::) or a preprocessor control 23248command (*note Preprocessing::). 23249 23250 The presence of an asterisk (‘*’) at the start of a line also 23251indicates a comment that extends to the end of that line. 23252 23253 The TIC54X assembler does not currently support a line separator 23254character. 23255 23256 23257File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 23258 232599.47 TIC6X Dependent Features 23260============================= 23261 23262* Menu: 23263 23264* TIC6X Options:: Options 23265* TIC6X Syntax:: Syntax 23266* TIC6X Directives:: Directives 23267 23268 23269File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 23270 232719.47.1 TIC6X Options 23272-------------------- 23273 23274‘-march=ARCH’ 23275 Enable (only) instructions from architecture ARCH. By default, all 23276 instructions are permitted. 23277 23278 The following values of ARCH are accepted: ‘c62x’, ‘c64x’, ‘c64x+’, 23279 ‘c67x’, ‘c67x+’, ‘c674x’. 23280 23281‘-mdsbt’ 23282‘-mno-dsbt’ 23283 The ‘-mdsbt’ option causes the assembler to generate the 23284 ‘Tag_ABI_DSBT’ attribute with a value of 1, indicating that the 23285 code is using DSBT addressing. The ‘-mno-dsbt’ option, the 23286 default, causes the tag to have a value of 0, indicating that the 23287 code does not use DSBT addressing. The linker will emit a warning 23288 if objects of different type (DSBT and non-DSBT) are linked 23289 together. 23290 23291‘-mpid=no’ 23292‘-mpid=near’ 23293‘-mpid=far’ 23294 The ‘-mpid=’ option causes the assembler to generate the 23295 ‘Tag_ABI_PID’ attribute with a value indicating the form of data 23296 addressing used by the code. ‘-mpid=no’, the default, indicates 23297 position-dependent data addressing, ‘-mpid=near’ indicates 23298 position-independent addressing with GOT accesses using near DP 23299 addressing, and ‘-mpid=far’ indicates position-independent 23300 addressing with GOT accesses using far DP addressing. The linker 23301 will emit a warning if objects built with different settings of 23302 this option are linked together. 23303 23304‘-mpic’ 23305‘-mno-pic’ 23306 The ‘-mpic’ option causes the assembler to generate the 23307 ‘Tag_ABI_PIC’ attribute with a value of 1, indicating that the code 23308 is using position-independent code addressing, The ‘-mno-pic’ 23309 option, the default, causes the tag to have a value of 0, 23310 indicating position-dependent code addressing. The linker will 23311 emit a warning if objects of different type (position-dependent and 23312 position-independent) are linked together. 23313 23314‘-mbig-endian’ 23315‘-mlittle-endian’ 23316 Generate code for the specified endianness. The default is 23317 little-endian. 23318 23319 23320File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 23321 233229.47.2 TIC6X Syntax 23323------------------- 23324 23325The presence of a ‘;’ on a line indicates the start of a comment that 23326extends to the end of the current line. If a ‘#’ or ‘*’ appears as the 23327first character of a line, the whole line is treated as a comment. Note 23328that if a line starts with a ‘#’ character then it can also be a logical 23329line number directive (*note Comments::) or a preprocessor control 23330command (*note Preprocessing::). 23331 23332 The ‘@’ character can be used instead of a newline to separate 23333statements. 23334 23335 Instruction, register and functional unit names are case-insensitive. 23336‘as’ requires fully-specified functional unit names, such as ‘.S1’, 23337‘.L1X’ or ‘.D1T2’, on all instructions using a functional unit. 23338 23339 For some instructions, there may be syntactic ambiguity between 23340register or functional unit names and the names of labels or other 23341symbols. To avoid this, enclose the ambiguous symbol name in 23342parentheses; register and functional unit names may not be enclosed in 23343parentheses. 23344 23345 23346File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 23347 233489.47.3 TIC6X Directives 23349----------------------- 23350 23351Directives controlling the set of instructions accepted by the assembler 23352have effect for instructions between the directive and any subsequent 23353directive overriding it. 23354 23355‘.arch ARCH’ 23356 This has the same effect as ‘-march=ARCH’. 23357 23358‘.cantunwind’ 23359 Prevents unwinding through the current function. No personality 23360 routine or exception table data is required or permitted. 23361 23362 If this is not specified then frame unwinding information will be 23363 constructed from CFI directives. *note CFI directives::. 23364 23365‘.c6xabi_attribute TAG, VALUE’ 23366 Set the C6000 EABI build attribute TAG to VALUE. 23367 23368 The TAG is either an attribute number or one of ‘Tag_ISA’, 23369 ‘Tag_ABI_wchar_t’, ‘Tag_ABI_stack_align_needed’, 23370 ‘Tag_ABI_stack_align_preserved’, ‘Tag_ABI_DSBT’, ‘Tag_ABI_PID’, 23371 ‘Tag_ABI_PIC’, ‘TAG_ABI_array_object_alignment’, 23372 ‘TAG_ABI_array_object_align_expected’, ‘Tag_ABI_compatibility’ and 23373 ‘Tag_ABI_conformance’. The VALUE is either a ‘number’, ‘"string"’, 23374 or ‘number, "string"’ depending on the tag. 23375 23376‘.ehtype SYMBOL’ 23377 Output an exception type table reference to SYMBOL. 23378 23379‘.endp’ 23380 Marks the end of and exception table or function. If preceded by a 23381 ‘.handlerdata’ directive then this also switched back to the 23382 previous text section. 23383 23384‘.handlerdata’ 23385 Marks the end of the current function, and the start of the 23386 exception table entry for that function. Anything between this 23387 directive and the ‘.endp’ directive will be added to the exception 23388 table entry. 23389 23390 Must be preceded by a CFI block containing a ‘.cfi_lsda’ directive. 23391 23392‘.nocmp’ 23393 Disallow use of C64x+ compact instructions in the current text 23394 section. 23395 23396‘.personalityindex INDEX’ 23397 Sets the personality routine for the current function to the ABI 23398 specified compact routine number INDEX 23399 23400‘.personality NAME’ 23401 Sets the personality routine for the current function to NAME. 23402 23403‘.scomm SYMBOL, SIZE, ALIGN’ 23404 Like ‘.comm’, creating a common symbol SYMBOL with size SIZE and 23405 alignment ALIGN, but unlike when using ‘.comm’, this symbol will be 23406 placed into the small BSS section by the linker. 23407 23408 23409File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 23410 234119.48 TILE-Gx Dependent Features 23412=============================== 23413 23414* Menu: 23415 23416* TILE-Gx Options:: TILE-Gx Options 23417* TILE-Gx Syntax:: TILE-Gx Syntax 23418* TILE-Gx Directives:: TILE-Gx Directives 23419 23420 23421File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent 23422 234239.48.1 Options 23424-------------- 23425 23426The following table lists all available TILE-Gx specific options: 23427 23428‘-m32 | -m64’ 23429 Select the word size, either 32 bits or 64 bits. 23430 23431‘-EB | -EL’ 23432 Select the endianness, either big-endian (-EB) or little-endian 23433 (-EL). 23434 23435 23436File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 23437 234389.48.2 Syntax 23439------------- 23440 23441Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may 23442be introduced by ‘#’. 23443 23444 Instructions consist of a leading opcode or macro name followed by 23445whitespace and an optional comma-separated list of operands: 23446 23447 OPCODE [OPERAND, ...] 23448 23449 Instructions must be separated by a newline or semicolon. 23450 23451 There are two ways to write code: either write naked instructions, 23452which the assembler is free to combine into VLIW bundles, or specify the 23453VLIW bundles explicitly. 23454 23455 Bundles are specified using curly braces: 23456 23457 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 23458 23459 A bundle can span multiple lines. If you want to put multiple 23460instructions on a line, whether in a bundle or not, you need to separate 23461them with semicolons as in this example. 23462 23463 A bundle may contain one or more instructions, up to the limit 23464specified by the ISA (currently three). If fewer instructions are 23465specified than the hardware supports in a bundle, the assembler inserts 23466‘fnop’ instructions automatically. 23467 23468 The assembler will prefer to preserve the ordering of instructions 23469within the bundle, putting the first instruction in a lower-numbered 23470pipeline than the next one, etc. This fact, combined with the optional 23471use of explicit ‘fnop’ or ‘nop’ instructions, allows precise control 23472over which pipeline executes each instruction. 23473 23474 If the instructions cannot be bundled in the listed order, the 23475assembler will automatically try to find a valid pipeline assignment. 23476If there is no way to bundle the instructions together, the assembler 23477reports an error. 23478 23479 The assembler does not yet auto-bundle (automatically combine 23480multiple instructions into one bundle), but it reserves the right to do 23481so in the future. If you want to force an instruction to run by itself, 23482put it in a bundle explicitly with curly braces and use ‘nop’ 23483instructions (not ‘fnop’) to fill the remaining pipeline slots in that 23484bundle. 23485 23486* Menu: 23487 23488* TILE-Gx Opcodes:: Opcode Naming Conventions. 23489* TILE-Gx Registers:: Register Naming. 23490* TILE-Gx Modifiers:: Symbolic Operand Modifiers. 23491 23492 23493File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax 23494 234959.48.2.1 Opcode Names 23496..................... 23497 23498For a complete list of opcodes and descriptions of their semantics, see 23499‘TILE-Gx Instruction Set Architecture’, available upon request at 23500www.tilera.com. 23501 23502 23503File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax 23504 235059.48.2.2 Register Names 23506....................... 23507 23508General-purpose registers are represented by predefined symbols of the 23509form ‘rN’, where N represents a number between ‘0’ and ‘63’. However, 23510the following registers have canonical names that must be used instead: 23511 23512‘r54’ 23513 sp 23514 23515‘r55’ 23516 lr 23517 23518‘r56’ 23519 sn 23520 23521‘r57’ 23522 idn0 23523 23524‘r58’ 23525 idn1 23526 23527‘r59’ 23528 udn0 23529 23530‘r60’ 23531 udn1 23532 23533‘r61’ 23534 udn2 23535 23536‘r62’ 23537 udn3 23538 23539‘r63’ 23540 zero 23541 23542 The assembler will emit a warning if a numeric name is used instead 23543of the non-numeric name. The ‘.no_require_canonical_reg_names’ 23544assembler pseudo-op turns off this warning. 23545‘.require_canonical_reg_names’ turns it back on. 23546 23547 23548File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax 23549 235509.48.2.3 Symbolic Operand Modifiers 23551................................... 23552 23553The assembler supports several modifiers when using symbol addresses in 23554TILE-Gx instruction operands. The general syntax is the following: 23555 23556 modifier(symbol) 23557 23558 The following modifiers are supported: 23559 23560‘hw0’ 23561 23562 This modifier is used to load bits 0-15 of the symbol’s address. 23563 23564‘hw1’ 23565 23566 This modifier is used to load bits 16-31 of the symbol’s address. 23567 23568‘hw2’ 23569 23570 This modifier is used to load bits 32-47 of the symbol’s address. 23571 23572‘hw3’ 23573 23574 This modifier is used to load bits 48-63 of the symbol’s address. 23575 23576‘hw0_last’ 23577 23578 This modifier yields the same value as ‘hw0’, but it also checks 23579 that the value does not overflow. 23580 23581‘hw1_last’ 23582 23583 This modifier yields the same value as ‘hw1’, but it also checks 23584 that the value does not overflow. 23585 23586‘hw2_last’ 23587 23588 This modifier yields the same value as ‘hw2’, but it also checks 23589 that the value does not overflow. 23590 23591 A 48-bit symbolic value is constructed by using the following 23592 idiom: 23593 23594 moveli r0, hw2_last(sym) 23595 shl16insli r0, r0, hw1(sym) 23596 shl16insli r0, r0, hw0(sym) 23597 23598‘hw0_got’ 23599 23600 This modifier is used to load bits 0-15 of the symbol’s offset in 23601 the GOT entry corresponding to the symbol. 23602 23603‘hw0_last_got’ 23604 23605 This modifier yields the same value as ‘hw0_got’, but it also 23606 checks that the value does not overflow. 23607 23608‘hw1_last_got’ 23609 23610 This modifier is used to load bits 16-31 of the symbol’s offset in 23611 the GOT entry corresponding to the symbol, and it also checks that 23612 the value does not overflow. 23613 23614‘plt’ 23615 23616 This modifier is used for function symbols. It causes a _procedure 23617 linkage table_, an array of code stubs, to be created at the time 23618 the shared object is created or linked against, together with a 23619 global offset table entry. The value is a pc-relative offset to 23620 the corresponding stub code in the procedure linkage table. This 23621 arrangement causes the run-time symbol resolver to be called to 23622 look up and set the value of the symbol the first time the function 23623 is called (at latest; depending environment variables). It is only 23624 safe to leave the symbol unresolved this way if all references are 23625 function calls. 23626 23627‘hw0_plt’ 23628 23629 This modifier is used to load bits 0-15 of the pc-relative address 23630 of a plt entry. 23631 23632‘hw1_plt’ 23633 23634 This modifier is used to load bits 16-31 of the pc-relative address 23635 of a plt entry. 23636 23637‘hw1_last_plt’ 23638 23639 This modifier yields the same value as ‘hw1_plt’, but it also 23640 checks that the value does not overflow. 23641 23642‘hw2_last_plt’ 23643 23644 This modifier is used to load bits 32-47 of the pc-relative address 23645 of a plt entry, and it also checks that the value does not 23646 overflow. 23647 23648‘hw0_tls_gd’ 23649 23650 This modifier is used to load bits 0-15 of the offset of the GOT 23651 entry of the symbol’s TLS descriptor, to be used for 23652 general-dynamic TLS accesses. 23653 23654‘hw0_last_tls_gd’ 23655 23656 This modifier yields the same value as ‘hw0_tls_gd’, but it also 23657 checks that the value does not overflow. 23658 23659‘hw1_last_tls_gd’ 23660 23661 This modifier is used to load bits 16-31 of the offset of the GOT 23662 entry of the symbol’s TLS descriptor, to be used for 23663 general-dynamic TLS accesses. It also checks that the value does 23664 not overflow. 23665 23666‘hw0_tls_ie’ 23667 23668 This modifier is used to load bits 0-15 of the offset of the GOT 23669 entry containing the offset of the symbol’s address from the TCB, 23670 to be used for initial-exec TLS accesses. 23671 23672‘hw0_last_tls_ie’ 23673 23674 This modifier yields the same value as ‘hw0_tls_ie’, but it also 23675 checks that the value does not overflow. 23676 23677‘hw1_last_tls_ie’ 23678 23679 This modifier is used to load bits 16-31 of the offset of the GOT 23680 entry containing the offset of the symbol’s address from the TCB, 23681 to be used for initial-exec TLS accesses. It also checks that the 23682 value does not overflow. 23683 23684‘hw0_tls_le’ 23685 23686 This modifier is used to load bits 0-15 of the offset of the 23687 symbol’s address from the TCB, to be used for local-exec TLS 23688 accesses. 23689 23690‘hw0_last_tls_le’ 23691 23692 This modifier yields the same value as ‘hw0_tls_le’, but it also 23693 checks that the value does not overflow. 23694 23695‘hw1_last_tls_le’ 23696 23697 This modifier is used to load bits 16-31 of the offset of the 23698 symbol’s address from the TCB, to be used for local-exec TLS 23699 accesses. It also checks that the value does not overflow. 23700 23701‘tls_gd_call’ 23702 23703 This modifier is used to tag an instruction as the “call” part of a 23704 calling sequence for a TLS GD reference of its operand. 23705 23706‘tls_gd_add’ 23707 23708 This modifier is used to tag an instruction as the “add” part of a 23709 calling sequence for a TLS GD reference of its operand. 23710 23711‘tls_ie_load’ 23712 23713 This modifier is used to tag an instruction as the “load” part of a 23714 calling sequence for a TLS IE reference of its operand. 23715 23716 23717File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 23718 237199.48.3 TILE-Gx Directives 23720------------------------- 23721 23722‘.align EXPRESSION [, EXPRESSION]’ 23723 This is the generic .ALIGN directive. The first argument is the 23724 requested alignment in bytes. 23725 23726‘.allow_suspicious_bundles’ 23727 Turns on error checking for combinations of instructions in a 23728 bundle that probably indicate a programming error. This is on by 23729 default. 23730 23731‘.no_allow_suspicious_bundles’ 23732 Turns off error checking for combinations of instructions in a 23733 bundle that probably indicate a programming error. 23734 23735‘.require_canonical_reg_names’ 23736 Require that canonical register names be used, and emit a warning 23737 if the numeric names are used. This is on by default. 23738 23739‘.no_require_canonical_reg_names’ 23740 Permit the use of numeric names for registers that have canonical 23741 names. 23742 23743 23744File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 23745 237469.49 TILEPro Dependent Features 23747=============================== 23748 23749* Menu: 23750 23751* TILEPro Options:: TILEPro Options 23752* TILEPro Syntax:: TILEPro Syntax 23753* TILEPro Directives:: TILEPro Directives 23754 23755 23756File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent 23757 237589.49.1 Options 23759-------------- 23760 23761‘as’ has no machine-dependent command-line options for TILEPro. 23762 23763 23764File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent 23765 237669.49.2 Syntax 23767------------- 23768 23769Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may 23770be introduced by ‘#’. 23771 23772 Instructions consist of a leading opcode or macro name followed by 23773whitespace and an optional comma-separated list of operands: 23774 23775 OPCODE [OPERAND, ...] 23776 23777 Instructions must be separated by a newline or semicolon. 23778 23779 There are two ways to write code: either write naked instructions, 23780which the assembler is free to combine into VLIW bundles, or specify the 23781VLIW bundles explicitly. 23782 23783 Bundles are specified using curly braces: 23784 23785 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 23786 23787 A bundle can span multiple lines. If you want to put multiple 23788instructions on a line, whether in a bundle or not, you need to separate 23789them with semicolons as in this example. 23790 23791 A bundle may contain one or more instructions, up to the limit 23792specified by the ISA (currently three). If fewer instructions are 23793specified than the hardware supports in a bundle, the assembler inserts 23794‘fnop’ instructions automatically. 23795 23796 The assembler will prefer to preserve the ordering of instructions 23797within the bundle, putting the first instruction in a lower-numbered 23798pipeline than the next one, etc. This fact, combined with the optional 23799use of explicit ‘fnop’ or ‘nop’ instructions, allows precise control 23800over which pipeline executes each instruction. 23801 23802 If the instructions cannot be bundled in the listed order, the 23803assembler will automatically try to find a valid pipeline assignment. 23804If there is no way to bundle the instructions together, the assembler 23805reports an error. 23806 23807 The assembler does not yet auto-bundle (automatically combine 23808multiple instructions into one bundle), but it reserves the right to do 23809so in the future. If you want to force an instruction to run by itself, 23810put it in a bundle explicitly with curly braces and use ‘nop’ 23811instructions (not ‘fnop’) to fill the remaining pipeline slots in that 23812bundle. 23813 23814* Menu: 23815 23816* TILEPro Opcodes:: Opcode Naming Conventions. 23817* TILEPro Registers:: Register Naming. 23818* TILEPro Modifiers:: Symbolic Operand Modifiers. 23819 23820 23821File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax 23822 238239.49.2.1 Opcode Names 23824..................... 23825 23826For a complete list of opcodes and descriptions of their semantics, see 23827‘TILE Processor User Architecture Manual’, available upon request at 23828www.tilera.com. 23829 23830 23831File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax 23832 238339.49.2.2 Register Names 23834....................... 23835 23836General-purpose registers are represented by predefined symbols of the 23837form ‘rN’, where N represents a number between ‘0’ and ‘63’. However, 23838the following registers have canonical names that must be used instead: 23839 23840‘r54’ 23841 sp 23842 23843‘r55’ 23844 lr 23845 23846‘r56’ 23847 sn 23848 23849‘r57’ 23850 idn0 23851 23852‘r58’ 23853 idn1 23854 23855‘r59’ 23856 udn0 23857 23858‘r60’ 23859 udn1 23860 23861‘r61’ 23862 udn2 23863 23864‘r62’ 23865 udn3 23866 23867‘r63’ 23868 zero 23869 23870 The assembler will emit a warning if a numeric name is used instead 23871of the canonical name. The ‘.no_require_canonical_reg_names’ assembler 23872pseudo-op turns off this warning. ‘.require_canonical_reg_names’ turns 23873it back on. 23874 23875 23876File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax 23877 238789.49.2.3 Symbolic Operand Modifiers 23879................................... 23880 23881The assembler supports several modifiers when using symbol addresses in 23882TILEPro instruction operands. The general syntax is the following: 23883 23884 modifier(symbol) 23885 23886 The following modifiers are supported: 23887 23888‘lo16’ 23889 23890 This modifier is used to load the low 16 bits of the symbol’s 23891 address, sign-extended to a 32-bit value (sign-extension allows it 23892 to be range-checked against signed 16 bit immediate operands 23893 without complaint). 23894 23895‘hi16’ 23896 23897 This modifier is used to load the high 16 bits of the symbol’s 23898 address, also sign-extended to a 32-bit value. 23899 23900‘ha16’ 23901 23902 ‘ha16(N)’ is identical to ‘hi16(N)’, except if ‘lo16(N)’ is 23903 negative it adds one to the ‘hi16(N)’ value. This way ‘lo16’ and 23904 ‘ha16’ can be added to create any 32-bit value using ‘auli’. For 23905 example, here is how you move an arbitrary 32-bit address into r3: 23906 23907 moveli r3, lo16(sym) 23908 auli r3, r3, ha16(sym) 23909 23910‘got’ 23911 23912 This modifier is used to load the offset of the GOT entry 23913 corresponding to the symbol. 23914 23915‘got_lo16’ 23916 23917 This modifier is used to load the sign-extended low 16 bits of the 23918 offset of the GOT entry corresponding to the symbol. 23919 23920‘got_hi16’ 23921 23922 This modifier is used to load the sign-extended high 16 bits of the 23923 offset of the GOT entry corresponding to the symbol. 23924 23925‘got_ha16’ 23926 23927 This modifier is like ‘got_hi16’, but it adds one if ‘got_lo16’ of 23928 the input value is negative. 23929 23930‘plt’ 23931 23932 This modifier is used for function symbols. It causes a _procedure 23933 linkage table_, an array of code stubs, to be created at the time 23934 the shared object is created or linked against, together with a 23935 global offset table entry. The value is a pc-relative offset to 23936 the corresponding stub code in the procedure linkage table. This 23937 arrangement causes the run-time symbol resolver to be called to 23938 look up and set the value of the symbol the first time the function 23939 is called (at latest; depending environment variables). It is only 23940 safe to leave the symbol unresolved this way if all references are 23941 function calls. 23942 23943‘tls_gd’ 23944 23945 This modifier is used to load the offset of the GOT entry of the 23946 symbol’s TLS descriptor, to be used for general-dynamic TLS 23947 accesses. 23948 23949‘tls_gd_lo16’ 23950 23951 This modifier is used to load the sign-extended low 16 bits of the 23952 offset of the GOT entry of the symbol’s TLS descriptor, to be used 23953 for general dynamic TLS accesses. 23954 23955‘tls_gd_hi16’ 23956 23957 This modifier is used to load the sign-extended high 16 bits of the 23958 offset of the GOT entry of the symbol’s TLS descriptor, to be used 23959 for general dynamic TLS accesses. 23960 23961‘tls_gd_ha16’ 23962 23963 This modifier is like ‘tls_gd_hi16’, but it adds one to the value 23964 if ‘tls_gd_lo16’ of the input value is negative. 23965 23966‘tls_ie’ 23967 23968 This modifier is used to load the offset of the GOT entry 23969 containing the offset of the symbol’s address from the TCB, to be 23970 used for initial-exec TLS accesses. 23971 23972‘tls_ie_lo16’ 23973 23974 This modifier is used to load the low 16 bits of the offset of the 23975 GOT entry containing the offset of the symbol’s address from the 23976 TCB, to be used for initial-exec TLS accesses. 23977 23978‘tls_ie_hi16’ 23979 23980 This modifier is used to load the high 16 bits of the offset of the 23981 GOT entry containing the offset of the symbol’s address from the 23982 TCB, to be used for initial-exec TLS accesses. 23983 23984‘tls_ie_ha16’ 23985 23986 This modifier is like ‘tls_ie_hi16’, but it adds one to the value 23987 if ‘tls_ie_lo16’ of the input value is negative. 23988 23989‘tls_le’ 23990 23991 This modifier is used to load the offset of the symbol’s address 23992 from the TCB, to be used for local-exec TLS accesses. 23993 23994‘tls_le_lo16’ 23995 23996 This modifier is used to load the low 16 bits of the offset of the 23997 symbol’s address from the TCB, to be used for local-exec TLS 23998 accesses. 23999 24000‘tls_le_hi16’ 24001 24002 This modifier is used to load the high 16 bits of the offset of the 24003 symbol’s address from the TCB, to be used for local-exec TLS 24004 accesses. 24005 24006‘tls_le_ha16’ 24007 24008 This modifier is like ‘tls_le_hi16’, but it adds one to the value 24009 if ‘tls_le_lo16’ of the input value is negative. 24010 24011‘tls_gd_call’ 24012 24013 This modifier is used to tag an instruction as the “call” part of a 24014 calling sequence for a TLS GD reference of its operand. 24015 24016‘tls_gd_add’ 24017 24018 This modifier is used to tag an instruction as the “add” part of a 24019 calling sequence for a TLS GD reference of its operand. 24020 24021‘tls_ie_load’ 24022 24023 This modifier is used to tag an instruction as the “load” part of a 24024 calling sequence for a TLS IE reference of its operand. 24025 24026 24027File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 24028 240299.49.3 TILEPro Directives 24030------------------------- 24031 24032‘.align EXPRESSION [, EXPRESSION]’ 24033 This is the generic .ALIGN directive. The first argument is the 24034 requested alignment in bytes. 24035 24036‘.allow_suspicious_bundles’ 24037 Turns on error checking for combinations of instructions in a 24038 bundle that probably indicate a programming error. This is on by 24039 default. 24040 24041‘.no_allow_suspicious_bundles’ 24042 Turns off error checking for combinations of instructions in a 24043 bundle that probably indicate a programming error. 24044 24045‘.require_canonical_reg_names’ 24046 Require that canonical register names be used, and emit a warning 24047 if the numeric names are used. This is on by default. 24048 24049‘.no_require_canonical_reg_names’ 24050 Permit the use of numeric names for registers that have canonical 24051 names. 24052 24053 24054File: as.info, Node: V850-Dependent, Next: Vax-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 24055 240569.50 v850 Dependent Features 24057============================ 24058 24059* Menu: 24060 24061* V850 Options:: Options 24062* V850 Syntax:: Syntax 24063* V850 Floating Point:: Floating Point 24064* V850 Directives:: V850 Machine Directives 24065* V850 Opcodes:: Opcodes 24066 24067 24068File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 24069 240709.50.1 Options 24071-------------- 24072 24073‘as’ supports the following additional command-line options for the V850 24074processor family: 24075 24076‘-wsigned_overflow’ 24077 Causes warnings to be produced when signed immediate values 24078 overflow the space available for then within their opcodes. By 24079 default this option is disabled as it is possible to receive 24080 spurious warnings due to using exact bit patterns as immediate 24081 constants. 24082 24083‘-wunsigned_overflow’ 24084 Causes warnings to be produced when unsigned immediate values 24085 overflow the space available for then within their opcodes. By 24086 default this option is disabled as it is possible to receive 24087 spurious warnings due to using exact bit patterns as immediate 24088 constants. 24089 24090‘-mv850’ 24091 Specifies that the assembled code should be marked as being 24092 targeted at the V850 processor. This allows the linker to detect 24093 attempts to link such code with code assembled for other 24094 processors. 24095 24096‘-mv850e’ 24097 Specifies that the assembled code should be marked as being 24098 targeted at the V850E processor. This allows the linker to detect 24099 attempts to link such code with code assembled for other 24100 processors. 24101 24102‘-mv850e1’ 24103 Specifies that the assembled code should be marked as being 24104 targeted at the V850E1 processor. This allows the linker to detect 24105 attempts to link such code with code assembled for other 24106 processors. 24107 24108‘-mv850any’ 24109 Specifies that the assembled code should be marked as being 24110 targeted at the V850 processor but support instructions that are 24111 specific to the extended variants of the process. This allows the 24112 production of binaries that contain target specific code, but which 24113 are also intended to be used in a generic fashion. For example 24114 libgcc.a contains generic routines used by the code produced by GCC 24115 for all versions of the v850 architecture, together with support 24116 routines only used by the V850E architecture. 24117 24118‘-mv850e2’ 24119 Specifies that the assembled code should be marked as being 24120 targeted at the V850E2 processor. This allows the linker to detect 24121 attempts to link such code with code assembled for other 24122 processors. 24123 24124‘-mv850e2v3’ 24125 Specifies that the assembled code should be marked as being 24126 targeted at the V850E2V3 processor. This allows the linker to 24127 detect attempts to link such code with code assembled for other 24128 processors. 24129 24130‘-mv850e2v4’ 24131 This is an alias for ‘-mv850e3v5’. 24132 24133‘-mv850e3v5’ 24134 Specifies that the assembled code should be marked as being 24135 targeted at the V850E3V5 processor. This allows the linker to 24136 detect attempts to link such code with code assembled for other 24137 processors. 24138 24139‘-mrelax’ 24140 Enables relaxation. This allows the .longcall and .longjump pseudo 24141 ops to be used in the assembler source code. These ops label 24142 sections of code which are either a long function call or a long 24143 branch. The assembler will then flag these sections of code and 24144 the linker will attempt to relax them. 24145 24146‘-mgcc-abi’ 24147 Marks the generated object file as supporting the old GCC ABI. 24148 24149‘-mrh850-abi’ 24150 Marks the generated object file as supporting the RH850 ABI. This 24151 is the default. 24152 24153‘-m8byte-align’ 24154 Marks the generated object file as supporting a maximum 64-bits of 24155 alignment for variables defined in the source code. 24156 24157‘-m4byte-align’ 24158 Marks the generated object file as supporting a maximum 32-bits of 24159 alignment for variables defined in the source code. This is the 24160 default. 24161 24162‘-msoft-float’ 24163 Marks the generated object file as not using any floating point 24164 instructions - and hence can be linked with other V850 binaries 24165 that do or do not use floating point. This is the default for 24166 binaries for architectures earlier than the ‘e2v3’. 24167 24168‘-mhard-float’ 24169 Marks the generated object file as one that uses floating point 24170 instructions - and hence can only be linked with other V850 24171 binaries that use the same kind of floating point instructions, or 24172 with binaries that do not use floating point at all. This is the 24173 default for binaries the ‘e2v3’ and later architectures. 24174 24175 24176File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 24177 241789.50.2 Syntax 24179------------- 24180 24181* Menu: 24182 24183* V850-Chars:: Special Characters 24184* V850-Regs:: Register Names 24185 24186 24187File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 24188 241899.50.2.1 Special Characters 24190........................... 24191 24192‘#’ is the line comment character. If a ‘#’ appears as the first 24193character of a line, the whole line is treated as a comment, but in this 24194case the line can also be a logical line number directive (*note 24195Comments::) or a preprocessor control command (*note Preprocessing::). 24196 24197 Two dashes (‘--’) can also be used to start a line comment. 24198 24199 The ‘;’ character can be used to separate statements on the same 24200line. 24201 24202 24203File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 24204 242059.50.2.2 Register Names 24206....................... 24207 24208‘as’ supports the following names for registers: 24209‘general register 0’ 24210 r0, zero 24211‘general register 1’ 24212 r1 24213‘general register 2’ 24214 r2, hp 24215‘general register 3’ 24216 r3, sp 24217‘general register 4’ 24218 r4, gp 24219‘general register 5’ 24220 r5, tp 24221‘general register 6’ 24222 r6 24223‘general register 7’ 24224 r7 24225‘general register 8’ 24226 r8 24227‘general register 9’ 24228 r9 24229‘general register 10’ 24230 r10 24231‘general register 11’ 24232 r11 24233‘general register 12’ 24234 r12 24235‘general register 13’ 24236 r13 24237‘general register 14’ 24238 r14 24239‘general register 15’ 24240 r15 24241‘general register 16’ 24242 r16 24243‘general register 17’ 24244 r17 24245‘general register 18’ 24246 r18 24247‘general register 19’ 24248 r19 24249‘general register 20’ 24250 r20 24251‘general register 21’ 24252 r21 24253‘general register 22’ 24254 r22 24255‘general register 23’ 24256 r23 24257‘general register 24’ 24258 r24 24259‘general register 25’ 24260 r25 24261‘general register 26’ 24262 r26 24263‘general register 27’ 24264 r27 24265‘general register 28’ 24266 r28 24267‘general register 29’ 24268 r29 24269‘general register 30’ 24270 r30, ep 24271‘general register 31’ 24272 r31, lp 24273‘system register 0’ 24274 eipc 24275‘system register 1’ 24276 eipsw 24277‘system register 2’ 24278 fepc 24279‘system register 3’ 24280 fepsw 24281‘system register 4’ 24282 ecr 24283‘system register 5’ 24284 psw 24285‘system register 16’ 24286 ctpc 24287‘system register 17’ 24288 ctpsw 24289‘system register 18’ 24290 dbpc 24291‘system register 19’ 24292 dbpsw 24293‘system register 20’ 24294 ctbp 24295 24296 24297File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 24298 242999.50.3 Floating Point 24300--------------------- 24301 24302The V850 family uses IEEE floating-point numbers. 24303 24304 24305File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 24306 243079.50.4 V850 Machine Directives 24308------------------------------ 24309 24310‘.offset <EXPRESSION>’ 24311 Moves the offset into the current section to the specified amount. 24312 24313‘.section "name", <type>’ 24314 This is an extension to the standard .section directive. It sets 24315 the current section to be <type> and creates an alias for this 24316 section called "name". 24317 24318‘.v850’ 24319 Specifies that the assembled code should be marked as being 24320 targeted at the V850 processor. This allows the linker to detect 24321 attempts to link such code with code assembled for other 24322 processors. 24323 24324‘.v850e’ 24325 Specifies that the assembled code should be marked as being 24326 targeted at the V850E processor. This allows the linker to detect 24327 attempts to link such code with code assembled for other 24328 processors. 24329 24330‘.v850e1’ 24331 Specifies that the assembled code should be marked as being 24332 targeted at the V850E1 processor. This allows the linker to detect 24333 attempts to link such code with code assembled for other 24334 processors. 24335 24336‘.v850e2’ 24337 Specifies that the assembled code should be marked as being 24338 targeted at the V850E2 processor. This allows the linker to detect 24339 attempts to link such code with code assembled for other 24340 processors. 24341 24342‘.v850e2v3’ 24343 Specifies that the assembled code should be marked as being 24344 targeted at the V850E2V3 processor. This allows the linker to 24345 detect attempts to link such code with code assembled for other 24346 processors. 24347 24348‘.v850e2v4’ 24349 Specifies that the assembled code should be marked as being 24350 targeted at the V850E3V5 processor. This allows the linker to 24351 detect attempts to link such code with code assembled for other 24352 processors. 24353 24354‘.v850e3v5’ 24355 Specifies that the assembled code should be marked as being 24356 targeted at the V850E3V5 processor. This allows the linker to 24357 detect attempts to link such code with code assembled for other 24358 processors. 24359 24360 24361File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 24362 243639.50.5 Opcodes 24364-------------- 24365 24366‘as’ implements all the standard V850 opcodes. 24367 24368 ‘as’ also implements the following pseudo ops: 24369 24370‘hi0()’ 24371 Computes the higher 16 bits of the given expression and stores it 24372 into the immediate operand field of the given instruction. For 24373 example: 24374 24375 ‘mulhi hi0(here - there), r5, r6’ 24376 24377 computes the difference between the address of labels ’here’ and 24378 ’there’, takes the upper 16 bits of this difference, shifts it down 24379 16 bits and then multiplies it by the lower 16 bits in register 5, 24380 putting the result into register 6. 24381 24382‘lo()’ 24383 Computes the lower 16 bits of the given expression and stores it 24384 into the immediate operand field of the given instruction. For 24385 example: 24386 24387 ‘addi lo(here - there), r5, r6’ 24388 24389 computes the difference between the address of labels ’here’ and 24390 ’there’, takes the lower 16 bits of this difference and adds it to 24391 register 5, putting the result into register 6. 24392 24393‘hi()’ 24394 Computes the higher 16 bits of the given expression and then adds 24395 the value of the most significant bit of the lower 16 bits of the 24396 expression and stores the result into the immediate operand field 24397 of the given instruction. For example the following code can be 24398 used to compute the address of the label ’here’ and store it into 24399 register 6: 24400 24401 ‘movhi hi(here), r0, r6’ ‘movea lo(here), r6, r6’ 24402 24403 The reason for this special behaviour is that movea performs a sign 24404 extension on its immediate operand. So for example if the address 24405 of ’here’ was 0xFFFFFFFF then without the special behaviour of the 24406 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 24407 then the movea instruction would takes its immediate operand, 24408 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into 24409 r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With 24410 the hi() pseudo op adding in the top bit of the lo() pseudo op, the 24411 movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), 24412 so that the movea instruction stores 0xFFFFFFFF into r6 - the right 24413 value. 24414 24415‘hilo()’ 24416 Computes the 32 bit value of the given expression and stores it 24417 into the immediate operand field of the given instruction (which 24418 must be a mov instruction). For example: 24419 24420 ‘mov hilo(here), r6’ 24421 24422 computes the absolute address of label ’here’ and puts the result 24423 into register 6. 24424 24425‘sdaoff()’ 24426 Computes the offset of the named variable from the start of the 24427 Small Data Area (whose address is held in register 4, the GP 24428 register) and stores the result as a 16 bit signed value in the 24429 immediate operand field of the given instruction. For example: 24430 24431 ‘ld.w sdaoff(_a_variable)[gp],r6’ 24432 24433 loads the contents of the location pointed to by the label 24434 ’_a_variable’ into register 6, provided that the label is located 24435 somewhere within +/- 32K of the address held in the GP register. 24436 [Note the linker assumes that the GP register contains a fixed 24437 address set to the address of the label called ’__gp’. This can 24438 either be set up automatically by the linker, or specifically set 24439 by using the ‘--defsym __gp=<value>’ command-line option]. 24440 24441‘tdaoff()’ 24442 Computes the offset of the named variable from the start of the 24443 Tiny Data Area (whose address is held in register 30, the EP 24444 register) and stores the result as a 4,5, 7 or 8 bit unsigned value 24445 in the immediate operand field of the given instruction. For 24446 example: 24447 24448 ‘sld.w tdaoff(_a_variable)[ep],r6’ 24449 24450 loads the contents of the location pointed to by the label 24451 ’_a_variable’ into register 6, provided that the label is located 24452 somewhere within +256 bytes of the address held in the EP register. 24453 [Note the linker assumes that the EP register contains a fixed 24454 address set to the address of the label called ’__ep’. This can 24455 either be set up automatically by the linker, or specifically set 24456 by using the ‘--defsym __ep=<value>’ command-line option]. 24457 24458‘zdaoff()’ 24459 Computes the offset of the named variable from address 0 and stores 24460 the result as a 16 bit signed value in the immediate operand field 24461 of the given instruction. For example: 24462 24463 ‘movea zdaoff(_a_variable),zero,r6’ 24464 24465 puts the address of the label ’_a_variable’ into register 6, 24466 assuming that the label is somewhere within the first 32K of 24467 memory. (Strictly speaking it also possible to access the last 32K 24468 of memory as well, as the offsets are signed). 24469 24470‘ctoff()’ 24471 Computes the offset of the named variable from the start of the 24472 Call Table Area (whose address is held in system register 20, the 24473 CTBP register) and stores the result a 6 or 16 bit unsigned value 24474 in the immediate field of then given instruction or piece of data. 24475 For example: 24476 24477 ‘callt ctoff(table_func1)’ 24478 24479 will put the call the function whose address is held in the call 24480 table at the location labeled ’table_func1’. 24481 24482‘.longcall name’ 24483 Indicates that the following sequence of instructions is a long 24484 call to function ‘name’. The linker will attempt to shorten this 24485 call sequence if ‘name’ is within a 22bit offset of the call. Only 24486 valid if the ‘-mrelax’ command-line switch has been enabled. 24487 24488‘.longjump name’ 24489 Indicates that the following sequence of instructions is a long 24490 jump to label ‘name’. The linker will attempt to shorten this code 24491 sequence if ‘name’ is within a 22bit offset of the jump. Only 24492 valid if the ‘-mrelax’ command-line switch has been enabled. 24493 24494 For information on the V850 instruction set, see ‘V850 Family 2449532-/16-Bit single-Chip Microcontroller Architecture Manual’ from NEC. 24496Ltd. 24497 24498 24499File: as.info, Node: Vax-Dependent, Next: Visium-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 24500 245019.51 VAX Dependent Features 24502=========================== 24503 24504* Menu: 24505 24506* VAX-Opts:: VAX Command-Line Options 24507* VAX-float:: VAX Floating Point 24508* VAX-directives:: Vax Machine Directives 24509* VAX-opcodes:: VAX Opcodes 24510* VAX-branch:: VAX Branch Improvement 24511* VAX-operands:: VAX Operands 24512* VAX-no:: Not Supported on VAX 24513* VAX-Syntax:: VAX Syntax 24514 24515 24516File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 24517 245189.51.1 VAX Command-Line Options 24519------------------------------- 24520 24521The Vax version of ‘as’ accepts any of the following options, gives a 24522warning message that the option was ignored and proceeds. These options 24523are for compatibility with scripts designed for other people’s 24524assemblers. 24525 24526‘-D (Debug)’ 24527‘-S (Symbol Table)’ 24528‘-T (Token Trace)’ 24529 These are obsolete options used to debug old assemblers. 24530 24531‘-d (Displacement size for JUMPs)’ 24532 This option expects a number following the ‘-d’. Like options that 24533 expect filenames, the number may immediately follow the ‘-d’ (old 24534 standard) or constitute the whole of the command-line argument that 24535 follows ‘-d’ (GNU standard). 24536 24537‘-V (Virtualize Interpass Temporary File)’ 24538 Some other assemblers use a temporary file. This option commanded 24539 them to keep the information in active memory rather than in a disk 24540 file. ‘as’ always does this, so this option is redundant. 24541 24542‘-J (JUMPify Longer Branches)’ 24543 Many 32-bit computers permit a variety of branch instructions to do 24544 the same job. Some of these instructions are short (and fast) but 24545 have a limited range; others are long (and slow) but can branch 24546 anywhere in virtual memory. Often there are 3 flavors of branch: 24547 short, medium and long. Some other assemblers would emit short and 24548 medium branches, unless told by this option to emit short and long 24549 branches. 24550 24551‘-t (Temporary File Directory)’ 24552 Some other assemblers may use a temporary file, and this option 24553 takes a filename being the directory to site the temporary file. 24554 Since ‘as’ does not use a temporary disk file, this option makes no 24555 difference. ‘-t’ needs exactly one filename. 24556 24557 The Vax version of the assembler accepts additional options when 24558compiled for VMS: 24559 24560‘-h N’ 24561 External symbol or section (used for global variables) names are 24562 not case sensitive on VAX/VMS and always mapped to upper case. 24563 This is contrary to the C language definition which explicitly 24564 distinguishes upper and lower case. To implement a standard 24565 conforming C compiler, names must be changed (mapped) to preserve 24566 the case information. The default mapping is to convert all lower 24567 case characters to uppercase and adding an underscore followed by a 24568 6 digit hex value, representing a 24 digit binary value. The one 24569 digits in the binary value represent which characters are uppercase 24570 in the original symbol name. 24571 24572 The ‘-h N’ option determines how we map names. This takes several 24573 values. No ‘-h’ switch at all allows case hacking as described 24574 above. A value of zero (‘-h0’) implies names should be upper case, 24575 and inhibits the case hack. A value of 2 (‘-h2’) implies names 24576 should be all lower case, with no case hack. A value of 3 (‘-h3’) 24577 implies that case should be preserved. The value 1 is unused. The 24578 ‘-H’ option directs ‘as’ to display every mapped symbol during 24579 assembly. 24580 24581 Symbols whose names include a dollar sign ‘$’ are exceptions to the 24582 general name mapping. These symbols are normally only used to 24583 reference VMS library names. Such symbols are always mapped to 24584 upper case. 24585 24586‘-+’ 24587 The ‘-+’ option causes ‘as’ to truncate any symbol name larger than 24588 31 characters. The ‘-+’ option also prevents some code following 24589 the ‘_main’ symbol normally added to make the object file 24590 compatible with Vax-11 "C". 24591 24592‘-1’ 24593 This option is ignored for backward compatibility with ‘as’ version 24594 1.x. 24595 24596‘-H’ 24597 The ‘-H’ option causes ‘as’ to print every symbol which was changed 24598 by case mapping. 24599 24600 24601File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 24602 246039.51.2 VAX Floating Point 24604------------------------- 24605 24606Conversion of flonums to floating point is correct, and compatible with 24607previous assemblers. Rounding is towards zero if the remainder is 24608exactly half the least significant bit. 24609 24610 ‘D’, ‘F’, ‘G’ and ‘H’ floating point formats are understood. 24611 24612 Immediate floating literals (_e.g._ ‘S`$6.9’) are rendered 24613correctly. Again, rounding is towards zero in the boundary case. 24614 24615 The ‘.float’ directive produces ‘f’ format numbers. The ‘.double’ 24616directive produces ‘d’ format numbers. 24617 24618 24619File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 24620 246219.51.3 Vax Machine Directives 24622----------------------------- 24623 24624The Vax version of the assembler supports four directives for generating 24625Vax floating point constants. They are described in the table below. 24626 24627‘.dfloat’ 24628 This expects zero or more flonums, separated by commas, and 24629 assembles Vax ‘d’ format 64-bit floating point constants. 24630 24631‘.ffloat’ 24632 This expects zero or more flonums, separated by commas, and 24633 assembles Vax ‘f’ format 32-bit floating point constants. 24634 24635‘.gfloat’ 24636 This expects zero or more flonums, separated by commas, and 24637 assembles Vax ‘g’ format 64-bit floating point constants. 24638 24639‘.hfloat’ 24640 This expects zero or more flonums, separated by commas, and 24641 assembles Vax ‘h’ format 128-bit floating point constants. 24642 24643 24644File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 24645 246469.51.4 VAX Opcodes 24647------------------ 24648 24649All DEC mnemonics are supported. Beware that ‘case...’ instructions 24650have exactly 3 operands. The dispatch table that follows the ‘case...’ 24651instruction should be made with ‘.word’ statements. This is compatible 24652with all unix assemblers we know of. 24653 24654 24655File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 24656 246579.51.5 VAX Branch Improvement 24658----------------------------- 24659 24660Certain pseudo opcodes are permitted. They are for branch instructions. 24661They expand to the shortest branch instruction that reaches the target. 24662Generally these mnemonics are made by substituting ‘j’ for ‘b’ at the 24663start of a DEC mnemonic. This feature is included both for 24664compatibility and to help compilers. If you do not need this feature, 24665avoid these opcodes. Here are the mnemonics, and the code they can 24666expand into. 24667 24668‘jbsb’ 24669 ‘Jsb’ is already an instruction mnemonic, so we chose ‘jbsb’. 24670 (byte displacement) 24671 ‘bsbb ...’ 24672 (word displacement) 24673 ‘bsbw ...’ 24674 (long displacement) 24675 ‘jsb ...’ 24676‘jbr’ 24677‘jr’ 24678 Unconditional branch. 24679 (byte displacement) 24680 ‘brb ...’ 24681 (word displacement) 24682 ‘brw ...’ 24683 (long displacement) 24684 ‘jmp ...’ 24685‘jCOND’ 24686 COND may be any one of the conditional branches ‘neq’, ‘nequ’, 24687 ‘eql’, ‘eqlu’, ‘gtr’, ‘geq’, ‘lss’, ‘gtru’, ‘lequ’, ‘vc’, ‘vs’, 24688 ‘gequ’, ‘cc’, ‘lssu’, ‘cs’. COND may also be one of the bit tests 24689 ‘bs’, ‘bc’, ‘bss’, ‘bcs’, ‘bsc’, ‘bcc’, ‘bssi’, ‘bcci’, ‘lbs’, 24690 ‘lbc’. NOTCOND is the opposite condition to COND. 24691 (byte displacement) 24692 ‘bCOND ...’ 24693 (word displacement) 24694 ‘bNOTCOND foo ; brw ... ; foo:’ 24695 (long displacement) 24696 ‘bNOTCOND foo ; jmp ... ; foo:’ 24697‘jacbX’ 24698 X may be one of ‘b d f g h l w’. 24699 (word displacement) 24700 ‘OPCODE ...’ 24701 (long displacement) 24702 OPCODE ..., foo ; 24703 brb bar ; 24704 foo: jmp ... ; 24705 bar: 24706‘jaobYYY’ 24707 YYY may be one of ‘lss leq’. 24708‘jsobZZZ’ 24709 ZZZ may be one of ‘geq gtr’. 24710 (byte displacement) 24711 ‘OPCODE ...’ 24712 (word displacement) 24713 OPCODE ..., foo ; 24714 brb bar ; 24715 foo: brw DESTINATION ; 24716 bar: 24717 (long displacement) 24718 OPCODE ..., foo ; 24719 brb bar ; 24720 foo: jmp DESTINATION ; 24721 bar: 24722‘aobleq’ 24723‘aoblss’ 24724‘sobgeq’ 24725‘sobgtr’ 24726 (byte displacement) 24727 ‘OPCODE ...’ 24728 (word displacement) 24729 OPCODE ..., foo ; 24730 brb bar ; 24731 foo: brw DESTINATION ; 24732 bar: 24733 (long displacement) 24734 OPCODE ..., foo ; 24735 brb bar ; 24736 foo: jmp DESTINATION ; 24737 bar: 24738 24739 24740File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 24741 247429.51.6 VAX Operands 24743------------------- 24744 24745The immediate character is ‘$’ for Unix compatibility, not ‘#’ as DEC 24746writes it. 24747 24748 The indirect character is ‘*’ for Unix compatibility, not ‘@’ as DEC 24749writes it. 24750 24751 The displacement sizing character is ‘`’ (an accent grave) for Unix 24752compatibility, not ‘^’ as DEC writes it. The letter preceding ‘`’ may 24753have either case. ‘G’ is not understood, but all other letters (‘b i l 24754s w’) are understood. 24755 24756 Register names understood are ‘r0 r1 r2 ... r15 ap fp sp pc’. Upper 24757and lower case letters are equivalent. 24758 24759 For instance 24760 tstb *w`$4(r5) 24761 24762 Any expression is permitted in an operand. Operands are comma 24763separated. 24764 24765 24766File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent 24767 247689.51.7 Not Supported on VAX 24769--------------------------- 24770 24771Vax bit fields can not be assembled with ‘as’. Someone can add the 24772required code if they really need it. 24773 24774 24775File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent 24776 247779.51.8 VAX Syntax 24778----------------- 24779 24780* Menu: 24781 24782* VAX-Chars:: Special Characters 24783 24784 24785File: as.info, Node: VAX-Chars, Up: VAX-Syntax 24786 247879.51.8.1 Special Characters 24788........................... 24789 24790The presence of a ‘#’ appearing anywhere on a line indicates the start 24791of a comment that extends to the end of that line. 24792 24793 If a ‘#’ appears as the first character of a line then the whole line 24794is treated as a comment, but in this case the line can also be a logical 24795line number directive (*note Comments::) or a preprocessor control 24796command (*note Preprocessing::). 24797 24798 The ‘;’ character can be used to separate statements on the same 24799line. 24800 24801 24802File: as.info, Node: Visium-Dependent, Next: WebAssembly-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies 24803 248049.52 Visium Dependent Features 24805============================== 24806 24807* Menu: 24808 24809* Visium Options:: Options 24810* Visium Syntax:: Syntax 24811* Visium Opcodes:: Opcodes 24812 24813 24814File: as.info, Node: Visium Options, Next: Visium Syntax, Up: Visium-Dependent 24815 248169.52.1 Options 24817-------------- 24818 24819The Visium assembler implements one machine-specific option: 24820 24821‘-mtune=ARCH’ 24822 This option specifies the target architecture. If an attempt is 24823 made to assemble an instruction that will not execute on the target 24824 architecture, the assembler will issue an error message. 24825 24826 The following names are recognized: ‘mcm24’ ‘mcm’ ‘gr5’ ‘gr6’ 24827 24828 24829File: as.info, Node: Visium Syntax, Next: Visium Opcodes, Prev: Visium Options, Up: Visium-Dependent 24830 248319.52.2 Syntax 24832------------- 24833 24834* Menu: 24835 24836* Visium Characters:: Special Characters 24837* Visium Registers:: Register Names 24838 24839 24840File: as.info, Node: Visium Characters, Next: Visium Registers, Up: Visium Syntax 24841 248429.52.2.1 Special Characters 24843........................... 24844 24845Line comments are introduced either by the ‘!’ character or by the ‘;’ 24846character appearing anywhere on a line. 24847 24848 A hash character (‘#’) as the first character on a line also marks 24849the start of a line comment, but in this case it could also be a logical 24850line number directive (*note Comments::) or a preprocessor control 24851command (*note Preprocessing::). 24852 24853 The Visium assembler does not currently support a line separator 24854character. 24855 24856 24857File: as.info, Node: Visium Registers, Prev: Visium Characters, Up: Visium Syntax 24858 248599.52.2.2 Register Names 24860....................... 24861 24862Registers can be specified either by using their canonical mnemonic 24863names or by using their alias if they have one, for example ‘sp’. 24864 24865 24866File: as.info, Node: Visium Opcodes, Prev: Visium Syntax, Up: Visium-Dependent 24867 248689.52.3 Opcodes 24869-------------- 24870 24871All the standard opcodes of the architecture are implemented, along with 24872the following three pseudo-instructions: ‘cmp’, ‘cmpc’, ‘move’. 24873 24874 In addition, the following two illegal opcodes are implemented and 24875used by the simulation: 24876 24877 stop 5-bit immediate, SourceA 24878 trace 5-bit immediate, SourceA 24879 24880 24881File: as.info, Node: WebAssembly-Dependent, Next: XGATE-Dependent, Prev: Visium-Dependent, Up: Machine Dependencies 24882 248839.53 WebAssembly Dependent Features 24884=================================== 24885 24886* Menu: 24887 24888* WebAssembly-Notes:: Notes 24889* WebAssembly-Syntax:: Syntax 24890* WebAssembly-Floating-Point:: Floating Point 24891* WebAssembly-Opcodes:: Opcodes 24892* WebAssembly-module-layout:: Module Layout 24893 24894 24895File: as.info, Node: WebAssembly-Notes, Next: WebAssembly-Syntax, Up: WebAssembly-Dependent 24896 248979.53.1 Notes 24898------------ 24899 24900While WebAssembly provides its own module format for executables, this 24901documentation describes how to use ‘as’ to produce intermediate ELF 24902object format files. 24903 24904 24905File: as.info, Node: WebAssembly-Syntax, Next: WebAssembly-Floating-Point, Prev: WebAssembly-Notes, Up: WebAssembly-Dependent 24906 249079.53.2 Syntax 24908------------- 24909 24910The assembler syntax directly encodes sequences of opcodes as defined in 24911the WebAssembly binary encoding specification at 24912https://github.com/webassembly/spec/BinaryEncoding.md. Structured 24913sexp-style expressions are not supported as input. 24914 24915* Menu: 24916 24917* WebAssembly-Chars:: Special Characters 24918* WebAssembly-Relocs:: Relocations 24919* WebAssembly-Signatures:: Signatures 24920 24921 24922File: as.info, Node: WebAssembly-Chars, Next: WebAssembly-Relocs, Up: WebAssembly-Syntax 24923 249249.53.2.1 Special Characters 24925........................... 24926 24927‘#’ and ‘;’ are the line comment characters. Note that if ‘#’ is the 24928first character on a line then it can also be a logical line number 24929directive (*note Comments::) or a preprocessor control command (*note 24930Preprocessing::). 24931 24932 24933File: as.info, Node: WebAssembly-Relocs, Next: WebAssembly-Signatures, Prev: WebAssembly-Chars, Up: WebAssembly-Syntax 24934 249359.53.2.2 Relocations 24936.................... 24937 24938Special relocations are available by using the ‘@PLT’, ‘@GOT’, or ‘@GOT’ 24939suffixes after a constant expression, which correspond to the 24940R_ASMJS_LEB128_PLT, R_ASMJS_LEB128_GOT, and R_ASMJS_LEB128_GOT_CODE 24941relocations, respectively. 24942 24943 The ‘@PLT’ suffix is followed by a symbol name in braces; the symbol 24944value is used to determine the function signature for which a PLT stub 24945is generated. Currently, the symbol _name_ is parsed from its last ‘F’ 24946character to determine the argument count of the function, which is also 24947necessary for generating a PLT stub. 24948 24949 24950File: as.info, Node: WebAssembly-Signatures, Prev: WebAssembly-Relocs, Up: WebAssembly-Syntax 24951 249529.53.2.3 Signatures 24953................... 24954 24955Function signatures are specified with the ‘signature’ pseudo-opcode, 24956followed by a simple function signature imitating a C++-mangled function 24957type: ‘F’ followed by an optional ‘v’, then a sequence of ‘i’, ‘l’, ‘f’, 24958and ‘d’ characters to mark i32, i64, f32, and f64 parameters, 24959respectively; followed by a final ‘E’ to mark the end of the function 24960signature. 24961 24962 24963File: as.info, Node: WebAssembly-Floating-Point, Next: WebAssembly-Opcodes, Prev: WebAssembly-Syntax, Up: WebAssembly-Dependent 24964 249659.53.3 Floating Point 24966--------------------- 24967 24968WebAssembly uses little-endian IEEE floating-point numbers. 24969 24970 24971File: as.info, Node: WebAssembly-Opcodes, Next: WebAssembly-module-layout, Prev: WebAssembly-Floating-Point, Up: WebAssembly-Dependent 24972 249739.53.4 Regular Opcodes 24974---------------------- 24975 24976Ordinary instructions are encoded with the WebAssembly mnemonics as 24977listed at: 24978<https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md>. 24979 24980 Opcodes are written directly in the order in which they are encoded, 24981without going through an intermediate sexp-style expression as in the 24982‘was’ format. 24983 24984 For “typed” opcodes (block, if, etc.), the type of the block is 24985specified in square brackets following the opcode: ‘if[i]’, ‘if[]’. 24986 24987 24988File: as.info, Node: WebAssembly-module-layout, Prev: WebAssembly-Opcodes, Up: WebAssembly-Dependent 24989 249909.53.5 WebAssembly Module Layout 24991-------------------------------- 24992 24993‘as’ will only produce ELF output, not a valid WebAssembly module. It 24994is possible to make ‘as’ produce output in a single ELF section which 24995becomes a valid WebAssembly module, but a linker script to do so may be 24996preferable, as it doesn’t require running the entire module through the 24997assembler at once. 24998 24999 25000File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: WebAssembly-Dependent, Up: Machine Dependencies 25001 250029.54 XGATE Dependent Features 25003============================= 25004 25005* Menu: 25006 25007* XGATE-Opts:: XGATE Options 25008* XGATE-Syntax:: Syntax 25009* XGATE-Directives:: Assembler Directives 25010* XGATE-Float:: Floating Point 25011* XGATE-opcodes:: Opcodes 25012 25013 25014File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent 25015 250169.54.1 XGATE Options 25017-------------------- 25018 25019The Freescale XGATE version of ‘as’ has a few machine dependent options. 25020 25021‘-mshort’ 25022 This option controls the ABI and indicates to use a 16-bit integer 25023 ABI. It has no effect on the assembled instructions. This is the 25024 default. 25025 25026‘-mlong’ 25027 This option controls the ABI and indicates to use a 32-bit integer 25028 ABI. 25029 25030‘-mshort-double’ 25031 This option controls the ABI and indicates to use a 32-bit float 25032 ABI. This is the default. 25033 25034‘-mlong-double’ 25035 This option controls the ABI and indicates to use a 64-bit float 25036 ABI. 25037 25038‘--print-insn-syntax’ 25039 You can use the ‘--print-insn-syntax’ option to obtain the syntax 25040 description of the instruction when an error is detected. 25041 25042‘--print-opcodes’ 25043 The ‘--print-opcodes’ option prints the list of all the 25044 instructions with their syntax. Once the list is printed ‘as’ 25045 exits. 25046 25047 25048File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent 25049 250509.54.2 Syntax 25051------------- 25052 25053In XGATE RISC syntax, the instruction name comes first and it may be 25054followed by up to three operands. Operands are separated by commas 25055(‘,’). ‘as’ will complain if too many operands are specified for a 25056given instruction. The same will happen if you specified too few 25057operands. 25058 25059 nop 25060 ldl #23 25061 CMP R1, R2 25062 25063 The presence of a ‘;’ character or a ‘!’ character anywhere on a line 25064indicates the start of a comment that extends to the end of that line. 25065 25066 A ‘*’ or a ‘#’ character at the start of a line also introduces a 25067line comment, but these characters do not work elsewhere on the line. 25068If the first character of the line is a ‘#’ then as well as starting a 25069comment, the line could also be logical line number directive (*note 25070Comments::) or a preprocessor control command (*note Preprocessing::). 25071 25072 The XGATE assembler does not currently support a line separator 25073character. 25074 25075 The following addressing modes are understood for XGATE: 25076“Inherent” 25077 ‘’ 25078 25079“Immediate 3 Bit Wide” 25080 ‘#NUMBER’ 25081 25082“Immediate 4 Bit Wide” 25083 ‘#NUMBER’ 25084 25085“Immediate 8 Bit Wide” 25086 ‘#NUMBER’ 25087 25088“Monadic Addressing” 25089 ‘REG’ 25090 25091“Dyadic Addressing” 25092 ‘REG, REG’ 25093 25094“Triadic Addressing” 25095 ‘REG, REG, REG’ 25096 25097“Relative Addressing 9 Bit Wide” 25098 ‘*SYMBOL’ 25099 25100“Relative Addressing 10 Bit Wide” 25101 ‘*SYMBOL’ 25102 25103“Index Register plus Immediate Offset” 25104 ‘REG, (REG, #NUMBER)’ 25105 25106“Index Register plus Register Offset” 25107 ‘REG, REG, REG’ 25108 25109“Index Register plus Register Offset with Post-increment” 25110 ‘REG, REG, REG+’ 25111 25112“Index Register plus Register Offset with Pre-decrement” 25113 ‘REG, REG, -REG’ 25114 25115 The register can be either ‘R0’, ‘R1’, ‘R2’, ‘R3’, ‘R4’, ‘R5’, ‘R6’ 25116 or ‘R7’. 25117 25118 Convene macro opcodes to deal with 16-bit values have been added. 25119 25120“Immediate 16 Bit Wide” 25121 ‘#NUMBER’, or ‘*SYMBOL’ 25122 25123 For example: 25124 25125 ldw R1, #1024 25126 ldw R3, timer 25127 ldw R1, (R1, #0) 25128 COM R1 25129 stw R2, (R1, #0) 25130 25131 25132File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent 25133 251349.54.3 Assembler Directives 25135--------------------------- 25136 25137The XGATE version of ‘as’ have the following specific assembler 25138directives: 25139 25140 25141File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent 25142 251439.54.4 Floating Point 25144--------------------- 25145 25146Packed decimal (P) format floating literals are not supported(yet). 25147 25148 The floating point formats generated by directives are these. 25149 25150‘.float’ 25151 ‘Single’ precision floating point constants. 25152 25153‘.double’ 25154 ‘Double’ precision floating point constants. 25155 25156‘.extend’ 25157‘.ldouble’ 25158 ‘Extended’ precision (‘long double’) floating point constants. 25159 25160 25161File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent 25162 251639.54.5 Opcodes 25164-------------- 25165 25166 25167File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies 25168 251699.55 XStormy16 Dependent Features 25170================================= 25171 25172* Menu: 25173 25174* XStormy16 Syntax:: Syntax 25175* XStormy16 Directives:: Machine Directives 25176* XStormy16 Opcodes:: Pseudo-Opcodes 25177 25178 25179File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent 25180 251819.55.1 Syntax 25182------------- 25183 25184* Menu: 25185 25186* XStormy16-Chars:: Special Characters 25187 25188 25189File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 25190 251919.55.1.1 Special Characters 25192........................... 25193 25194‘#’ is the line comment character. If a ‘#’ appears as the first 25195character of a line, the whole line is treated as a comment, but in this 25196case the line can also be a logical line number directive (*note 25197Comments::) or a preprocessor control command (*note Preprocessing::). 25198 25199 A semicolon (‘;’) can be used to start a comment that extends from 25200wherever the character appears on the line up to the end of the line. 25201 25202 The ‘|’ character can be used to separate statements on the same 25203line. 25204 25205 25206File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent 25207 252089.55.2 XStormy16 Machine Directives 25209----------------------------------- 25210 25211‘.16bit_pointers’ 25212 Like the ‘--16bit-pointers’ command-line option this directive 25213 indicates that the assembly code makes use of 16-bit pointers. 25214 25215‘.32bit_pointers’ 25216 Like the ‘--32bit-pointers’ command-line option this directive 25217 indicates that the assembly code makes use of 32-bit pointers. 25218 25219‘.no_pointers’ 25220 Like the ‘--no-pointers’ command-line option this directive 25221 indicates that the assembly code does not makes use pointers. 25222 25223 25224File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 25225 252269.55.3 XStormy16 Pseudo-Opcodes 25227------------------------------- 25228 25229‘as’ implements all the standard XStormy16 opcodes. 25230 25231 ‘as’ also implements the following pseudo ops: 25232 25233‘@lo()’ 25234 Computes the lower 16 bits of the given expression and stores it 25235 into the immediate operand field of the given instruction. For 25236 example: 25237 25238 ‘add r6, @lo(here - there)’ 25239 25240 computes the difference between the address of labels ’here’ and 25241 ’there’, takes the lower 16 bits of this difference and adds it to 25242 register 6. 25243 25244‘@hi()’ 25245 Computes the higher 16 bits of the given expression and stores it 25246 into the immediate operand field of the given instruction. For 25247 example: 25248 25249 ‘addc r7, @hi(here - there)’ 25250 25251 computes the difference between the address of labels ’here’ and 25252 ’there’, takes the upper 16 bits of this difference, shifts it down 25253 16 bits and then adds it, along with the carry bit, to the value in 25254 register 7. 25255 25256 25257File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies 25258 252599.56 Xtensa Dependent Features 25260============================== 25261 25262This chapter covers features of the GNU assembler that are specific to 25263the Xtensa architecture. For details about the Xtensa instruction set, 25264please consult the ‘Xtensa Instruction Set Architecture (ISA) Reference 25265Manual’. 25266 25267* Menu: 25268 25269* Xtensa Options:: Command-line Options. 25270* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 25271* Xtensa Optimizations:: Assembler Optimizations. 25272* Xtensa Relaxation:: Other Automatic Transformations. 25273* Xtensa Directives:: Directives for Xtensa Processors. 25274 25275 25276File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 25277 252789.56.1 Command-line Options 25279--------------------------- 25280 25281‘--text-section-literals | --no-text-section-literals’ 25282 Control the treatment of literal pools. The default is 25283 ‘--no-text-section-literals’, which places literals in separate 25284 sections in the output file. This allows the literal pool to be 25285 placed in a data RAM/ROM. With ‘--text-section-literals’, the 25286 literals are interspersed in the text section in order to keep them 25287 as close as possible to their references. This may be necessary 25288 for large assembly files, where the literals would otherwise be out 25289 of range of the ‘L32R’ instructions in the text section. Literals 25290 are grouped into pools following ‘.literal_position’ directives or 25291 preceding ‘ENTRY’ instructions. These options only affect literals 25292 referenced via PC-relative ‘L32R’ instructions; literals for 25293 absolute mode ‘L32R’ instructions are handled separately. *Note 25294 literal: Literal Directive. 25295 25296‘--auto-litpools | --no-auto-litpools’ 25297 Control the treatment of literal pools. The default is 25298 ‘--no-auto-litpools’, which in the absence of 25299 ‘--text-section-literals’ places literals in separate sections in 25300 the output file. This allows the literal pool to be placed in a 25301 data RAM/ROM. With ‘--auto-litpools’, the literals are interspersed 25302 in the text section in order to keep them as close as possible to 25303 their references, explicit ‘.literal_position’ directives are not 25304 required. This may be necessary for very large functions, where 25305 single literal pool at the beginning of the function may not be 25306 reachable by ‘L32R’ instructions at the end. These options only 25307 affect literals referenced via PC-relative ‘L32R’ instructions; 25308 literals for absolute mode ‘L32R’ instructions are handled 25309 separately. When used together with ‘--text-section-literals’, 25310 ‘--auto-litpools’ takes precedence. *Note literal: Literal 25311 Directive. 25312 25313‘--absolute-literals | --no-absolute-literals’ 25314 Indicate to the assembler whether ‘L32R’ instructions use absolute 25315 or PC-relative addressing. If the processor includes the absolute 25316 addressing option, the default is to use absolute ‘L32R’ 25317 relocations. Otherwise, only the PC-relative ‘L32R’ relocations 25318 can be used. 25319 25320‘--target-align | --no-target-align’ 25321 Enable or disable automatic alignment to reduce branch penalties at 25322 some expense in code size. *Note Automatic Instruction Alignment: 25323 Xtensa Automatic Alignment. This optimization is enabled by 25324 default. Note that the assembler will always align instructions 25325 like ‘LOOP’ that have fixed alignment requirements. 25326 25327‘--longcalls | --no-longcalls’ 25328 Enable or disable transformation of call instructions to allow 25329 calls across a greater range of addresses. *Note Function Call 25330 Relaxation: Xtensa Call Relaxation. This option should be used 25331 when call targets can potentially be out of range. It may degrade 25332 both code size and performance, but the linker can generally 25333 optimize away the unnecessary overhead when a call ends up within 25334 range. The default is ‘--no-longcalls’. 25335 25336‘--transform | --no-transform’ 25337 Enable or disable all assembler transformations of Xtensa 25338 instructions, including both relaxation and optimization. The 25339 default is ‘--transform’; ‘--no-transform’ should only be used in 25340 the rare cases when the instructions must be exactly as specified 25341 in the assembly source. Using ‘--no-transform’ causes out of range 25342 instruction operands to be errors. 25343 25344‘--rename-section OLDNAME=NEWNAME’ 25345 Rename the OLDNAME section to NEWNAME. This option can be used 25346 multiple times to rename multiple sections. 25347 25348‘--trampolines | --no-trampolines’ 25349 Enable or disable transformation of jump instructions to allow 25350 jumps across a greater range of addresses. *Note Jump Trampolines: 25351 Xtensa Jump Relaxation. This option should be used when jump 25352 targets can potentially be out of range. In the absence of such 25353 jumps this option does not affect code size or performance. The 25354 default is ‘--trampolines’. 25355 25356‘--abi-windowed | --abi-call0’ 25357 Choose ABI tag written to the ‘.xtensa.info’ section. ABI tag 25358 indicates ABI of the assembly code. A warning is issued by the 25359 linker on an attempt to link object files with inconsistent ABI 25360 tags. Default ABI is chosen by the Xtensa core configuration. 25361 25362 25363File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 25364 253659.56.2 Assembler Syntax 25366----------------------- 25367 25368Block comments are delimited by ‘/*’ and ‘*/’. End of line comments may 25369be introduced with either ‘#’ or ‘//’. 25370 25371 If a ‘#’ appears as the first character of a line then the whole line 25372is treated as a comment, but in this case the line could also be a 25373logical line number directive (*note Comments::) or a preprocessor 25374control command (*note Preprocessing::). 25375 25376 Instructions consist of a leading opcode or macro name followed by 25377whitespace and an optional comma-separated list of operands: 25378 25379 OPCODE [OPERAND, ...] 25380 25381 Instructions must be separated by a newline or semicolon (‘;’). 25382 25383 FLIX instructions, which bundle multiple opcodes together in a single 25384instruction, are specified by enclosing the bundled opcodes inside 25385braces: 25386 25387 { 25388 [FORMAT] 25389 OPCODE0 [OPERANDS] 25390 OPCODE1 [OPERANDS] 25391 OPCODE2 [OPERANDS] 25392 ... 25393 } 25394 25395 The opcodes in a FLIX instruction are listed in the same order as the 25396corresponding instruction slots in the TIE format declaration. 25397Directives and labels are not allowed inside the braces of a FLIX 25398instruction. A particular TIE format name can optionally be specified 25399immediately after the opening brace, but this is usually unnecessary. 25400The assembler will automatically search for a format that can encode the 25401specified opcodes, so the format name need only be specified in rare 25402cases where there is more than one applicable format and where it 25403matters which of those formats is used. A FLIX instruction can also be 25404specified on a single line by separating the opcodes with semicolons: 25405 25406 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 25407 25408 If an opcode can only be encoded in a FLIX instruction but is not 25409specified as part of a FLIX bundle, the assembler will choose the 25410smallest format where the opcode can be encoded and will fill unused 25411instruction slots with no-ops. 25412 25413* Menu: 25414 25415* Xtensa Opcodes:: Opcode Naming Conventions. 25416* Xtensa Registers:: Register Naming. 25417 25418 25419File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 25420 254219.56.2.1 Opcode Names 25422..................... 25423 25424See the ‘Xtensa Instruction Set Architecture (ISA) Reference Manual’ for 25425a complete list of opcodes and descriptions of their semantics. 25426 25427 If an opcode name is prefixed with an underscore character (‘_’), 25428‘as’ will not transform that instruction in any way. The underscore 25429prefix disables both optimization (*note Xtensa Optimizations: Xtensa 25430Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 25431Relaxation.) for that particular instruction. Only use the underscore 25432prefix when it is essential to select the exact opcode produced by the 25433assembler. Using this feature unnecessarily makes the code less 25434efficient by disabling assembler optimization and less flexible by 25435disabling relaxation. 25436 25437 Note that this special handling of underscore prefixes only applies 25438to Xtensa opcodes, not to either built-in macros or user-defined macros. 25439When an underscore prefix is used with a macro (e.g., ‘_MOV’), it refers 25440to a different macro. The assembler generally provides built-in macros 25441both with and without the underscore prefix, where the underscore 25442versions behave as if the underscore carries through to the instructions 25443in the macros. For example, ‘_MOV’ may expand to ‘_MOV.N’. 25444 25445 The underscore prefix only applies to individual instructions, not to 25446series of instructions. For example, if a series of instructions have 25447underscore prefixes, the assembler will not transform the individual 25448instructions, but it may insert other instructions between them (e.g., 25449to align a ‘LOOP’ instruction). To prevent the assembler from modifying 25450a series of instructions as a whole, use the ‘no-transform’ directive. 25451*Note transform: Transform Directive. 25452 25453 25454File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 25455 254569.56.2.2 Register Names 25457....................... 25458 25459The assembly syntax for a register file entry is the “short” name for a 25460TIE register file followed by the index into that register file. For 25461example, the general-purpose ‘AR’ register file has a short name of ‘a’, 25462so these registers are named ‘a0’...‘a15’. As a special feature, ‘sp’ 25463is also supported as a synonym for ‘a1’. Additional registers may be 25464added by processor configuration options and by designer-defined TIE 25465extensions. An initial ‘$’ character is optional in all register names. 25466 25467 25468File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 25469 254709.56.3 Xtensa Optimizations 25471--------------------------- 25472 25473The optimizations currently supported by ‘as’ are generation of density 25474instructions where appropriate and automatic branch target alignment. 25475 25476* Menu: 25477 25478* Density Instructions:: Using Density Instructions. 25479* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 25480 25481 25482File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 25483 254849.56.3.1 Using Density Instructions 25485................................... 25486 25487The Xtensa instruction set has a code density option that provides 2548816-bit versions of some of the most commonly used opcodes. Use of these 25489opcodes can significantly reduce code size. When possible, the 25490assembler automatically translates instructions from the core Xtensa 25491instruction set into equivalent instructions from the Xtensa code 25492density option. This translation can be disabled by using underscore 25493prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 25494‘--no-transform’ command-line option (*note Command Line Options: Xtensa 25495Options.), or by using the ‘no-transform’ directive (*note transform: 25496Transform Directive.). 25497 25498 It is a good idea _not_ to use the density instructions directly. 25499The assembler will automatically select dense instructions where 25500possible. If you later need to use an Xtensa processor without the code 25501density option, the same assembly code will then work without 25502modification. 25503 25504 25505File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 25506 255079.56.3.2 Automatic Instruction Alignment 25508........................................ 25509 25510The Xtensa assembler will automatically align certain instructions, both 25511to optimize performance and to satisfy architectural requirements. 25512 25513 As an optimization to improve performance, the assembler attempts to 25514align branch targets so they do not cross instruction fetch boundaries. 25515(Xtensa processors can be configured with either 32-bit or 64-bit 25516instruction fetch widths.) An instruction immediately following a call 25517is treated as a branch target in this context, because it will be the 25518target of a return from the call. This alignment has the potential to 25519reduce branch penalties at some expense in code size. This optimization 25520is enabled by default. You can disable it with the ‘--no-target-align’ 25521command-line option (*note Command-line Options: Xtensa Options.). 25522 25523 The target alignment optimization is done without adding instructions 25524that could increase the execution time of the program. If there are 25525density instructions in the code preceding a target, the assembler can 25526change the target alignment by widening some of those instructions to 25527the equivalent 24-bit instructions. Extra bytes of padding can be 25528inserted immediately following unconditional jump and return 25529instructions. This approach is usually successful in aligning many, but 25530not all, branch targets. 25531 25532 The ‘LOOP’ family of instructions must be aligned such that the first 25533instruction in the loop body does not cross an instruction fetch 25534boundary (e.g., with a 32-bit fetch width, a ‘LOOP’ instruction must be 25535on either a 1 or 2 mod 4 byte boundary). The assembler knows about this 25536restriction and inserts the minimal number of 2 or 3 byte no-op 25537instructions to satisfy it. When no-op instructions are added, any 25538label immediately preceding the original loop will be moved in order to 25539refer to the loop instruction, not the newly generated no-op 25540instruction. To preserve binary compatibility across processors with 25541different fetch widths, the assembler conservatively assumes a 32-bit 25542fetch width when aligning ‘LOOP’ instructions (except if the first 25543instruction in the loop is a 64-bit instruction). 25544 25545 Previous versions of the assembler automatically aligned ‘ENTRY’ 25546instructions to 4-byte boundaries, but that alignment is now the 25547programmer’s responsibility. 25548 25549 25550File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 25551 255529.56.4 Xtensa Relaxation 25553------------------------ 25554 25555When an instruction operand is outside the range allowed for that 25556particular instruction field, ‘as’ can transform the code to use a 25557functionally-equivalent instruction or sequence of instructions. This 25558process is known as “relaxation”. This is typically done for branch 25559instructions because the distance of the branch targets is not known 25560until assembly-time. The Xtensa assembler offers branch relaxation and 25561also extends this concept to function calls, ‘MOVI’ instructions and 25562other instructions with immediate fields. 25563 25564* Menu: 25565 25566* Xtensa Branch Relaxation:: Relaxation of Branches. 25567* Xtensa Call Relaxation:: Relaxation of Function Calls. 25568* Xtensa Jump Relaxation:: Relaxation of Jumps. 25569* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 25570 25571 25572File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 25573 255749.56.4.1 Conditional Branch Relaxation 25575...................................... 25576 25577When the target of a branch is too far away from the branch itself, 25578i.e., when the offset from the branch to the target is too large to fit 25579in the immediate field of the branch instruction, it may be necessary to 25580replace the branch with a branch around a jump. For example, 25581 25582 beqz a2, L 25583 25584 may result in: 25585 25586 bnez.n a2, M 25587 j L 25588 M: 25589 25590 (The ‘BNEZ.N’ instruction would be used in this example only if the 25591density option is available. Otherwise, ‘BNEZ’ would be used.) 25592 25593 This relaxation works well because the unconditional jump instruction 25594has a much larger offset range than the various conditional branches. 25595However, an error will occur if a branch target is beyond the range of a 25596jump instruction. ‘as’ cannot relax unconditional jumps. Similarly, an 25597error will occur if the original input contains an unconditional jump to 25598a target that is out of range. 25599 25600 Branch relaxation is enabled by default. It can be disabled by using 25601underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 25602‘--no-transform’ command-line option (*note Command-line Options: Xtensa 25603Options.), or the ‘no-transform’ directive (*note transform: Transform 25604Directive.). 25605 25606 25607File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 25608 256099.56.4.2 Function Call Relaxation 25610................................. 25611 25612Function calls may require relaxation because the Xtensa immediate call 25613instructions (‘CALL0’, ‘CALL4’, ‘CALL8’ and ‘CALL12’) provide a 25614PC-relative offset of only 512 Kbytes in either direction. For larger 25615programs, it may be necessary to use indirect calls (‘CALLX0’, ‘CALLX4’, 25616‘CALLX8’ and ‘CALLX12’) where the target address is specified in a 25617register. The Xtensa assembler can automatically relax immediate call 25618instructions into indirect call instructions. This relaxation is done 25619by loading the address of the called function into the callee’s return 25620address register and then using a ‘CALLX’ instruction. So, for example: 25621 25622 call8 func 25623 25624 might be relaxed to: 25625 25626 .literal .L1, func 25627 l32r a8, .L1 25628 callx8 a8 25629 25630 Because the addresses of targets of function calls are not generally 25631known until link-time, the assembler must assume the worst and relax all 25632the calls to functions in other source files, not just those that really 25633will be out of range. The linker can recognize calls that were 25634unnecessarily relaxed, and it will remove the overhead introduced by the 25635assembler for those cases where direct calls are sufficient. 25636 25637 Call relaxation is disabled by default because it can have a negative 25638effect on both code size and performance, although the linker can 25639usually eliminate the unnecessary overhead. If a program is too large 25640and some of the calls are out of range, function call relaxation can be 25641enabled using the ‘--longcalls’ command-line option or the ‘longcalls’ 25642directive (*note longcalls: Longcalls Directive.). 25643 25644 25645File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 25646 256479.56.4.3 Jump Relaxation 25648........................ 25649 25650Jump instruction may require relaxation because the Xtensa jump 25651instruction (‘J’) provide a PC-relative offset of only 128 Kbytes in 25652either direction. One option is to use jump long (‘J.L’) instruction, 25653which depending on jump distance may be assembled as jump (‘J’) or 25654indirect jump (‘JX’). However it needs a free register. When there’s 25655no spare register it is possible to plant intermediate jump sites 25656(trampolines) between the jump instruction and its target. These sites 25657may be located in areas unreachable by normal code execution flow, in 25658that case they only contain intermediate jumps, or they may be inserted 25659in the middle of code block, in which case there’s an additional jump 25660from the beginning of the trampoline to the instruction past its end. 25661So, for example: 25662 25663 j 1f 25664 ... 25665 retw 25666 ... 25667 mov a10, a2 25668 call8 func 25669 ... 25670 1: 25671 ... 25672 25673 might be relaxed to: 25674 25675 j .L0_TR_1 25676 ... 25677 retw 25678 .L0_TR_1: 25679 j 1f 25680 ... 25681 mov a10, a2 25682 call8 func 25683 ... 25684 1: 25685 ... 25686 25687 or to: 25688 25689 j .L0_TR_1 25690 ... 25691 retw 25692 ... 25693 mov a10, a2 25694 j .L0_TR_0 25695 .L0_TR_1: 25696 j 1f 25697 .L0_TR_0: 25698 call8 func 25699 ... 25700 1: 25701 ... 25702 25703 The Xtensa assembler uses trampolines with jump around only when it 25704cannot find suitable unreachable trampoline. There may be multiple 25705trampolines between the jump instruction and its target. 25706 25707 This relaxation does not apply to jumps to undefined symbols, 25708assuming they will reach their targets once resolved. 25709 25710 Jump relaxation is enabled by default because it does not affect code 25711size or performance while the code itself is small. This relaxation may 25712be disabled completely with ‘--no-trampolines’ or ‘--no-transform’ 25713command-line options (*note Command-line Options: Xtensa Options.). 25714 25715 25716File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation 25717 257189.56.4.4 Other Immediate Field Relaxation 25719......................................... 25720 25721The assembler normally performs the following other relaxations. They 25722can be disabled by using underscore prefixes (*note Opcode Names: Xtensa 25723Opcodes.), the ‘--no-transform’ command-line option (*note Command-line 25724Options: Xtensa Options.), or the ‘no-transform’ directive (*note 25725transform: Transform Directive.). 25726 25727 The ‘MOVI’ machine instruction can only materialize values in the 25728range from -2048 to 2047. Values outside this range are best 25729materialized with ‘L32R’ instructions. Thus: 25730 25731 movi a0, 100000 25732 25733 is assembled into the following machine code: 25734 25735 .literal .L1, 100000 25736 l32r a0, .L1 25737 25738 The ‘L8UI’ machine instruction can only be used with immediate 25739offsets in the range from 0 to 255. The ‘L16SI’ and ‘L16UI’ machine 25740instructions can only be used with offsets from 0 to 510. The ‘L32I’ 25741machine instruction can only be used with offsets from 0 to 1020. A 25742load offset outside these ranges can be materialized with an ‘L32R’ 25743instruction if the destination register of the load is different than 25744the source address register. For example: 25745 25746 l32i a1, a0, 2040 25747 25748 is translated to: 25749 25750 .literal .L1, 2040 25751 l32r a1, .L1 25752 add a1, a0, a1 25753 l32i a1, a1, 0 25754 25755If the load destination and source address register are the same, an 25756out-of-range offset causes an error. 25757 25758 The Xtensa ‘ADDI’ instruction only allows immediate operands in the 25759range from -128 to 127. There are a number of alternate instruction 25760sequences for the ‘ADDI’ operation. First, if the immediate is 0, the 25761‘ADDI’ will be turned into a ‘MOV.N’ instruction (or the equivalent ‘OR’ 25762instruction if the code density option is not available). If the ‘ADDI’ 25763immediate is outside of the range -128 to 127, but inside the range 25764-32896 to 32639, an ‘ADDMI’ instruction or ‘ADDMI’/‘ADDI’ sequence will 25765be used. Finally, if the immediate is outside of this range and a free 25766register is available, an ‘L32R’/‘ADD’ sequence will be used with a 25767literal allocated from the literal pool. 25768 25769 For example: 25770 25771 addi a5, a6, 0 25772 addi a5, a6, 512 25773 addi a5, a6, 513 25774 addi a5, a6, 50000 25775 25776 is assembled into the following: 25777 25778 .literal .L1, 50000 25779 mov.n a5, a6 25780 addmi a5, a6, 0x200 25781 addmi a5, a6, 0x200 25782 addi a5, a5, 1 25783 l32r a5, .L1 25784 add a5, a6, a5 25785 25786 25787File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 25788 257899.56.5 Directives 25790----------------- 25791 25792The Xtensa assembler supports a region-based directive syntax: 25793 25794 .begin DIRECTIVE [OPTIONS] 25795 ... 25796 .end DIRECTIVE 25797 25798 All the Xtensa-specific directives that apply to a region of code use 25799this syntax. 25800 25801 The directive applies to code between the ‘.begin’ and the ‘.end’. 25802The state of the option after the ‘.end’ reverts to what it was before 25803the ‘.begin’. A nested ‘.begin’/‘.end’ region can further change the 25804state of the directive without having to be aware of its outer state. 25805For example, consider: 25806 25807 .begin no-transform 25808 L: add a0, a1, a2 25809 .begin transform 25810 M: add a0, a1, a2 25811 .end transform 25812 N: add a0, a1, a2 25813 .end no-transform 25814 25815 The ‘ADD’ opcodes at ‘L’ and ‘N’ in the outer ‘no-transform’ region 25816both result in ‘ADD’ machine instructions, but the assembler selects an 25817‘ADD.N’ instruction for the ‘ADD’ at ‘M’ in the inner ‘transform’ 25818region. 25819 25820 The advantage of this style is that it works well inside macros which 25821can preserve the context of their callers. 25822 25823 The following directives are available: 25824* Menu: 25825 25826* Schedule Directive:: Enable instruction scheduling. 25827* Longcalls Directive:: Use Indirect Calls for Greater Range. 25828* Transform Directive:: Disable All Assembler Transformations. 25829* Literal Directive:: Intermix Literals with Instructions. 25830* Literal Position Directive:: Specify Inline Literal Pool Locations. 25831* Literal Prefix Directive:: Specify Literal Section Name Prefix. 25832* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 25833 25834 25835File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 25836 258379.56.5.1 schedule 25838................. 25839 25840The ‘schedule’ directive is recognized only for compatibility with 25841Tensilica’s assembler. 25842 25843 .begin [no-]schedule 25844 .end [no-]schedule 25845 25846 This directive is ignored and has no effect on ‘as’. 25847 25848 25849File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 25850 258519.56.5.2 longcalls 25852.................. 25853 25854The ‘longcalls’ directive enables or disables function call relaxation. 25855*Note Function Call Relaxation: Xtensa Call Relaxation. 25856 25857 .begin [no-]longcalls 25858 .end [no-]longcalls 25859 25860 Call relaxation is disabled by default unless the ‘--longcalls’ 25861command-line option is specified. The ‘longcalls’ directive overrides 25862the default determined by the command-line options. 25863 25864 25865File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 25866 258679.56.5.3 transform 25868.................. 25869 25870This directive enables or disables all assembler transformation, 25871including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 25872optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 25873 25874 .begin [no-]transform 25875 .end [no-]transform 25876 25877 Transformations are enabled by default unless the ‘--no-transform’ 25878option is used. The ‘transform’ directive overrides the default 25879determined by the command-line options. An underscore opcode prefix, 25880disabling transformation of that opcode, always takes precedence over 25881both directives and command-line flags. 25882 25883 25884File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 25885 258869.56.5.4 literal 25887................ 25888 25889The ‘.literal’ directive is used to define literal pool data, i.e., 25890read-only 32-bit data accessed via ‘L32R’ instructions. 25891 25892 .literal LABEL, VALUE[, VALUE...] 25893 25894 This directive is similar to the standard ‘.word’ directive, except 25895that the actual location of the literal data is determined by the 25896assembler and linker, not by the position of the ‘.literal’ directive. 25897Using this directive gives the assembler freedom to locate the literal 25898data in the most appropriate place and possibly to combine identical 25899literals. For example, the code: 25900 25901 entry sp, 40 25902 .literal .L1, sym 25903 l32r a4, .L1 25904 25905 can be used to load a pointer to the symbol ‘sym’ into register ‘a4’. 25906The value of ‘sym’ will not be placed between the ‘ENTRY’ and ‘L32R’ 25907instructions; instead, the assembler puts the data in a literal pool. 25908 25909 Literal pools are placed by default in separate literal sections; 25910however, when using the ‘--text-section-literals’ option (*note 25911Command-line Options: Xtensa Options.), the literal pools for 25912PC-relative mode ‘L32R’ instructions are placed in the current 25913section.(1) These text section literal pools are created automatically 25914before ‘ENTRY’ instructions and manually after ‘.literal_position’ 25915directives (*note literal_position: Literal Position Directive.). If 25916there are no preceding ‘ENTRY’ instructions, explicit 25917‘.literal_position’ directives must be used to place the text section 25918literal pools; otherwise, ‘as’ will report an error. 25919 25920 When literals are placed in separate sections, the literal section 25921names are derived from the names of the sections where the literals are 25922defined. The base literal section names are ‘.literal’ for PC-relative 25923mode ‘L32R’ instructions and ‘.lit4’ for absolute mode ‘L32R’ 25924instructions (*note absolute-literals: Absolute Literals Directive.). 25925These base names are used for literals defined in the default ‘.text’ 25926section. For literals defined in other sections or within the scope of 25927a ‘literal_prefix’ directive (*note literal_prefix: Literal Prefix 25928Directive.), the following rules determine the literal section name: 25929 25930 1. If the current section is a member of a section group, the literal 25931 section name includes the group name as a suffix to the base 25932 ‘.literal’ or ‘.lit4’ name, with a period to separate the base name 25933 and group name. The literal section is also made a member of the 25934 group. 25935 25936 2. If the current section name (or ‘literal_prefix’ value) begins with 25937 “‘.gnu.linkonce.KIND.’”, the literal section name is formed by 25938 replacing “‘.KIND’” with the base ‘.literal’ or ‘.lit4’ name. For 25939 example, for literals defined in a section named 25940 ‘.gnu.linkonce.t.func’, the literal section will be 25941 ‘.gnu.linkonce.literal.func’ or ‘.gnu.linkonce.lit4.func’. 25942 25943 3. If the current section name (or ‘literal_prefix’ value) ends with 25944 ‘.text’, the literal section name is formed by replacing that 25945 suffix with the base ‘.literal’ or ‘.lit4’ name. For example, for 25946 literals defined in a section named ‘.iram0.text’, the literal 25947 section will be ‘.iram0.literal’ or ‘.iram0.lit4’. 25948 25949 4. If none of the preceding conditions apply, the literal section name 25950 is formed by adding the base ‘.literal’ or ‘.lit4’ name as a suffix 25951 to the current section name (or ‘literal_prefix’ value). 25952 25953 ---------- Footnotes ---------- 25954 25955 (1) Literals for the ‘.init’ and ‘.fini’ sections are always placed 25956in separate sections, even when ‘--text-section-literals’ is enabled. 25957 25958 25959File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 25960 259619.56.5.5 literal_position 25962......................... 25963 25964When using ‘--text-section-literals’ to place literals inline in the 25965section being assembled, the ‘.literal_position’ directive can be used 25966to mark a potential location for a literal pool. 25967 25968 .literal_position 25969 25970 The ‘.literal_position’ directive is ignored when the 25971‘--text-section-literals’ option is not used or when ‘L32R’ instructions 25972use the absolute addressing mode. 25973 25974 The assembler will automatically place text section literal pools 25975before ‘ENTRY’ instructions, so the ‘.literal_position’ directive is 25976only needed to specify some other location for a literal pool. You may 25977need to add an explicit jump instruction to skip over an inline literal 25978pool. 25979 25980 For example, an interrupt vector does not begin with an ‘ENTRY’ 25981instruction so the assembler will be unable to automatically find a good 25982place to put a literal pool. Moreover, the code for the interrupt 25983vector must be at a specific starting address, so the literal pool 25984cannot come before the start of the code. The literal pool for the 25985vector must be explicitly positioned in the middle of the vector (before 25986any uses of the literals, due to the negative offsets used by 25987PC-relative ‘L32R’ instructions). The ‘.literal_position’ directive can 25988be used to do this. In the following code, the literal for ‘M’ will 25989automatically be aligned correctly and is placed after the unconditional 25990jump. 25991 25992 .global M 25993 code_start: 25994 j continue 25995 .literal_position 25996 .align 4 25997 continue: 25998 movi a4, M 25999 26000 26001File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 26002 260039.56.5.6 literal_prefix 26004....................... 26005 26006The ‘literal_prefix’ directive allows you to override the default 26007literal section names, which are derived from the names of the sections 26008where the literals are defined. 26009 26010 .begin literal_prefix [NAME] 26011 .end literal_prefix 26012 26013 For literals defined within the delimited region, the literal section 26014names are derived from the NAME argument instead of the name of the 26015current section. The rules used to derive the literal section names do 26016not change. *Note literal: Literal Directive. If the NAME argument is 26017omitted, the literal sections revert to the defaults. This directive 26018has no effect when using the ‘--text-section-literals’ option (*note 26019Command-line Options: Xtensa Options.). 26020 26021 26022File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 26023 260249.56.5.7 absolute-literals 26025.......................... 26026 26027The ‘absolute-literals’ and ‘no-absolute-literals’ directives control 26028the absolute vs. PC-relative mode for ‘L32R’ instructions. These are 26029relevant only for Xtensa configurations that include the absolute 26030addressing option for ‘L32R’ instructions. 26031 26032 .begin [no-]absolute-literals 26033 .end [no-]absolute-literals 26034 26035 These directives do not change the ‘L32R’ mode—they only cause the 26036assembler to emit the appropriate kind of relocation for ‘L32R’ 26037instructions and to place the literal values in the appropriate section. 26038To change the ‘L32R’ mode, the program must write the ‘LITBASE’ special 26039register. It is the programmer’s responsibility to keep track of the 26040mode and indicate to the assembler which mode is used in each region of 26041code. 26042 26043 If the Xtensa configuration includes the absolute ‘L32R’ addressing 26044option, the default is to assume absolute ‘L32R’ addressing unless the 26045‘--no-absolute-literals’ command-line option is specified. Otherwise, 26046the default is to assume PC-relative ‘L32R’ addressing. The 26047‘absolute-literals’ directive can then be used to override the default 26048determined by the command-line options. 26049 26050 26051File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 26052 260539.57 Z80 Dependent Features 26054=========================== 26055 26056* Menu: 26057 26058* Z80 Options:: Options 26059* Z80 Syntax:: Syntax 26060* Z80 Floating Point:: Floating Point 26061* Z80 Directives:: Z80 Machine Directives 26062* Z80 Opcodes:: Opcodes 26063 26064 26065File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 26066 260679.57.1 Command-line Options 26068--------------------------- 26069 26070‘-march=CPU[-EXT...][+EXT...]’ 26071 This option specifies the target processor. The assembler will 26072 issue an error message if an attempt is made to assemble an 26073 instruction which will not execute on the target processor. The 26074 following processor names are recognized: ‘z80’, ‘z180’, ‘ez80’, 26075 ‘gbz80’, ‘z80n’, ‘r800’. In addition to the basic instruction set, 26076 the assembler can be told to accept some extension mnemonics. For 26077 example, ‘-march=z180+sli+infc’ extends Z180 with SLI instructions 26078 and IN F,(C). The following extensions are currently supported: 26079 ‘full’ (all known instructions), ‘adl’ (ADL CPU mode by default, 26080 eZ80 only), ‘sli’ (instruction known as SLI, SLL or SL1), ‘xyhl’ 26081 (instructions with halves of index registers: IXL, IXH, IYL, IYH), 26082 ‘xdcb’ (instructions like ROTOP (II+D),R and BITOP N,(II+D),R), 26083 ‘infc’ (instruction IN F,(C) or IN (C)), ‘outc0’ (instruction OUT 26084 (C),0). Note that rather than extending a basic instruction set, 26085 the extension mnemonics starting with ‘-’ revoke the respective 26086 functionality: ‘-march=z80-full+xyhl’ first removes all default 26087 extensions and adds support for index registers halves only. 26088 26089 If this option is not specified then ‘-march=z80+xyhl+infc’ is 26090 assumed. 26091 26092‘-local-prefix=PREFIX’ 26093 Mark all labels with specified prefix as local. But such label can 26094 be marked global explicitly in the code. This option do not change 26095 default local label prefix ‘.L’, it is just adds new one. 26096 26097‘-colonless’ 26098 Accept colonless labels. All symbols at line begin are treated as 26099 labels. 26100 26101‘-sdcc’ 26102 Accept assembler code produced by SDCC. 26103 26104‘-fp-s=FORMAT’ 26105 Single precision floating point numbers format. Default: ieee754 26106 (32 bit). 26107 26108‘-fp-d=FORMAT’ 26109 Double precision floating point numbers format. Default: ieee754 26110 (64 bit). 26111 26112 Floating point numbers formats. 26113‘ieee754’ 26114 Single or double precision IEEE754 compatible format. 26115 26116‘half’ 26117 Half precision IEEE754 compatible format (16 bits). 26118 26119‘single’ 26120 Single precision IEEE754 compatible format (32 bits). 26121 26122‘double’ 26123 Double precision IEEE754 compatible format (64 bits). 26124 26125‘zeda32’ 26126 32 bit floating point format from z80float library by Zeda. 26127 26128‘math48’ 26129 48 bit floating point format from Math48 package by Anders 26130 Hejlsberg. 26131 26132 26133File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 26134 261359.57.2 Syntax 26136------------- 26137 26138The assembler syntax closely follows the ’Z80 family CPU User Manual’ by 26139Zilog. In expressions a single ‘=’ may be used as “is equal to” 26140comparison operator. 26141 26142 Suffices can be used to indicate the radix of integer constants; ‘H’ 26143or ‘h’ for hexadecimal, ‘D’ or ‘d’ for decimal, ‘Q’, ‘O’, ‘q’ or ‘o’ for 26144octal, and ‘B’ for binary. 26145 26146 The suffix ‘b’ denotes a backreference to local label. 26147 26148* Menu: 26149 26150* Z80-Chars:: Special Characters 26151* Z80-Regs:: Register Names 26152* Z80-Case:: Case Sensitivity 26153* Z80-Labels:: Labels 26154 26155 26156File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 26157 261589.57.2.1 Special Characters 26159........................... 26160 26161The semicolon ‘;’ is the line comment character; 26162 26163 If a ‘#’ appears as the first character of a line then the whole line 26164is treated as a comment, but in this case the line could also be a 26165logical line number directive (*note Comments::) or a preprocessor 26166control command (*note Preprocessing::). 26167 26168 The Z80 assembler does not support a line separator character. 26169 26170 The dollar sign ‘$’ can be used as a prefix for hexadecimal numbers 26171and as a symbol denoting the current location counter. 26172 26173 A backslash ‘\’ is an ordinary character for the Z80 assembler. 26174 26175 The single quote ‘'’ must be followed by a closing quote. If there 26176is one character in between, it is a character constant, otherwise it is 26177a string constant. 26178 26179 26180File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 26181 261829.57.2.2 Register Names 26183....................... 26184 26185The registers are referred to with the letters assigned to them by 26186Zilog. In addition ‘as’ recognizes ‘ixl’ and ‘ixh’ as the least and 26187most significant octet in ‘ix’, and similarly ‘iyl’ and ‘iyh’ as parts 26188of ‘iy’. 26189 26190 26191File: as.info, Node: Z80-Case, Next: Z80-Labels, Prev: Z80-Regs, Up: Z80 Syntax 26192 261939.57.2.3 Case Sensitivity 26194......................... 26195 26196Upper and lower case are equivalent in register names, opcodes, 26197condition codes and assembler directives. The case of letters is 26198significant in labels and symbol names. The case is also important to 26199distinguish the suffix ‘b’ for a backward reference to a local label 26200from the suffix ‘B’ for a number in binary notation. 26201 26202 26203File: as.info, Node: Z80-Labels, Prev: Z80-Case, Up: Z80 Syntax 26204 262059.57.2.4 Labels 26206............... 26207 26208Labels started by ‘.L’ acts as local labels. You may specify custom 26209local label prefix by ‘-local-prefix’ command-line option. Dollar, 26210forward and backward local labels are supported. By default, all labels 26211are followed by colon. Legacy code with colonless labels can be built 26212with ‘-colonless’ command-line option specified. In this case all 26213tokens at line begin are treated as labels. 26214 26215 26216File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 26217 262189.57.3 Floating Point 26219--------------------- 26220 26221Floating-point numbers of following types are supported: 26222 26223‘ieee754’ 26224 Supported half, single and double precision IEEE754 compatible 26225 numbers. 26226 26227‘zeda32’ 26228 32 bit floating point numbers from z80float library by Zeda. 26229 26230‘math48’ 26231 48 bit floating point numbers from Math48 package by Anders 26232 Hejlsberg. 26233 26234 26235File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 26236 262379.57.4 Z80 Assembler Directives 26238------------------------------- 26239 26240‘as’ for the Z80 supports some additional directives for compatibility 26241with other assemblers. 26242 26243 These are the additional directives in ‘as’ for the Z80: 26244 26245‘.assume ADL = EXPRESSION’ 26246 Set ADL status for eZ80. Non-zero value enable compilation in ADL 26247 mode else used Z80 mode. ADL and Z80 mode produces incompatible 26248 object code. Mixing both of them within one binary may lead 26249 problems with disassembler. 26250 26251‘db EXPRESSION|STRING[,EXPRESSION|STRING...]’ 26252‘defb EXPRESSION|STRING[,EXPRESSION|STRING...]’ 26253‘defm STRING[,STRING...]’ 26254 For each STRING the characters are copied to the object file, for 26255 each other EXPRESSION the value is stored in one byte. A warning 26256 is issued in case of an overflow. Backslash symbol in the strings 26257 is generic symbol, it cannot be used as escape character. *Note 26258 ‘.ascii’: Ascii. 26259 26260‘dw EXPRESSION[,EXPRESSION...]’ 26261‘defw EXPRESSION[,EXPRESSION...]’ 26262 For each EXPRESSION the value is stored in two bytes, ignoring 26263 overflow. 26264 26265‘d24 EXPRESSION[,EXPRESSION...]’ 26266‘def24 EXPRESSION[,EXPRESSION...]’ 26267 For each EXPRESSION the value is stored in three bytes, ignoring 26268 overflow. 26269 26270‘d32 EXPRESSION[,EXPRESSION...]’ 26271‘def32 EXPRESSION[,EXPRESSION...]’ 26272 For each EXPRESSION the value is stored in four bytes, ignoring 26273 overflow. 26274 26275‘ds COUNT[, VALUE]’ 26276‘defs COUNT[, VALUE]’ 26277 Fill COUNT bytes in the object file with VALUE, if VALUE is omitted 26278 it defaults to zero. 26279 26280‘SYMBOL defl EXPRESSION’ 26281 The ‘defl’ directive is like ‘.set’ but with different syntax. 26282 *Note ‘.set’: Set. It set the value of SYMBOL to EXPRESSION. 26283 Symbols defined with ‘defl’ are not protected from redefinition. 26284 26285‘SYMBOL equ EXPRESSION’ 26286 The ‘equ’ directive is like ‘.equiv’ but with different syntax. 26287 *Note ‘.equiv’: Equiv. It set the value of SYMBOL to EXPRESSION. 26288 It is an error if SYMBOL is already defined. Symbols defined with 26289 ‘equ’ are not protected from redefinition. 26290 26291‘psect NAME’ 26292 A synonym for ‘.section’, no second argument should be given. 26293 *Note ‘.section’: Section. 26294 26295‘xdef SYMBOL’ 26296 A synonym for ‘.global’, make SYMBOL is visible to linker. *Note 26297 ‘.global’: Global. 26298 26299‘xref NAME’ 26300 A synonym for ‘.extern’ (*note ‘.extern’: Extern.). 26301 26302 26303File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 26304 263059.57.5 Opcodes 26306-------------- 26307 26308In line with common practice, Z80 mnemonics are used for the Z80, Z80N, 26309Z180, eZ80, Ascii R800 and the GameBoy Z80. 26310 26311 In many instructions it is possible to use one of the half index 26312registers (‘ixl’,‘ixh’,‘iyl’,‘iyh’) in stead of an 8-bit general purpose 26313register. This yields instructions that are documented on the eZ80 and 26314the R800, undocumented on the Z80 and unsupported on the Z180. 26315Similarly ‘in f,(c)’ is documented on the R800, undocumented on the Z80 26316and unsupported on the Z180 and the eZ80. 26317 26318 The assembler also supports the following undocumented 26319Z80-instructions, that have not been adopted in any other instruction 26320set: 26321‘out (c),0’ 26322 Sends zero to the port pointed to by register ‘C’. 26323 26324‘sli M’ 26325 Equivalent to ‘M = (M<<1)+1’, the operand M can be any operand that 26326 is valid for ‘sla’. One can use ‘sll’ as a synonym for ‘sli’. 26327 26328‘OP (ix+D), R’ 26329 This is equivalent to 26330 26331 ld R, (ix+D) 26332 OP R 26333 ld (ix+D), R 26334 26335 The operation ‘OP’ may be any of ‘res B,’, ‘set B,’, ‘rl’, ‘rlc’, 26336 ‘rr’, ‘rrc’, ‘sla’, ‘sli’, ‘sra’ and ‘srl’, and the register ‘R’ 26337 may be any of ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, ‘h’ and ‘l’. 26338 26339‘OP (iy+D), R’ 26340 As above, but with ‘iy’ instead of ‘ix’. 26341 26342 The web site at <http://www.z80.info> is a good starting place to 26343find more information on programming the Z80. 26344 26345 You may enable or disable any of these instructions for any target 26346CPU even this instruction is not supported by any real CPU of this type. 26347Useful for custom CPU cores. 26348 26349 26350File: as.info, Node: Z8000-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 26351 263529.58 Z8000 Dependent Features 26353============================= 26354 26355The Z8000 as supports both members of the Z8000 family: the unsegmented 26356Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit 26357addresses. 26358 26359 When the assembler is in unsegmented mode (specified with the 26360‘unsegm’ directive), an address takes up one word (16 bit) sized 26361register. When the assembler is in segmented mode (specified with the 26362‘segm’ directive), a 24-bit address takes up a long (32 bit) register. 26363*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 26364of other Z8000 specific assembler directives. 26365 26366* Menu: 26367 26368* Z8000 Options:: Command-line options for the Z8000 26369* Z8000 Syntax:: Assembler syntax for the Z8000 26370* Z8000 Directives:: Special directives for the Z8000 26371* Z8000 Opcodes:: Opcodes 26372 26373 26374File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 26375 263769.58.1 Options 26377-------------- 26378 26379‘-z8001’ 26380 Generate segmented code by default. 26381 26382‘-z8002’ 26383 Generate unsegmented code by default. 26384 26385 26386File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 26387 263889.58.2 Syntax 26389------------- 26390 26391* Menu: 26392 26393* Z8000-Chars:: Special Characters 26394* Z8000-Regs:: Register Names 26395* Z8000-Addressing:: Addressing Modes 26396 26397 26398File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 26399 264009.58.2.1 Special Characters 26401........................... 26402 26403‘!’ is the line comment character. 26404 26405 If a ‘#’ appears as the first character of a line then the whole line 26406is treated as a comment, but in this case the line could also be a 26407logical line number directive (*note Comments::) or a preprocessor 26408control command (*note Preprocessing::). 26409 26410 You can use ‘;’ instead of a newline to separate statements. 26411 26412 26413File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 26414 264159.58.2.2 Register Names 26416....................... 26417 26418The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 26419to different sized groups of registers by register number, with the 26420prefix ‘r’ for 16 bit registers, ‘rr’ for 32 bit registers and ‘rq’ for 2642164 bit registers. You can also refer to the contents of the first eight 26422(of the sixteen 16 bit registers) by bytes. They are named ‘rlN’ and 26423‘rhN’. 26424 26425_byte registers_ 26426 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 26427 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 26428 26429_word registers_ 26430 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 26431 26432_long word registers_ 26433 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 26434 26435_quad word registers_ 26436 rq0 rq4 rq8 rq12 26437 26438 26439File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 26440 264419.58.2.3 Addressing Modes 26442......................... 26443 26444as understands the following addressing modes for the Z8000: 26445 26446‘rlN’ 26447‘rhN’ 26448‘rN’ 26449‘rrN’ 26450‘rqN’ 26451 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 26452 26453‘@rN’ 26454‘@rrN’ 26455 Indirect register: @rrN in segmented mode, @rN in unsegmented mode. 26456 26457‘ADDR’ 26458 Direct: the 16 bit or 24 bit address (depending on whether the 26459 assembler is in segmented or unsegmented mode) of the operand is in 26460 the instruction. 26461 26462‘address(rN)’ 26463 Indexed: the 16 or 24 bit address is added to the 16 bit register 26464 to produce the final address in memory of the operand. 26465 26466‘rN(#IMM)’ 26467‘rrN(#IMM)’ 26468 Base Address: the 16 or 24 bit register is added to the 16 bit sign 26469 extended immediate displacement to produce the final address in 26470 memory of the operand. 26471 26472‘rN(rM)’ 26473‘rrN(rM)’ 26474 Base Index: the 16 or 24 bit register rN or rrN is added to the 26475 sign extended 16 bit index register rM to produce the final address 26476 in memory of the operand. 26477 26478‘#XX’ 26479 Immediate data XX. 26480 26481 26482File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 26483 264849.58.3 Assembler Directives for the Z8000 26485----------------------------------------- 26486 26487The Z8000 port of as includes additional assembler directives, for 26488compatibility with other Z8000 assemblers. These do not begin with ‘.’ 26489(unlike the ordinary as directives). 26490 26491‘segm’ 26492‘.z8001’ 26493 Generate code for the segmented Z8001. 26494 26495‘unsegm’ 26496‘.z8002’ 26497 Generate code for the unsegmented Z8002. 26498 26499‘name’ 26500 Synonym for ‘.file’ 26501 26502‘global’ 26503 Synonym for ‘.global’ 26504 26505‘wval’ 26506 Synonym for ‘.word’ 26507 26508‘lval’ 26509 Synonym for ‘.long’ 26510 26511‘bval’ 26512 Synonym for ‘.byte’ 26513 26514‘sval’ 26515 Assemble a string. ‘sval’ expects one string literal, delimited by 26516 single quotes. It assembles each byte of the string into 26517 consecutive addresses. You can use the escape sequence ‘%XX’ 26518 (where XX represents a two-digit hexadecimal number) to represent 26519 the character whose ASCII value is XX. Use this feature to 26520 describe single quote and other characters that may not appear in 26521 string literals as themselves. For example, the C statement 26522 ‘char *a = "he said \"it's 50% off\"";’ is represented in Z8000 26523 assembly language (shown with the assembler output in hex at the 26524 left) as 26525 26526 68652073 sval 'he said %22it%27s 50%25 off%22%00' 26527 61696420 26528 22697427 26529 73203530 26530 25206F66 26531 662200 26532 26533‘rsect’ 26534 synonym for ‘.section’ 26535 26536‘block’ 26537 synonym for ‘.space’ 26538 26539‘even’ 26540 special case of ‘.align’; aligns output to even byte boundary. 26541 26542 26543File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 26544 265459.58.4 Opcodes 26546-------------- 26547 26548For detailed information on the Z8000 machine instruction set, see 26549‘Z8000 Technical Manual’. 26550 26551 The following table summarizes the opcodes and their arguments: 26552 26553 rs 16 bit source register 26554 rd 16 bit destination register 26555 rbs 8 bit source register 26556 rbd 8 bit destination register 26557 rrs 32 bit source register 26558 rrd 32 bit destination register 26559 rqs 64 bit source register 26560 rqd 64 bit destination register 26561 addr 16/24 bit address 26562 imm immediate data 26563 26564 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 26565 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 26566 add rd,@rs clrb rbd dab rbd 26567 add rd,addr com @rd dbjnz rbd,disp7 26568 add rd,addr(rs) com addr dec @rd,imm4m1 26569 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 26570 add rd,rs com rd dec addr,imm4m1 26571 addb rbd,@rs comb @rd dec rd,imm4m1 26572 addb rbd,addr comb addr decb @rd,imm4m1 26573 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 26574 addb rbd,imm8 comb rbd decb addr,imm4m1 26575 addb rbd,rbs comflg flags decb rbd,imm4m1 26576 addl rrd,@rs cp @rd,imm16 di i2 26577 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 26578 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 26579 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 26580 addl rrd,rrs cp rd,addr div rrd,imm16 26581 and rd,@rs cp rd,addr(rs) div rrd,rs 26582 and rd,addr cp rd,imm16 divl rqd,@rs 26583 and rd,addr(rs) cp rd,rs divl rqd,addr 26584 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 26585 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 26586 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 26587 andb rbd,addr cpb rbd,@rs djnz rd,disp7 26588 andb rbd,addr(rs) cpb rbd,addr ei i2 26589 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 26590 andb rbd,rbs cpb rbd,imm8 ex rd,addr 26591 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 26592 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 26593 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 26594 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 26595 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 26596 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 26597 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 26598 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 26599 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 26600 bitb rbd,rs cpl rrd,@rs ext8f imm8 26601 bpt cpl rrd,addr exts rrd 26602 call @rd cpl rrd,addr(rs) extsb rd 26603 call addr cpl rrd,imm32 extsl rqd 26604 call addr(rd) cpl rrd,rrs halt 26605 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 26606 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 26607 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 26608 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 26609 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 26610 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 26611 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 26612 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 26613 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 26614 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 26615 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 26616 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 26617 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 26618 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 26619 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 26620 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 26621 iret ldib @rd,@rs,rr neg addr(rd) 26622 jp cc,@rd ldir @rd,@rs,rr neg rd 26623 jp cc,addr ldirb @rd,@rs,rr negb @rd 26624 jp cc,addr(rd) ldk rd,imm4 negb addr 26625 jr cc,disp8 ldl @rd,rrs negb addr(rd) 26626 ld @rd,imm16 ldl addr(rd),rrs negb rbd 26627 ld @rd,rs ldl addr,rrs nop 26628 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 26629 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 26630 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 26631 ld addr,rs ldl rrd,addr or rd,imm16 26632 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 26633 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 26634 ld rd,@rs ldl rrd,rrs orb rbd,addr 26635 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 26636 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 26637 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 26638 ld rd,rs ldm addr(rd),rs,n out @rd,rs 26639 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 26640 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 26641 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 26642 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 26643 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 26644 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 26645 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 26646 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 26647 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 26648 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 26649 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 26650 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 26651 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 26652 ldb rbd,@rs mbit popl addr,@rs 26653 ldb rbd,addr mreq rd popl rrd,@rs 26654 ldb rbd,addr(rs) mres push @rd,@rs 26655 ldb rbd,imm8 mset push @rd,addr 26656 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 26657 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 26658 push @rd,rs set addr,imm4 subl rrd,imm32 26659 pushl @rd,@rs set rd,imm4 subl rrd,rrs 26660 pushl @rd,addr set rd,rs tcc cc,rd 26661 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 26662 pushl @rd,rrs setb addr(rd),imm4 test @rd 26663 res @rd,imm4 setb addr,imm4 test addr 26664 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 26665 res addr,imm4 setb rbd,rs test rd 26666 res rd,imm4 setflg imm4 testb @rd 26667 res rd,rs sinb rbd,imm16 testb addr 26668 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 26669 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 26670 resb addr,imm4 sindb @rd,@rs,rba testl @rd 26671 resb rbd,imm4 sinib @rd,@rs,ra testl addr 26672 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 26673 resflg imm4 sla rd,imm8 testl rrd 26674 ret cc slab rbd,imm8 trdb @rd,@rs,rba 26675 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 26676 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 26677 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 26678 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 26679 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 26680 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 26681 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 26682 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 26683 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 26684 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 26685 rsvd36 sra rd,imm8 tset rd 26686 rsvd38 srab rbd,imm8 tsetb @rd 26687 rsvd78 sral rrd,imm8 tsetb addr 26688 rsvd7e srl rd,imm8 tsetb addr(rd) 26689 rsvd9d srlb rbd,imm8 tsetb rbd 26690 rsvd9f srll rrd,imm8 xor rd,@rs 26691 rsvdb9 sub rd,@rs xor rd,addr 26692 rsvdbf sub rd,addr xor rd,addr(rs) 26693 sbc rd,rs sub rd,addr(rs) xor rd,imm16 26694 sbcb rbd,rbs sub rd,imm16 xor rd,rs 26695 sc imm8 sub rd,rs xorb rbd,@rs 26696 sda rd,rs subb rbd,@rs xorb rbd,addr 26697 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 26698 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 26699 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 26700 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 26701 sdll rrd,rs subl rrd,@rs 26702 set @rd,imm4 subl rrd,addr 26703 set addr(rd),imm4 subl rrd,addr(rs) 26704 26705 26706File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 26707 2670810 Reporting Bugs 26709***************** 26710 26711Your bug reports play an essential role in making ‘as’ reliable. 26712 26713 Reporting a bug may help you by bringing a solution to your problem, 26714or it may not. But in any case the principal function of a bug report 26715is to help the entire community by making the next version of ‘as’ work 26716better. Bug reports are your contribution to the maintenance of ‘as’. 26717 26718 In order for a bug report to serve its purpose, you must include the 26719information that enables us to fix the bug. 26720 26721* Menu: 26722 26723* Bug Criteria:: Have you found a bug? 26724* Bug Reporting:: How to report bugs 26725 26726 26727File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 26728 2672910.1 Have You Found a Bug? 26730========================== 26731 26732If you are not sure whether you have found a bug, here are some 26733guidelines: 26734 26735 • If the assembler gets a fatal signal, for any input whatever, that 26736 is a ‘as’ bug. Reliable assemblers never crash. 26737 26738 • If ‘as’ produces an error message for valid input, that is a bug. 26739 26740 • If ‘as’ does not produce an error message for invalid input, that 26741 is a bug. However, you should note that your idea of “invalid 26742 input” might be our idea of “an extension” or “support for 26743 traditional practice”. 26744 26745 • If you are an experienced user of assemblers, your suggestions for 26746 improvement of ‘as’ are welcome in any case. 26747 26748 26749File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 26750 2675110.2 How to Report Bugs 26752======================= 26753 26754A number of companies and individuals offer support for GNU products. 26755If you obtained ‘as’ from a support organization, we recommend you 26756contact that organization first. 26757 26758 You can find contact information for many support companies and 26759individuals in the file ‘etc/SERVICE’ in the GNU Emacs distribution. 26760 26761 In any event, we also recommend that you send bug reports for ‘as’ to 26762<https://sourceware.org/bugzilla/>. 26763 26764 The fundamental principle of reporting bugs usefully is this: *report 26765all the facts*. If you are not sure whether to state a fact or leave it 26766out, state it! 26767 26768 Often people omit facts because they think they know what causes the 26769problem and assume that some details do not matter. Thus, you might 26770assume that the name of a symbol you use in an example does not matter. 26771Well, probably it does not, but one cannot be sure. Perhaps the bug is 26772a stray memory reference which happens to fetch from the location where 26773that name is stored in memory; perhaps, if the name were different, the 26774contents of that location would fool the assembler into doing the right 26775thing despite the bug. Play it safe and give a specific, complete 26776example. That is the easiest thing for you to do, and the most helpful. 26777 26778 Keep in mind that the purpose of a bug report is to enable us to fix 26779the bug if it is new to us. Therefore, always write your bug reports on 26780the assumption that the bug has not been reported previously. 26781 26782 Sometimes people give a few sketchy facts and ask, “Does this ring a 26783bell?” This cannot help us fix a bug, so it is basically useless. We 26784respond by asking for enough details to enable us to investigate. You 26785might as well expedite matters by sending them to begin with. 26786 26787 To enable us to fix the bug, you should include all these things: 26788 26789 • The version of ‘as’. ‘as’ announces it if you start it with the 26790 ‘--version’ argument. 26791 26792 Without this, we will not know whether there is any point in 26793 looking for the bug in the current version of ‘as’. 26794 26795 • Any patches you may have applied to the ‘as’ source. 26796 26797 • The type of machine you are using, and the operating system name 26798 and version number. 26799 26800 • What compiler (and its version) was used to compile ‘as’—e.g. 26801 “‘gcc-2.7’”. 26802 26803 • The command arguments you gave the assembler to assemble your 26804 example and observe the bug. To guarantee you will not omit 26805 something important, list them all. A copy of the Makefile (or the 26806 output from make) is sufficient. 26807 26808 If we were to try to guess the arguments, we would probably guess 26809 wrong and then we might not encounter the bug. 26810 26811 • A complete input file that will reproduce the bug. If the bug is 26812 observed when the assembler is invoked via a compiler, send the 26813 assembler source, not the high level language source. Most 26814 compilers will produce the assembler source when run with the ‘-S’ 26815 option. If you are using ‘gcc’, use the options ‘-v --save-temps’; 26816 this will save the assembler source in a file with an extension of 26817 ‘.s’, and also show you exactly how ‘as’ is being run. 26818 26819 • A description of what behavior you observe that you believe is 26820 incorrect. For example, “It gets a fatal signal.” 26821 26822 Of course, if the bug is that ‘as’ gets a fatal signal, then we 26823 will certainly notice it. But if the bug is incorrect output, we 26824 might not notice unless it is glaringly wrong. You might as well 26825 not give us a chance to make a mistake. 26826 26827 Even if the problem you experience is a fatal signal, you should 26828 still say so explicitly. Suppose something strange is going on, 26829 such as, your copy of ‘as’ is out of sync, or you have encountered 26830 a bug in the C library on your system. (This has happened!) Your 26831 copy might crash and ours would not. If you told us to expect a 26832 crash, then when ours fails to crash, we would know that the bug 26833 was not happening for us. If you had not told us to expect a 26834 crash, then we would not be able to draw any conclusion from our 26835 observations. 26836 26837 • If you wish to suggest changes to the ‘as’ source, send us context 26838 diffs, as generated by ‘diff’ with the ‘-u’, ‘-c’, or ‘-p’ option. 26839 Always send diffs from the old file to the new file. If you even 26840 discuss something in the ‘as’ source, refer to it by context, not 26841 by line number. 26842 26843 The line numbers in our development sources will not match those in 26844 your sources. Your line numbers would convey no useful information 26845 to us. 26846 26847 Here are some things that are not necessary: 26848 26849 • A description of the envelope of the bug. 26850 26851 Often people who encounter a bug spend a lot of time investigating 26852 which changes to the input file will make the bug go away and which 26853 changes will not affect it. 26854 26855 This is often time consuming and not very useful, because the way 26856 we will find the bug is by running a single example under the 26857 debugger with breakpoints, not by pure deduction from a series of 26858 examples. We recommend that you save your time for something else. 26859 26860 Of course, if you can find a simpler example to report _instead_ of 26861 the original one, that is a convenience for us. Errors in the 26862 output will be easier to spot, running under the debugger will take 26863 less time, and so on. 26864 26865 However, simplification is not vital; if you do not want to do 26866 this, report the bug anyway and send us the entire test case you 26867 used. 26868 26869 • A patch for the bug. 26870 26871 A patch for the bug does help us if it is a good one. But do not 26872 omit the necessary information, such as the test case, on the 26873 assumption that a patch is all we need. We might see problems with 26874 your patch and decide to fix the problem another way, or we might 26875 not understand it at all. 26876 26877 Sometimes with a program as complicated as ‘as’ it is very hard to 26878 construct an example that will make the program follow a certain 26879 path through the code. If you do not send us the example, we will 26880 not be able to construct one, so we will not be able to verify that 26881 the bug is fixed. 26882 26883 And if we cannot understand what bug you are trying to fix, or why 26884 your patch should be an improvement, we will not install it. A 26885 test case will help us to understand. 26886 26887 • A guess about what the bug is or what it depends on. 26888 26889 Such guesses are usually wrong. Even we cannot guess right about 26890 such things without first using the debugger to find the facts. 26891 26892 26893File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 26894 2689511 Acknowledgements 26896******************* 26897 26898If you have contributed to GAS and your name isn’t listed here, it is 26899not meant as a slight. We just don’t know about it. Send mail to the 26900maintainer, and we’ll correct the situation. Currently the maintainer 26901is Nick Clifton (email address ‘nickc@redhat.com’). 26902 26903 Dean Elsner wrote the original GNU assembler for the VAX.(1) 26904 26905 Jay Fenlason maintained GAS for a while, adding support for 26906GDB-specific debug information and the 68k series machines, most of the 26907preprocessing pass, and extensive changes in ‘messages.c’, 26908‘input-file.c’, ‘write.c’. 26909 26910 K. Richard Pixley maintained GAS for a while, adding various 26911enhancements and many bug fixes, including merging support for several 26912processors, breaking GAS up to handle multiple object file format back 26913ends (including heavy rewrite, testing, an integration of the coff and 26914b.out back ends), adding configuration including heavy testing and 26915verification of cross assemblers and file splits and renaming, converted 26916GAS to strictly ANSI C including full prototypes, added support for 26917m680[34]0 and cpu32, did considerable work on i960 including a COFF port 26918(including considerable amounts of reverse engineering), a SPARC opcode 26919file rewrite, DECstation, rs6000, and hp300hpux host ports, updated 26920“know” assertions and made them work, much other reorganization, 26921cleanup, and lint. 26922 26923 Ken Raeburn wrote the high-level BFD interface code to replace most 26924of the code in format-specific I/O modules. 26925 26926 The original VMS support was contributed by David L. Kashtan. Eric 26927Youngdale has done much work with it since. 26928 26929 The Intel 80386 machine description was written by Eliot Dresselhaus. 26930 26931 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 26932 26933 The Motorola 88k machine description was contributed by Devon Bowen 26934of Buffalo University and Torbjorn Granlund of the Swedish Institute of 26935Computer Science. 26936 26937 Keith Knowles at the Open Software Foundation wrote the original MIPS 26938back end (‘tc-mips.c’, ‘tc-mips.h’), and contributed Rose format support 26939(which hasn’t been merged in yet). Ralph Campbell worked with the MIPS 26940code to support a.out format. 26941 26942 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 26943tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 26944Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 26945end to use BFD for some low-level operations, for use with the H8/300 26946and AMD 29k targets. 26947 26948 John Gilmore built the AMD 29000 support, added ‘.include’ support, 26949and simplified the configuration of which versions accept which 26950directives. He updated the 68k machine description so that Motorola’s 26951opcodes always produced fixed-size instructions (e.g., ‘jsr’), while 26952synthetic instructions remained shrinkable (‘jbsr’). John fixed many 26953bugs, including true tested cross-compilation support, and one bug in 26954relaxation that took a week and required the proverbial one-bit fix. 26955 26956 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax 26957for the 68k, completed support for some COFF targets (68k, i386 SVR3, 26958and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the 26959initial RS/6000 and PowerPC assembler, and made a few other minor 26960patches. 26961 26962 Steve Chamberlain made GAS able to generate listings. 26963 26964 Hewlett-Packard contributed support for the HP9000/300. 26965 26966 Jeff Law wrote GAS and BFD support for the native HPPA object format 26967(SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF 26968object formats). This work was supported by both the Center for 26969Software Science at the University of Utah and Cygnus Support. 26970 26971 Support for ELF format files has been worked on by Mark Eichin of 26972Cygnus Support (original, incomplete implementation for SPARC), Pete 26973Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael 26974Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn 26975of Cygnus Support (sparc, and some initial 64-bit support). 26976 26977 Linas Vepstas added GAS support for the ESA/390 “IBM 370” 26978architecture. 26979 26980 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 26981GAS and BFD support for openVMS/Alpha. 26982 26983 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 26984various tic* flavors. 26985 26986 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 26987Tensilica, Inc. added support for Xtensa processors. 26988 26989 Several engineers at Cygnus Support have also provided many small bug 26990fixes and configuration enhancements. 26991 26992 Jon Beniston added support for the Lattice Mico32 architecture. 26993 26994 Many others have contributed large or small bugfixes and 26995enhancements. If you have contributed significant work and are not 26996mentioned on this list, and want to be, let us know. Some of the 26997history has been lost; we are not intentionally leaving anyone out. 26998 26999 ---------- Footnotes ---------- 27000 27001 (1) Any more details? 27002 27003 27004File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 27005 27006Appendix A GNU Free Documentation License 27007***************************************** 27008 27009 Version 1.3, 3 November 2008 27010 27011 Copyright © 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 27012 <http://fsf.org/> 27013 27014 Everyone is permitted to copy and distribute verbatim copies 27015 of this license document, but changing it is not allowed. 27016 27017 0. PREAMBLE 27018 27019 The purpose of this License is to make a manual, textbook, or other 27020 functional and useful document “free” in the sense of freedom: to 27021 assure everyone the effective freedom to copy and redistribute it, 27022 with or without modifying it, either commercially or 27023 noncommercially. Secondarily, this License preserves for the 27024 author and publisher a way to get credit for their work, while not 27025 being considered responsible for modifications made by others. 27026 27027 This License is a kind of “copyleft”, which means that derivative 27028 works of the document must themselves be free in the same sense. 27029 It complements the GNU General Public License, which is a copyleft 27030 license designed for free software. 27031 27032 We have designed this License in order to use it for manuals for 27033 free software, because free software needs free documentation: a 27034 free program should come with manuals providing the same freedoms 27035 that the software does. But this License is not limited to 27036 software manuals; it can be used for any textual work, regardless 27037 of subject matter or whether it is published as a printed book. We 27038 recommend this License principally for works whose purpose is 27039 instruction or reference. 27040 27041 1. APPLICABILITY AND DEFINITIONS 27042 27043 This License applies to any manual or other work, in any medium, 27044 that contains a notice placed by the copyright holder saying it can 27045 be distributed under the terms of this License. Such a notice 27046 grants a world-wide, royalty-free license, unlimited in duration, 27047 to use that work under the conditions stated herein. The 27048 “Document”, below, refers to any such manual or work. Any member 27049 of the public is a licensee, and is addressed as “you”. You accept 27050 the license if you copy, modify or distribute the work in a way 27051 requiring permission under copyright law. 27052 27053 A “Modified Version” of the Document means any work containing the 27054 Document or a portion of it, either copied verbatim, or with 27055 modifications and/or translated into another language. 27056 27057 A “Secondary Section” is a named appendix or a front-matter section 27058 of the Document that deals exclusively with the relationship of the 27059 publishers or authors of the Document to the Document’s overall 27060 subject (or to related matters) and contains nothing that could 27061 fall directly within that overall subject. (Thus, if the Document 27062 is in part a textbook of mathematics, a Secondary Section may not 27063 explain any mathematics.) The relationship could be a matter of 27064 historical connection with the subject or with related matters, or 27065 of legal, commercial, philosophical, ethical or political position 27066 regarding them. 27067 27068 The “Invariant Sections” are certain Secondary Sections whose 27069 titles are designated, as being those of Invariant Sections, in the 27070 notice that says that the Document is released under this License. 27071 If a section does not fit the above definition of Secondary then it 27072 is not allowed to be designated as Invariant. The Document may 27073 contain zero Invariant Sections. If the Document does not identify 27074 any Invariant Sections then there are none. 27075 27076 The “Cover Texts” are certain short passages of text that are 27077 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 27078 that says that the Document is released under this License. A 27079 Front-Cover Text may be at most 5 words, and a Back-Cover Text may 27080 be at most 25 words. 27081 27082 A “Transparent” copy of the Document means a machine-readable copy, 27083 represented in a format whose specification is available to the 27084 general public, that is suitable for revising the document 27085 straightforwardly with generic text editors or (for images composed 27086 of pixels) generic paint programs or (for drawings) some widely 27087 available drawing editor, and that is suitable for input to text 27088 formatters or for automatic translation to a variety of formats 27089 suitable for input to text formatters. A copy made in an otherwise 27090 Transparent file format whose markup, or absence of markup, has 27091 been arranged to thwart or discourage subsequent modification by 27092 readers is not Transparent. An image format is not Transparent if 27093 used for any substantial amount of text. A copy that is not 27094 “Transparent” is called “Opaque”. 27095 27096 Examples of suitable formats for Transparent copies include plain 27097 ASCII without markup, Texinfo input format, LaTeX input format, 27098 SGML or XML using a publicly available DTD, and standard-conforming 27099 simple HTML, PostScript or PDF designed for human modification. 27100 Examples of transparent image formats include PNG, XCF and JPG. 27101 Opaque formats include proprietary formats that can be read and 27102 edited only by proprietary word processors, SGML or XML for which 27103 the DTD and/or processing tools are not generally available, and 27104 the machine-generated HTML, PostScript or PDF produced by some word 27105 processors for output purposes only. 27106 27107 The “Title Page” means, for a printed book, the title page itself, 27108 plus such following pages as are needed to hold, legibly, the 27109 material this License requires to appear in the title page. For 27110 works in formats which do not have any title page as such, “Title 27111 Page” means the text near the most prominent appearance of the 27112 work’s title, preceding the beginning of the body of the text. 27113 27114 The “publisher” means any person or entity that distributes copies 27115 of the Document to the public. 27116 27117 A section “Entitled XYZ” means a named subunit of the Document 27118 whose title either is precisely XYZ or contains XYZ in parentheses 27119 following text that translates XYZ in another language. (Here XYZ 27120 stands for a specific section name mentioned below, such as 27121 “Acknowledgements”, “Dedications”, “Endorsements”, or “History”.) 27122 To “Preserve the Title” of such a section when you modify the 27123 Document means that it remains a section “Entitled XYZ” according 27124 to this definition. 27125 27126 The Document may include Warranty Disclaimers next to the notice 27127 which states that this License applies to the Document. These 27128 Warranty Disclaimers are considered to be included by reference in 27129 this License, but only as regards disclaiming warranties: any other 27130 implication that these Warranty Disclaimers may have is void and 27131 has no effect on the meaning of this License. 27132 27133 2. VERBATIM COPYING 27134 27135 You may copy and distribute the Document in any medium, either 27136 commercially or noncommercially, provided that this License, the 27137 copyright notices, and the license notice saying this License 27138 applies to the Document are reproduced in all copies, and that you 27139 add no other conditions whatsoever to those of this License. You 27140 may not use technical measures to obstruct or control the reading 27141 or further copying of the copies you make or distribute. However, 27142 you may accept compensation in exchange for copies. If you 27143 distribute a large enough number of copies you must also follow the 27144 conditions in section 3. 27145 27146 You may also lend copies, under the same conditions stated above, 27147 and you may publicly display copies. 27148 27149 3. COPYING IN QUANTITY 27150 27151 If you publish printed copies (or copies in media that commonly 27152 have printed covers) of the Document, numbering more than 100, and 27153 the Document’s license notice requires Cover Texts, you must 27154 enclose the copies in covers that carry, clearly and legibly, all 27155 these Cover Texts: Front-Cover Texts on the front cover, and 27156 Back-Cover Texts on the back cover. Both covers must also clearly 27157 and legibly identify you as the publisher of these copies. The 27158 front cover must present the full title with all words of the title 27159 equally prominent and visible. You may add other material on the 27160 covers in addition. Copying with changes limited to the covers, as 27161 long as they preserve the title of the Document and satisfy these 27162 conditions, can be treated as verbatim copying in other respects. 27163 27164 If the required texts for either cover are too voluminous to fit 27165 legibly, you should put the first ones listed (as many as fit 27166 reasonably) on the actual cover, and continue the rest onto 27167 adjacent pages. 27168 27169 If you publish or distribute Opaque copies of the Document 27170 numbering more than 100, you must either include a machine-readable 27171 Transparent copy along with each Opaque copy, or state in or with 27172 each Opaque copy a computer-network location from which the general 27173 network-using public has access to download using public-standard 27174 network protocols a complete Transparent copy of the Document, free 27175 of added material. If you use the latter option, you must take 27176 reasonably prudent steps, when you begin distribution of Opaque 27177 copies in quantity, to ensure that this Transparent copy will 27178 remain thus accessible at the stated location until at least one 27179 year after the last time you distribute an Opaque copy (directly or 27180 through your agents or retailers) of that edition to the public. 27181 27182 It is requested, but not required, that you contact the authors of 27183 the Document well before redistributing any large number of copies, 27184 to give them a chance to provide you with an updated version of the 27185 Document. 27186 27187 4. MODIFICATIONS 27188 27189 You may copy and distribute a Modified Version of the Document 27190 under the conditions of sections 2 and 3 above, provided that you 27191 release the Modified Version under precisely this License, with the 27192 Modified Version filling the role of the Document, thus licensing 27193 distribution and modification of the Modified Version to whoever 27194 possesses a copy of it. In addition, you must do these things in 27195 the Modified Version: 27196 27197 A. Use in the Title Page (and on the covers, if any) a title 27198 distinct from that of the Document, and from those of previous 27199 versions (which should, if there were any, be listed in the 27200 History section of the Document). You may use the same title 27201 as a previous version if the original publisher of that 27202 version gives permission. 27203 27204 B. List on the Title Page, as authors, one or more persons or 27205 entities responsible for authorship of the modifications in 27206 the Modified Version, together with at least five of the 27207 principal authors of the Document (all of its principal 27208 authors, if it has fewer than five), unless they release you 27209 from this requirement. 27210 27211 C. State on the Title page the name of the publisher of the 27212 Modified Version, as the publisher. 27213 27214 D. Preserve all the copyright notices of the Document. 27215 27216 E. Add an appropriate copyright notice for your modifications 27217 adjacent to the other copyright notices. 27218 27219 F. Include, immediately after the copyright notices, a license 27220 notice giving the public permission to use the Modified 27221 Version under the terms of this License, in the form shown in 27222 the Addendum below. 27223 27224 G. Preserve in that license notice the full lists of Invariant 27225 Sections and required Cover Texts given in the Document’s 27226 license notice. 27227 27228 H. Include an unaltered copy of this License. 27229 27230 I. Preserve the section Entitled “History”, Preserve its Title, 27231 and add to it an item stating at least the title, year, new 27232 authors, and publisher of the Modified Version as given on the 27233 Title Page. If there is no section Entitled “History” in the 27234 Document, create one stating the title, year, authors, and 27235 publisher of the Document as given on its Title Page, then add 27236 an item describing the Modified Version as stated in the 27237 previous sentence. 27238 27239 J. Preserve the network location, if any, given in the Document 27240 for public access to a Transparent copy of the Document, and 27241 likewise the network locations given in the Document for 27242 previous versions it was based on. These may be placed in the 27243 “History” section. You may omit a network location for a work 27244 that was published at least four years before the Document 27245 itself, or if the original publisher of the version it refers 27246 to gives permission. 27247 27248 K. For any section Entitled “Acknowledgements” or “Dedications”, 27249 Preserve the Title of the section, and preserve in the section 27250 all the substance and tone of each of the contributor 27251 acknowledgements and/or dedications given therein. 27252 27253 L. Preserve all the Invariant Sections of the Document, unaltered 27254 in their text and in their titles. Section numbers or the 27255 equivalent are not considered part of the section titles. 27256 27257 M. Delete any section Entitled “Endorsements”. Such a section 27258 may not be included in the Modified Version. 27259 27260 N. Do not retitle any existing section to be Entitled 27261 “Endorsements” or to conflict in title with any Invariant 27262 Section. 27263 27264 O. Preserve any Warranty Disclaimers. 27265 27266 If the Modified Version includes new front-matter sections or 27267 appendices that qualify as Secondary Sections and contain no 27268 material copied from the Document, you may at your option designate 27269 some or all of these sections as invariant. To do this, add their 27270 titles to the list of Invariant Sections in the Modified Version’s 27271 license notice. These titles must be distinct from any other 27272 section titles. 27273 27274 You may add a section Entitled “Endorsements”, provided it contains 27275 nothing but endorsements of your Modified Version by various 27276 parties—for example, statements of peer review or that the text has 27277 been approved by an organization as the authoritative definition of 27278 a standard. 27279 27280 You may add a passage of up to five words as a Front-Cover Text, 27281 and a passage of up to 25 words as a Back-Cover Text, to the end of 27282 the list of Cover Texts in the Modified Version. Only one passage 27283 of Front-Cover Text and one of Back-Cover Text may be added by (or 27284 through arrangements made by) any one entity. If the Document 27285 already includes a cover text for the same cover, previously added 27286 by you or by arrangement made by the same entity you are acting on 27287 behalf of, you may not add another; but you may replace the old 27288 one, on explicit permission from the previous publisher that added 27289 the old one. 27290 27291 The author(s) and publisher(s) of the Document do not by this 27292 License give permission to use their names for publicity for or to 27293 assert or imply endorsement of any Modified Version. 27294 27295 5. COMBINING DOCUMENTS 27296 27297 You may combine the Document with other documents released under 27298 this License, under the terms defined in section 4 above for 27299 modified versions, provided that you include in the combination all 27300 of the Invariant Sections of all of the original documents, 27301 unmodified, and list them all as Invariant Sections of your 27302 combined work in its license notice, and that you preserve all 27303 their Warranty Disclaimers. 27304 27305 The combined work need only contain one copy of this License, and 27306 multiple identical Invariant Sections may be replaced with a single 27307 copy. If there are multiple Invariant Sections with the same name 27308 but different contents, make the title of each such section unique 27309 by adding at the end of it, in parentheses, the name of the 27310 original author or publisher of that section if known, or else a 27311 unique number. Make the same adjustment to the section titles in 27312 the list of Invariant Sections in the license notice of the 27313 combined work. 27314 27315 In the combination, you must combine any sections Entitled 27316 “History” in the various original documents, forming one section 27317 Entitled “History”; likewise combine any sections Entitled 27318 “Acknowledgements”, and any sections Entitled “Dedications”. You 27319 must delete all sections Entitled “Endorsements.” 27320 27321 6. COLLECTIONS OF DOCUMENTS 27322 27323 You may make a collection consisting of the Document and other 27324 documents released under this License, and replace the individual 27325 copies of this License in the various documents with a single copy 27326 that is included in the collection, provided that you follow the 27327 rules of this License for verbatim copying of each of the documents 27328 in all other respects. 27329 27330 You may extract a single document from such a collection, and 27331 distribute it individually under this License, provided you insert 27332 a copy of this License into the extracted document, and follow this 27333 License in all other respects regarding verbatim copying of that 27334 document. 27335 27336 7. AGGREGATION WITH INDEPENDENT WORKS 27337 27338 A compilation of the Document or its derivatives with other 27339 separate and independent documents or works, in or on a volume of a 27340 storage or distribution medium, is called an “aggregate” if the 27341 copyright resulting from the compilation is not used to limit the 27342 legal rights of the compilation’s users beyond what the individual 27343 works permit. When the Document is included in an aggregate, this 27344 License does not apply to the other works in the aggregate which 27345 are not themselves derivative works of the Document. 27346 27347 If the Cover Text requirement of section 3 is applicable to these 27348 copies of the Document, then if the Document is less than one half 27349 of the entire aggregate, the Document’s Cover Texts may be placed 27350 on covers that bracket the Document within the aggregate, or the 27351 electronic equivalent of covers if the Document is in electronic 27352 form. Otherwise they must appear on printed covers that bracket 27353 the whole aggregate. 27354 27355 8. TRANSLATION 27356 27357 Translation is considered a kind of modification, so you may 27358 distribute translations of the Document under the terms of section 27359 4. Replacing Invariant Sections with translations requires special 27360 permission from their copyright holders, but you may include 27361 translations of some or all Invariant Sections in addition to the 27362 original versions of these Invariant Sections. You may include a 27363 translation of this License, and all the license notices in the 27364 Document, and any Warranty Disclaimers, provided that you also 27365 include the original English version of this License and the 27366 original versions of those notices and disclaimers. In case of a 27367 disagreement between the translation and the original version of 27368 this License or a notice or disclaimer, the original version will 27369 prevail. 27370 27371 If a section in the Document is Entitled “Acknowledgements”, 27372 “Dedications”, or “History”, the requirement (section 4) to 27373 Preserve its Title (section 1) will typically require changing the 27374 actual title. 27375 27376 9. TERMINATION 27377 27378 You may not copy, modify, sublicense, or distribute the Document 27379 except as expressly provided under this License. Any attempt 27380 otherwise to copy, modify, sublicense, or distribute it is void, 27381 and will automatically terminate your rights under this License. 27382 27383 However, if you cease all violation of this License, then your 27384 license from a particular copyright holder is reinstated (a) 27385 provisionally, unless and until the copyright holder explicitly and 27386 finally terminates your license, and (b) permanently, if the 27387 copyright holder fails to notify you of the violation by some 27388 reasonable means prior to 60 days after the cessation. 27389 27390 Moreover, your license from a particular copyright holder is 27391 reinstated permanently if the copyright holder notifies you of the 27392 violation by some reasonable means, this is the first time you have 27393 received notice of violation of this License (for any work) from 27394 that copyright holder, and you cure the violation prior to 30 days 27395 after your receipt of the notice. 27396 27397 Termination of your rights under this section does not terminate 27398 the licenses of parties who have received copies or rights from you 27399 under this License. If your rights have been terminated and not 27400 permanently reinstated, receipt of a copy of some or all of the 27401 same material does not give you any rights to use it. 27402 27403 10. FUTURE REVISIONS OF THIS LICENSE 27404 27405 The Free Software Foundation may publish new, revised versions of 27406 the GNU Free Documentation License from time to time. Such new 27407 versions will be similar in spirit to the present version, but may 27408 differ in detail to address new problems or concerns. See 27409 <http://www.gnu.org/copyleft/>. 27410 27411 Each version of the License is given a distinguishing version 27412 number. If the Document specifies that a particular numbered 27413 version of this License “or any later version” applies to it, you 27414 have the option of following the terms and conditions either of 27415 that specified version or of any later version that has been 27416 published (not as a draft) by the Free Software Foundation. If the 27417 Document does not specify a version number of this License, you may 27418 choose any version ever published (not as a draft) by the Free 27419 Software Foundation. If the Document specifies that a proxy can 27420 decide which future versions of this License can be used, that 27421 proxy’s public statement of acceptance of a version permanently 27422 authorizes you to choose that version for the Document. 27423 27424 11. RELICENSING 27425 27426 “Massive Multiauthor Collaboration Site” (or “MMC Site”) means any 27427 World Wide Web server that publishes copyrightable works and also 27428 provides prominent facilities for anybody to edit those works. A 27429 public wiki that anybody can edit is an example of such a server. 27430 A “Massive Multiauthor Collaboration” (or “MMC”) contained in the 27431 site means any set of copyrightable works thus published on the MMC 27432 site. 27433 27434 “CC-BY-SA” means the Creative Commons Attribution-Share Alike 3.0 27435 license published by Creative Commons Corporation, a not-for-profit 27436 corporation with a principal place of business in San Francisco, 27437 California, as well as future copyleft versions of that license 27438 published by that same organization. 27439 27440 “Incorporate” means to publish or republish a Document, in whole or 27441 in part, as part of another Document. 27442 27443 An MMC is “eligible for relicensing” if it is licensed under this 27444 License, and if all works that were first published under this 27445 License somewhere other than this MMC, and subsequently 27446 incorporated in whole or in part into the MMC, (1) had no cover 27447 texts or invariant sections, and (2) were thus incorporated prior 27448 to November 1, 2008. 27449 27450 The operator of an MMC Site may republish an MMC contained in the 27451 site under CC-BY-SA on the same site at any time before August 1, 27452 2009, provided the MMC is eligible for relicensing. 27453 27454ADDENDUM: How to use this License for your documents 27455==================================================== 27456 27457To use this License in a document you have written, include a copy of 27458the License in the document and put the following copyright and license 27459notices just after the title page: 27460 27461 Copyright (C) YEAR YOUR NAME. 27462 Permission is granted to copy, distribute and/or modify this document 27463 under the terms of the GNU Free Documentation License, Version 1.3 27464 or any later version published by the Free Software Foundation; 27465 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover 27466 Texts. A copy of the license is included in the section entitled ``GNU 27467 Free Documentation License''. 27468 27469 If you have Invariant Sections, Front-Cover Texts and Back-Cover 27470Texts, replace the “with...Texts.” line with this: 27471 27472 with the Invariant Sections being LIST THEIR TITLES, with 27473 the Front-Cover Texts being LIST, and with the Back-Cover Texts 27474 being LIST. 27475 27476 If you have Invariant Sections without Cover Texts, or some other 27477combination of the three, merge those two alternatives to suit the 27478situation. 27479 27480 If your document contains nontrivial examples of program code, we 27481recommend releasing these examples in parallel under your choice of free 27482software license, such as the GNU General Public License, to permit 27483their use in free software. 27484 27485 27486File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 27487 27488AS Index 27489******** 27490 27491�[index�] 27492* Menu: 27493 27494* \" (doublequote character): Strings. (line 43) 27495* \b (backspace character): Strings. (line 15) 27496* \DDD (octal character code): Strings. (line 30) 27497* \f (formfeed character): Strings. (line 18) 27498* \n (newline character): Strings. (line 21) 27499* \r (carriage return character): Strings. (line 24) 27500* \t (tab): Strings. (line 27) 27501* \XD... (hex character code): Strings. (line 36) 27502* \\ (\ character): Strings. (line 40) 27503* #: Comments. (line 33) 27504* #APP: Preprocessing. (line 28) 27505* #NO_APP: Preprocessing. (line 28) 27506* $ in symbol names: D10V-Chars. (line 46) 27507* $ in symbol names <1>: D30V-Chars. (line 70) 27508* $ in symbol names <2>: Meta-Chars. (line 10) 27509* $ in symbol names <3>: SH-Chars. (line 15) 27510* $a: ARM Mapping Symbols. 27511 (line 9) 27512* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 27513* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 27514* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 27515* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 27516* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 27517* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 27518* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 27519* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 27520* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 27521* $d: AArch64 Mapping Symbols. 27522 (line 12) 27523* $d <1>: ARM Mapping Symbols. 27524 (line 15) 27525* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 27526* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 27527* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 27528* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 27529* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 27530* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 27531* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 27532* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 27533* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 27534* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 27535* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 27536* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 27537* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 27538* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 27539* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 27540* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 27541* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 27542* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 27543* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 27544* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 27545* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 27546* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 27547* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 27548* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 27549* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 27550* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 27551* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 27552* $t: ARM Mapping Symbols. 27553 (line 12) 27554* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 27555* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 27556* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 27557* $x: AArch64 Mapping Symbols. 27558 (line 9) 27559* %gp: RX-Modifiers. (line 6) 27560* %gpreg: RX-Modifiers. (line 22) 27561* %pidreg: RX-Modifiers. (line 25) 27562* -+ option, VAX/VMS: VAX-Opts. (line 71) 27563* --: Command Line. (line 10) 27564* --32 option, i386: i386-Options. (line 8) 27565* --32 option, x86-64: i386-Options. (line 8) 27566* --64 option, i386: i386-Options. (line 8) 27567* --64 option, x86-64: i386-Options. (line 8) 27568* --abi-call0: Xtensa Options. (line 82) 27569* --abi-windowed: Xtensa Options. (line 82) 27570* --absolute-literals: Xtensa Options. (line 39) 27571* --all-sfr option, KVX: KVX Options. (line 39) 27572* --allow-reg-prefix: SH Options. (line 9) 27573* --alternate: alternate. (line 6) 27574* --auto-litpools: Xtensa Options. (line 22) 27575* --base-size-default-16: M68K-Opts. (line 66) 27576* --base-size-default-32: M68K-Opts. (line 66) 27577* --big: SH Options. (line 9) 27578* --bitwise-or option, M680x0: M68K-Opts. (line 59) 27579* --check-resources option, KVX: KVX Options. (line 12) 27580* --compress-debug-sections= option: Overview. (line 399) 27581* --diagnostics option, KVX: KVX Options. (line 45) 27582* --disp-size-default-16: M68K-Opts. (line 75) 27583* --disp-size-default-32: M68K-Opts. (line 75) 27584* --divide option, i386: i386-Options. (line 25) 27585* --dsp: SH Options. (line 9) 27586* --dump-insn option, KVX: KVX Options. (line 6) 27587* --dump-table option, KVX: KVX Options. (line 27) 27588* --emulation=crisaout command-line option, CRIS: CRIS-Opts. (line 9) 27589* --emulation=criself command-line option, CRIS: CRIS-Opts. (line 9) 27590* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 27591* --fatal-warnings: W. (line 16) 27592* --fdpic: SH Options. (line 31) 27593* --fix-v4bx command-line option, ARM: ARM Options. (line 439) 27594* --fixed-special-register-names command-line option, MMIX: MMIX-Opts. 27595 (line 8) 27596* --force-long-branches: M68HC11-Opts. (line 81) 27597* --generate-example: M68HC11-Opts. (line 98) 27598* --generate-illegal-code option, KVX: KVX Options. (line 20) 27599* --globalize-symbols command-line option, MMIX: MMIX-Opts. (line 12) 27600* --gnu-syntax command-line option, MMIX: MMIX-Opts. (line 16) 27601* --linker-allocated-gregs command-line option, MMIX: MMIX-Opts. 27602 (line 67) 27603* --listing-cont-lines: listing. (line 34) 27604* --listing-lhs-width: listing. (line 16) 27605* --listing-lhs-width2: listing. (line 21) 27606* --listing-rhs-width: listing. (line 28) 27607* --little: SH Options. (line 9) 27608* --longcalls: Xtensa Options. (line 53) 27609* --march=ARCHITECTURE command-line option, CRIS: CRIS-Opts. (line 34) 27610* --MD: MD. (line 6) 27611* --mnopic option, KVX: KVX Options. (line 33) 27612* --mpic option, KVX: KVX Options. (line 30) 27613* --mPIC option, KVX: KVX Options. (line 30) 27614* --mul-bug-abort command-line option, CRIS: CRIS-Opts. (line 63) 27615* --no-absolute-literals: Xtensa Options. (line 39) 27616* --no-auto-litpools: Xtensa Options. (line 22) 27617* --no-check-resources option, KVX: KVX Options. (line 16) 27618* --no-diagnostics option, KVX: KVX Options. (line 48) 27619* --no-expand command-line option, MMIX: MMIX-Opts. (line 31) 27620* --no-longcalls: Xtensa Options. (line 53) 27621* --no-merge-gregs command-line option, MMIX: MMIX-Opts. (line 36) 27622* --no-mul-bug-abort command-line option, CRIS: CRIS-Opts. (line 63) 27623* --no-pad-sections: no-pad-sections. (line 6) 27624* --no-predefined-syms command-line option, MMIX: MMIX-Opts. (line 22) 27625* --no-pushj-stubs command-line option, MMIX: MMIX-Opts. (line 54) 27626* --no-stubs command-line option, MMIX: MMIX-Opts. (line 54) 27627* --no-target-align: Xtensa Options. (line 46) 27628* --no-text-section-literals: Xtensa Options. (line 7) 27629* --no-trampolines: Xtensa Options. (line 74) 27630* --no-transform: Xtensa Options. (line 62) 27631* --no-underscore command-line option, CRIS: CRIS-Opts. (line 15) 27632* --no-warn: W. (line 11) 27633* --pcrel: M68K-Opts. (line 87) 27634* --pic command-line option, CRIS: CRIS-Opts. (line 27) 27635* --print-insn-syntax: M68HC11-Opts. (line 87) 27636* --print-insn-syntax <1>: XGATE-Opts. (line 25) 27637* --print-opcodes: M68HC11-Opts. (line 91) 27638* --print-opcodes <1>: XGATE-Opts. (line 29) 27639* --register-prefix-optional option, M680x0: M68K-Opts. (line 46) 27640* --relax: SH Options. (line 9) 27641* --relax command-line option, MMIX: MMIX-Opts. (line 19) 27642* --rename-section: Xtensa Options. (line 70) 27643* --renesas: SH Options. (line 9) 27644* --sectname-subst: Section. (line 71) 27645* --short-branches: M68HC11-Opts. (line 67) 27646* --small: SH Options. (line 9) 27647* --statistics: statistics. (line 6) 27648* --strict-direct-mode: M68HC11-Opts. (line 57) 27649* --target-align: Xtensa Options. (line 46) 27650* --text-section-literals: Xtensa Options. (line 7) 27651* --traditional-format: traditional-format. (line 6) 27652* --trampolines: Xtensa Options. (line 74) 27653* --transform: Xtensa Options. (line 62) 27654* --underscore command-line option, CRIS: CRIS-Opts. (line 15) 27655* --warn: W. (line 19) 27656* --x32 option, i386: i386-Options. (line 8) 27657* --x32 option, x86-64: i386-Options. (line 8) 27658* --xgate-ramoffset: M68HC11-Opts. (line 36) 27659* -1 option, VAX/VMS: VAX-Opts. (line 77) 27660* -32addr command-line option, Alpha: Alpha Options. (line 57) 27661* -a: a. (line 6) 27662* -ac: a. (line 6) 27663* -ad: a. (line 6) 27664* -ag: a. (line 6) 27665* -ah: a. (line 6) 27666* -al: a. (line 6) 27667* -Aleon: Sparc-Opts. (line 25) 27668* -ali: a. (line 6) 27669* -an: a. (line 6) 27670* -as: a. (line 6) 27671* -Asparc: Sparc-Opts. (line 25) 27672* -Asparcfmaf: Sparc-Opts. (line 25) 27673* -Asparcima: Sparc-Opts. (line 25) 27674* -Asparclet: Sparc-Opts. (line 25) 27675* -Asparclite: Sparc-Opts. (line 25) 27676* -Asparcvis: Sparc-Opts. (line 25) 27677* -Asparcvis2: Sparc-Opts. (line 25) 27678* -Asparcvis3: Sparc-Opts. (line 25) 27679* -Asparcvis3r: Sparc-Opts. (line 25) 27680* -Av6: Sparc-Opts. (line 25) 27681* -Av7: Sparc-Opts. (line 25) 27682* -Av8: Sparc-Opts. (line 25) 27683* -Av9: Sparc-Opts. (line 25) 27684* -Av9a: Sparc-Opts. (line 25) 27685* -Av9b: Sparc-Opts. (line 25) 27686* -Av9c: Sparc-Opts. (line 25) 27687* -Av9d: Sparc-Opts. (line 25) 27688* -Av9e: Sparc-Opts. (line 25) 27689* -Av9m: Sparc-Opts. (line 25) 27690* -Av9v: Sparc-Opts. (line 25) 27691* -big option, M32R: M32R-Opts. (line 35) 27692* -colonless command-line option, Z80: Z80 Options. (line 33) 27693* -D: D. (line 6) 27694* -D, ignored on VAX: VAX-Opts. (line 11) 27695* -d, VAX option: VAX-Opts. (line 16) 27696* -eabi= command-line option, ARM: ARM Options. (line 415) 27697* -EB command-line option, AArch64: AArch64 Options. (line 6) 27698* -EB command-line option, ARC: ARC Options. (line 84) 27699* -EB command-line option, ARM: ARM Options. (line 420) 27700* -EB command-line option, BPF: BPF Options. (line 6) 27701* -EB option (MIPS): MIPS Options. (line 13) 27702* -EB option, M32R: M32R-Opts. (line 39) 27703* -EB option, TILE-Gx: TILE-Gx Options. (line 11) 27704* -EL command-line option, AArch64: AArch64 Options. (line 10) 27705* -EL command-line option, ARC: ARC Options. (line 88) 27706* -EL command-line option, ARM: ARM Options. (line 431) 27707* -EL command-line option, BPF: BPF Options. (line 10) 27708* -EL option (MIPS): MIPS Options. (line 13) 27709* -EL option, M32R: M32R-Opts. (line 32) 27710* -EL option, TILE-Gx: TILE-Gx Options. (line 11) 27711* -f: f. (line 6) 27712* -F command-line option, Alpha: Alpha Options. (line 57) 27713* -fno-pic option, RISC-V: RISC-V-Options. (line 12) 27714* -fp-d command-line option, Z80: Z80 Options. (line 44) 27715* -fp-s command-line option, Z80: Z80 Options. (line 40) 27716* -fpic option, RISC-V: RISC-V-Options. (line 8) 27717* -g command-line option, Alpha: Alpha Options. (line 47) 27718* -G command-line option, Alpha: Alpha Options. (line 53) 27719* -G option (MIPS): MIPS Options. (line 8) 27720* -h option, VAX/VMS: VAX-Opts. (line 45) 27721* -H option, VAX/VMS: VAX-Opts. (line 81) 27722* -I PATH: I. (line 6) 27723* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 27724* -Ip option, M32RX: M32R-Opts. (line 97) 27725* -J, ignored on VAX: VAX-Opts. (line 27) 27726* -K: K. (line 6) 27727* -k command-line option, ARM: ARM Options. (line 435) 27728* -KPIC option, M32R: M32R-Opts. (line 42) 27729* -KPIC option, MIPS: MIPS Options. (line 21) 27730* -L: L. (line 6) 27731* -l option, M680x0: M68K-Opts. (line 34) 27732* -little option, M32R: M32R-Opts. (line 27) 27733* -local-prefix command-line option, Z80: Z80 Options. (line 28) 27734* -M: M. (line 6) 27735* -m11/03: PDP-11-Options. (line 140) 27736* -m11/04: PDP-11-Options. (line 143) 27737* -m11/05: PDP-11-Options. (line 146) 27738* -m11/10: PDP-11-Options. (line 146) 27739* -m11/15: PDP-11-Options. (line 149) 27740* -m11/20: PDP-11-Options. (line 149) 27741* -m11/21: PDP-11-Options. (line 152) 27742* -m11/23: PDP-11-Options. (line 155) 27743* -m11/24: PDP-11-Options. (line 155) 27744* -m11/34: PDP-11-Options. (line 158) 27745* -m11/34a: PDP-11-Options. (line 161) 27746* -m11/35: PDP-11-Options. (line 164) 27747* -m11/40: PDP-11-Options. (line 164) 27748* -m11/44: PDP-11-Options. (line 167) 27749* -m11/45: PDP-11-Options. (line 170) 27750* -m11/50: PDP-11-Options. (line 170) 27751* -m11/53: PDP-11-Options. (line 173) 27752* -m11/55: PDP-11-Options. (line 170) 27753* -m11/60: PDP-11-Options. (line 176) 27754* -m11/70: PDP-11-Options. (line 170) 27755* -m11/73: PDP-11-Options. (line 173) 27756* -m11/83: PDP-11-Options. (line 173) 27757* -m11/84: PDP-11-Options. (line 173) 27758* -m11/93: PDP-11-Options. (line 173) 27759* -m11/94: PDP-11-Options. (line 173) 27760* -m16c option, M16C: M32C-Opts. (line 12) 27761* -m31 option, s390: s390 Options. (line 8) 27762* -m32 option, KVX: KVX Options. (line 36) 27763* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) 27764* -m32bit-doubles: RX-Opts. (line 9) 27765* -m32c option, M32C: M32C-Opts. (line 9) 27766* -m32r option, M32R: M32R-Opts. (line 21) 27767* -m32rx option, M32R2: M32R-Opts. (line 17) 27768* -m32rx option, M32RX: M32R-Opts. (line 9) 27769* -m4byte-align command-line option, V850: V850 Options. (line 90) 27770* -m64 option, s390: s390 Options. (line 8) 27771* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) 27772* -m64bit-doubles: RX-Opts. (line 15) 27773* -m68000 and related options: M68K-Opts. (line 99) 27774* -m68hc11: M68HC11-Opts. (line 9) 27775* -m68hc12: M68HC11-Opts. (line 14) 27776* -m68hcs12: M68HC11-Opts. (line 21) 27777* -m8byte-align command-line option, V850: V850 Options. (line 86) 27778* -mabi= command-line option, AArch64: AArch64 Options. (line 14) 27779* -mabi=ABI option, RISC-V: RISC-V-Options. (line 33) 27780* -madd-bnd-prefix option, i386: i386-Options. (line 163) 27781* -madd-bnd-prefix option, x86-64: i386-Options. (line 163) 27782* -malign-branch-boundary= option, i386: i386-Options. (line 209) 27783* -malign-branch-boundary= option, x86-64: i386-Options. (line 209) 27784* -malign-branch-prefix-size= option, i386: i386-Options. (line 224) 27785* -malign-branch-prefix-size= option, x86-64: i386-Options. (line 224) 27786* -malign-branch= option, i386: i386-Options. (line 216) 27787* -malign-branch= option, x86-64: i386-Options. (line 216) 27788* -mall: PDP-11-Options. (line 26) 27789* -mall-enabled command-line option, LM32: LM32 Options. (line 30) 27790* -mall-extensions: PDP-11-Options. (line 26) 27791* -mall-opcodes command-line option, AVR: AVR Options. (line 111) 27792* -mamd64 option, x86-64: i386-Options. (line 294) 27793* -mapcs-26 command-line option, ARM: ARM Options. (line 387) 27794* -mapcs-32 command-line option, ARM: ARM Options. (line 387) 27795* -mapcs-float command-line option, ARM: ARM Options. (line 401) 27796* -mapcs-reentrant command-line option, ARM: ARM Options. (line 406) 27797* -march option, KVX: KVX Options. (line 9) 27798* -march-attr option, RISC-V: RISC-V-Options. (line 47) 27799* -march= command-line option, AArch64: AArch64 Options. (line 45) 27800* -march= command-line option, ARM: ARM Options. (line 86) 27801* -march= command-line option, M680x0: M68K-Opts. (line 8) 27802* -march= command-line option, TIC6X: TIC6X Options. (line 6) 27803* -march= command-line option, Z80: Z80 Options. (line 6) 27804* -march= option, i386: i386-Options. (line 32) 27805* -march= option, s390: s390 Options. (line 25) 27806* -march= option, x86-64: i386-Options. (line 32) 27807* -march=ISA option, RISC-V: RISC-V-Options. (line 15) 27808* -matpcs command-line option, ARM: ARM Options. (line 393) 27809* -mavxscalar= option, i386: i386-Options. (line 108) 27810* -mavxscalar= option, x86-64: i386-Options. (line 108) 27811* -mbarrel-shift-enabled command-line option, LM32: LM32 Options. 27812 (line 12) 27813* -mbig-endian: RX-Opts. (line 20) 27814* -mbig-endian option, RISC-V: RISC-V-Options. (line 70) 27815* -mbig-obj option, i386: i386-Options. (line 177) 27816* -mbig-obj option, x86-64: i386-Options. (line 177) 27817* -mbranches-within-32B-boundaries option, i386: i386-Options. 27818 (line 229) 27819* -mbranches-within-32B-boundaries option, x86-64: i386-Options. 27820 (line 229) 27821* -mbreak-enabled command-line option, LM32: LM32 Options. (line 27) 27822* -mccs command-line option, ARM: ARM Options. (line 448) 27823* -mcis: PDP-11-Options. (line 32) 27824* -mcode-density command-line option, ARC: ARC Options. (line 93) 27825* -mconstant-gp command-line option, IA-64: IA-64 Options. (line 6) 27826* -mCPU command-line option, Alpha: Alpha Options. (line 6) 27827* -mcpu option, cpu: TIC54X-Opts. (line 15) 27828* -mcpu=: RX-Opts. (line 75) 27829* -mcpu= command-line option, AArch64: AArch64 Options. (line 19) 27830* -mcpu= command-line option, ARM: ARM Options. (line 6) 27831* -mcpu= command-line option, Blackfin: Blackfin Options. (line 6) 27832* -mcpu= command-line option, M680x0: M68K-Opts. (line 14) 27833* -mcpu=CPU command-line option, ARC: ARC Options. (line 10) 27834* -mcsm: PDP-11-Options. (line 43) 27835* -mcsr-check option, RISC-V: RISC-V-Options. (line 59) 27836* -mdcache-enabled command-line option, LM32: LM32 Options. (line 24) 27837* -mdebug command-line option, Alpha: Alpha Options. (line 25) 27838* -mdialect command-line options, BPF: BPF Options. (line 14) 27839* -mdivide-enabled command-line option, LM32: LM32 Options. (line 9) 27840* -mdollar-hex option, dollar-hex: S12Z Options. (line 17) 27841* -mdpfp command-line option, ARC: ARC Options. (line 108) 27842* -mdsbt command-line option, TIC6X: TIC6X Options. (line 13) 27843* -me option, stderr redirect: TIC54X-Opts. (line 20) 27844* -meis: PDP-11-Options. (line 46) 27845* -mepiphany command-line option, Epiphany: Epiphany Options. 27846 (line 9) 27847* -mepiphany16 command-line option, Epiphany: Epiphany Options. 27848 (line 13) 27849* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 27850* -mesa option, s390: s390 Options. (line 17) 27851* -mevexlig= option, i386: i386-Options. (line 129) 27852* -mevexlig= option, x86-64: i386-Options. (line 129) 27853* -mevexrcig= option, i386: i386-Options. (line 284) 27854* -mevexrcig= option, x86-64: i386-Options. (line 284) 27855* -mevexwig= option, i386: i386-Options. (line 139) 27856* -mevexwig= option, x86-64: i386-Options. (line 139) 27857* -mf option, far-mode: TIC54X-Opts. (line 8) 27858* -mf11: PDP-11-Options. (line 122) 27859* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 27860* -mfdpic command-line option, Blackfin: Blackfin Options. (line 19) 27861* -mfence-as-lock-add= option, i386: i386-Options. (line 190) 27862* -mfence-as-lock-add= option, x86-64: i386-Options. (line 190) 27863* -mfis: PDP-11-Options. (line 51) 27864* -mfloat-abi= command-line option, ARM: ARM Options. (line 410) 27865* -mfp-11: PDP-11-Options. (line 56) 27866* -mfp16-format= command-line option: ARM Options. (line 348) 27867* -mfpp: PDP-11-Options. (line 56) 27868* -mfpu: PDP-11-Options. (line 56) 27869* -mfpu= command-line option, ARM: ARM Options. (line 324) 27870* -mfpuda command-line option, ARC: ARC Options. (line 111) 27871* -mgcc-abi: RX-Opts. (line 63) 27872* -mgcc-abi command-line option, V850: V850 Options. (line 79) 27873* -mgcc-isr command-line option, AVR: AVR Options. (line 132) 27874* -mhard-float command-line option, V850: V850 Options. (line 101) 27875* -micache-enabled command-line option, LM32: LM32 Options. (line 21) 27876* -mimplicit-it command-line option, ARM: ARM Options. (line 371) 27877* -mint-register: RX-Opts. (line 57) 27878* -mintel64 option, x86-64: i386-Options. (line 294) 27879* -mip2022 option, IP2K: IP2K-Opts. (line 14) 27880* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 27881* -misa-spec command-line options, BPF: BPF Options. (line 18) 27882* -misa-spec=ISAspec option, RISC-V: RISC-V-Options. (line 21) 27883* -mj11: PDP-11-Options. (line 126) 27884* -mka11: PDP-11-Options. (line 92) 27885* -mkb11: PDP-11-Options. (line 95) 27886* -mkd11a: PDP-11-Options. (line 98) 27887* -mkd11b: PDP-11-Options. (line 101) 27888* -mkd11d: PDP-11-Options. (line 104) 27889* -mkd11e: PDP-11-Options. (line 107) 27890* -mkd11f: PDP-11-Options. (line 110) 27891* -mkd11h: PDP-11-Options. (line 110) 27892* -mkd11k: PDP-11-Options. (line 114) 27893* -mkd11q: PDP-11-Options. (line 110) 27894* -mkd11z: PDP-11-Options. (line 118) 27895* -mkev11: PDP-11-Options. (line 51) 27896* -mkev11 <1>: PDP-11-Options. (line 51) 27897* -mlfence-after-load= option, i386: i386-Options. (line 237) 27898* -mlfence-after-load= option, x86-64: i386-Options. (line 237) 27899* -mlfence-before-indirect-branch= option, i386: i386-Options. 27900 (line 244) 27901* -mlfence-before-indirect-branch= option, x86-64: i386-Options. 27902 (line 244) 27903* -mlfence-before-ret= option, i386: i386-Options. (line 264) 27904* -mlfence-before-ret= option, x86-64: i386-Options. (line 264) 27905* -mlimited-eis: PDP-11-Options. (line 64) 27906* -mlink-relax command-line option, AVR: AVR Options. (line 123) 27907* -mlittle-endian: RX-Opts. (line 26) 27908* -mlittle-endian option, RISC-V: RISC-V-Options. (line 67) 27909* -mlong: M68HC11-Opts. (line 45) 27910* -mlong <1>: XGATE-Opts. (line 13) 27911* -mlong-double: M68HC11-Opts. (line 53) 27912* -mlong-double <1>: XGATE-Opts. (line 21) 27913* -mm9s12x: M68HC11-Opts. (line 27) 27914* -mm9s12xg: M68HC11-Opts. (line 32) 27915* -mmcu= command-line option, AVR: AVR Options. (line 6) 27916* -mmfpt: PDP-11-Options. (line 70) 27917* -mmicrocode: PDP-11-Options. (line 83) 27918* -mmnemonic= option, i386: i386-Options. (line 146) 27919* -mmnemonic= option, x86-64: i386-Options. (line 146) 27920* -mmultiply-enabled command-line option, LM32: LM32 Options. 27921 (line 6) 27922* -mmutiproc: PDP-11-Options. (line 73) 27923* -mmxps: PDP-11-Options. (line 77) 27924* -mnaked-reg option, i386: i386-Options. (line 158) 27925* -mnaked-reg option, x86-64: i386-Options. (line 158) 27926* -mnan= command-line option, MIPS: MIPS Options. (line 444) 27927* -mno-allow-string-insns: RX-Opts. (line 82) 27928* -mno-arch-attr option, RISC-V: RISC-V-Options. (line 55) 27929* -mno-cis: PDP-11-Options. (line 32) 27930* -mno-csm: PDP-11-Options. (line 43) 27931* -mno-csr-check option, RISC-V: RISC-V-Options. (line 64) 27932* -mno-dollar-line-separator command line option, AVR: AVR Options. 27933 (line 135) 27934* -mno-dsbt command-line option, TIC6X: TIC6X Options. (line 13) 27935* -mno-eis: PDP-11-Options. (line 46) 27936* -mno-extensions: PDP-11-Options. (line 29) 27937* -mno-fdpic command-line option, Blackfin: Blackfin Options. 27938 (line 22) 27939* -mno-fis: PDP-11-Options. (line 51) 27940* -mno-fp-11: PDP-11-Options. (line 56) 27941* -mno-fpp: PDP-11-Options. (line 56) 27942* -mno-fpu: PDP-11-Options. (line 56) 27943* -mno-kev11: PDP-11-Options. (line 51) 27944* -mno-limited-eis: PDP-11-Options. (line 64) 27945* -mno-link-relax command-line option, AVR: AVR Options. (line 127) 27946* -mno-mfpt: PDP-11-Options. (line 70) 27947* -mno-microcode: PDP-11-Options. (line 83) 27948* -mno-mutiproc: PDP-11-Options. (line 73) 27949* -mno-mxps: PDP-11-Options. (line 77) 27950* -mno-pic: PDP-11-Options. (line 11) 27951* -mno-pic command-line option, TIC6X: TIC6X Options. (line 36) 27952* -mno-regnames option, s390: s390 Options. (line 51) 27953* -mno-relax command-line options, BPF: BPF Options. (line 27) 27954* -mno-relax option, RISC-V: RISC-V-Options. (line 44) 27955* -mno-skip-bug command-line option, AVR: AVR Options. (line 114) 27956* -mno-spl: PDP-11-Options. (line 80) 27957* -mno-sym32: MIPS Options. (line 353) 27958* -mno-verbose-error command-line option, AArch64: AArch64 Options. 27959 (line 67) 27960* -mno-wrap command-line option, AVR: AVR Options. (line 117) 27961* -mnopic command-line option, Blackfin: Blackfin Options. (line 22) 27962* -mnps400 command-line option, ARC: ARC Options. (line 102) 27963* -momit-lock-prefix= option, i386: i386-Options. (line 181) 27964* -momit-lock-prefix= option, x86-64: i386-Options. (line 181) 27965* -mpic: PDP-11-Options. (line 11) 27966* -mpic command-line option, TIC6X: TIC6X Options. (line 36) 27967* -mpid: RX-Opts. (line 50) 27968* -mpid= command-line option, TIC6X: TIC6X Options. (line 23) 27969* -mpriv-spec=PRIVspec option, RISC-V: RISC-V-Options. (line 27) 27970* -mreg-prefix=PREFIX option, reg-prefix: S12Z Options. (line 9) 27971* -mregnames option, s390: s390 Options. (line 48) 27972* -mrelax command-line option, ARC: ARC Options. (line 97) 27973* -mrelax command-line option, V850: V850 Options. (line 72) 27974* -mrelax option, RISC-V: RISC-V-Options. (line 40) 27975* -mrelax-relocations= option, i386: i386-Options. (line 199) 27976* -mrelax-relocations= option, x86-64: i386-Options. (line 199) 27977* -mrh850-abi command-line option, V850: V850 Options. (line 82) 27978* -mrmw command-line option, AVR: AVR Options. (line 120) 27979* -mrx-abi: RX-Opts. (line 69) 27980* -mshared option, i386: i386-Options. (line 168) 27981* -mshared option, x86-64: i386-Options. (line 168) 27982* -mshort: M68HC11-Opts. (line 40) 27983* -mshort <1>: XGATE-Opts. (line 8) 27984* -mshort-double: M68HC11-Opts. (line 49) 27985* -mshort-double <1>: XGATE-Opts. (line 17) 27986* -msign-extend-enabled command-line option, LM32: LM32 Options. 27987 (line 15) 27988* -msmall-data-limit: RX-Opts. (line 42) 27989* -msoft-float command-line option, V850: V850 Options. (line 95) 27990* -mspfp command-line option, ARC: ARC Options. (line 105) 27991* -mspl: PDP-11-Options. (line 80) 27992* -msse-check= option, i386: i386-Options. (line 98) 27993* -msse-check= option, x86-64: i386-Options. (line 98) 27994* -msse2avx option, i386: i386-Options. (line 90) 27995* -msse2avx option, x86-64: i386-Options. (line 90) 27996* -msym32: MIPS Options. (line 353) 27997* -msyntax= option, i386: i386-Options. (line 152) 27998* -msyntax= option, x86-64: i386-Options. (line 152) 27999* -mt11: PDP-11-Options. (line 130) 28000* -mthumb command-line option, ARM: ARM Options. (line 361) 28001* -mthumb-interwork command-line option, ARM: ARM Options. (line 366) 28002* -mtune= option, i386: i386-Options. (line 82) 28003* -mtune= option, x86-64: i386-Options. (line 82) 28004* -mtune=ARCH command-line option, Visium: Visium Options. (line 8) 28005* -muse-conventional-section-names: RX-Opts. (line 33) 28006* -muse-renesas-section-names: RX-Opts. (line 37) 28007* -muse-unaligned-vector-move option, i386: i386-Options. (line 94) 28008* -muse-unaligned-vector-move option, x86-64: i386-Options. (line 94) 28009* -muser-enabled command-line option, LM32: LM32 Options. (line 18) 28010* -mv850 command-line option, V850: V850 Options. (line 23) 28011* -mv850any command-line option, V850: V850 Options. (line 41) 28012* -mv850e command-line option, V850: V850 Options. (line 29) 28013* -mv850e1 command-line option, V850: V850 Options. (line 35) 28014* -mv850e2 command-line option, V850: V850 Options. (line 51) 28015* -mv850e2v3 command-line option, V850: V850 Options. (line 57) 28016* -mv850e2v4 command-line option, V850: V850 Options. (line 63) 28017* -mv850e3v5 command-line option, V850: V850 Options. (line 66) 28018* -mverbose-error command-line option, AArch64: AArch64 Options. 28019 (line 63) 28020* -mvexwig= option, i386: i386-Options. (line 119) 28021* -mvexwig= option, x86-64: i386-Options. (line 119) 28022* -mvxworks-pic option, MIPS: MIPS Options. (line 26) 28023* -mwarn-areg-zero option, s390: s390 Options. (line 54) 28024* -mwarn-deprecated command-line option, ARM: ARM Options. (line 443) 28025* -mwarn-syms command-line option, ARM: ARM Options. (line 451) 28026* -mx86-used-note= option, i386: i386-Options. (line 277) 28027* -mx86-used-note= option, x86-64: i386-Options. (line 277) 28028* -mzarch option, s390: s390 Options. (line 17) 28029* -m[no-]68851 command-line option, M680x0: M68K-Opts. (line 21) 28030* -m[no-]68881 command-line option, M680x0: M68K-Opts. (line 21) 28031* -m[no-]div command-line option, M680x0: M68K-Opts. (line 21) 28032* -m[no-]emac command-line option, M680x0: M68K-Opts. (line 21) 28033* -m[no-]float command-line option, M680x0: M68K-Opts. (line 21) 28034* -m[no-]mac command-line option, M680x0: M68K-Opts. (line 21) 28035* -m[no-]usp command-line option, M680x0: M68K-Opts. (line 21) 28036* -N command-line option, CRIS: CRIS-Opts. (line 59) 28037* -nIp option, M32RX: M32R-Opts. (line 101) 28038* -no-bitinst, M32R2: M32R-Opts. (line 54) 28039* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 28040* -no-mdebug command-line option, Alpha: Alpha Options. (line 25) 28041* -no-parallel option, M32RX: M32R-Opts. (line 51) 28042* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 28043 (line 79) 28044* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 28045* -nocpp ignored (MIPS): MIPS Options. (line 356) 28046* -noreplace command-line option, Alpha: Alpha Options. (line 40) 28047* -o: o. (line 6) 28048* -O option, i386: i386-Options. (line 300) 28049* -O option, M32RX: M32R-Opts. (line 59) 28050* -O option, x86-64: i386-Options. (line 300) 28051* -O0 option, i386: i386-Options. (line 300) 28052* -O0 option, x86-64: i386-Options. (line 300) 28053* -O1 option, i386: i386-Options. (line 300) 28054* -O1 option, x86-64: i386-Options. (line 300) 28055* -O2 option, i386: i386-Options. (line 300) 28056* -O2 option, x86-64: i386-Options. (line 300) 28057* -Os option, i386: i386-Options. (line 300) 28058* -Os option, x86-64: i386-Options. (line 300) 28059* -parallel option, M32RX: M32R-Opts. (line 46) 28060* -R: R. (line 6) 28061* -relax command-line option, Alpha: Alpha Options. (line 32) 28062* -replace command-line option, Alpha: Alpha Options. (line 40) 28063* -S, ignored on VAX: VAX-Opts. (line 11) 28064* -sdcc command-line option, Z80: Z80 Options. (line 37) 28065* -T, ignored on VAX: VAX-Opts. (line 11) 28066* -t, ignored on VAX: VAX-Opts. (line 36) 28067* -v: v. (line 6) 28068* -V, redundant on VAX: VAX-Opts. (line 22) 28069* -version: v. (line 6) 28070* -W: W. (line 11) 28071* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 28072 (line 65) 28073* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 28074* -Wnp option, M32RX: M32R-Opts. (line 83) 28075* -Wnuh option, M32RX: M32R-Opts. (line 117) 28076* -Wp option, M32RX: M32R-Opts. (line 75) 28077* -wsigned_overflow command-line option, V850: V850 Options. (line 9) 28078* -Wuh option, M32RX: M32R-Opts. (line 114) 28079* -wunsigned_overflow command-line option, V850: V850 Options. 28080 (line 16) 28081* -x command-line option, MMIX: MMIX-Opts. (line 44) 28082* -z8001 command-line option, Z8000: Z8000 Options. (line 6) 28083* -z8002 command-line option, Z8000: Z8000 Options. (line 9) 28084* . (symbol): Dot. (line 6) 28085* .align directive, ARM: ARM Directives. (line 6) 28086* .align directive, KVX: KVX Directives. (line 6) 28087* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) 28088* .align directive, TILEPro: TILEPro Directives. (line 6) 28089* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. 28090 (line 10) 28091* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. 28092 (line 10) 28093* .arch directive, AArch64: AArch64 Directives. (line 6) 28094* .arch directive, ARM: ARM Directives. (line 13) 28095* .arch directive, TIC6X: TIC6X Directives. (line 10) 28096* .arch_extension directive, AArch64: AArch64 Directives. (line 13) 28097* .arch_extension directive, ARM: ARM Directives. (line 21) 28098* .arc_attribute directive, ARC: ARC Directives. (line 240) 28099* .arm directive, ARM: ARM Directives. (line 30) 28100* .assume directive, Z80: Z80 Directives. (line 12) 28101* .attribute directive, RISC-V: RISC-V-Directives. (line 121) 28102* .big directive, M32RX: M32R-Directives. (line 88) 28103* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) 28104* .cantunwind directive, ARM: ARM Directives. (line 33) 28105* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) 28106* .cfi_b_key_frame directive, AArch64: AArch64 Directives. (line 96) 28107* .code directive, ARM: ARM Directives. (line 37) 28108* .cpu directive, AArch64: AArch64 Directives. (line 21) 28109* .cpu directive, ARM: ARM Directives. (line 41) 28110* .dn and .qn directives, ARM: ARM Directives. (line 49) 28111* .dword directive, AArch64: AArch64 Directives. (line 25) 28112* .dword directive, KVX: KVX Directives. (line 9) 28113* .eabi_attribute directive, ARM: ARM Directives. (line 73) 28114* .ehtype directive, TIC6X: TIC6X Directives. (line 31) 28115* .endp directive, KVX: KVX Directives. (line 12) 28116* .endp directive, TIC6X: TIC6X Directives. (line 34) 28117* .even directive, AArch64: AArch64 Directives. (line 28) 28118* .even directive, ARM: ARM Directives. (line 102) 28119* .extend directive, ARM: ARM Directives. (line 105) 28120* .file directive, KVX: KVX Directives. (line 27) 28121* .float16 directive, AArch64: AArch64 Directives. (line 32) 28122* .float16 directive, ARM: ARM Directives. (line 111) 28123* .float16_format directive, ARM: ARM Directives. (line 119) 28124* .fnend directive, ARM: ARM Directives. (line 126) 28125* .fnstart directive, ARM: ARM Directives. (line 134) 28126* .force_thumb directive, ARM: ARM Directives. (line 137) 28127* .fpu directive, ARM: ARM Directives. (line 141) 28128* .global: MIPS insn. (line 12) 28129* .gnu_attribute 4, N directive, MIPS: MIPS FP ABI History. 28130 (line 6) 28131* .gnu_attribute Tag_GNU_MIPS_ABI_FP, N directive, MIPS: MIPS FP ABI History. 28132 (line 6) 28133* .handlerdata directive, ARM: ARM Directives. (line 145) 28134* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) 28135* .insn: MIPS insn. (line 6) 28136* .insn directive, s390: s390 Directives. (line 11) 28137* .inst directive, AArch64: AArch64 Directives. (line 38) 28138* .inst directive, ARM: ARM Directives. (line 154) 28139* .ldouble directive, ARM: ARM Directives. (line 105) 28140* .little directive, M32RX: M32R-Directives. (line 82) 28141* .loc directive, KVX: KVX Directives. (line 31) 28142* .long directive, s390: s390 Directives. (line 16) 28143* .ltorg directive, AArch64: AArch64 Directives. (line 42) 28144* .ltorg directive, ARM: ARM Directives. (line 164) 28145* .ltorg directive, s390: s390 Directives. (line 79) 28146* .m32r directive, M32R: M32R-Directives. (line 66) 28147* .m32r2 directive, M32R2: M32R-Directives. (line 77) 28148* .m32rx directive, M32RX: M32R-Directives. (line 72) 28149* .machine directive, s390: s390 Directives. (line 84) 28150* .machinemode directive, s390: s390 Directives. (line 101) 28151* .module: MIPS assembly options. 28152 (line 6) 28153* .module fp=NN directive, MIPS: MIPS FP ABI Selection. 28154 (line 6) 28155* .movsp directive, ARM: ARM Directives. (line 178) 28156* .nan directive, MIPS: MIPS NaN Encodings. (line 6) 28157* .nocmp directive, TIC6X: TIC6X Directives. (line 47) 28158* .no_pointers directive, XStormy16: XStormy16 Directives. 28159 (line 14) 28160* .o: Object. (line 6) 28161* .object_arch directive, ARM: ARM Directives. (line 183) 28162* .packed directive, ARM: ARM Directives. (line 189) 28163* .pacspval directive, ARM: ARM Directives. (line 194) 28164* .pad directive, ARM: ARM Directives. (line 198) 28165* .param on HPPA: HPPA Directives. (line 19) 28166* .personality directive, ARM: ARM Directives. (line 203) 28167* .personality directive, TIC6X: TIC6X Directives. (line 55) 28168* .personalityindex directive, ARM: ARM Directives. (line 206) 28169* .personalityindex directive, TIC6X: TIC6X Directives. (line 51) 28170* .pool directive, AArch64: AArch64 Directives. (line 56) 28171* .pool directive, ARM: ARM Directives. (line 210) 28172* .proc directive, KVX: KVX Directives. (line 35) 28173* .quad directive, s390: s390 Directives. (line 16) 28174* .req directive, AArch64: AArch64 Directives. (line 59) 28175* .req directive, ARM: ARM Directives. (line 213) 28176* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. 28177 (line 19) 28178* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. 28179 (line 19) 28180* .save directive, ARM: ARM Directives. (line 218) 28181* .scomm directive, TIC6X: TIC6X Directives. (line 58) 28182* .secrel32 directive, ARM: ARM Directives. (line 256) 28183* .set arch=CPU: MIPS ISA. (line 18) 28184* .set at: MIPS Macros. (line 41) 28185* .set at=REG: MIPS Macros. (line 35) 28186* .set autoextend: MIPS autoextend. (line 6) 28187* .set crc: MIPS ASE Instruction Generation Overrides. 28188 (line 68) 28189* .set doublefloat: MIPS Floating-Point. 28190 (line 12) 28191* .set dsp: MIPS ASE Instruction Generation Overrides. 28192 (line 21) 28193* .set dspr2: MIPS ASE Instruction Generation Overrides. 28194 (line 26) 28195* .set dspr3: MIPS ASE Instruction Generation Overrides. 28196 (line 31) 28197* .set ginv: MIPS ASE Instruction Generation Overrides. 28198 (line 72) 28199* .set hardfloat: MIPS Floating-Point. 28200 (line 6) 28201* .set insn32: MIPS assembly options. 28202 (line 18) 28203* .set loongson-cam: MIPS ASE Instruction Generation Overrides. 28204 (line 81) 28205* .set loongson-ext: MIPS ASE Instruction Generation Overrides. 28206 (line 86) 28207* .set loongson-ext2: MIPS ASE Instruction Generation Overrides. 28208 (line 91) 28209* .set loongson-mmi: MIPS ASE Instruction Generation Overrides. 28210 (line 76) 28211* .set macro: MIPS Macros. (line 30) 28212* .set mcu: MIPS ASE Instruction Generation Overrides. 28213 (line 42) 28214* .set mdmx: MIPS ASE Instruction Generation Overrides. 28215 (line 16) 28216* .set mips16e2: MIPS ASE Instruction Generation Overrides. 28217 (line 61) 28218* .set mips3d: MIPS ASE Instruction Generation Overrides. 28219 (line 6) 28220* .set mipsN: MIPS ISA. (line 6) 28221* .set msa: MIPS ASE Instruction Generation Overrides. 28222 (line 47) 28223* .set mt: MIPS ASE Instruction Generation Overrides. 28224 (line 37) 28225* .set noat: MIPS Macros. (line 41) 28226* .set noautoextend: MIPS autoextend. (line 6) 28227* .set nocrc: MIPS ASE Instruction Generation Overrides. 28228 (line 68) 28229* .set nodsp: MIPS ASE Instruction Generation Overrides. 28230 (line 21) 28231* .set nodspr2: MIPS ASE Instruction Generation Overrides. 28232 (line 26) 28233* .set nodspr3: MIPS ASE Instruction Generation Overrides. 28234 (line 31) 28235* .set noginv: MIPS ASE Instruction Generation Overrides. 28236 (line 72) 28237* .set noinsn32: MIPS assembly options. 28238 (line 18) 28239* .set noloongson-cam: MIPS ASE Instruction Generation Overrides. 28240 (line 81) 28241* .set noloongson-ext: MIPS ASE Instruction Generation Overrides. 28242 (line 86) 28243* .set noloongson-ext2: MIPS ASE Instruction Generation Overrides. 28244 (line 91) 28245* .set noloongson-mmi: MIPS ASE Instruction Generation Overrides. 28246 (line 76) 28247* .set nomacro: MIPS Macros. (line 30) 28248* .set nomcu: MIPS ASE Instruction Generation Overrides. 28249 (line 42) 28250* .set nomdmx: MIPS ASE Instruction Generation Overrides. 28251 (line 16) 28252* .set nomips16e2: MIPS ASE Instruction Generation Overrides. 28253 (line 61) 28254* .set nomips3d: MIPS ASE Instruction Generation Overrides. 28255 (line 6) 28256* .set nomsa: MIPS ASE Instruction Generation Overrides. 28257 (line 47) 28258* .set nomt: MIPS ASE Instruction Generation Overrides. 28259 (line 37) 28260* .set nosmartmips: MIPS ASE Instruction Generation Overrides. 28261 (line 11) 28262* .set nosym32: MIPS Symbol Sizes. (line 6) 28263* .set novirt: MIPS ASE Instruction Generation Overrides. 28264 (line 52) 28265* .set noxpa: MIPS ASE Instruction Generation Overrides. 28266 (line 57) 28267* .set pop: MIPS Option Stack. (line 6) 28268* .set push: MIPS Option Stack. (line 6) 28269* .set singlefloat: MIPS Floating-Point. 28270 (line 12) 28271* .set smartmips: MIPS ASE Instruction Generation Overrides. 28272 (line 11) 28273* .set softfloat: MIPS Floating-Point. 28274 (line 6) 28275* .set sym32: MIPS Symbol Sizes. (line 6) 28276* .set virt: MIPS ASE Instruction Generation Overrides. 28277 (line 52) 28278* .set xpa: MIPS ASE Instruction Generation Overrides. 28279 (line 57) 28280* .setfp directive, ARM: ARM Directives. (line 242) 28281* .short directive, s390: s390 Directives. (line 16) 28282* .syntax directive, ARM: ARM Directives. (line 261) 28283* .thumb directive, ARM: ARM Directives. (line 265) 28284* .thumb_func directive, ARM: ARM Directives. (line 268) 28285* .thumb_set directive, ARM: ARM Directives. (line 279) 28286* .tlsdescadd directive, AArch64: AArch64 Directives. (line 67) 28287* .tlsdesccall directive, AArch64: AArch64 Directives. (line 70) 28288* .tlsdescldr directive, AArch64: AArch64 Directives. (line 73) 28289* .tlsdescseq directive, ARM: ARM Directives. (line 286) 28290* .unreq directive, AArch64: AArch64 Directives. (line 76) 28291* .unreq directive, ARM: ARM Directives. (line 291) 28292* .unwind_raw directive, ARM: ARM Directives. (line 302) 28293* .v850 directive, V850: V850 Directives. (line 14) 28294* .v850e directive, V850: V850 Directives. (line 20) 28295* .v850e1 directive, V850: V850 Directives. (line 26) 28296* .v850e2 directive, V850: V850 Directives. (line 32) 28297* .v850e2v3 directive, V850: V850 Directives. (line 38) 28298* .v850e2v4 directive, V850: V850 Directives. (line 44) 28299* .v850e3v5 directive, V850: V850 Directives. (line 50) 28300* .variant_pcs directive, AArch64: AArch64 Directives. (line 87) 28301* .vsave directive, ARM: ARM Directives. (line 309) 28302* .word directive, KVX: KVX Directives. (line 40) 28303* .xword directive, AArch64: AArch64 Directives. (line 92) 28304* .z8001: Z8000 Directives. (line 11) 28305* .z8002: Z8000 Directives. (line 15) 28306* 16-bit code, i386: i386-16bit. (line 6) 28307* 16bit_pointers directive, XStormy16: XStormy16 Directives. 28308 (line 6) 28309* 16byte directive, Nios II: Nios II Directives. (line 28) 28310* 16byte directive, PRU: PRU Directives. (line 25) 28311* 2byte directive: 2byte. (line 6) 28312* 2byte directive, Nios II: Nios II Directives. (line 19) 28313* 2byte directive, PRU: PRU Directives. (line 16) 28314* 32bit_pointers directive, XStormy16: XStormy16 Directives. 28315 (line 10) 28316* 3DNow!, i386: i386-SIMD. (line 6) 28317* 3DNow!, x86-64: i386-SIMD. (line 6) 28318* 430 support: MSP430-Dependent. (line 6) 28319* 4byte directive: 4byte. (line 6) 28320* 4byte directive, Nios II: Nios II Directives. (line 22) 28321* 4byte directive, PRU: PRU Directives. (line 19) 28322* 8byte directive: 8byte. (line 6) 28323* 8byte directive, Nios II: Nios II Directives. (line 25) 28324* 8byte directive, PRU: PRU Directives. (line 22) 28325* : (label): Statements. (line 31) 28326* @gotoff(SYMBOL), ARC modifier: ARC Modifiers. (line 20) 28327* @gotpc(SYMBOL), ARC modifier: ARC Modifiers. (line 16) 28328* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) 28329* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) 28330* @pcl(SYMBOL), ARC modifier: ARC Modifiers. (line 12) 28331* @plt(SYMBOL), ARC modifier: ARC Modifiers. (line 23) 28332* @sda(SYMBOL), ARC modifier: ARC Modifiers. (line 28) 28333* @word modifier, D10V: D10V-Word. (line 6) 28334* _ opcode prefix: Xtensa Opcodes. (line 9) 28335* __DYNAMIC__, ARC pre-defined symbol: ARC Symbols. (line 14) 28336* __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol: ARC Symbols. 28337 (line 11) 28338* a.out: Object. (line 6) 28339* a.out symbol attributes: a.out Symbols. (line 6) 28340* AArch64 floating point (IEEE): AArch64 Floating Point. 28341 (line 6) 28342* AArch64 immediate character: AArch64-Chars. (line 13) 28343* AArch64 line comment character: AArch64-Chars. (line 6) 28344* AArch64 line separator: AArch64-Chars. (line 10) 28345* AArch64 machine directives: AArch64 Directives. (line 6) 28346* AArch64 machine directives <1>: KVX Directives. (line 6) 28347* AArch64 opcodes: AArch64 Opcodes. (line 6) 28348* AArch64 options (none): AArch64 Options. (line 6) 28349* AArch64 register names: AArch64-Regs. (line 6) 28350* AArch64 relocations: AArch64-Relocations. 28351 (line 6) 28352* AArch64 support: AArch64-Dependent. (line 6) 28353* abort directive: Abort. (line 6) 28354* ABORT directive: ABORT (COFF). (line 6) 28355* absolute section: Ld Sections. (line 29) 28356* absolute-literals directive: Absolute Literals Directive. 28357 (line 6) 28358* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 28359 (line 43) 28360* addition, permitted arguments: Infix Ops. (line 45) 28361* addresses: Expressions. (line 6) 28362* addresses, format of: Secs Background. (line 65) 28363* addressing modes, D10V: D10V-Addressing. (line 6) 28364* addressing modes, D30V: D30V-Addressing. (line 6) 28365* addressing modes, H8/300: H8/300-Addressing. (line 6) 28366* addressing modes, M680x0: M68K-Syntax. (line 21) 28367* addressing modes, M68HC11: M68HC11-Syntax. (line 29) 28368* addressing modes, S12Z: S12Z Addressing Modes. 28369 (line 6) 28370* addressing modes, SH: SH-Addressing. (line 6) 28371* addressing modes, XGATE: XGATE-Syntax. (line 28) 28372* addressing modes, Z8000: Z8000-Addressing. (line 6) 28373* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 28374* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 43) 28375* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations. 28376 (line 14) 28377* advancing location counter: Org. (line 6) 28378* align directive: Align. (line 6) 28379* align directive <1>: RISC-V-Directives. (line 8) 28380* align directive, Nios II: Nios II Directives. (line 6) 28381* align directive, OpenRISC: OpenRISC-Directives. 28382 (line 9) 28383* align directive, PRU: PRU Directives. (line 6) 28384* align directive, SPARC: Sparc-Directives. (line 9) 28385* align directive, TIC54X: TIC54X-Directives. (line 6) 28386* aligned instruction bundle: Bundle directives. (line 9) 28387* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 28388* alignment of branch targets: Xtensa Automatic Alignment. 28389 (line 6) 28390* alignment of LOOP instructions: Xtensa Automatic Alignment. 28391 (line 6) 28392* Alpha floating point (IEEE): Alpha Floating Point. 28393 (line 6) 28394* Alpha line comment character: Alpha-Chars. (line 6) 28395* Alpha line separator: Alpha-Chars. (line 11) 28396* Alpha notes: Alpha Notes. (line 6) 28397* Alpha options: Alpha Options. (line 6) 28398* Alpha registers: Alpha-Regs. (line 6) 28399* Alpha relocations: Alpha-Relocs. (line 6) 28400* Alpha support: Alpha-Dependent. (line 6) 28401* Alpha Syntax: Alpha Options. (line 60) 28402* Alpha-only directives: Alpha Directives. (line 9) 28403* Altera Nios II support: NiosII-Dependent. (line 6) 28404* altered difference tables: Word. (line 12) 28405* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 28406* ARC Branch Target Address: ARC-Regs. (line 60) 28407* ARC BTA saved on exception entry: ARC-Regs. (line 79) 28408* ARC Build configuration for: BTA Registers: ARC-Regs. (line 89) 28409* ARC Build configuration for: Core Registers: ARC-Regs. (line 97) 28410* ARC Build configuration for: Interrupts: ARC-Regs. (line 93) 28411* ARC Build Configuration Registers Version: ARC-Regs. (line 85) 28412* ARC C preprocessor macro separator: ARC-Chars. (line 31) 28413* ARC core general registers: ARC-Regs. (line 10) 28414* ARC DCCM RAM Configuration Register: ARC-Regs. (line 101) 28415* ARC Exception Cause Register: ARC-Regs. (line 63) 28416* ARC Exception Return Address: ARC-Regs. (line 76) 28417* ARC extension core registers: ARC-Regs. (line 38) 28418* ARC frame pointer: ARC-Regs. (line 17) 28419* ARC global pointer: ARC-Regs. (line 14) 28420* ARC interrupt link register: ARC-Regs. (line 27) 28421* ARC Interrupt Vector Base address: ARC-Regs. (line 66) 28422* ARC level 1 interrupt link register: ARC-Regs. (line 23) 28423* ARC level 2 interrupt link register: ARC-Regs. (line 31) 28424* ARC line comment character: ARC-Chars. (line 11) 28425* ARC line separator: ARC-Chars. (line 27) 28426* ARC link register: ARC-Regs. (line 35) 28427* ARC loop counter: ARC-Regs. (line 41) 28428* ARC machine directives: ARC Directives. (line 6) 28429* ARC opcodes: ARC Opcodes. (line 6) 28430* ARC options: ARC Options. (line 6) 28431* ARC Processor Identification register: ARC-Regs. (line 51) 28432* ARC Program Counter: ARC-Regs. (line 54) 28433* ARC register name prefix character: ARC-Chars. (line 7) 28434* ARC register names: ARC-Regs. (line 6) 28435* ARC Saved User Stack Pointer: ARC-Regs. (line 73) 28436* ARC stack pointer: ARC-Regs. (line 20) 28437* ARC Status register: ARC-Regs. (line 57) 28438* ARC STATUS32 saved on exception: ARC-Regs. (line 82) 28439* ARC Stored STATUS32 register on entry to level P0 interrupts: ARC-Regs. 28440 (line 69) 28441* ARC support: ARC-Dependent. (line 6) 28442* ARC symbol prefix character: ARC-Chars. (line 20) 28443* ARC word aligned program counter: ARC-Regs. (line 44) 28444* arch directive, i386: i386-Arch. (line 6) 28445* arch directive, M680x0: M68K-Directives. (line 22) 28446* arch directive, MSP 430: MSP430 Directives. (line 18) 28447* arch directive, x86-64: i386-Arch. (line 6) 28448* architecture options, IP2022: IP2K-Opts. (line 9) 28449* architecture options, IP2K: IP2K-Opts. (line 14) 28450* architecture options, M16C: M32C-Opts. (line 12) 28451* architecture options, M32C: M32C-Opts. (line 9) 28452* architecture options, M32R: M32R-Opts. (line 21) 28453* architecture options, M32R2: M32R-Opts. (line 17) 28454* architecture options, M32RX: M32R-Opts. (line 9) 28455* architecture options, M680x0: M68K-Opts. (line 99) 28456* Architecture variant option, CRIS: CRIS-Opts. (line 34) 28457* architectures, Meta: Meta Options. (line 6) 28458* architectures, PowerPC: PowerPC-Opts. (line 6) 28459* architectures, SCORE: SCORE-Opts. (line 6) 28460* architectures, SPARC: Sparc-Opts. (line 6) 28461* arguments for addition: Infix Ops. (line 45) 28462* arguments for subtraction: Infix Ops. (line 50) 28463* arguments in expressions: Arguments. (line 6) 28464* arithmetic functions: Operators. (line 6) 28465* arithmetic operands: Arguments. (line 6) 28466* ARM data relocations: ARM-Relocations. (line 6) 28467* ARM floating point (IEEE): ARM Floating Point. (line 6) 28468* ARM identifiers: ARM-Chars. (line 19) 28469* ARM immediate character: ARM-Chars. (line 17) 28470* ARM line comment character: ARM-Chars. (line 6) 28471* ARM line separator: ARM-Chars. (line 14) 28472* ARM machine directives: ARM Directives. (line 6) 28473* ARM opcodes: ARM Opcodes. (line 6) 28474* ARM options (none): ARM Options. (line 6) 28475* ARM register names: ARM-Regs. (line 6) 28476* ARM support: ARM-Dependent. (line 6) 28477* ascii directive: Ascii. (line 6) 28478* asciz directive: Asciz. (line 6) 28479* asg directive, TIC54X: TIC54X-Directives. (line 18) 28480* assembler bugs, reporting: Bug Reporting. (line 6) 28481* assembler crash: Bug Criteria. (line 9) 28482* assembler directive .3byte, RX: RX-Directives. (line 9) 28483* assembler directive .arch, CRIS: CRIS-Pseudos. (line 50) 28484* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 28485* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 28486* assembler directive .fetchalign, RX: RX-Directives. (line 13) 28487* assembler directive .interrupt, M68HC11: M68HC11-Directives. 28488 (line 26) 28489* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 28490* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 28491* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18) 28492* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 28493* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137) 28494* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101) 28495* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137) 28496* assembler directive GREG, MMIX: MMIX-Pseudos. (line 53) 28497* assembler directive IS, MMIX: MMIX-Pseudos. (line 44) 28498* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 28499* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29) 28500* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113) 28501* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125) 28502* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113) 28503* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113) 28504* assembler directives, CRIS: CRIS-Pseudos. (line 6) 28505* assembler directives, M68HC11: M68HC11-Directives. (line 6) 28506* assembler directives, M68HC12: M68HC11-Directives. (line 6) 28507* assembler directives, MMIX: MMIX-Pseudos. (line 6) 28508* assembler directives, RL78: RL78-Directives. (line 6) 28509* assembler directives, RX: RX-Directives. (line 6) 28510* assembler directives, XGATE: XGATE-Directives. (line 6) 28511* assembler internal logic error: As Sections. (line 13) 28512* assembler version: v. (line 6) 28513* assembler, and linker: Secs Background. (line 10) 28514* assembly listings, enabling: a. (line 6) 28515* assigning values to symbols: Setting Symbols. (line 6) 28516* assigning values to symbols <1>: Equ. (line 6) 28517* at register, MIPS: MIPS Macros. (line 35) 28518* attributes, symbol: Symbol Attributes. (line 6) 28519* att_syntax pseudo op, i386: i386-Variations. (line 6) 28520* att_syntax pseudo op, x86-64: i386-Variations. (line 6) 28521* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 28522* auxiliary symbol information, COFF: Dim. (line 6) 28523* AVR line comment character: AVR-Chars. (line 6) 28524* AVR line separator: AVR-Chars. (line 14) 28525* AVR modifiers: AVR-Modifiers. (line 6) 28526* AVR opcode summary: AVR Opcodes. (line 6) 28527* AVR options (none): AVR Options. (line 6) 28528* AVR register names: AVR-Regs. (line 6) 28529* AVR support: AVR-Dependent. (line 6) 28530* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 28531* backslash (\\): Strings. (line 40) 28532* backspace (\b): Strings. (line 15) 28533* balign directive: Balign. (line 6) 28534* balignl directive: Balign. (line 29) 28535* balignw directive: Balign. (line 29) 28536* bes directive, TIC54X: TIC54X-Directives. (line 194) 28537* bfloat16 directive, i386: i386-Float. (line 14) 28538* bfloat16 directive, x86-64: i386-Float. (line 14) 28539* big endian output, MIPS: Overview. (line 931) 28540* big endian output, PJ: Overview. (line 835) 28541* big-endian output, MIPS: MIPS Options. (line 13) 28542* big-endian output, TIC6X: TIC6X Options. (line 46) 28543* bignums: Bignums. (line 6) 28544* binary constants, TIC54X: TIC54X-Constants. (line 8) 28545* binary files, including: Incbin. (line 6) 28546* binary integers: Integers. (line 6) 28547* bit names, IA-64: IA-64-Bits. (line 6) 28548* bitfields, not supported on VAX: VAX-no. (line 6) 28549* Blackfin directives: Blackfin Directives. 28550 (line 6) 28551* Blackfin options (none): Blackfin Options. (line 6) 28552* Blackfin support: Blackfin-Dependent. (line 6) 28553* Blackfin syntax: Blackfin Syntax. (line 6) 28554* block: Z8000 Directives. (line 55) 28555* block comments, BPF: BPF Special Characters. 28556 (line 9) 28557* BMI, i386: i386-BMI. (line 6) 28558* BMI, x86-64: i386-BMI. (line 6) 28559* BPF block comments: BPF Special Characters. 28560 (line 9) 28561* BPF line comment character: BPF Special Characters. 28562 (line 6) 28563* BPF opcodes: BPF Instructions. (line 6) 28564* BPF options (none): BPF Options. (line 6) 28565* BPF register names: BPF Registers. (line 6) 28566* BPF support: BPF-Dependent. (line 6) 28567* branch improvement, M680x0: M68K-Branch. (line 6) 28568* branch improvement, M68HC11: M68HC11-Branch. (line 6) 28569* branch improvement, VAX: VAX-branch. (line 6) 28570* branch instructions, relaxation: Xtensa Branch Relaxation. 28571 (line 6) 28572* Branch Target Address, ARC: ARC-Regs. (line 60) 28573* branch target alignment: Xtensa Automatic Alignment. 28574 (line 6) 28575* break directive, TIC54X: TIC54X-Directives. (line 141) 28576* BSD syntax: PDP-11-Syntax. (line 6) 28577* bss directive: Bss. (line 6) 28578* bss directive, TIC54X: TIC54X-Directives. (line 27) 28579* bss section: Ld Sections. (line 20) 28580* bss section <1>: bss. (line 6) 28581* BTA saved on exception entry, ARC: ARC-Regs. (line 79) 28582* bug criteria: Bug Criteria. (line 6) 28583* bug reports: Bug Reporting. (line 6) 28584* bugs in assembler: Reporting Bugs. (line 6) 28585* Build configuration for: BTA Registers, ARC: ARC-Regs. (line 89) 28586* Build configuration for: Core Registers, ARC: ARC-Regs. (line 97) 28587* Build configuration for: Interrupts, ARC: ARC-Regs. (line 93) 28588* Build Configuration Registers Version, ARC: ARC-Regs. (line 85) 28589* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 28590* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 28591* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 28592* bundle: Bundle directives. (line 9) 28593* bundle-locked: Bundle directives. (line 38) 28594* bundle_align_mode directive: Bundle directives. (line 9) 28595* bundle_lock directive: Bundle directives. (line 31) 28596* bundle_unlock directive: Bundle directives. (line 31) 28597* bus lock prefixes, i386: i386-Prefixes. (line 36) 28598* bval: Z8000 Directives. (line 30) 28599* byte directive: Byte. (line 6) 28600* byte directive, TIC54X: TIC54X-Directives. (line 34) 28601* C preprocessor macro separator, ARC: ARC-Chars. (line 31) 28602* C-SKY options: C-SKY Options. (line 6) 28603* C-SKY support: C-SKY-Dependent. (line 6) 28604* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 28605* call directive, Nios II: Nios II Relocations. 28606 (line 38) 28607* call instructions, i386: i386-Mnemonics. (line 118) 28608* call instructions, relaxation: Xtensa Call Relaxation. 28609 (line 6) 28610* call instructions, x86-64: i386-Mnemonics. (line 118) 28611* call_hiadj directive, Nios II: Nios II Relocations. 28612 (line 38) 28613* call_lo directive, Nios II: Nios II Relocations. 28614 (line 38) 28615* carriage return (backslash-r): Strings. (line 24) 28616* case sensitivity, Z80: Z80-Case. (line 6) 28617* cfi_endproc directive: CFI directives. (line 43) 28618* cfi_fde_data directive: CFI directives. (line 69) 28619* cfi_personality directive: CFI directives. (line 50) 28620* cfi_personality_id directive: CFI directives. (line 62) 28621* cfi_sections directive: CFI directives. (line 9) 28622* cfi_startproc directive: CFI directives. (line 33) 28623* char directive, TIC54X: TIC54X-Directives. (line 34) 28624* character constant, Z80: Z80-Chars. (line 20) 28625* character constants: Characters. (line 6) 28626* character escape codes: Strings. (line 15) 28627* character escapes, Z80: Z80-Chars. (line 18) 28628* character, single: Chars. (line 6) 28629* characters used in symbols: Symbol Intro. (line 6) 28630* clink directive, TIC54X: TIC54X-Directives. (line 43) 28631* code16 directive, i386: i386-16bit. (line 6) 28632* code16gcc directive, i386: i386-16bit. (line 6) 28633* code32 directive, i386: i386-16bit. (line 6) 28634* code64 directive, i386: i386-16bit. (line 6) 28635* code64 directive, x86-64: i386-16bit. (line 6) 28636* COFF auxiliary symbol information: Dim. (line 6) 28637* COFF structure debugging: Tag. (line 6) 28638* COFF symbol attributes: COFF Symbols. (line 6) 28639* COFF symbol descriptor: Desc. (line 6) 28640* COFF symbol storage class: Scl. (line 6) 28641* COFF symbol type: Type. (line 11) 28642* COFF symbols, debugging: Def. (line 6) 28643* COFF value attribute: Val. (line 6) 28644* COMDAT: Linkonce. (line 6) 28645* comm directive: Comm. (line 6) 28646* command line conventions: Command Line. (line 6) 28647* command-line options ignored, VAX: VAX-Opts. (line 6) 28648* command-line options, V850: V850 Options. (line 9) 28649* comment character, XStormy16: XStormy16-Chars. (line 11) 28650* comments: Comments. (line 6) 28651* comments, M680x0: M68K-Chars. (line 6) 28652* comments, removed by preprocessor: Preprocessing. (line 11) 28653* common directive, SPARC: Sparc-Directives. (line 12) 28654* common sections: Linkonce. (line 6) 28655* common variable storage: bss. (line 6) 28656* comparison expressions: Infix Ops. (line 56) 28657* conditional assembly: If. (line 6) 28658* constant, single character: Chars. (line 6) 28659* constants: Constants. (line 6) 28660* constants, bignum: Bignums. (line 6) 28661* constants, character: Characters. (line 6) 28662* constants, converted by preprocessor: Preprocessing. (line 14) 28663* constants, floating point: Flonums. (line 6) 28664* constants, integer: Integers. (line 6) 28665* constants, number: Numbers. (line 6) 28666* constants, Sparc: Sparc-Constants. (line 6) 28667* constants, string: Strings. (line 6) 28668* constants, TIC54X: TIC54X-Constants. (line 6) 28669* conversion instructions, i386: i386-Mnemonics. (line 69) 28670* conversion instructions, x86-64: i386-Mnemonics. (line 69) 28671* coprocessor wait, i386: i386-Prefixes. (line 40) 28672* copy directive, TIC54X: TIC54X-Directives. (line 52) 28673* core general registers, ARC: ARC-Regs. (line 10) 28674* cpu directive, ARC: ARC Directives. (line 27) 28675* cpu directive, M680x0: M68K-Directives. (line 30) 28676* cpu directive, MSP 430: MSP430 Directives. (line 22) 28677* CR16 line comment character: CR16-Chars. (line 6) 28678* CR16 line separator: CR16-Chars. (line 12) 28679* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 28680 (line 6) 28681* CR16 support: CR16-Dependent. (line 6) 28682* crash of assembler: Bug Criteria. (line 9) 28683* CRIS --emulation=crisaout command-line option: CRIS-Opts. (line 9) 28684* CRIS --emulation=criself command-line option: CRIS-Opts. (line 9) 28685* CRIS --march=ARCHITECTURE command-line option: CRIS-Opts. (line 34) 28686* CRIS --mul-bug-abort command-line option: CRIS-Opts. (line 63) 28687* CRIS --no-mul-bug-abort command-line option: CRIS-Opts. (line 63) 28688* CRIS --no-underscore command-line option: CRIS-Opts. (line 15) 28689* CRIS --pic command-line option: CRIS-Opts. (line 27) 28690* CRIS --underscore command-line option: CRIS-Opts. (line 15) 28691* CRIS -N command-line option: CRIS-Opts. (line 59) 28692* CRIS architecture variant option: CRIS-Opts. (line 34) 28693* CRIS assembler directive .arch: CRIS-Pseudos. (line 50) 28694* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 28695* CRIS assembler directive .syntax: CRIS-Pseudos. (line 18) 28696* CRIS assembler directives: CRIS-Pseudos. (line 6) 28697* CRIS built-in symbols: CRIS-Symbols. (line 6) 28698* CRIS instruction expansion: CRIS-Expand. (line 6) 28699* CRIS line comment characters: CRIS-Chars. (line 6) 28700* CRIS options: CRIS-Opts. (line 6) 28701* CRIS position-independent code: CRIS-Opts. (line 27) 28702* CRIS pseudo-op .arch: CRIS-Pseudos. (line 50) 28703* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 28704* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18) 28705* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 28706* CRIS register names: CRIS-Regs. (line 6) 28707* CRIS support: CRIS-Dependent. (line 6) 28708* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 28709* ctbp register, V850: V850-Regs. (line 90) 28710* ctoff pseudo-op, V850: V850 Opcodes. (line 110) 28711* ctpc register, V850: V850-Regs. (line 82) 28712* ctpsw register, V850: V850-Regs. (line 84) 28713* current address: Dot. (line 6) 28714* current address, advancing: Org. (line 6) 28715* custom (vendor-defined) extensions, RISC-V: RISC-V-CustomExts. 28716 (line 6) 28717* c_mode directive, TIC54X: TIC54X-Directives. (line 49) 28718* D10V @word modifier: D10V-Word. (line 6) 28719* D10V addressing modes: D10V-Addressing. (line 6) 28720* D10V floating point: D10V-Float. (line 6) 28721* D10V line comment character: D10V-Chars. (line 6) 28722* D10V opcode summary: D10V-Opcodes. (line 6) 28723* D10V optimization: Overview. (line 714) 28724* D10V options: D10V-Opts. (line 6) 28725* D10V registers: D10V-Regs. (line 6) 28726* D10V size modifiers: D10V-Size. (line 6) 28727* D10V sub-instruction ordering: D10V-Chars. (line 14) 28728* D10V sub-instructions: D10V-Subs. (line 6) 28729* D10V support: D10V-Dependent. (line 6) 28730* D10V syntax: D10V-Syntax. (line 6) 28731* d24 directive, Z80: Z80 Directives. (line 32) 28732* D30V addressing modes: D30V-Addressing. (line 6) 28733* D30V floating point: D30V-Float. (line 6) 28734* D30V Guarded Execution: D30V-Guarded. (line 6) 28735* D30V line comment character: D30V-Chars. (line 6) 28736* D30V nops: Overview. (line 722) 28737* D30V nops after 32-bit multiply: Overview. (line 725) 28738* D30V opcode summary: D30V-Opcodes. (line 6) 28739* D30V optimization: Overview. (line 719) 28740* D30V options: D30V-Opts. (line 6) 28741* D30V registers: D30V-Regs. (line 6) 28742* D30V size modifiers: D30V-Size. (line 6) 28743* D30V sub-instruction ordering: D30V-Chars. (line 14) 28744* D30V sub-instructions: D30V-Subs. (line 6) 28745* D30V support: D30V-Dependent. (line 6) 28746* D30V syntax: D30V-Syntax. (line 6) 28747* d32 directive, Z80: Z80 Directives. (line 37) 28748* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 28749* data and text sections, joining: R. (line 6) 28750* data directive: Data. (line 6) 28751* data directive, TIC54X: TIC54X-Directives. (line 59) 28752* Data directives: RISC-V-Directives. (line 12) 28753* data relocations, ARM: ARM-Relocations. (line 6) 28754* data section: Ld Sections. (line 9) 28755* data1 directive, M680x0: M68K-Directives. (line 9) 28756* data2 directive, M680x0: M68K-Directives. (line 12) 28757* db directive, Z80: Z80 Directives. (line 18) 28758* dbpc register, V850: V850-Regs. (line 86) 28759* dbpsw register, V850: V850-Regs. (line 88) 28760* dc directive: Dc. (line 6) 28761* dcb directive: Dcb. (line 6) 28762* DCCM RAM Configuration Register, ARC: ARC-Regs. (line 101) 28763* debuggers, and symbol order: Symbols. (line 10) 28764* debugging COFF symbols: Def. (line 6) 28765* DEC syntax: PDP-11-Syntax. (line 6) 28766* decimal integers: Integers. (line 12) 28767* def directive: Def. (line 6) 28768* def directive, TIC54X: TIC54X-Directives. (line 101) 28769* def24 directive, Z80: Z80 Directives. (line 33) 28770* def32 directive, Z80: Z80 Directives. (line 38) 28771* defb directive, Z80: Z80 Directives. (line 19) 28772* defl directive, Z80: Z80 Directives. (line 47) 28773* defm directive, Z80: Z80 Directives. (line 20) 28774* defs directive, Z80: Z80 Directives. (line 43) 28775* defw directive, Z80: Z80 Directives. (line 28) 28776* density instructions: Density Instructions. 28777 (line 6) 28778* dependency tracking: MD. (line 6) 28779* deprecated directives: Deprecated. (line 6) 28780* desc directive: Desc. (line 6) 28781* descriptor, of a.out symbol: Symbol Desc. (line 6) 28782* dfloat directive, VAX: VAX-directives. (line 9) 28783* difference tables altered: Word. (line 12) 28784* difference tables, warning: K. (line 6) 28785* differences, mmixal: MMIX-mmixal. (line 6) 28786* dim directive: Dim. (line 6) 28787* directives and instructions: Statements. (line 20) 28788* directives for PowerPC: PowerPC-Pseudo. (line 6) 28789* directives for SCORE: SCORE-Pseudo. (line 6) 28790* directives, Blackfin: Blackfin Directives. 28791 (line 6) 28792* directives, M32R: M32R-Directives. (line 6) 28793* directives, M680x0: M68K-Directives. (line 6) 28794* directives, machine independent: Pseudo Ops. (line 6) 28795* directives, Xtensa: Xtensa Directives. (line 6) 28796* directives, Z8000: Z8000 Directives. (line 6) 28797* Disable floating-point instructions: MIPS Floating-Point. 28798 (line 6) 28799* Disable single-precision floating-point operations: MIPS Floating-Point. 28800 (line 12) 28801* displacement sizing character, VAX: VAX-operands. (line 12) 28802* dollar local symbols: Symbol Names. (line 123) 28803* dot (symbol): Dot. (line 6) 28804* double directive: Double. (line 6) 28805* double directive, i386: i386-Float. (line 14) 28806* double directive, M680x0: M68K-Float. (line 14) 28807* double directive, M68HC11: M68HC11-Float. (line 14) 28808* double directive, RX: RX-Float. (line 11) 28809* double directive, TIC54X: TIC54X-Directives. (line 62) 28810* double directive, VAX: VAX-float. (line 15) 28811* double directive, x86-64: i386-Float. (line 14) 28812* double directive, XGATE: XGATE-Float. (line 13) 28813* doublequote (\"): Strings. (line 43) 28814* drlist directive, TIC54X: TIC54X-Directives. (line 71) 28815* drnolist directive, TIC54X: TIC54X-Directives. (line 71) 28816* ds directive: Ds. (line 6) 28817* ds directive, Z80: Z80 Directives. (line 42) 28818* DTP-relative data directives: RISC-V-Directives. (line 18) 28819* dw directive, Z80: Z80 Directives. (line 27) 28820* dword directive, BPF: BPF Directives. (line 15) 28821* dword directive, Nios II: Nios II Directives. (line 16) 28822* dword directive, PRU: PRU Directives. (line 13) 28823* EB command-line option, C-SKY: C-SKY Options. (line 18) 28824* EB command-line option, Nios II: Nios II Options. (line 22) 28825* ecr register, V850: V850-Regs. (line 78) 28826* eight-byte integer: Quad. (line 11) 28827* eight-byte integer <1>: 8byte. (line 6) 28828* eipc register, V850: V850-Regs. (line 70) 28829* eipsw register, V850: V850-Regs. (line 72) 28830* eject directive: Eject. (line 6) 28831* EL command-line option, C-SKY: C-SKY Options. (line 14) 28832* EL command-line option, Nios II: Nios II Options. (line 25) 28833* ELF symbol type: Type. (line 22) 28834* else directive: Else. (line 6) 28835* elseif directive: Elseif. (line 6) 28836* empty expressions: Empty Exprs. (line 6) 28837* emsg directive, TIC54X: TIC54X-Directives. (line 75) 28838* emulation: Overview. (line 1185) 28839* encoding options, i386: i386-Mnemonics. (line 38) 28840* encoding options, x86-64: i386-Mnemonics. (line 38) 28841* end directive: End. (line 6) 28842* endef directive: Endef. (line 6) 28843* endfunc directive: Endfunc. (line 6) 28844* endianness, MIPS: Overview. (line 931) 28845* endianness, PJ: Overview. (line 835) 28846* endif directive: Endif. (line 6) 28847* endloop directive, TIC54X: TIC54X-Directives. (line 141) 28848* endm directive: Macro. (line 162) 28849* endm directive, TIC54X: TIC54X-Directives. (line 151) 28850* endproc directive, OpenRISC: OpenRISC-Directives. 28851 (line 24) 28852* endstruct directive, TIC54X: TIC54X-Directives. (line 214) 28853* endunion directive, TIC54X: TIC54X-Directives. (line 248) 28854* environment settings, TIC54X: TIC54X-Env. (line 6) 28855* EOF, newline must precede: Statements. (line 14) 28856* ep register, V850: V850-Regs. (line 66) 28857* Epiphany line comment character: Epiphany-Chars. (line 6) 28858* Epiphany line separator: Epiphany-Chars. (line 14) 28859* Epiphany options: Epiphany Options. (line 6) 28860* Epiphany support: Epiphany-Dependent. (line 6) 28861* equ directive: Equ. (line 6) 28862* equ directive, TIC54X: TIC54X-Directives. (line 189) 28863* equ directive, Z80: Z80 Directives. (line 52) 28864* equiv directive: Equiv. (line 6) 28865* eqv directive: Eqv. (line 6) 28866* err directive: Err. (line 6) 28867* error directive: Error. (line 6) 28868* error messages: Errors. (line 6) 28869* error on valid input: Bug Criteria. (line 12) 28870* errors, caused by warnings: W. (line 16) 28871* errors, continuing after: Z. (line 6) 28872* escape codes, character: Strings. (line 15) 28873* eval directive, TIC54X: TIC54X-Directives. (line 22) 28874* even: Z8000 Directives. (line 58) 28875* even directive, M680x0: M68K-Directives. (line 15) 28876* even directive, TIC54X: TIC54X-Directives. (line 6) 28877* Exception Cause Register, ARC: ARC-Regs. (line 63) 28878* Exception Return Address, ARC: ARC-Regs. (line 76) 28879* exitm directive: Macro. (line 165) 28880* expr (internal section): As Sections. (line 17) 28881* expression arguments: Arguments. (line 6) 28882* expressions: Expressions. (line 6) 28883* expressions, comparison: Infix Ops. (line 56) 28884* expressions, empty: Empty Exprs. (line 6) 28885* expressions, integer: Integer Exprs. (line 6) 28886* extAuxRegister directive, ARC: ARC Directives. (line 105) 28887* extCondCode directive, ARC: ARC Directives. (line 126) 28888* extCoreRegister directive, ARC: ARC Directives. (line 137) 28889* extend directive M680x0: M68K-Float. (line 17) 28890* extend directive M68HC11: M68HC11-Float. (line 17) 28891* extend directive XGATE: XGATE-Float. (line 16) 28892* extension core registers, ARC: ARC-Regs. (line 38) 28893* extension instructions, i386: i386-Mnemonics. (line 88) 28894* extension instructions, x86-64: i386-Mnemonics. (line 88) 28895* extern directive: Extern. (line 6) 28896* extInstruction directive, ARC: ARC Directives. (line 164) 28897* fail directive: Fail. (line 6) 28898* far_mode directive, TIC54X: TIC54X-Directives. (line 80) 28899* faster processing (-f): f. (line 6) 28900* fatal signal: Bug Criteria. (line 9) 28901* fclist directive, TIC54X: TIC54X-Directives. (line 85) 28902* fcnolist directive, TIC54X: TIC54X-Directives. (line 85) 28903* fepc register, V850: V850-Regs. (line 74) 28904* fepsw register, V850: V850-Regs. (line 76) 28905* ffloat directive, VAX: VAX-directives. (line 13) 28906* field directive, TIC54X: TIC54X-Directives. (line 89) 28907* file directive: File. (line 6) 28908* file directive, MSP 430: MSP430 Directives. (line 6) 28909* file name, logical: File. (line 13) 28910* file names and line numbers, in warnings/errors: Errors. (line 16) 28911* files, including: Include. (line 6) 28912* files, input: Input Files. (line 6) 28913* fill directive: Fill. (line 6) 28914* filling memory: Skip. (line 6) 28915* filling memory <1>: Space. (line 6) 28916* filling memory with no-op instructions: Nop. (line 6) 28917* filling memory with no-op instructions <1>: Nops. (line 6) 28918* filling memory with zero bytes: Zero. (line 6) 28919* FLIX syntax: Xtensa Syntax. (line 6) 28920* float directive: Float. (line 6) 28921* float directive, i386: i386-Float. (line 14) 28922* float directive, M680x0: M68K-Float. (line 11) 28923* float directive, M68HC11: M68HC11-Float. (line 11) 28924* float directive, RX: RX-Float. (line 8) 28925* float directive, TIC54X: TIC54X-Directives. (line 62) 28926* float directive, VAX: VAX-float. (line 15) 28927* float directive, x86-64: i386-Float. (line 14) 28928* float directive, XGATE: XGATE-Float. (line 10) 28929* floating point numbers: Flonums. (line 6) 28930* floating point numbers (double): Double. (line 6) 28931* floating point numbers (single): Float. (line 6) 28932* floating point numbers (single) <1>: Single. (line 6) 28933* floating point, AArch64 (IEEE): AArch64 Floating Point. 28934 (line 6) 28935* floating point, Alpha (IEEE): Alpha Floating Point. 28936 (line 6) 28937* floating point, ARM (IEEE): ARM Floating Point. (line 6) 28938* floating point, D10V: D10V-Float. (line 6) 28939* floating point, D30V: D30V-Float. (line 6) 28940* floating point, H8/300 (IEEE): H8/300 Floating Point. 28941 (line 6) 28942* floating point, HPPA (IEEE): HPPA Floating Point. 28943 (line 6) 28944* floating point, i386: i386-Float. (line 6) 28945* floating point, M680x0: M68K-Float. (line 6) 28946* floating point, M68HC11: M68HC11-Float. (line 6) 28947* floating point, MSP 430 (IEEE): MSP430 Floating Point. 28948 (line 6) 28949* floating point, OPENRISC (IEEE): OpenRISC-Float. (line 6) 28950* floating point, risc-v (IEEE): RISC-V-Floating-Point. 28951 (line 6) 28952* floating point, RX: RX-Float. (line 6) 28953* floating point, s390: s390 Floating Point. 28954 (line 6) 28955* floating point, SH (IEEE): SH Floating Point. (line 6) 28956* floating point, SPARC (IEEE): Sparc-Float. (line 6) 28957* floating point, V850 (IEEE): V850 Floating Point. 28958 (line 6) 28959* floating point, VAX: VAX-float. (line 6) 28960* floating point, WebAssembly (IEEE): WebAssembly-Floating-Point. 28961 (line 6) 28962* floating point, x86-64: i386-Float. (line 6) 28963* floating point, XGATE: XGATE-Float. (line 6) 28964* floating point, Z80: Z80 Floating Point. (line 6) 28965* flonums: Flonums. (line 6) 28966* force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 28967* format of error messages: Errors. (line 38) 28968* format of warning messages: Errors. (line 12) 28969* formfeed (\f): Strings. (line 18) 28970* four-byte integer: 4byte. (line 6) 28971* fpic command-line option, C-SKY: C-SKY Options. (line 22) 28972* frame pointer, ARC: ARC-Regs. (line 17) 28973* func directive: Func. (line 6) 28974* functions, in expressions: Operators. (line 6) 28975* gfloat directive, VAX: VAX-directives. (line 17) 28976* global: Z8000 Directives. (line 21) 28977* global directive: Global. (line 6) 28978* global directive, TIC54X: TIC54X-Directives. (line 101) 28979* global pointer, ARC: ARC-Regs. (line 14) 28980* got directive, Nios II: Nios II Relocations. 28981 (line 38) 28982* gotoff directive, Nios II: Nios II Relocations. 28983 (line 38) 28984* gotoff_hiadj directive, Nios II: Nios II Relocations. 28985 (line 38) 28986* gotoff_lo directive, Nios II: Nios II Relocations. 28987 (line 38) 28988* got_hiadj directive, Nios II: Nios II Relocations. 28989 (line 38) 28990* got_lo directive, Nios II: Nios II Relocations. 28991 (line 38) 28992* gp register, MIPS: MIPS Small Data. (line 6) 28993* gp register, V850: V850-Regs. (line 14) 28994* gprel directive, Nios II: Nios II Relocations. 28995 (line 26) 28996* grouping data: Sub-Sections. (line 6) 28997* H8/300 addressing modes: H8/300-Addressing. (line 6) 28998* H8/300 floating point (IEEE): H8/300 Floating Point. 28999 (line 6) 29000* H8/300 line comment character: H8/300-Chars. (line 6) 29001* H8/300 line separator: H8/300-Chars. (line 8) 29002* H8/300 machine directives (none): H8/300 Directives. (line 6) 29003* H8/300 opcode summary: H8/300 Opcodes. (line 6) 29004* H8/300 options: H8/300 Options. (line 6) 29005* H8/300 registers: H8/300-Regs. (line 6) 29006* H8/300 size suffixes: H8/300 Opcodes. (line 160) 29007* H8/300 support: H8/300-Dependent. (line 6) 29008* H8/300H, assembling for: H8/300 Directives. (line 8) 29009* half directive, BPF: BPF Directives. (line 9) 29010* half directive, Nios II: Nios II Directives. (line 10) 29011* half directive, SPARC: Sparc-Directives. (line 17) 29012* half directive, TIC54X: TIC54X-Directives. (line 109) 29013* hex character code (\XD...): Strings. (line 36) 29014* hexadecimal integers: Integers. (line 15) 29015* hexadecimal prefix, S12Z: S12Z Options. (line 17) 29016* hexadecimal prefix, Z80: Z80-Chars. (line 15) 29017* hfloat directive, i386: i386-Float. (line 14) 29018* hfloat directive, VAX: VAX-directives. (line 21) 29019* hfloat directive, x86-64: i386-Float. (line 14) 29020* hi directive, Nios II: Nios II Relocations. 29021 (line 20) 29022* hi pseudo-op, V850: V850 Opcodes. (line 33) 29023* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 29024* hiadj directive, Nios II: Nios II Relocations. 29025 (line 6) 29026* hidden directive: Hidden. (line 6) 29027* high directive, M32R: M32R-Directives. (line 18) 29028* hilo pseudo-op, V850: V850 Opcodes. (line 55) 29029* HPPA directives not supported: HPPA Directives. (line 11) 29030* HPPA floating point (IEEE): HPPA Floating Point. 29031 (line 6) 29032* HPPA Syntax: HPPA Options. (line 7) 29033* HPPA-only directives: HPPA Directives. (line 24) 29034* hword directive: hword. (line 6) 29035* i386 16-bit code: i386-16bit. (line 6) 29036* i386 arch directive: i386-Arch. (line 6) 29037* i386 att_syntax pseudo op: i386-Variations. (line 6) 29038* i386 conversion instructions: i386-Mnemonics. (line 69) 29039* i386 extension instructions: i386-Mnemonics. (line 88) 29040* i386 floating point: i386-Float. (line 6) 29041* i386 immediate operands: i386-Variations. (line 15) 29042* i386 instruction naming: i386-Mnemonics. (line 9) 29043* i386 instruction prefixes: i386-Prefixes. (line 6) 29044* i386 intel_syntax pseudo op: i386-Variations. (line 6) 29045* i386 jump optimization: i386-Jumps. (line 6) 29046* i386 jump, call, return: i386-Variations. (line 45) 29047* i386 jump/call operands: i386-Variations. (line 15) 29048* i386 line comment character: i386-Chars. (line 6) 29049* i386 line separator: i386-Chars. (line 18) 29050* i386 memory references: i386-Memory. (line 6) 29051* i386 mnemonic compatibility: i386-Mnemonics. (line 124) 29052* i386 mul, imul instructions: i386-Notes. (line 6) 29053* i386 options: i386-Options. (line 6) 29054* i386 register operands: i386-Variations. (line 15) 29055* i386 registers: i386-Regs. (line 6) 29056* i386 sections: i386-Variations. (line 51) 29057* i386 size suffixes: i386-Variations. (line 28) 29058* i386 source, destination operands: i386-Variations. (line 21) 29059* i386 support: i386-Dependent. (line 6) 29060* i386 syntax compatibility: i386-Variations. (line 6) 29061* i80386 support: i386-Dependent. (line 6) 29062* IA-64 line comment character: IA-64-Chars. (line 6) 29063* IA-64 line separator: IA-64-Chars. (line 8) 29064* IA-64 options: IA-64 Options. (line 6) 29065* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 29066* IA-64 registers: IA-64-Regs. (line 6) 29067* IA-64 relocations: IA-64-Relocs. (line 6) 29068* IA-64 support: IA-64-Dependent. (line 6) 29069* IA-64 Syntax: IA-64 Options. (line 85) 29070* ident directive: Ident. (line 6) 29071* identifiers, ARM: ARM-Chars. (line 19) 29072* identifiers, MSP 430: MSP430-Chars. (line 17) 29073* if directive: If. (line 6) 29074* ifb directive: If. (line 21) 29075* ifc directive: If. (line 25) 29076* ifdef directive: If. (line 16) 29077* ifeq directive: If. (line 33) 29078* ifeqs directive: If. (line 36) 29079* ifge directive: If. (line 40) 29080* ifgt directive: If. (line 44) 29081* ifle directive: If. (line 48) 29082* iflt directive: If. (line 52) 29083* ifnb directive: If. (line 56) 29084* ifnc directive: If. (line 61) 29085* ifndef directive: If. (line 65) 29086* ifne directive: If. (line 72) 29087* ifnes directive: If. (line 76) 29088* ifnotdef directive: If. (line 65) 29089* immediate character, AArch64: AArch64-Chars. (line 13) 29090* immediate character, ARM: ARM-Chars. (line 17) 29091* immediate character, M680x0: M68K-Chars. (line 13) 29092* immediate character, VAX: VAX-operands. (line 6) 29093* immediate fields, relaxation: Xtensa Immediate Relaxation. 29094 (line 6) 29095* immediate operands, i386: i386-Variations. (line 15) 29096* immediate operands, x86-64: i386-Variations. (line 15) 29097* imul instruction, i386: i386-Notes. (line 6) 29098* imul instruction, x86-64: i386-Notes. (line 6) 29099* incbin directive: Incbin. (line 6) 29100* include directive: Include. (line 6) 29101* include directive search path: I. (line 6) 29102* indirect character, VAX: VAX-operands. (line 9) 29103* infix operators: Infix Ops. (line 6) 29104* inhibiting interrupts, i386: i386-Prefixes. (line 36) 29105* input: Input Files. (line 6) 29106* input file linenumbers: Input Files. (line 35) 29107* insn directive: i386-Directives. (line 31) 29108* INSN directives: RISC-V-Directives. (line 103) 29109* instruction aliases, s390: s390 Aliases. (line 6) 29110* instruction bundle: Bundle directives. (line 9) 29111* instruction expansion, CRIS: CRIS-Expand. (line 6) 29112* instruction expansion, MMIX: MMIX-Expand. (line 6) 29113* instruction formats, risc-v: RISC-V-Formats. (line 6) 29114* instruction formats, s390: s390 Formats. (line 6) 29115* instruction marker, s390: s390 Instruction Marker. 29116 (line 6) 29117* instruction mnemonics, s390: s390 Mnemonics. (line 6) 29118* instruction naming, i386: i386-Mnemonics. (line 9) 29119* instruction naming, x86-64: i386-Mnemonics. (line 9) 29120* instruction operand modifier, s390: s390 Operand Modifier. 29121 (line 6) 29122* instruction operands, s390: s390 Operands. (line 6) 29123* instruction prefixes, i386: i386-Prefixes. (line 6) 29124* instruction set, M680x0: M68K-opcodes. (line 6) 29125* instruction set, M68HC11: M68HC11-opcodes. (line 6) 29126* instruction set, XGATE: XGATE-opcodes. (line 5) 29127* instruction summary, AVR: AVR Opcodes. (line 6) 29128* instruction summary, D10V: D10V-Opcodes. (line 6) 29129* instruction summary, D30V: D30V-Opcodes. (line 6) 29130* instruction summary, H8/300: H8/300 Opcodes. (line 6) 29131* instruction summary, LM32: LM32 Opcodes. (line 6) 29132* instruction summary, LM32 <1>: OpenRISC-Opcodes. (line 6) 29133* instruction summary, SH: SH Opcodes. (line 6) 29134* instruction summary, Z8000: Z8000 Opcodes. (line 6) 29135* instruction syntax, s390: s390 Syntax. (line 6) 29136* instructions and directives: Statements. (line 20) 29137* int directive: Int. (line 6) 29138* int directive, H8/300: H8/300 Directives. (line 6) 29139* int directive, i386: i386-Float. (line 22) 29140* int directive, TIC54X: TIC54X-Directives. (line 109) 29141* int directive, x86-64: i386-Float. (line 22) 29142* integer expressions: Integer Exprs. (line 6) 29143* integer, 16-byte: Octa. (line 6) 29144* integer, 2-byte: 2byte. (line 6) 29145* integer, 4-byte: 4byte. (line 6) 29146* integer, 8-byte: Quad. (line 11) 29147* integer, 8-byte <1>: 8byte. (line 6) 29148* integers: Integers. (line 6) 29149* integers, 16-bit: hword. (line 6) 29150* integers, 32-bit: Int. (line 6) 29151* integers, binary: Integers. (line 6) 29152* integers, decimal: Integers. (line 12) 29153* integers, hexadecimal: Integers. (line 15) 29154* integers, octal: Integers. (line 9) 29155* integers, one byte: Byte. (line 6) 29156* intel_syntax pseudo op, i386: i386-Variations. (line 6) 29157* intel_syntax pseudo op, x86-64: i386-Variations. (line 6) 29158* internal assembler sections: As Sections. (line 6) 29159* internal directive: Internal. (line 6) 29160* interrupt link register, ARC: ARC-Regs. (line 27) 29161* Interrupt Vector Base address, ARC: ARC-Regs. (line 66) 29162* invalid input: Bug Criteria. (line 14) 29163* invocation summary: Overview. (line 6) 29164* IP2K architecture options: IP2K-Opts. (line 9) 29165* IP2K architecture options <1>: IP2K-Opts. (line 14) 29166* IP2K line comment character: IP2K-Chars. (line 6) 29167* IP2K line separator: IP2K-Chars. (line 14) 29168* IP2K options: IP2K-Opts. (line 6) 29169* IP2K support: IP2K-Dependent. (line 6) 29170* irp directive: Irp. (line 6) 29171* irpc directive: Irpc. (line 6) 29172* joining text and data sections: R. (line 6) 29173* jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 29174* jump instructions, i386: i386-Mnemonics. (line 118) 29175* jump instructions, relaxation: Xtensa Jump Relaxation. 29176 (line 6) 29177* jump instructions, x86-64: i386-Mnemonics. (line 118) 29178* jump optimization, i386: i386-Jumps. (line 6) 29179* jump optimization, x86-64: i386-Jumps. (line 6) 29180* jump/call operands, i386: i386-Variations. (line 15) 29181* jump/call operands, x86-64: i386-Variations. (line 15) 29182* KVX Options: KVX Options. (line 6) 29183* KVX support: KVX-Dependent. (line 8) 29184* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 29185 (line 23) 29186* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 29187 (line 23) 29188* L32I instructions, relaxation: Xtensa Immediate Relaxation. 29189 (line 23) 29190* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 29191 (line 23) 29192* label (:): Statements. (line 31) 29193* label directive, TIC54X: TIC54X-Directives. (line 121) 29194* labels: Labels. (line 6) 29195* labels, Z80: Z80-Labels. (line 6) 29196* largecomm directive, ELF: i386-Directives. (line 17) 29197* lcomm directive: Lcomm. (line 6) 29198* lcomm directive <1>: ARC Directives. (line 9) 29199* lcomm directive, COFF: i386-Directives. (line 6) 29200* lcommon directive, ARC: ARC Directives. (line 24) 29201* ld: Object. (line 15) 29202* ldouble directive M680x0: M68K-Float. (line 17) 29203* ldouble directive M68HC11: M68HC11-Float. (line 17) 29204* ldouble directive XGATE: XGATE-Float. (line 16) 29205* ldouble directive, TIC54X: TIC54X-Directives. (line 62) 29206* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9) 29207* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 29208* LEB128 directives: RISC-V-Directives. (line 24) 29209* length directive, TIC54X: TIC54X-Directives. (line 125) 29210* length of symbols: Symbol Intro. (line 20) 29211* level 1 interrupt link register, ARC: ARC-Regs. (line 23) 29212* level 2 interrupt link register, ARC: ARC-Regs. (line 31) 29213* lflags directive (ignored): Lflags. (line 6) 29214* line: ARC-Chars. (line 30) 29215* line comment character: Comments. (line 19) 29216* line comment character, AArch64: AArch64-Chars. (line 6) 29217* line comment character, Alpha: Alpha-Chars. (line 6) 29218* line comment character, ARC: ARC-Chars. (line 11) 29219* line comment character, ARM: ARM-Chars. (line 6) 29220* line comment character, AVR: AVR-Chars. (line 6) 29221* line comment character, BPF: BPF Special Characters. 29222 (line 6) 29223* line comment character, CR16: CR16-Chars. (line 6) 29224* line comment character, D10V: D10V-Chars. (line 6) 29225* line comment character, D30V: D30V-Chars. (line 6) 29226* line comment character, Epiphany: Epiphany-Chars. (line 6) 29227* line comment character, H8/300: H8/300-Chars. (line 6) 29228* line comment character, i386: i386-Chars. (line 6) 29229* line comment character, IA-64: IA-64-Chars. (line 6) 29230* line comment character, IP2K: IP2K-Chars. (line 6) 29231* line comment character, LM32: LM32-Chars. (line 6) 29232* line comment character, M32C: M32C-Chars. (line 6) 29233* line comment character, M680x0: M68K-Chars. (line 6) 29234* line comment character, M68HC11: M68HC11-Syntax. (line 17) 29235* line comment character, Meta: Meta-Chars. (line 6) 29236* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6) 29237* line comment character, MIPS: MIPS-Chars. (line 6) 29238* line comment character, MSP 430: MSP430-Chars. (line 6) 29239* line comment character, Nios II: Nios II Chars. (line 6) 29240* line comment character, NS32K: NS32K-Chars. (line 6) 29241* line comment character, OpenRISC: OpenRISC-Chars. (line 6) 29242* line comment character, PJ: PJ-Chars. (line 6) 29243* line comment character, PowerPC: PowerPC-Chars. (line 6) 29244* line comment character, PRU: PRU Chars. (line 6) 29245* line comment character, RL78: RL78-Chars. (line 6) 29246* line comment character, RX: RX-Chars. (line 6) 29247* line comment character, S12Z: S12Z Syntax Overview. 29248 (line 32) 29249* line comment character, s390: s390 Characters. (line 6) 29250* line comment character, SCORE: SCORE-Chars. (line 6) 29251* line comment character, SH: SH-Chars. (line 6) 29252* line comment character, Sparc: Sparc-Chars. (line 6) 29253* line comment character, TIC54X: TIC54X-Chars. (line 6) 29254* line comment character, TIC6X: TIC6X Syntax. (line 6) 29255* line comment character, V850: V850-Chars. (line 6) 29256* line comment character, VAX: VAX-Chars. (line 6) 29257* line comment character, Visium: Visium Characters. (line 6) 29258* line comment character, WebAssembly: WebAssembly-Chars. (line 6) 29259* line comment character, XGATE: XGATE-Syntax. (line 16) 29260* line comment character, XStormy16: XStormy16-Chars. (line 6) 29261* line comment character, Z80: Z80-Chars. (line 6) 29262* line comment character, Z8000: Z8000-Chars. (line 6) 29263* line comment characters, CRIS: CRIS-Chars. (line 6) 29264* line comment characters, MMIX: MMIX-Chars. (line 6) 29265* line directive: Line. (line 6) 29266* line directive, MSP 430: MSP430 Directives. (line 14) 29267* line numbers, in input files: Input Files. (line 35) 29268* line separator character: Statements. (line 6) 29269* line separator character, Nios II: Nios II Chars. (line 6) 29270* line separator, AArch64: AArch64-Chars. (line 10) 29271* line separator, Alpha: Alpha-Chars. (line 11) 29272* line separator, ARC: ARC-Chars. (line 27) 29273* line separator, ARM: ARM-Chars. (line 14) 29274* line separator, AVR: AVR-Chars. (line 14) 29275* line separator, CR16: CR16-Chars. (line 12) 29276* line separator, Epiphany: Epiphany-Chars. (line 14) 29277* line separator, H8/300: H8/300-Chars. (line 8) 29278* line separator, i386: i386-Chars. (line 18) 29279* line separator, IA-64: IA-64-Chars. (line 8) 29280* line separator, IP2K: IP2K-Chars. (line 14) 29281* line separator, LM32: LM32-Chars. (line 12) 29282* line separator, M32C: M32C-Chars. (line 14) 29283* line separator, M680x0: M68K-Chars. (line 20) 29284* line separator, M68HC11: M68HC11-Syntax. (line 26) 29285* line separator, Meta: Meta-Chars. (line 8) 29286* line separator, MicroBlaze: MicroBlaze-Chars. (line 14) 29287* line separator, MIPS: MIPS-Chars. (line 14) 29288* line separator, MSP 430: MSP430-Chars. (line 14) 29289* line separator, NS32K: NS32K-Chars. (line 18) 29290* line separator, OpenRISC: OpenRISC-Chars. (line 9) 29291* line separator, PJ: PJ-Chars. (line 14) 29292* line separator, PowerPC: PowerPC-Chars. (line 18) 29293* line separator, RL78: RL78-Chars. (line 14) 29294* line separator, RX: RX-Chars. (line 14) 29295* line separator, S12Z: S12Z Syntax Overview. 29296 (line 41) 29297* line separator, s390: s390 Characters. (line 13) 29298* line separator, SCORE: SCORE-Chars. (line 14) 29299* line separator, SH: SH-Chars. (line 8) 29300* line separator, Sparc: Sparc-Chars. (line 14) 29301* line separator, TIC54X: TIC54X-Chars. (line 17) 29302* line separator, TIC6X: TIC6X Syntax. (line 13) 29303* line separator, V850: V850-Chars. (line 13) 29304* line separator, VAX: VAX-Chars. (line 14) 29305* line separator, Visium: Visium Characters. (line 14) 29306* line separator, XGATE: XGATE-Syntax. (line 25) 29307* line separator, XStormy16: XStormy16-Chars. (line 14) 29308* line separator, Z80: Z80-Chars. (line 13) 29309* line separator, Z8000: Z8000-Chars. (line 13) 29310* lines starting with #: Comments. (line 33) 29311* link register, ARC: ARC-Regs. (line 35) 29312* linker: Object. (line 15) 29313* linker, and assembler: Secs Background. (line 10) 29314* linkonce directive: Linkonce. (line 6) 29315* list directive: List. (line 6) 29316* list directive, TIC54X: TIC54X-Directives. (line 129) 29317* listing control, turning off: Nolist. (line 6) 29318* listing control, turning on: List. (line 6) 29319* listing control: new page: Eject. (line 6) 29320* listing control: paper size: Psize. (line 6) 29321* listing control: subtitle: Sbttl. (line 6) 29322* listing control: title line: Title. (line 6) 29323* listings, enabling: a. (line 6) 29324* literal directive: Literal Directive. (line 6) 29325* literal pool entries, s390: s390 Literal Pool Entries. 29326 (line 6) 29327* literal_position directive: Literal Position Directive. 29328 (line 6) 29329* literal_prefix directive: Literal Prefix Directive. 29330 (line 6) 29331* little endian output, MIPS: Overview. (line 934) 29332* little endian output, PJ: Overview. (line 838) 29333* little-endian output, MIPS: MIPS Options. (line 13) 29334* little-endian output, TIC6X: TIC6X Options. (line 46) 29335* LM32 line comment character: LM32-Chars. (line 6) 29336* LM32 line separator: LM32-Chars. (line 12) 29337* LM32 modifiers: LM32-Modifiers. (line 6) 29338* LM32 opcode summary: LM32 Opcodes. (line 6) 29339* LM32 options (none): LM32 Options. (line 6) 29340* LM32 register names: LM32-Regs. (line 6) 29341* LM32 support: LM32-Dependent. (line 6) 29342* ln directive: Ln. (line 6) 29343* lo directive, Nios II: Nios II Relocations. 29344 (line 23) 29345* lo pseudo-op, V850: V850 Opcodes. (line 22) 29346* loc directive: Loc. (line 6) 29347* local common symbols: Lcomm. (line 6) 29348* local directive: Local. (line 6) 29349* local labels: Symbol Names. (line 53) 29350* local symbol names: Symbol Names. (line 40) 29351* local symbols, retaining in output: L. (line 6) 29352* location counter: Dot. (line 6) 29353* location counter, advancing: Org. (line 6) 29354* location counter, Z80: Z80-Chars. (line 15) 29355* loc_mark_labels directive: Loc_mark_labels. (line 6) 29356* logical file name: File. (line 13) 29357* logical line number: Line. (line 6) 29358* logical line numbers: Comments. (line 33) 29359* long directive: Long. (line 6) 29360* long directive, i386: i386-Float. (line 22) 29361* long directive, TIC54X: TIC54X-Directives. (line 133) 29362* long directive, x86-64: i386-Float. (line 22) 29363* longcall pseudo-op, V850: V850 Opcodes. (line 122) 29364* longcalls directive: Longcalls Directive. 29365 (line 6) 29366* longjump pseudo-op, V850: V850 Opcodes. (line 128) 29367* Loongson Content Address Memory (CAM) generation override: MIPS ASE Instruction Generation Overrides. 29368 (line 81) 29369* Loongson EXTensions (EXT) instructions generation override: MIPS ASE Instruction Generation Overrides. 29370 (line 86) 29371* Loongson EXTensions R2 (EXT2) instructions generation override: MIPS ASE Instruction Generation Overrides. 29372 (line 91) 29373* Loongson MultiMedia extensions Instructions (MMI) generation override: MIPS ASE Instruction Generation Overrides. 29374 (line 76) 29375* loop counter, ARC: ARC-Regs. (line 41) 29376* loop directive, TIC54X: TIC54X-Directives. (line 141) 29377* LOOP instructions, alignment: Xtensa Automatic Alignment. 29378 (line 6) 29379* low directive, M32R: M32R-Directives. (line 9) 29380* lp register, V850: V850-Regs. (line 68) 29381* lval: Z8000 Directives. (line 27) 29382* LWP, i386: i386-LWP. (line 6) 29383* LWP, x86-64: i386-LWP. (line 6) 29384* M16C architecture option: M32C-Opts. (line 12) 29385* M32C architecture option: M32C-Opts. (line 9) 29386* M32C line comment character: M32C-Chars. (line 6) 29387* M32C line separator: M32C-Chars. (line 14) 29388* M32C modifiers: M32C-Modifiers. (line 6) 29389* M32C options: M32C-Opts. (line 6) 29390* M32C support: M32C-Dependent. (line 6) 29391* M32R architecture options: M32R-Opts. (line 9) 29392* M32R architecture options <1>: M32R-Opts. (line 17) 29393* M32R architecture options <2>: M32R-Opts. (line 21) 29394* M32R directives: M32R-Directives. (line 6) 29395* M32R options: M32R-Opts. (line 6) 29396* M32R support: M32R-Dependent. (line 6) 29397* M32R warnings: M32R-Warnings. (line 6) 29398* M680x0 addressing modes: M68K-Syntax. (line 21) 29399* M680x0 architecture options: M68K-Opts. (line 99) 29400* M680x0 branch improvement: M68K-Branch. (line 6) 29401* M680x0 directives: M68K-Directives. (line 6) 29402* M680x0 floating point: M68K-Float. (line 6) 29403* M680x0 immediate character: M68K-Chars. (line 13) 29404* M680x0 line comment character: M68K-Chars. (line 6) 29405* M680x0 line separator: M68K-Chars. (line 20) 29406* M680x0 opcodes: M68K-opcodes. (line 6) 29407* M680x0 options: M68K-Opts. (line 6) 29408* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 29409* M680x0 size modifiers: M68K-Syntax. (line 8) 29410* M680x0 support: M68K-Dependent. (line 6) 29411* M680x0 syntax: M68K-Syntax. (line 8) 29412* M68HC11 addressing modes: M68HC11-Syntax. (line 29) 29413* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 29414* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 29415* M68HC11 assembler directive .interrupt: M68HC11-Directives. 29416 (line 26) 29417* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 29418* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 29419* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 29420* M68HC11 assembler directives: M68HC11-Directives. (line 6) 29421* M68HC11 branch improvement: M68HC11-Branch. (line 6) 29422* M68HC11 floating point: M68HC11-Float. (line 6) 29423* M68HC11 line comment character: M68HC11-Syntax. (line 17) 29424* M68HC11 line separator: M68HC11-Syntax. (line 26) 29425* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 29426* M68HC11 opcodes: M68HC11-opcodes. (line 6) 29427* M68HC11 options: M68HC11-Opts. (line 6) 29428* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 29429* M68HC11 syntax: M68HC11-Syntax. (line 6) 29430* M68HC12 assembler directives: M68HC11-Directives. (line 6) 29431* mA6 command-line option, ARC: ARC Options. (line 14) 29432* mA7 command-line option, ARC: ARC Options. (line 39) 29433* machine dependencies: Machine Dependencies. 29434 (line 6) 29435* machine directives, AArch64: AArch64 Directives. (line 6) 29436* machine directives, AArch64 <1>: KVX Directives. (line 6) 29437* machine directives, ARC: ARC Directives. (line 6) 29438* machine directives, ARM: ARM Directives. (line 6) 29439* machine directives, BPF: BPF Directives. (line 6) 29440* machine directives, H8/300 (none): H8/300 Directives. (line 6) 29441* machine directives, MSP 430: MSP430 Directives. (line 6) 29442* machine directives, Nios II: Nios II Directives. (line 6) 29443* machine directives, OPENRISC: OpenRISC-Directives. 29444 (line 6) 29445* machine directives, PRU: PRU Directives. (line 6) 29446* machine directives, RISC-V: RISC-V-Directives. (line 6) 29447* machine directives, SH: SH Directives. (line 6) 29448* machine directives, SPARC: Sparc-Directives. (line 6) 29449* machine directives, TIC54X: TIC54X-Directives. (line 6) 29450* machine directives, TIC6X: TIC6X Directives. (line 6) 29451* machine directives, TILE-Gx: TILE-Gx Directives. (line 6) 29452* machine directives, TILEPro: TILEPro Directives. (line 6) 29453* machine directives, V850: V850 Directives. (line 6) 29454* machine directives, VAX: VAX-directives. (line 6) 29455* machine directives, x86: i386-Directives. (line 6) 29456* machine directives, XStormy16: XStormy16 Directives. 29457 (line 6) 29458* machine independent directives: Pseudo Ops. (line 6) 29459* machine instructions (not covered): Manual. (line 14) 29460* machine relocations, Nios II: Nios II Relocations. 29461 (line 6) 29462* machine relocations, PRU: PRU Relocations. (line 6) 29463* machine-independent syntax: Syntax. (line 6) 29464* macro directive: Macro. (line 28) 29465* macro directive, TIC54X: TIC54X-Directives. (line 151) 29466* macros: Macro. (line 6) 29467* macros, count executed: Macro. (line 167) 29468* Macros, MSP 430: MSP430-Macros. (line 6) 29469* macros, TIC54X: TIC54X-Macros. (line 6) 29470* make rules: MD. (line 6) 29471* manual, structure and purpose: Manual. (line 6) 29472* marc600 command-line option, ARC: ARC Options. (line 14) 29473* mARC601 command-line option, ARC: ARC Options. (line 27) 29474* mARC700 command-line option, ARC: ARC Options. (line 39) 29475* march command-line option, C-SKY: C-SKY Options. (line 6) 29476* march command-line option, Nios II: Nios II Options. (line 28) 29477* math builtins, TIC54X: TIC54X-Builtins. (line 6) 29478* Maximum number of continuation lines: listing. (line 34) 29479* mbig-endian command-line option, C-SKY: C-SKY Options. (line 18) 29480* mbranch-stub command-line option, C-SKY: C-SKY Options. (line 34) 29481* mcache command-line option, C-SKY: C-SKY Options. (line 100) 29482* mcp command-line option, C-SKY: C-SKY Options. (line 97) 29483* mcpu command-line option, C-SKY: C-SKY Options. (line 10) 29484* mdsp command-line option, C-SKY: C-SKY Options. (line 109) 29485* medsp command-line option, C-SKY: C-SKY Options. (line 112) 29486* melrw command-line option, C-SKY: C-SKY Options. (line 64) 29487* mEM command-line option, ARC: ARC Options. (line 42) 29488* memory references, i386: i386-Memory. (line 6) 29489* memory references, x86-64: i386-Memory. (line 6) 29490* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 29491* merging text and data sections: R. (line 6) 29492* messages from assembler: Errors. (line 6) 29493* Meta architectures: Meta Options. (line 6) 29494* Meta line comment character: Meta-Chars. (line 6) 29495* Meta line separator: Meta-Chars. (line 8) 29496* Meta options: Meta Options. (line 6) 29497* Meta registers: Meta-Regs. (line 6) 29498* Meta support: Meta-Dependent. (line 6) 29499* mforce2bsr command-line option, C-SKY: C-SKY Options. (line 43) 29500* mhard-float command-line option, C-SKY: C-SKY Options. (line 91) 29501* mHS command-line option, ARC: ARC Options. (line 64) 29502* MicroBlaze architectures: MicroBlaze-Dependent. 29503 (line 6) 29504* MicroBlaze directives: MicroBlaze Directives. 29505 (line 6) 29506* MicroBlaze line comment character: MicroBlaze-Chars. (line 6) 29507* MicroBlaze line separator: MicroBlaze-Chars. (line 14) 29508* MicroBlaze Options: MicroBlaze Options. (line 8) 29509* MicroBlaze support: MicroBlaze-Dependent. 29510 (line 12) 29511* minus, permitted arguments: Infix Ops. (line 50) 29512* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. 29513 (line 18) 29514* MIPS architecture options: MIPS Options. (line 29) 29515* MIPS big-endian output: MIPS Options. (line 13) 29516* MIPS CPU override: MIPS ISA. (line 18) 29517* MIPS cyclic redundancy check (CRC) instruction generation override: MIPS ASE Instruction Generation Overrides. 29518 (line 68) 29519* MIPS directives to override command-line options: MIPS assembly options. 29520 (line 6) 29521* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides. 29522 (line 21) 29523* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides. 29524 (line 26) 29525* MIPS DSP Release 3 instruction generation override: MIPS ASE Instruction Generation Overrides. 29526 (line 31) 29527* MIPS endianness: Overview. (line 931) 29528* MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides. 29529 (line 57) 29530* MIPS Global INValidate (GINV) instruction generation override: MIPS ASE Instruction Generation Overrides. 29531 (line 72) 29532* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings. 29533 (line 6) 29534* MIPS ISA: Overview. (line 937) 29535* MIPS ISA override: MIPS ISA. (line 6) 29536* MIPS line comment character: MIPS-Chars. (line 6) 29537* MIPS line separator: MIPS-Chars. (line 14) 29538* MIPS little-endian output: MIPS Options. (line 13) 29539* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides. 29540 (line 42) 29541* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides. 29542 (line 16) 29543* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides. 29544 (line 6) 29545* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides. 29546 (line 37) 29547* MIPS option stack: MIPS Option Stack. (line 6) 29548* MIPS processor: MIPS-Dependent. (line 6) 29549* MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides. 29550 (line 47) 29551* MIPS16e2 instruction generation override: MIPS ASE Instruction Generation Overrides. 29552 (line 61) 29553* mistack command-line option, C-SKY: C-SKY Options. (line 82) 29554* MIT: M68K-Syntax. (line 6) 29555* mjsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 29556* mlabr command-line option, C-SKY: C-SKY Options. (line 75) 29557* mlaf command-line option, C-SKY: C-SKY Options. (line 69) 29558* mlib directive, TIC54X: TIC54X-Directives. (line 157) 29559* mlink-relax command-line option, PRU: PRU Options. (line 6) 29560* mlist directive, TIC54X: TIC54X-Directives. (line 162) 29561* mliterals-after-br command-line option, C-SKY: C-SKY Options. 29562 (line 75) 29563* mliterals-after-func command-line option, C-SKY: C-SKY Options. 29564 (line 69) 29565* mlittle-endian command-line option, C-SKY: C-SKY Options. (line 14) 29566* mljump command-line option, C-SKY: C-SKY Options. (line 26) 29567* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137) 29568* MMIX assembler directive BYTE: MMIX-Pseudos. (line 101) 29569* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137) 29570* MMIX assembler directive GREG: MMIX-Pseudos. (line 53) 29571* MMIX assembler directive IS: MMIX-Pseudos. (line 44) 29572* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 29573* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29) 29574* MMIX assembler directive OCTA: MMIX-Pseudos. (line 113) 29575* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125) 29576* MMIX assembler directive TETRA: MMIX-Pseudos. (line 113) 29577* MMIX assembler directive WYDE: MMIX-Pseudos. (line 113) 29578* MMIX assembler directives: MMIX-Pseudos. (line 6) 29579* MMIX line comment characters: MMIX-Chars. (line 6) 29580* MMIX options: MMIX-Opts. (line 6) 29581* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137) 29582* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101) 29583* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137) 29584* MMIX pseudo-op GREG: MMIX-Pseudos. (line 53) 29585* MMIX pseudo-op IS: MMIX-Pseudos. (line 44) 29586* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 29587* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29) 29588* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113) 29589* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125) 29590* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113) 29591* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113) 29592* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 29593* MMIX register names: MMIX-Regs. (line 6) 29594* MMIX support: MMIX-Dependent. (line 6) 29595* mmixal differences: MMIX-mmixal. (line 6) 29596* mmp command-line option, C-SKY: C-SKY Options. (line 94) 29597* mmregs directive, TIC54X: TIC54X-Directives. (line 167) 29598* mmsg directive, TIC54X: TIC54X-Directives. (line 75) 29599* MMX, i386: i386-SIMD. (line 6) 29600* MMX, x86-64: i386-SIMD. (line 6) 29601* mnemonic compatibility, i386: i386-Mnemonics. (line 124) 29602* mnemonic suffixes, i386: i386-Variations. (line 28) 29603* mnemonic suffixes, x86-64: i386-Variations. (line 28) 29604* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 29605* mnemonics, AVR: AVR Opcodes. (line 6) 29606* mnemonics, D10V: D10V-Opcodes. (line 6) 29607* mnemonics, D30V: D30V-Opcodes. (line 6) 29608* mnemonics, H8/300: H8/300 Opcodes. (line 6) 29609* mnemonics, LM32: LM32 Opcodes. (line 6) 29610* mnemonics, OpenRISC: OpenRISC-Opcodes. (line 6) 29611* mnemonics, SH: SH Opcodes. (line 6) 29612* mnemonics, Z8000: Z8000 Opcodes. (line 6) 29613* mno-branch-stub command-line option, C-SKY: C-SKY Options. (line 34) 29614* mno-elrw command-line option, C-SKY: C-SKY Options. (line 64) 29615* mno-force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 29616* mno-istack command-line option, C-SKY: C-SKY Options. (line 82) 29617* mno-jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 29618* mno-labr command-line option, C-SKY: C-SKY Options. (line 75) 29619* mno-laf command-line option, C-SKY: C-SKY Options. (line 69) 29620* mno-link-relax command-line option, PRU: PRU Options. (line 12) 29621* mno-literals-after-func command-line option, C-SKY: C-SKY Options. 29622 (line 69) 29623* mno-ljump command-line option, C-SKY: C-SKY Options. (line 26) 29624* mno-lrw command-line option, C-SKY: C-SKY Options. (line 59) 29625* mno-warn-regname-label command-line option, PRU: PRU Options. 29626 (line 16) 29627* mnolist directive, TIC54X: TIC54X-Directives. (line 162) 29628* mnoliterals-after-br command-line option, C-SKY: C-SKY Options. 29629 (line 75) 29630* mnolrw command-line option, C-SKY: C-SKY Options. (line 59) 29631* mnps400 command-line option, ARC: ARC Options. (line 79) 29632* modifiers, M32C: M32C-Modifiers. (line 6) 29633* module layout, WebAssembly: WebAssembly-module-layout. 29634 (line 6) 29635* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 29636* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 29637 (line 12) 29638* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations. 29639 (line 6) 29640* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21) 29641* MRI compatibility mode: M. (line 6) 29642* mri directive: MRI. (line 6) 29643* MRI mode, temporarily: MRI. (line 6) 29644* msecurity command-line option, C-SKY: C-SKY Options. (line 103) 29645* MSP 430 floating point (IEEE): MSP430 Floating Point. 29646 (line 6) 29647* MSP 430 identifiers: MSP430-Chars. (line 17) 29648* MSP 430 line comment character: MSP430-Chars. (line 6) 29649* MSP 430 line separator: MSP430-Chars. (line 14) 29650* MSP 430 machine directives: MSP430 Directives. (line 6) 29651* MSP 430 macros: MSP430-Macros. (line 6) 29652* MSP 430 opcodes: MSP430 Opcodes. (line 6) 29653* MSP 430 options (none): MSP430 Options. (line 6) 29654* MSP 430 profiling capability: MSP430 Profiling Capability. 29655 (line 6) 29656* MSP 430 register names: MSP430-Regs. (line 6) 29657* MSP 430 support: MSP430-Dependent. (line 6) 29658* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 29659* mspabi_attribute directive, MSP430: MSP430 Directives. (line 38) 29660* mtrust command-line option, C-SKY: C-SKY Options. (line 106) 29661* mul instruction, i386: i386-Notes. (line 6) 29662* mul instruction, x86-64: i386-Notes. (line 6) 29663* mvdsp command-line option, C-SKY: C-SKY Options. (line 115) 29664* N32K support: NS32K-Dependent. (line 6) 29665* name: Z8000 Directives. (line 18) 29666* named section: Section. (line 6) 29667* named sections: Ld Sections. (line 8) 29668* names, symbol: Symbol Names. (line 6) 29669* naming object file: o. (line 6) 29670* NDS32 options: NDS32 Options. (line 6) 29671* NDS32 processor: NDS32-Dependent. (line 6) 29672* new page, in listings: Eject. (line 6) 29673* newblock directive, TIC54X: TIC54X-Directives. (line 173) 29674* newline (\n): Strings. (line 21) 29675* newline, required at file end: Statements. (line 14) 29676* Nios II line comment character: Nios II Chars. (line 6) 29677* Nios II line separator character: Nios II Chars. (line 6) 29678* Nios II machine directives: Nios II Directives. (line 6) 29679* Nios II machine relocations: Nios II Relocations. 29680 (line 6) 29681* Nios II opcodes: Nios II Opcodes. (line 6) 29682* Nios II options: Nios II Options. (line 6) 29683* Nios II support: NiosII-Dependent. (line 6) 29684* Nios support: NiosII-Dependent. (line 6) 29685* no-absolute-literals directive: Absolute Literals Directive. 29686 (line 6) 29687* no-force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 29688* no-jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 29689* no-longcalls directive: Longcalls Directive. 29690 (line 6) 29691* no-relax command-line option, Nios II: Nios II Options. (line 19) 29692* no-schedule directive: Schedule Directive. (line 6) 29693* no-transform directive: Transform Directive. 29694 (line 6) 29695* nodelay directive, OpenRISC: OpenRISC-Directives. 29696 (line 15) 29697* nolist directive: Nolist. (line 6) 29698* nolist directive, TIC54X: TIC54X-Directives. (line 129) 29699* nop directive: Nop. (line 6) 29700* NOP pseudo op, ARM: ARM Opcodes. (line 9) 29701* nops directive: Nops. (line 6) 29702* notes for Alpha: Alpha Notes. (line 6) 29703* notes for WebAssembly: WebAssembly-Notes. (line 6) 29704* NS32K line comment character: NS32K-Chars. (line 6) 29705* NS32K line separator: NS32K-Chars. (line 18) 29706* null-terminated strings: Asciz. (line 6) 29707* number constants: Numbers. (line 6) 29708* number of macros executed: Macro. (line 167) 29709* numbered subsections: Sub-Sections. (line 6) 29710* numbers, 16-bit: hword. (line 6) 29711* numeric values: Expressions. (line 6) 29712* nword directive, SPARC: Sparc-Directives. (line 20) 29713* Object Attribute, RISC-V: RISC-V-ATTRIBUTE. (line 6) 29714* object attributes: Object Attributes. (line 6) 29715* object file: Object. (line 6) 29716* object file format: Object Formats. (line 6) 29717* object file name: o. (line 6) 29718* object file, after errors: Z. (line 6) 29719* obsolescent directives: Deprecated. (line 6) 29720* octa directive: Octa. (line 6) 29721* octal character code (\DDD): Strings. (line 30) 29722* octal integers: Integers. (line 9) 29723* offset directive: Offset. (line 6) 29724* offset directive, V850: V850 Directives. (line 6) 29725* opcode mnemonics, VAX: VAX-opcodes. (line 6) 29726* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) 29727* opcode names, TILEPro: TILEPro Opcodes. (line 6) 29728* opcode names, Xtensa: Xtensa Opcodes. (line 6) 29729* opcode summary, AVR: AVR Opcodes. (line 6) 29730* opcode summary, D10V: D10V-Opcodes. (line 6) 29731* opcode summary, D30V: D30V-Opcodes. (line 6) 29732* opcode summary, H8/300: H8/300 Opcodes. (line 6) 29733* opcode summary, LM32: LM32 Opcodes. (line 6) 29734* opcode summary, OpenRISC: OpenRISC-Opcodes. (line 6) 29735* opcode summary, SH: SH Opcodes. (line 6) 29736* opcode summary, Z8000: Z8000 Opcodes. (line 6) 29737* opcodes for AArch64: AArch64 Opcodes. (line 6) 29738* opcodes for ARC: ARC Opcodes. (line 6) 29739* opcodes for ARM: ARM Opcodes. (line 6) 29740* opcodes for BPF: BPF Instructions. (line 6) 29741* opcodes for MSP 430: MSP430 Opcodes. (line 6) 29742* opcodes for Nios II: Nios II Opcodes. (line 6) 29743* opcodes for PRU: PRU Opcodes. (line 6) 29744* opcodes for V850: V850 Opcodes. (line 6) 29745* opcodes, M680x0: M68K-opcodes. (line 6) 29746* opcodes, M68HC11: M68HC11-opcodes. (line 6) 29747* opcodes, WebAssembly: WebAssembly-Opcodes. 29748 (line 6) 29749* OPENRISC floating point (IEEE): OpenRISC-Float. (line 6) 29750* OpenRISC line comment character: OpenRISC-Chars. (line 6) 29751* OpenRISC line separator: OpenRISC-Chars. (line 9) 29752* OPENRISC machine directives: OpenRISC-Directives. 29753 (line 6) 29754* OpenRISC opcode summary: OpenRISC-Opcodes. (line 6) 29755* OpenRISC registers: OpenRISC-Regs. (line 6) 29756* OpenRISC relocations: OpenRISC-Relocs. (line 6) 29757* OPENRISC support: OpenRISC-Dependent. (line 6) 29758* OPENRISC syntax: OpenRISC-Dependent. (line 13) 29759* operand delimiters, i386: i386-Variations. (line 15) 29760* operand delimiters, x86-64: i386-Variations. (line 15) 29761* operand notation, VAX: VAX-operands. (line 6) 29762* operands in expressions: Arguments. (line 6) 29763* operator precedence: Infix Ops. (line 11) 29764* operators, in expressions: Operators. (line 6) 29765* operators, permitted arguments: Infix Ops. (line 6) 29766* optimization, D10V: Overview. (line 714) 29767* optimization, D30V: Overview. (line 719) 29768* optimizations: Xtensa Optimizations. 29769 (line 6) 29770* Option directive: RISC-V-Directives. (line 31) 29771* option directive: RISC-V-Directives. (line 31) 29772* option directive, TIC54X: TIC54X-Directives. (line 177) 29773* option summary: Overview. (line 6) 29774* options for AArch64 (none): AArch64 Options. (line 6) 29775* options for Alpha: Alpha Options. (line 6) 29776* options for ARC: ARC Options. (line 6) 29777* options for ARM (none): ARM Options. (line 6) 29778* options for AVR (none): AVR Options. (line 6) 29779* options for Blackfin (none): Blackfin Options. (line 6) 29780* options for BPF (none): BPF Options. (line 6) 29781* options for C-SKY: C-SKY Options. (line 6) 29782* options for i386: i386-Options. (line 6) 29783* options for IA-64: IA-64 Options. (line 6) 29784* options for KVX: KVX Options. (line 6) 29785* options for LM32 (none): LM32 Options. (line 6) 29786* options for Meta: Meta Options. (line 6) 29787* options for MSP430 (none): MSP430 Options. (line 6) 29788* options for NDS32: NDS32 Options. (line 6) 29789* options for Nios II: Nios II Options. (line 6) 29790* options for PDP-11: PDP-11-Options. (line 6) 29791* options for PowerPC: PowerPC-Opts. (line 6) 29792* options for PRU: PRU Options. (line 6) 29793* options for s390: s390 Options. (line 6) 29794* options for SCORE: SCORE-Opts. (line 6) 29795* options for SPARC: Sparc-Opts. (line 6) 29796* options for TIC6X: TIC6X Options. (line 6) 29797* options for V850 (none): V850 Options. (line 6) 29798* options for VAX/VMS: VAX-Opts. (line 42) 29799* options for Visium: Visium Options. (line 6) 29800* options for x86-64: i386-Options. (line 6) 29801* options for Z80: Z80 Options. (line 6) 29802* options, all versions of assembler: Invoking. (line 6) 29803* options, command line: Command Line. (line 13) 29804* options, CRIS: CRIS-Opts. (line 6) 29805* options, D10V: D10V-Opts. (line 6) 29806* options, D30V: D30V-Opts. (line 6) 29807* options, Epiphany: Epiphany Options. (line 6) 29808* options, H8/300: H8/300 Options. (line 6) 29809* options, IP2K: IP2K-Opts. (line 6) 29810* options, M32C: M32C-Opts. (line 6) 29811* options, M32R: M32R-Opts. (line 6) 29812* options, M680x0: M68K-Opts. (line 6) 29813* options, M68HC11: M68HC11-Opts. (line 6) 29814* options, MMIX: MMIX-Opts. (line 6) 29815* options, PJ: PJ Options. (line 6) 29816* options, RL78: RL78-Opts. (line 6) 29817* options, RX: RX-Opts. (line 6) 29818* options, S12Z: S12Z Options. (line 6) 29819* options, SH: SH Options. (line 6) 29820* options, TIC54X: TIC54X-Opts. (line 6) 29821* options, XGATE: XGATE-Opts. (line 6) 29822* options, Z8000: Z8000 Options. (line 6) 29823* org directive: Org. (line 6) 29824* other attribute, of a.out symbol: Symbol Other. (line 6) 29825* output file: Object. (line 6) 29826* output section padding: no-pad-sections. (line 6) 29827* p2align directive: P2align. (line 6) 29828* p2alignl directive: P2align. (line 30) 29829* p2alignw directive: P2align. (line 30) 29830* padding the location counter: Align. (line 6) 29831* padding the location counter given a power of two: P2align. 29832 (line 6) 29833* padding the location counter given number of bytes: Balign. 29834 (line 6) 29835* page, in listings: Eject. (line 6) 29836* paper size, for listings: Psize. (line 6) 29837* paths for .include: I. (line 6) 29838* patterns, writing in memory: Fill. (line 6) 29839* PDP-11 comments: PDP-11-Syntax. (line 16) 29840* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 29841* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 29842* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 29843* PDP-11 line separator: PDP-11-Syntax. (line 19) 29844* PDP-11 support: PDP-11-Dependent. (line 6) 29845* PDP-11 syntax: PDP-11-Syntax. (line 6) 29846* PIC code generation for ARM: ARM Options. (line 435) 29847* PIC code generation for M32R: M32R-Opts. (line 42) 29848* pic command-line option, C-SKY: C-SKY Options. (line 22) 29849* PIC selection, MIPS: MIPS Options. (line 21) 29850* PJ endianness: Overview. (line 835) 29851* PJ line comment character: PJ-Chars. (line 6) 29852* PJ line separator: PJ-Chars. (line 14) 29853* PJ options: PJ Options. (line 6) 29854* PJ support: PJ-Dependent. (line 6) 29855* plus, permitted arguments: Infix Ops. (line 45) 29856* pmem directive, PRU: PRU Relocations. (line 6) 29857* popsection directive: PopSection. (line 6) 29858* Position-independent code, CRIS: CRIS-Opts. (line 27) 29859* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 29860* PowerPC architectures: PowerPC-Opts. (line 6) 29861* PowerPC directives: PowerPC-Pseudo. (line 6) 29862* PowerPC line comment character: PowerPC-Chars. (line 6) 29863* PowerPC line separator: PowerPC-Chars. (line 18) 29864* PowerPC options: PowerPC-Opts. (line 6) 29865* PowerPC support: PPC-Dependent. (line 6) 29866* precedence of operators: Infix Ops. (line 11) 29867* precision, floating point: Flonums. (line 6) 29868* prefix operators: Prefix Ops. (line 6) 29869* prefixes, i386: i386-Prefixes. (line 6) 29870* preprocessing: Preprocessing. (line 6) 29871* preprocessing, turning on and off: Preprocessing. (line 28) 29872* previous directive: Previous. (line 6) 29873* primary attributes, COFF symbols: COFF Symbols. (line 13) 29874* print directive: Print. (line 6) 29875* proc directive, OpenRISC: OpenRISC-Directives. 29876 (line 20) 29877* proc directive, SPARC: Sparc-Directives. (line 25) 29878* Processor Identification register, ARC: ARC-Regs. (line 51) 29879* profiler directive, MSP 430: MSP430 Directives. (line 26) 29880* profiling capability for MSP 430: MSP430 Profiling Capability. 29881 (line 6) 29882* Program Counter, ARC: ARC-Regs. (line 54) 29883* protected directive: Protected. (line 6) 29884* PRU line comment character: PRU Chars. (line 6) 29885* PRU machine directives: PRU Directives. (line 6) 29886* PRU machine relocations: PRU Relocations. (line 6) 29887* PRU opcodes: PRU Opcodes. (line 6) 29888* PRU options: PRU Options. (line 6) 29889* PRU support: PRU-Dependent. (line 6) 29890* psect directive, Z80: Z80 Directives. (line 58) 29891* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50) 29892* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 29893* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18) 29894* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137) 29895* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101) 29896* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137) 29897* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53) 29898* pseudo-op IS, MMIX: MMIX-Pseudos. (line 44) 29899* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 29900* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29) 29901* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113) 29902* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125) 29903* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113) 29904* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113) 29905* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) 29906* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 29907* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 29908* pseudo-ops for branch, VAX: VAX-branch. (line 6) 29909* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 29910* pseudo-ops, machine independent: Pseudo Ops. (line 6) 29911* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 29912* psize directive: Psize. (line 6) 29913* PSR bits: IA-64-Bits. (line 6) 29914* pstring directive, TIC54X: TIC54X-Directives. (line 206) 29915* psw register, V850: V850-Regs. (line 80) 29916* purgem directive: Purgem. (line 6) 29917* purpose of GNU assembler: GNU Assembler. (line 12) 29918* pushsection directive: PushSection. (line 6) 29919* quad directive: Quad. (line 6) 29920* quad directive, i386: i386-Float. (line 22) 29921* quad directive, x86-64: i386-Float. (line 22) 29922* real-mode code, i386: i386-16bit. (line 6) 29923* ref directive, TIC54X: TIC54X-Directives. (line 101) 29924* refsym directive, MSP 430: MSP430 Directives. (line 30) 29925* register directive, SPARC: Sparc-Directives. (line 29) 29926* register name prefix character, ARC: ARC-Chars. (line 7) 29927* register names, AArch64: AArch64-Regs. (line 6) 29928* register names, Alpha: Alpha-Regs. (line 6) 29929* register names, ARC: ARC-Regs. (line 6) 29930* register names, ARM: ARM-Regs. (line 6) 29931* register names, AVR: AVR-Regs. (line 6) 29932* register names, BPF: BPF Registers. (line 6) 29933* register names, CRIS: CRIS-Regs. (line 6) 29934* register names, H8/300: H8/300-Regs. (line 6) 29935* register names, IA-64: IA-64-Regs. (line 6) 29936* register names, LM32: LM32-Regs. (line 6) 29937* register names, MMIX: MMIX-Regs. (line 6) 29938* register names, MSP 430: MSP430-Regs. (line 6) 29939* register names, OpenRISC: OpenRISC-Regs. (line 6) 29940* register names, S12Z: S12Z Addressing Modes. 29941 (line 28) 29942* register names, Sparc: Sparc-Regs. (line 6) 29943* register names, TILE-Gx: TILE-Gx Registers. (line 6) 29944* register names, TILEPro: TILEPro Registers. (line 6) 29945* register names, V850: V850-Regs. (line 6) 29946* register names, VAX: VAX-operands. (line 17) 29947* register names, Visium: Visium Registers. (line 6) 29948* register names, Xtensa: Xtensa Registers. (line 6) 29949* register names, Z80: Z80-Regs. (line 6) 29950* register naming, s390: s390 Register. (line 6) 29951* register notation, S12Z: S12Z Register Notation. 29952 (line 6) 29953* register operands, i386: i386-Variations. (line 15) 29954* register operands, x86-64: i386-Variations. (line 15) 29955* registers, D10V: D10V-Regs. (line 6) 29956* registers, D30V: D30V-Regs. (line 6) 29957* registers, i386: i386-Regs. (line 6) 29958* registers, Meta: Meta-Regs. (line 6) 29959* registers, SH: SH-Regs. (line 6) 29960* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 29961* registers, x86-64: i386-Regs. (line 6) 29962* registers, Z8000: Z8000-Regs. (line 6) 29963* relax-all command-line option, Nios II: Nios II Options. (line 13) 29964* relax-section command-line option, Nios II: Nios II Options. 29965 (line 6) 29966* relaxation: Xtensa Relaxation. (line 6) 29967* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 29968 (line 43) 29969* relaxation of branch instructions: Xtensa Branch Relaxation. 29970 (line 6) 29971* relaxation of call instructions: Xtensa Call Relaxation. 29972 (line 6) 29973* relaxation of immediate fields: Xtensa Immediate Relaxation. 29974 (line 6) 29975* relaxation of jump instructions: Xtensa Jump Relaxation. 29976 (line 6) 29977* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 29978 (line 23) 29979* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 29980 (line 23) 29981* relaxation of L32I instructions: Xtensa Immediate Relaxation. 29982 (line 23) 29983* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 29984 (line 23) 29985* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 29986 (line 12) 29987* reloc directive: Reloc. (line 6) 29988* relocation: Sections. (line 6) 29989* relocation example: Ld Sections. (line 40) 29990* relocations, AArch64: AArch64-Relocations. 29991 (line 6) 29992* relocations, Alpha: Alpha-Relocs. (line 6) 29993* relocations, OpenRISC: OpenRISC-Relocs. (line 6) 29994* relocations, Sparc: Sparc-Relocs. (line 6) 29995* relocations, WebAssembly: WebAssembly-Relocs. (line 6) 29996* repeat prefixes, i386: i386-Prefixes. (line 44) 29997* reporting bugs in assembler: Reporting Bugs. (line 6) 29998* rept directive: Rept. (line 6) 29999* reserve directive, SPARC: Sparc-Directives. (line 39) 30000* return instructions, i386: i386-Variations. (line 45) 30001* return instructions, x86-64: i386-Variations. (line 45) 30002* REX prefixes, i386: i386-Prefixes. (line 46) 30003* RISC-V custom (vendor-defined) extensions: RISC-V-CustomExts. 30004 (line 6) 30005* RISC-V floating point (IEEE): RISC-V-Floating-Point. 30006 (line 6) 30007* RISC-V instruction formats: RISC-V-Formats. (line 6) 30008* RISC-V machine directives: RISC-V-Directives. (line 6) 30009* RISC-V support: RISC-V-Dependent. (line 6) 30010* RL78 assembler directives: RL78-Directives. (line 6) 30011* RL78 line comment character: RL78-Chars. (line 6) 30012* RL78 line separator: RL78-Chars. (line 14) 30013* RL78 modifiers: RL78-Modifiers. (line 6) 30014* RL78 options: RL78-Opts. (line 6) 30015* RL78 support: RL78-Dependent. (line 6) 30016* rsect: Z8000 Directives. (line 52) 30017* RX assembler directive .3byte: RX-Directives. (line 9) 30018* RX assembler directive .fetchalign: RX-Directives. (line 13) 30019* RX assembler directives: RX-Directives. (line 6) 30020* RX floating point: RX-Float. (line 6) 30021* RX line comment character: RX-Chars. (line 6) 30022* RX line separator: RX-Chars. (line 14) 30023* RX modifiers: RX-Modifiers. (line 6) 30024* RX options: RX-Opts. (line 6) 30025* RX support: RX-Dependent. (line 6) 30026* S12Z addressing modes: S12Z Addressing Modes. 30027 (line 6) 30028* S12Z line separator: S12Z Syntax Overview. 30029 (line 41) 30030* S12Z options: S12Z Options. (line 6) 30031* S12Z support: S12Z-Dependent. (line 8) 30032* S12Z syntax: S12Z Syntax. (line 12) 30033* s390 floating point: s390 Floating Point. 30034 (line 6) 30035* s390 instruction aliases: s390 Aliases. (line 6) 30036* s390 instruction formats: s390 Formats. (line 6) 30037* s390 instruction marker: s390 Instruction Marker. 30038 (line 6) 30039* s390 instruction mnemonics: s390 Mnemonics. (line 6) 30040* s390 instruction operand modifier: s390 Operand Modifier. 30041 (line 6) 30042* s390 instruction operands: s390 Operands. (line 6) 30043* s390 instruction syntax: s390 Syntax. (line 6) 30044* s390 line comment character: s390 Characters. (line 6) 30045* s390 line separator: s390 Characters. (line 13) 30046* s390 literal pool entries: s390 Literal Pool Entries. 30047 (line 6) 30048* s390 options: s390 Options. (line 6) 30049* s390 register naming: s390 Register. (line 6) 30050* s390 support: S/390-Dependent. (line 6) 30051* Saved User Stack Pointer, ARC: ARC-Regs. (line 73) 30052* sblock directive, TIC54X: TIC54X-Directives. (line 180) 30053* sbttl directive: Sbttl. (line 6) 30054* schedule directive: Schedule Directive. (line 6) 30055* scl directive: Scl. (line 6) 30056* SCORE architectures: SCORE-Opts. (line 6) 30057* SCORE directives: SCORE-Pseudo. (line 6) 30058* SCORE line comment character: SCORE-Chars. (line 6) 30059* SCORE line separator: SCORE-Chars. (line 14) 30060* SCORE options: SCORE-Opts. (line 6) 30061* SCORE processor: SCORE-Dependent. (line 6) 30062* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 30063* search path for .include: I. (line 6) 30064* sect directive, TIC54X: TIC54X-Directives. (line 186) 30065* section directive (COFF version): Section. (line 16) 30066* section directive (ELF version): Section. (line 67) 30067* section directive, V850: V850 Directives. (line 9) 30068* section name substitution: Section. (line 71) 30069* section override prefixes, i386: i386-Prefixes. (line 23) 30070* Section Stack: PopSection. (line 6) 30071* Section Stack <1>: Previous. (line 6) 30072* Section Stack <2>: PushSection. (line 6) 30073* Section Stack <3>: Section. (line 62) 30074* Section Stack <4>: SubSection. (line 6) 30075* section-relative addressing: Secs Background. (line 65) 30076* sections: Sections. (line 6) 30077* sections in messages, internal: As Sections. (line 6) 30078* sections, i386: i386-Variations. (line 51) 30079* sections, named: Ld Sections. (line 8) 30080* sections, x86-64: i386-Variations. (line 51) 30081* seg directive, SPARC: Sparc-Directives. (line 44) 30082* segm: Z8000 Directives. (line 10) 30083* set at directive, Nios II: Nios II Directives. (line 35) 30084* set break directive, Nios II: Nios II Directives. (line 43) 30085* set directive: Set. (line 6) 30086* set directive, Nios II: Nios II Directives. (line 57) 30087* set directive, TIC54X: TIC54X-Directives. (line 189) 30088* set noat directive, Nios II: Nios II Directives. (line 31) 30089* set nobreak directive, Nios II: Nios II Directives. (line 39) 30090* set norelax directive, Nios II: Nios II Directives. (line 46) 30091* set no_warn_regname_label directive, PRU: PRU Directives. (line 28) 30092* set relaxall directive, Nios II: Nios II Directives. (line 53) 30093* set relaxsection directive, Nios II: Nios II Directives. (line 49) 30094* SH addressing modes: SH-Addressing. (line 6) 30095* SH floating point (IEEE): SH Floating Point. (line 6) 30096* SH line comment character: SH-Chars. (line 6) 30097* SH line separator: SH-Chars. (line 8) 30098* SH machine directives: SH Directives. (line 6) 30099* SH opcode summary: SH Opcodes. (line 6) 30100* SH options: SH Options. (line 6) 30101* SH registers: SH-Regs. (line 6) 30102* SH support: SH-Dependent. (line 6) 30103* shigh directive, M32R: M32R-Directives. (line 26) 30104* short directive: Short. (line 6) 30105* short directive, TIC54X: TIC54X-Directives. (line 109) 30106* signatures, WebAssembly: WebAssembly-Signatures. 30107 (line 6) 30108* SIMD, i386: i386-SIMD. (line 6) 30109* SIMD, x86-64: i386-SIMD. (line 6) 30110* single character constant: Chars. (line 6) 30111* single directive: Single. (line 6) 30112* single directive, i386: i386-Float. (line 14) 30113* single directive, x86-64: i386-Float. (line 14) 30114* single quote, Z80: Z80-Chars. (line 20) 30115* sixteen bit integers: hword. (line 6) 30116* sixteen byte integer: Octa. (line 6) 30117* size directive (COFF version): Size. (line 11) 30118* size directive (ELF version): Size. (line 19) 30119* size modifiers, D10V: D10V-Size. (line 6) 30120* size modifiers, D30V: D30V-Size. (line 6) 30121* size modifiers, M680x0: M68K-Syntax. (line 8) 30122* size prefixes, i386: i386-Prefixes. (line 27) 30123* size suffixes, H8/300: H8/300 Opcodes. (line 160) 30124* size, translations, Sparc: Sparc-Size-Translations. 30125 (line 6) 30126* sizes operands, i386: i386-Variations. (line 28) 30127* sizes operands, x86-64: i386-Variations. (line 28) 30128* skip directive: Skip. (line 6) 30129* skip directive, M680x0: M68K-Directives. (line 19) 30130* skip directive, SPARC: Sparc-Directives. (line 48) 30131* sleb128 directive: Sleb128. (line 6) 30132* small data, MIPS: MIPS Small Data. (line 6) 30133* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides. 30134 (line 11) 30135* SOM symbol attributes: SOM Symbols. (line 6) 30136* source program: Input Files. (line 6) 30137* source, destination operands; i386: i386-Variations. (line 21) 30138* source, destination operands; x86-64: i386-Variations. (line 21) 30139* sp register: Xtensa Registers. (line 6) 30140* sp register, V850: V850-Regs. (line 12) 30141* space directive: Space. (line 6) 30142* space directive, TIC54X: TIC54X-Directives. (line 194) 30143* space used, maximum for assembly: statistics. (line 6) 30144* SPARC architectures: Sparc-Opts. (line 6) 30145* Sparc constants: Sparc-Constants. (line 6) 30146* SPARC data alignment: Sparc-Aligned-Data. (line 6) 30147* SPARC floating point (IEEE): Sparc-Float. (line 6) 30148* Sparc line comment character: Sparc-Chars. (line 6) 30149* Sparc line separator: Sparc-Chars. (line 14) 30150* SPARC machine directives: Sparc-Directives. (line 6) 30151* SPARC options: Sparc-Opts. (line 6) 30152* Sparc registers: Sparc-Regs. (line 6) 30153* Sparc relocations: Sparc-Relocs. (line 6) 30154* Sparc size translations: Sparc-Size-Translations. 30155 (line 6) 30156* SPARC support: Sparc-Dependent. (line 6) 30157* SPARC syntax: Sparc-Aligned-Data. (line 21) 30158* special characters, M680x0: M68K-Chars. (line 6) 30159* special purpose registers, MSP 430: MSP430-Regs. (line 11) 30160* sslist directive, TIC54X: TIC54X-Directives. (line 201) 30161* ssnolist directive, TIC54X: TIC54X-Directives. (line 201) 30162* stabd directive: Stab. (line 38) 30163* stabn directive: Stab. (line 49) 30164* stabs directive: Stab. (line 52) 30165* stabX directives: Stab. (line 6) 30166* stack pointer, ARC: ARC-Regs. (line 20) 30167* standard assembler sections: Secs Background. (line 27) 30168* standard input, as input file: Command Line. (line 10) 30169* statement separator character: Statements. (line 6) 30170* statement separator, AArch64: AArch64-Chars. (line 10) 30171* statement separator, Alpha: Alpha-Chars. (line 11) 30172* statement separator, ARC: ARC-Chars. (line 27) 30173* statement separator, ARM: ARM-Chars. (line 14) 30174* statement separator, AVR: AVR-Chars. (line 14) 30175* statement separator, BPF: BPF Special Characters. 30176 (line 13) 30177* statement separator, CR16: CR16-Chars. (line 12) 30178* statement separator, Epiphany: Epiphany-Chars. (line 14) 30179* statement separator, H8/300: H8/300-Chars. (line 8) 30180* statement separator, i386: i386-Chars. (line 18) 30181* statement separator, IA-64: IA-64-Chars. (line 8) 30182* statement separator, IP2K: IP2K-Chars. (line 14) 30183* statement separator, LM32: LM32-Chars. (line 12) 30184* statement separator, M32C: M32C-Chars. (line 14) 30185* statement separator, M68HC11: M68HC11-Syntax. (line 26) 30186* statement separator, Meta: Meta-Chars. (line 8) 30187* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) 30188* statement separator, MIPS: MIPS-Chars. (line 14) 30189* statement separator, MSP 430: MSP430-Chars. (line 14) 30190* statement separator, NS32K: NS32K-Chars. (line 18) 30191* statement separator, OpenRISC: OpenRISC-Chars. (line 9) 30192* statement separator, PJ: PJ-Chars. (line 14) 30193* statement separator, PowerPC: PowerPC-Chars. (line 18) 30194* statement separator, RL78: RL78-Chars. (line 14) 30195* statement separator, RX: RX-Chars. (line 14) 30196* statement separator, S12Z: S12Z Syntax Overview. 30197 (line 41) 30198* statement separator, s390: s390 Characters. (line 13) 30199* statement separator, SCORE: SCORE-Chars. (line 14) 30200* statement separator, SH: SH-Chars. (line 8) 30201* statement separator, Sparc: Sparc-Chars. (line 14) 30202* statement separator, TIC54X: TIC54X-Chars. (line 17) 30203* statement separator, TIC6X: TIC6X Syntax. (line 13) 30204* statement separator, V850: V850-Chars. (line 13) 30205* statement separator, VAX: VAX-Chars. (line 14) 30206* statement separator, Visium: Visium Characters. (line 14) 30207* statement separator, XGATE: XGATE-Syntax. (line 25) 30208* statement separator, XStormy16: XStormy16-Chars. (line 14) 30209* statement separator, Z80: Z80-Chars. (line 13) 30210* statement separator, Z8000: Z8000-Chars. (line 13) 30211* statements, structure of: Statements. (line 6) 30212* statistics, about assembly: statistics. (line 6) 30213* Status register, ARC: ARC-Regs. (line 57) 30214* STATUS32 saved on exception, ARC: ARC-Regs. (line 82) 30215* stopping the assembly: Abort. (line 6) 30216* Stored STATUS32 register on entry to level P0 interrupts, ARC: ARC-Regs. 30217 (line 69) 30218* string constants: Strings. (line 6) 30219* string directive: String. (line 8) 30220* string directive on HPPA: HPPA Directives. (line 137) 30221* string directive, TIC54X: TIC54X-Directives. (line 206) 30222* string literals: Ascii. (line 6) 30223* string, copying to object file: String. (line 8) 30224* string16 directive: String. (line 8) 30225* string16, copying to object file: String. (line 8) 30226* string32 directive: String. (line 8) 30227* string32, copying to object file: String. (line 8) 30228* string64 directive: String. (line 8) 30229* string64, copying to object file: String. (line 8) 30230* string8 directive: String. (line 8) 30231* string8, copying to object file: String. (line 8) 30232* struct directive: Struct. (line 6) 30233* struct directive, TIC54X: TIC54X-Directives. (line 214) 30234* structure debugging, COFF: Tag. (line 6) 30235* sub-instruction ordering, D10V: D10V-Chars. (line 14) 30236* sub-instruction ordering, D30V: D30V-Chars. (line 14) 30237* sub-instructions, D10V: D10V-Subs. (line 6) 30238* sub-instructions, D30V: D30V-Subs. (line 6) 30239* subexpressions: Arguments. (line 24) 30240* subsection directive: SubSection. (line 6) 30241* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 30242* subtitles for listings: Sbttl. (line 6) 30243* subtraction, permitted arguments: Infix Ops. (line 50) 30244* summary of options: Overview. (line 6) 30245* support: HPPA-Dependent. (line 6) 30246* supporting files, including: Include. (line 6) 30247* suppressing warnings: W. (line 11) 30248* sval: Z8000 Directives. (line 33) 30249* symbol attributes: Symbol Attributes. (line 6) 30250* symbol attributes, a.out: a.out Symbols. (line 6) 30251* symbol attributes, COFF: COFF Symbols. (line 6) 30252* symbol attributes, SOM: SOM Symbols. (line 6) 30253* symbol descriptor, COFF: Desc. (line 6) 30254* symbol modifiers: AVR-Modifiers. (line 12) 30255* symbol modifiers <1>: LM32-Modifiers. (line 12) 30256* symbol modifiers <2>: M32C-Modifiers. (line 11) 30257* symbol modifiers <3>: M68HC11-Modifiers. (line 12) 30258* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) 30259* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) 30260* symbol names: Symbol Names. (line 6) 30261* symbol names, $ in: D10V-Chars. (line 46) 30262* symbol names, $ in <1>: D30V-Chars. (line 70) 30263* symbol names, $ in <2>: Meta-Chars. (line 10) 30264* symbol names, $ in <3>: SH-Chars. (line 15) 30265* symbol names, local: Symbol Names. (line 40) 30266* symbol names, temporary: Symbol Names. (line 53) 30267* symbol prefix character, ARC: ARC-Chars. (line 20) 30268* symbol storage class (COFF): Scl. (line 6) 30269* symbol type: Symbol Type. (line 6) 30270* symbol type, COFF: Type. (line 11) 30271* symbol type, ELF: Type. (line 22) 30272* symbol value: Symbol Value. (line 6) 30273* symbol value, setting: Set. (line 6) 30274* symbol values, assigning: Setting Symbols. (line 6) 30275* symbol versioning: Symver. (line 6) 30276* symbol, common: Comm. (line 6) 30277* symbol, making visible to linker: Global. (line 6) 30278* symbolic debuggers, information for: Stab. (line 6) 30279* symbols: Symbols. (line 6) 30280* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 30281* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 30282* symbols, assigning values to: Equ. (line 6) 30283* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 30284* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 30285* symbols, local common: Lcomm. (line 6) 30286* symver directive: Symver. (line 6) 30287* syntax compatibility, i386: i386-Variations. (line 6) 30288* syntax compatibility, x86-64: i386-Variations. (line 6) 30289* syntax, AVR: AVR-Modifiers. (line 6) 30290* syntax, Blackfin: Blackfin Syntax. (line 6) 30291* syntax, D10V: D10V-Syntax. (line 6) 30292* syntax, D30V: D30V-Syntax. (line 6) 30293* syntax, LM32: LM32-Modifiers. (line 6) 30294* syntax, M680x0: M68K-Syntax. (line 8) 30295* syntax, M68HC11: M68HC11-Syntax. (line 6) 30296* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) 30297* syntax, machine-independent: Syntax. (line 6) 30298* syntax, OPENRISC: OpenRISC-Dependent. (line 12) 30299* syntax, RL78: RL78-Modifiers. (line 6) 30300* syntax, RX: RX-Modifiers. (line 6) 30301* syntax, S12Z: S12Z Syntax. (line 11) 30302* syntax, SPARC: Sparc-Aligned-Data. (line 20) 30303* syntax, TILE-Gx: TILE-Gx Syntax. (line 6) 30304* syntax, TILEPro: TILEPro Syntax. (line 6) 30305* syntax, XGATE: XGATE-Syntax. (line 6) 30306* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 30307* tab (\t): Strings. (line 27) 30308* tab directive, TIC54X: TIC54X-Directives. (line 245) 30309* tag directive: Tag. (line 6) 30310* tag directive, TIC54X: TIC54X-Directives. (line 214) 30311* tag directive, TIC54X <1>: TIC54X-Directives. (line 248) 30312* TBM, i386: i386-TBM. (line 6) 30313* TBM, x86-64: i386-TBM. (line 6) 30314* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 30315* temporary symbol names: Symbol Names. (line 53) 30316* text and data sections, joining: R. (line 6) 30317* text directive: Text. (line 6) 30318* text section: Ld Sections. (line 9) 30319* tfloat directive, i386: i386-Float. (line 14) 30320* tfloat directive, x86-64: i386-Float. (line 14) 30321* Thumb support: ARM-Dependent. (line 6) 30322* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 30323* TIC54X line comment character: TIC54X-Chars. (line 6) 30324* TIC54X line separator: TIC54X-Chars. (line 17) 30325* TIC54X machine directives: TIC54X-Directives. (line 6) 30326* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 30327* TIC54X options: TIC54X-Opts. (line 6) 30328* TIC54X subsym builtins: TIC54X-Macros. (line 16) 30329* TIC54X support: TIC54X-Dependent. (line 6) 30330* TIC54X-specific macros: TIC54X-Macros. (line 6) 30331* TIC6X big-endian output: TIC6X Options. (line 46) 30332* TIC6X line comment character: TIC6X Syntax. (line 6) 30333* TIC6X line separator: TIC6X Syntax. (line 13) 30334* TIC6X little-endian output: TIC6X Options. (line 46) 30335* TIC6X machine directives: TIC6X Directives. (line 6) 30336* TIC6X options: TIC6X Options. (line 6) 30337* TIC6X support: TIC6X-Dependent. (line 6) 30338* TILE-Gx machine directives: TILE-Gx Directives. (line 6) 30339* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6) 30340* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6) 30341* TILE-Gx register names: TILE-Gx Registers. (line 6) 30342* TILE-Gx support: TILE-Gx-Dependent. (line 6) 30343* TILE-Gx syntax: TILE-Gx Syntax. (line 6) 30344* TILEPro machine directives: TILEPro Directives. (line 6) 30345* TILEPro modifiers: TILEPro Modifiers. (line 6) 30346* TILEPro opcode names: TILEPro Opcodes. (line 6) 30347* TILEPro register names: TILEPro Registers. (line 6) 30348* TILEPro support: TILEPro-Dependent. (line 6) 30349* TILEPro syntax: TILEPro Syntax. (line 6) 30350* time, total for assembly: statistics. (line 6) 30351* title directive: Title. (line 6) 30352* tls_common directive: Tls_common. (line 6) 30353* tls_gd directive, Nios II: Nios II Relocations. 30354 (line 38) 30355* tls_ie directive, Nios II: Nios II Relocations. 30356 (line 38) 30357* tls_ldm directive, Nios II: Nios II Relocations. 30358 (line 38) 30359* tls_ldo directive, Nios II: Nios II Relocations. 30360 (line 38) 30361* tls_le directive, Nios II: Nios II Relocations. 30362 (line 38) 30363* TMS320C6X support: TIC6X-Dependent. (line 6) 30364* tp register, V850: V850-Regs. (line 16) 30365* transform directive: Transform Directive. 30366 (line 6) 30367* trusted compiler: f. (line 6) 30368* turning preprocessing on and off: Preprocessing. (line 28) 30369* two-byte integer: 2byte. (line 6) 30370* type directive (COFF version): Type. (line 11) 30371* type directive (ELF version): Type. (line 22) 30372* type of a symbol: Symbol Type. (line 6) 30373* ualong directive, SH: SH Directives. (line 6) 30374* uaquad directive, SH: SH Directives. (line 6) 30375* uaword directive, SH: SH Directives. (line 6) 30376* ubyte directive, TIC54X: TIC54X-Directives. (line 34) 30377* uchar directive, TIC54X: TIC54X-Directives. (line 34) 30378* uhalf directive, TIC54X: TIC54X-Directives. (line 109) 30379* uint directive, TIC54X: TIC54X-Directives. (line 109) 30380* uleb128 directive: Uleb128. (line 6) 30381* ulong directive, TIC54X: TIC54X-Directives. (line 133) 30382* undefined section: Ld Sections. (line 36) 30383* union directive, TIC54X: TIC54X-Directives. (line 248) 30384* unsegm: Z8000 Directives. (line 14) 30385* usect directive, TIC54X: TIC54X-Directives. (line 260) 30386* ushort directive, TIC54X: TIC54X-Directives. (line 109) 30387* uword directive, TIC54X: TIC54X-Directives. (line 109) 30388* V850 command-line options: V850 Options. (line 9) 30389* V850 floating point (IEEE): V850 Floating Point. 30390 (line 6) 30391* V850 line comment character: V850-Chars. (line 6) 30392* V850 line separator: V850-Chars. (line 13) 30393* V850 machine directives: V850 Directives. (line 6) 30394* V850 opcodes: V850 Opcodes. (line 6) 30395* V850 options (none): V850 Options. (line 6) 30396* V850 register names: V850-Regs. (line 6) 30397* V850 support: V850-Dependent. (line 6) 30398* val directive: Val. (line 6) 30399* value attribute, COFF: Val. (line 6) 30400* value directive: i386-Directives. (line 26) 30401* value of a symbol: Symbol Value. (line 6) 30402* var directive, TIC54X: TIC54X-Directives. (line 270) 30403* VAX bitfields not supported: VAX-no. (line 6) 30404* VAX branch improvement: VAX-branch. (line 6) 30405* VAX command-line options ignored: VAX-Opts. (line 6) 30406* VAX displacement sizing character: VAX-operands. (line 12) 30407* VAX floating point: VAX-float. (line 6) 30408* VAX immediate character: VAX-operands. (line 6) 30409* VAX indirect character: VAX-operands. (line 9) 30410* VAX line comment character: VAX-Chars. (line 6) 30411* VAX line separator: VAX-Chars. (line 14) 30412* VAX machine directives: VAX-directives. (line 6) 30413* VAX opcode mnemonics: VAX-opcodes. (line 6) 30414* VAX operand notation: VAX-operands. (line 6) 30415* VAX register names: VAX-operands. (line 17) 30416* VAX support: Vax-Dependent. (line 6) 30417* Vax-11 C compatibility: VAX-Opts. (line 42) 30418* VAX/VMS options: VAX-Opts. (line 42) 30419* version directive: Version. (line 6) 30420* version directive, TIC54X: TIC54X-Directives. (line 274) 30421* version of assembler: v. (line 6) 30422* versions of symbols: Symver. (line 6) 30423* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides. 30424 (line 52) 30425* visibility: Hidden. (line 6) 30426* visibility <1>: Internal. (line 6) 30427* visibility <2>: Protected. (line 6) 30428* Visium line comment character: Visium Characters. (line 6) 30429* Visium line separator: Visium Characters. (line 14) 30430* Visium options: Visium Options. (line 6) 30431* Visium registers: Visium Registers. (line 6) 30432* Visium support: Visium-Dependent. (line 6) 30433* VMS (VAX) options: VAX-Opts. (line 42) 30434* vtable_entry directive: VTableEntry. (line 6) 30435* vtable_inherit directive: VTableInherit. (line 6) 30436* warning directive: Warning. (line 6) 30437* warning for altered difference tables: K. (line 6) 30438* warning messages: Errors. (line 6) 30439* warnings, causing error: W. (line 16) 30440* warnings, M32R: M32R-Warnings. (line 6) 30441* warnings, suppressing: W. (line 11) 30442* warnings, switching on: W. (line 19) 30443* weak directive: Weak. (line 6) 30444* weakref directive: Weakref. (line 6) 30445* WebAssembly floating point (IEEE): WebAssembly-Floating-Point. 30446 (line 6) 30447* WebAssembly line comment character: WebAssembly-Chars. (line 6) 30448* WebAssembly module layout: WebAssembly-module-layout. 30449 (line 6) 30450* WebAssembly notes: WebAssembly-Notes. (line 6) 30451* WebAssembly opcodes: WebAssembly-Opcodes. 30452 (line 6) 30453* WebAssembly relocations: WebAssembly-Relocs. (line 6) 30454* WebAssembly signatures: WebAssembly-Signatures. 30455 (line 6) 30456* WebAssembly support: WebAssembly-Dependent. 30457 (line 6) 30458* WebAssembly Syntax: WebAssembly-Syntax. (line 6) 30459* whitespace: Whitespace. (line 6) 30460* whitespace, removed by preprocessor: Preprocessing. (line 7) 30461* wide floating point directives, VAX: VAX-directives. (line 9) 30462* width directive, TIC54X: TIC54X-Directives. (line 125) 30463* Width of continuation lines of disassembly output: listing. 30464 (line 21) 30465* Width of first line disassembly output: listing. (line 16) 30466* Width of source line output: listing. (line 28) 30467* wmsg directive, TIC54X: TIC54X-Directives. (line 75) 30468* word aligned program counter, ARC: ARC-Regs. (line 44) 30469* word directive: Word. (line 6) 30470* word directive, BPF: BPF Directives. (line 12) 30471* word directive, H8/300: H8/300 Directives. (line 6) 30472* word directive, i386: i386-Float. (line 22) 30473* word directive, Nios II: Nios II Directives. (line 13) 30474* word directive, OpenRISC: OpenRISC-Directives. 30475 (line 12) 30476* word directive, PRU: PRU Directives. (line 10) 30477* word directive, SPARC: Sparc-Directives. (line 51) 30478* word directive, TIC54X: TIC54X-Directives. (line 109) 30479* word directive, x86-64: i386-Float. (line 22) 30480* writing patterns in memory: Fill. (line 6) 30481* wval: Z8000 Directives. (line 24) 30482* x86 machine directives: i386-Directives. (line 6) 30483* x86-64 arch directive: i386-Arch. (line 6) 30484* x86-64 att_syntax pseudo op: i386-Variations. (line 6) 30485* x86-64 conversion instructions: i386-Mnemonics. (line 69) 30486* x86-64 extension instructions: i386-Mnemonics. (line 88) 30487* x86-64 floating point: i386-Float. (line 6) 30488* x86-64 immediate operands: i386-Variations. (line 15) 30489* x86-64 instruction naming: i386-Mnemonics. (line 9) 30490* x86-64 intel_syntax pseudo op: i386-Variations. (line 6) 30491* x86-64 jump optimization: i386-Jumps. (line 6) 30492* x86-64 jump, call, return: i386-Variations. (line 45) 30493* x86-64 jump/call operands: i386-Variations. (line 15) 30494* x86-64 memory references: i386-Memory. (line 6) 30495* x86-64 options: i386-Options. (line 6) 30496* x86-64 register operands: i386-Variations. (line 15) 30497* x86-64 registers: i386-Regs. (line 6) 30498* x86-64 sections: i386-Variations. (line 51) 30499* x86-64 size suffixes: i386-Variations. (line 28) 30500* x86-64 source, destination operands: i386-Variations. (line 21) 30501* x86-64 support: i386-Dependent. (line 6) 30502* x86-64 syntax compatibility: i386-Variations. (line 6) 30503* xdef directive, Z80: Z80 Directives. (line 62) 30504* xfloat directive, TIC54X: TIC54X-Directives. (line 62) 30505* XGATE addressing modes: XGATE-Syntax. (line 28) 30506* XGATE assembler directives: XGATE-Directives. (line 6) 30507* XGATE floating point: XGATE-Float. (line 6) 30508* XGATE line comment character: XGATE-Syntax. (line 16) 30509* XGATE line separator: XGATE-Syntax. (line 25) 30510* XGATE opcodes: XGATE-opcodes. (line 6) 30511* XGATE options: XGATE-Opts. (line 6) 30512* XGATE support: XGATE-Dependent. (line 6) 30513* XGATE syntax: XGATE-Syntax. (line 6) 30514* xlong directive, TIC54X: TIC54X-Directives. (line 133) 30515* xref directive, Z80: Z80 Directives. (line 66) 30516* XStormy16 comment character: XStormy16-Chars. (line 11) 30517* XStormy16 line comment character: XStormy16-Chars. (line 6) 30518* XStormy16 line separator: XStormy16-Chars. (line 14) 30519* XStormy16 machine directives: XStormy16 Directives. 30520 (line 6) 30521* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6) 30522* XStormy16 support: XSTORMY16-Dependent. 30523 (line 6) 30524* Xtensa architecture: Xtensa-Dependent. (line 6) 30525* Xtensa assembler syntax: Xtensa Syntax. (line 6) 30526* Xtensa directives: Xtensa Directives. (line 6) 30527* Xtensa opcode names: Xtensa Opcodes. (line 6) 30528* Xtensa register names: Xtensa Registers. (line 6) 30529* xword directive, SPARC: Sparc-Directives. (line 55) 30530* Z80 $: Z80-Chars. (line 15) 30531* Z80 ’: Z80-Chars. (line 20) 30532* Z80 floating point: Z80 Floating Point. (line 6) 30533* Z80 labels: Z80-Labels. (line 6) 30534* Z80 line comment character: Z80-Chars. (line 6) 30535* Z80 line separator: Z80-Chars. (line 13) 30536* Z80 options: Z80 Options. (line 6) 30537* Z80 registers: Z80-Regs. (line 6) 30538* Z80 support: Z80-Dependent. (line 6) 30539* Z80 Syntax: Z80 Options. (line 67) 30540* Z80, case sensitivity: Z80-Case. (line 6) 30541* Z80, \: Z80-Chars. (line 18) 30542* Z80-only directives: Z80 Directives. (line 6) 30543* Z800 addressing modes: Z8000-Addressing. (line 6) 30544* Z8000 directives: Z8000 Directives. (line 6) 30545* Z8000 line comment character: Z8000-Chars. (line 6) 30546* Z8000 line separator: Z8000-Chars. (line 13) 30547* Z8000 opcode summary: Z8000 Opcodes. (line 6) 30548* Z8000 options: Z8000 Options. (line 6) 30549* Z8000 registers: Z8000-Regs. (line 6) 30550* Z8000 support: Z8000-Dependent. (line 6) 30551* zdaoff pseudo-op, V850: V850 Opcodes. (line 98) 30552* zero directive: Zero. (line 6) 30553* zero register, V850: V850-Regs. (line 7) 30554* zero-terminated strings: Asciz. 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