1@c Copyright (C) 2016-2022 Free Software Foundation, Inc. 2@c This is part of the GAS anual. 3@c For copying conditions, see the file as.texinfo 4@c man end 5 6@ifset GENERIC 7@page 8@node RISC-V-Dependent 9@chapter RISC-V Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter RISC-V Dependent Features 14@end ifclear 15 16@cindex RISC-V support 17@menu 18* RISC-V-Options:: RISC-V Options 19* RISC-V-Directives:: RISC-V Directives 20* RISC-V-Modifiers:: RISC-V Assembler Modifiers 21* RISC-V-Formats:: RISC-V Instruction Formats 22* RISC-V-ATTRIBUTE:: RISC-V Object Attribute 23@end menu 24 25@node RISC-V-Options 26@section RISC-V Options 27 28The following table lists all available RISC-V specific options. 29 30@c man begin OPTIONS 31@table @gcctabopt 32 33@cindex @samp{-fpic} option, RISC-V 34@item -fpic 35@itemx -fPIC 36Generate position-independent code 37 38@cindex @samp{-fno-pic} option, RISC-V 39@item -fno-pic 40Don't generate position-independent code (default) 41 42@cindex @samp{-march=ISA} option, RISC-V 43@item -march=ISA 44Select the base isa, as specified by ISA. For example -march=rv32ima. 45If this option and the architecture attributes aren't set, then assembler 46will check the default configure setting --with-arch=ISA. 47 48@cindex @samp{-misa-spec=ISAspec} option, RISC-V 49@item -misa-spec=ISAspec 50Select the default isa spec version. If the version of ISA isn't set 51by -march, then assembler helps to set the version according to 52the default chosen spec. If this option isn't set, then assembler will 53check the default configure setting --with-isa-spec=ISAspec. 54 55@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V 56@item -mpriv-spec=PRIVspec 57Select the privileged spec version. We can decide whether the CSR is valid or 58not according to the chosen spec. If this option and the privilege attributes 59aren't set, then assembler will check the default configure setting 60--with-priv-spec=PRIVspec. 61 62@cindex @samp{-mabi=ABI} option, RISC-V 63@item -mabi=ABI 64Selects the ABI, which is either "ilp32" or "lp64", optionally followed 65by "f", "d", or "q" to indicate single-precision, double-precision, or 66quad-precision floating-point calling convention, or none to indicate 67the soft-float calling convention. Also, "ilp32" can optionally be followed 68by "e" to indicate the RVE ABI, which is always soft-float. 69 70@cindex @samp{-mrelax} option, RISC-V 71@item -mrelax 72Take advantage of linker relaxations to reduce the number of instructions 73required to materialize symbol addresses. (default) 74 75@cindex @samp{-mno-relax} option, RISC-V 76@item -mno-relax 77Don't do linker relaxations. 78 79@cindex @samp{-march-attr} option, RISC-V 80@item -march-attr 81Generate the default contents for the riscv elf attribute section if the 82.attribute directives are not set. This section is used to record the 83information that a linker or runtime loader needs to check compatibility. 84This information includes ISA string, stack alignment requirement, unaligned 85memory accesses, and the major, minor and revision version of privileged 86specification. 87 88@cindex @samp{-mno-arch-attr} option, RISC-V 89@item -mno-arch-attr 90Don't generate the default riscv elf attribute section if the .attribute 91directives are not set. 92 93@cindex @samp{-mcsr-check} option, RISC-V 94@item -mcsr-check 95Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. 96The ISA-dependent CSR are only valid when the specific ISA is set. The 97read-only CSR can not be written by the CSR instructions. 98 99@cindex @samp{-mno-csr-check} option, RISC-V 100@item -mno-csr-check 101Don't do CSR checking. 102 103@cindex @samp{-mlittle-endian} option, RISC-V 104@item -mlittle-endian 105Generate code for a little endian machine. 106 107@cindex @samp{-mbig-endian} option, RISC-V 108@item -mbig-endian 109Generate code for a big endian machine. 110@end table 111@c man end 112 113@node RISC-V-Directives 114@section RISC-V Directives 115@cindex machine directives, RISC-V 116@cindex RISC-V machine directives 117 118The following table lists all available RISC-V specific directives. 119 120@table @code 121 122@cindex @code{align} directive 123@item .align @var{size-log-2} 124Align to the given boundary, with the size given as log2 the number of bytes to 125align to. 126 127@cindex Data directives 128@item .half @var{value} 129@itemx .word @var{value} 130@itemx .dword @var{value} 131Emits a half-word, word, or double-word value at the current position. 132 133@cindex DTP-relative data directives 134@item .dtprelword @var{value} 135@itemx .dtpreldword @var{value} 136Emits a DTP-relative word (or double-word) at the current position. This is 137meant to be used by the compiler in shared libraries for DWARF debug info for 138thread local variables. 139 140@cindex BSS directive 141@item .bss 142Sets the current section to the BSS section. 143 144@cindex LEB128 directives 145@item .uleb128 @var{value} 146@itemx .sleb128 @var{value} 147Emits a signed or unsigned LEB128 value at the current position. This only 148accepts constant expressions, because symbol addresses can change with 149relaxation, and we don't support relocations to modify LEB128 values at link 150time. 151 152@cindex Option directive 153@cindex @code{option} directive 154@item .option @var{argument} 155Modifies RISC-V specific assembler options inline with the assembly code. 156This is used when particular instruction sequences must be assembled with a 157specific set of options. For example, since we relax addressing sequences to 158shorter GP-relative sequences when possible the initial load of GP must not be 159relaxed and should be emitted as something like 160 161@smallexample 162 .option push 163 .option norelax 164 la gp, __global_pointer$ 165 .option pop 166@end smallexample 167 168in order to produce after linker relaxation the expected 169 170@smallexample 171 auipc gp, %pcrel_hi(__global_pointer$) 172 addi gp, gp, %pcrel_lo(__global_pointer$) 173@end smallexample 174 175instead of just 176 177@smallexample 178 addi gp, gp, 0 179@end smallexample 180 181It's not expected that options are changed in this manner during regular use, 182but there are a handful of esoteric cases like the one above where users need 183to disable particular features of the assembler for particular code sequences. 184The complete list of option arguments is shown below: 185 186@table @code 187@item push 188@itemx pop 189Pushes or pops the current option stack. These should be used whenever 190changing an option in line with assembly code in order to ensure the user's 191command-line options are respected for the bulk of the file being assembled. 192 193@item rvc 194@itemx norvc 195Enables or disables the generation of compressed instructions. Instructions 196are opportunistically compressed by the RISC-V assembler when possible, but 197sometimes this behavior is not desirable, especially when handling alignments. 198 199@item pic 200@itemx nopic 201Enables or disables position-independent code generation. Unless you really 202know what you're doing, this should only be at the top of a file. 203 204@item relax 205@itemx norelax 206Enables or disables relaxation. The RISC-V assembler and linker 207opportunistically relax some code sequences, but sometimes this behavior is not 208desirable. 209 210@item csr-check 211@itemx no-csr-check 212Enables or disables the CSR checking. 213 214@item arch, @var{+extension[version]} [,...,@var{+extension_n[version_n]}] 215@itemx arch, @var{-extension} [,...,@var{-extension_n}] 216@itemx arch, @var{=ISA} 217Enables or disables the extensions for specific code region. For example, 218@samp{.option arch, +m2p0} means add m extension with version 2.0, and 219@samp{.option arch, -f, -d} means remove extensions, f and d, from the 220architecture string. Note that, @samp{.option arch, +c, -c} have the same 221behavior as @samp{.option rvc, norvc}. However, they are also undesirable 222sometimes. Besides, @samp{.option arch, -i} is illegal, since we cannot 223remove the base i extension anytime. If you want to reset the whole ISA 224string, you can also use @samp{.option arch, =rv32imac} to overwrite the 225previous settings. 226@end table 227 228@cindex INSN directives 229@item .insn @var{type}, @var{operand} [,...,@var{operand_n}] 230@itemx .insn @var{insn_length}, @var{value} 231@itemx .insn @var{value} 232This directive permits the numeric representation of an instructions 233and makes the assembler insert the operands according to one of the 234instruction formats for @samp{.insn} (@ref{RISC-V-Formats}). 235For example, the instruction @samp{add a0, a1, a2} could be written as 236@samp{.insn r 0x33, 0, 0, a0, a1, a2}. But in fact, the instruction 237formats are difficult to use for some users, so most of them are using 238@samp{.word} to encode the instruction directly, rather than using 239@samp{.insn}. It is fine for now, but will be wrong when the mapping 240symbols are supported, since @samp{.word} will not be shown as an 241instruction, it should be shown as data. Therefore, we also support 242two more formats of the @samp{.insn}, the instruction @samp{add a0, a1, a2} 243could also be written as @samp{.insn 0x4, 0xc58533} or @samp{.insn 0xc58533}. 244When the @var{insn_length} is set, then assembler will check if the 245@var{value} is a valid @var{insn_length} bytes instruction. 246 247@cindex @code{.attribute} directive, RISC-V 248@item .attribute @var{tag}, @var{value} 249Set the object attribute @var{tag} to @var{value}. 250 251The @var{tag} is either an attribute number, or one of the following: 252@code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align}, 253@code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec}, 254@code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}. 255 256@end table 257 258@node RISC-V-Modifiers 259@section RISC-V Assembler Modifiers 260 261The RISC-V assembler supports following modifiers for relocatable addresses 262used in RISC-V instruction operands. However, we also support some pseudo 263instructions that are easier to use than these modifiers. 264 265@table @code 266@item %lo(@var{symbol}) 267The low 12 bits of absolute address for @var{symbol}. 268 269@item %hi(@var{symbol}) 270The high 20 bits of absolute address for @var{symbol}. This is usually 271used with the %lo modifier to represent a 32-bit absolute address. 272 273@smallexample 274 lui a0, %hi(@var{symbol}) // R_RISCV_HI20 275 addi a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I 276 277 lui a0, %hi(@var{symbol}) // R_RISCV_HI20 278 load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S 279@end smallexample 280 281@item %pcrel_lo(@var{label}) 282The low 12 bits of relative address between pc and @var{symbol}. 283The @var{symbol} is related to the high part instruction which is marked 284by @var{label}. 285 286@item %pcrel_hi(@var{symbol}) 287The high 20 bits of relative address between pc and @var{symbol}. 288This is usually used with the %pcrel_lo modifier to represent a +/-2GB 289pc-relative range. 290 291@smallexample 292@var{label}: 293 auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20 294 addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I 295 296@var{label}: 297 auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20 298 load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S 299@end smallexample 300 301Or you can use the pseudo lla/lw/sw/... instruction to do this. 302 303@smallexample 304 lla a0, @var{symbol} 305@end smallexample 306 307@item %got_pcrel_hi(@var{symbol}) 308The high 20 bits of relative address between pc and the GOT entry of 309@var{symbol}. This is usually used with the %pcrel_lo modifier to access 310the GOT entry. 311 312@smallexample 313@var{label}: 314 auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 315 addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I 316 317@var{label}: 318 auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 319 load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S 320@end smallexample 321 322Also, the pseudo la instruction with PIC has similar behavior. 323 324@item %tprel_add(@var{symbol}) 325This is used purely to associate the R_RISCV_TPREL_ADD relocation for 326TLS relaxation. This one is only valid as the fourth operand to the normally 3273 operand add instruction. 328 329@item %tprel_lo(@var{symbol}) 330The low 12 bits of relative address between tp and @var{symbol}. 331 332@item %tprel_hi(@var{symbol}) 333The high 20 bits of relative address between tp and @var{symbol}. This is 334usually used with the %tprel_lo and %tprel_add modifiers to access the thread 335local variable @var{symbol} in TLS Local Exec. 336 337@smallexample 338 lui a5, %tprel_hi(@var{symbol}) // R_RISCV_TPREL_HI20 339 add a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD 340 load/store t0, %tprel_lo(@var{symbol})(a5) // R_RISCV_TPREL_LO12_I/S 341@end smallexample 342 343@item %tls_ie_pcrel_hi(@var{symbol}) 344The high 20 bits of relative address between pc and GOT entry. It is 345usually used with the %pcrel_lo modifier to access the thread local 346variable @var{symbol} in TLS Initial Exec. 347 348@smallexample 349 la.tls.ie a5, @var{symbol} 350 add a5, a5, tp 351 load/store t0, 0(a5) 352@end smallexample 353 354The pseudo la.tls.ie instruction can be expended to 355 356@smallexample 357@var{label}: 358 auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20 359 load a5, %pcrel_lo(@var{label})(a5) // R_RISCV_PCREL_LO12_I 360@end smallexample 361 362@item %tls_gd_pcrel_hi(@var{symbol}) 363The high 20 bits of relative address between pc and GOT entry. It is 364usually used with the %pcrel_lo modifier to access the thread local variable 365@var{symbol} in TLS Global Dynamic. 366 367@smallexample 368 la.tls.gd a0, @var{symbol} 369 call __tls_get_addr@@plt 370 mv a5, a0 371 load/store t0, 0(a5) 372@end smallexample 373 374The pseudo la.tls.gd instruction can be expended to 375 376@smallexample 377@var{label}: 378 auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20 379 addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I 380@end smallexample 381 382@end table 383 384@node RISC-V-Formats 385@section RISC-V Instruction Formats 386@cindex instruction formats, risc-v 387@cindex RISC-V instruction formats 388 389The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15 390instruction formats where some of the formats have multiple variants. 391For the @samp{.insn} pseudo directive the assembler recognizes some 392of the formats. 393Typically, the most general variant of the instruction format is used 394by the @samp{.insn} directive. 395 396The following table lists the abbreviations used in the table of 397instruction formats: 398 399@display 400@multitable @columnfractions .15 .40 401@item opcode @tab Unsigned immediate or opcode name for 7-bits opcode. 402@item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode. 403@item func7 @tab Unsigned immediate for 7-bits function code. 404@item func6 @tab Unsigned immediate for 6-bits function code. 405@item func4 @tab Unsigned immediate for 4-bits function code. 406@item func3 @tab Unsigned immediate for 3-bits function code. 407@item func2 @tab Unsigned immediate for 2-bits function code. 408@item rd @tab Destination register number for operand x, can be GPR or FPR. 409@item rd' @tab Destination register number for operand x, 410only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 411@item rs1 @tab First source register number for operand x, can be GPR or FPR. 412@item rs1' @tab First source register number for operand x, 413only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 414@item rs2 @tab Second source register number for operand x, can be GPR or FPR. 415@item rs2' @tab Second source register number for operand x, 416only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 417@item simm12 @tab Sign-extended 12-bit immediate for operand x. 418@item simm20 @tab Sign-extended 20-bit immediate for operand x. 419@item simm6 @tab Sign-extended 6-bit immediate for operand x. 420@item uimm5 @tab Unsigned 5-bit immediate for operand x. 421@item uimm6 @tab Unsigned 6-bit immediate for operand x. 422@item uimm8 @tab Unsigned 8-bit immediate for operand x. 423@item symbol @tab Symbol or lable reference for operand x. 424@end multitable 425@end display 426 427The following table lists all available opcode name: 428 429@table @code 430@item C0 431@item C1 432@item C2 433Opcode space for compressed instructions. 434 435@item LOAD 436Opcode space for load instructions. 437 438@item LOAD_FP 439Opcode space for floating-point load instructions. 440 441@item STORE 442Opcode space for store instructions. 443 444@item STORE_FP 445Opcode space for floating-point store instructions. 446 447@item AUIPC 448Opcode space for auipc instruction. 449 450@item LUI 451Opcode space for lui instruction. 452 453@item BRANCH 454Opcode space for branch instructions. 455 456@item JAL 457Opcode space for jal instruction. 458 459@item JALR 460Opcode space for jalr instruction. 461 462@item OP 463Opcode space for ALU instructions. 464 465@item OP_32 466Opcode space for 32-bits ALU instructions. 467 468@item OP_IMM 469Opcode space for ALU with immediate instructions. 470 471@item OP_IMM_32 472Opcode space for 32-bits ALU with immediate instructions. 473 474@item OP_FP 475Opcode space for floating-point operation instructions. 476 477@item MADD 478Opcode space for madd instruction. 479 480@item MSUB 481Opcode space for msub instruction. 482 483@item NMADD 484Opcode space for nmadd instruction. 485 486@item NMSUB 487Opcode space for msub instruction. 488 489@item AMO 490Opcode space for atomic memory operation instructions. 491 492@item MISC_MEM 493Opcode space for misc instructions. 494 495@item SYSTEM 496Opcode space for system instructions. 497 498@item CUSTOM_0 499@item CUSTOM_1 500@item CUSTOM_2 501@item CUSTOM_3 502Opcode space for customize instructions. 503 504@end table 505 506An instruction is two or four bytes in length and must be aligned 507on a 2 byte boundary. The first two bits of the instruction specify the 508length of the instruction, 00, 01 and 10 indicates a two byte instruction, 50911 indicates a four byte instruction. 510 511The following table lists the RISC-V instruction formats that are available 512with the @samp{.insn} pseudo directive: 513 514@table @code 515@item R type: .insn r opcode6, func3, func7, rd, rs1, rs2 516@verbatim 517+-------+-----+-----+-------+----+---------+ 518| func7 | rs2 | rs1 | func3 | rd | opcode6 | 519+-------+-----+-----+-------+----+---------+ 52031 25 20 15 12 7 0 521@end verbatim 522 523@item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3 524@itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3 525@verbatim 526+-----+-------+-----+-----+-------+----+---------+ 527| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 | 528+-----+-------+-----+-----+-------+----+---------+ 52931 27 25 20 15 12 7 0 530@end verbatim 531 532@item I type: .insn i opcode6, func3, rd, rs1, simm12 533@itemx I type: .insn i opcode6, func3, rd, simm12(rs1) 534@verbatim 535+--------------+-----+-------+----+---------+ 536| simm12[11:0] | rs1 | func3 | rd | opcode6 | 537+--------------+-----+-------+----+---------+ 53831 20 15 12 7 0 539@end verbatim 540 541@item S type: .insn s opcode6, func3, rs2, simm12(rs1) 542@verbatim 543+--------------+-----+-----+-------+-------------+---------+ 544| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 | 545+--------------+-----+-----+-------+-------------+---------+ 54631 25 20 15 12 7 0 547@end verbatim 548 549@item B type: .insn s opcode6, func3, rs1, rs2, symbol 550@itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol 551@verbatim 552+-----------------+-----+-----+-------+----------------+---------+ 553| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 | 554+-----------------+-----+-----+-------+----------------+---------+ 55531 25 20 15 12 7 0 556@end verbatim 557 558@item U type: .insn u opcode6, rd, simm20 559@verbatim 560+--------------------------+----+---------+ 561| simm20[20|10:1|11|19:12] | rd | opcode6 | 562+--------------------------+----+---------+ 56331 12 7 0 564@end verbatim 565 566@item J type: .insn j opcode6, rd, symbol 567@itemx UJ type: .insn uj opcode6, rd, symbol 568@verbatim 569+------------+--------------+------------+---------------+----+---------+ 570| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 | 571+------------+--------------+------------+---------------+----+---------+ 57231 30 21 20 12 7 0 573@end verbatim 574 575@item CR type: .insn cr opcode2, func4, rd, rs2 576@verbatim 577+-------+--------+-----+---------+ 578| func4 | rd/rs1 | rs2 | opcode2 | 579+-------+--------+-----+---------+ 58015 12 7 2 0 581@end verbatim 582 583@item CI type: .insn ci opcode2, func3, rd, simm6 584@verbatim 585+-------+----------+--------+------------+---------+ 586| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 | 587+-------+----------+--------+------------+---------+ 58815 13 12 7 2 0 589@end verbatim 590 591@item CIW type: .insn ciw opcode2, func3, rd', uimm8 592@verbatim 593+-------+------------+-----+---------+ 594| func3 | uimm8[7:0] | rd' | opcode2 | 595+-------+-------- ---+-----+---------+ 59615 13 5 2 0 597@end verbatim 598 599@item CSS type: .insn css opcode2, func3, rd, uimm6 600@verbatim 601+-------+------------+----+---------+ 602| func3 | uimm6[5:0] | rd | opcode2 | 603+-------+------------+----+---------+ 60415 13 7 2 0 605@end verbatim 606 607@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1') 608@verbatim 609+-------+------------+------+------------+------+---------+ 610| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 | 611+-------+------------+------+------------+------+---------+ 61215 13 10 7 5 2 0 613@end verbatim 614 615@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1') 616@verbatim 617+-------+------------+------+------------+------+---------+ 618| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 | 619+-------+------------+------+------------+------+---------+ 62015 13 10 7 5 2 0 621@end verbatim 622 623@item CA type: .insn ca opcode2, func6, func2, rd', rs2' 624@verbatim 625+-- ----+----------+-------+------+---------+ 626| func6 | rd'/rs1' | func2 | rs2' | opcode2 | 627+-------+----------+-------+------+---------+ 62815 10 7 5 2 0 629@end verbatim 630 631@item CB type: .insn cb opcode2, func3, rs1', symbol 632@verbatim 633+-------+--------------+------+------------------+---------+ 634| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 | 635+-------+--------------+------+------------------+---------+ 63615 13 10 7 2 0 637@end verbatim 638 639@item CJ type: .insn cj opcode2, symbol 640@verbatim 641+-------+-------------------------------+---------+ 642| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 | 643+-------+-------------------------------+---------+ 64415 13 2 0 645@end verbatim 646 647 648@end table 649 650For the complete list of all instruction format variants see 651The RISC-V Instruction Set Manual Volume I: User-Level ISA. 652 653@node RISC-V-ATTRIBUTE 654@section RISC-V Object Attribute 655@cindex Object Attribute, RISC-V 656 657RISC-V attributes have a string value if the tag number is odd and an integer 658value if the tag number is even. 659 660@table @r 661@item Tag_RISCV_stack_align (4) 662Tag_RISCV_strict_align records the N-byte stack alignment for this object. The 663default value is 16 for RV32I or RV64I, and 4 for RV32E. 664 665The smallest value will be used if object files with different 666Tag_RISCV_stack_align values are merged. 667 668@item Tag_RISCV_arch (5) 669Tag_RISCV_arch contains a string for the target architecture taken from the 670option @option{-march}. Different architectures will be integrated into a 671superset when object files are merged. 672 673Note that the version information of the target architecture must be presented 674explicitly in the attribute and abbreviations must be expanded. The version 675information, if not given by @option{-march}, must be in accordance with the 676default specified by the tool. For example, the architecture @code{RV32I} has 677to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands 678for the default version of its base ISA. On the other hand, the architecture 679@code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in 680which the abbreviation @code{G} is expanded to the @code{IMAFD} combination 681with default versions of the standard extensions. 682 683@item Tag_RISCV_unaligned_access (6) 684Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned 685memory accesses, and 1 for files that do allow unaligned memory accesses. 686 687@item Tag_RISCV_priv_spec (8) 688@item Tag_RISCV_priv_spec_minor (10) 689@item Tag_RISCV_priv_spec_revision (12) 690Tag_RISCV_priv_spec contains the major/minor/revision version information of 691the privileged specification. It will report errors if object files of 692different privileged specification versions are merged. 693 694@end table 695