1@c Copyright (C) 2006-2022 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4 5@ifset GENERIC 6@page 7@node AVR-Dependent 8@chapter AVR Dependent Features 9@end ifset 10 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter AVR Dependent Features 14@end ifclear 15 16@cindex AVR support 17@menu 18* AVR Options:: Options 19* AVR Syntax:: Syntax 20* AVR Opcodes:: Opcodes 21* AVR Pseudo Instructions:: Pseudo Instructions 22@end menu 23 24@node AVR Options 25@section Options 26@cindex AVR options (none) 27@cindex options for AVR (none) 28 29@table @code 30 31@cindex @code{-mmcu=} command-line option, AVR 32@item -mmcu=@var{mcu} 33Specify ATMEL AVR instruction set or MCU type. 34 35Instruction set avr1 is for the minimal AVR core, not supported by the C 36compiler, only for assembler programs (MCU types: at90s1200, 37attiny11, attiny12, attiny15, attiny28). 38 39Instruction set avr2 (default) is for the classic AVR core with up to 408K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343, 41attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, 42at90s8535). 43 44Instruction set avr25 is for the classic AVR core with up to 8K program memory 45space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, 46attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, 47attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, 48attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 49attiny828, at86rf401, ata6289, ata5272). 50 51Instruction set avr3 is for the classic AVR core with up to 128K program 52memory space (MCU types: at43usb355, at76c711). 53 54Instruction set avr31 is for the classic AVR core with exactly 128K program 55memory space (MCU types: atmega103, at43usb320). 56 57Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP 58instructions (MCU types: attiny167, attiny1634, at90usb82, at90usb162, 59atmega8u2, atmega16u2, atmega32u2, ata5505). 60 61Instruction set avr4 is for the enhanced AVR core with up to 8K program 62memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, 63atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, 64atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, 65ata6285, ata6286). 66 67Instruction set avr5 is for the enhanced AVR core with up to 128K program 68memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, 69atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 70atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 71atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, 72atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, 73atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 74atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, 75atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, 76atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, 77atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, 78atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, 79atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, 80atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, 81atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, 82at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, 83atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, 84at90scr100, ata5790, ata5795). 85 86Instruction set avr51 is for the enhanced AVR core with exactly 128K 87program memory space (MCU types: atmega128, atmega128a, atmega1280, 88atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, 89atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000). 90 91Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 92(MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 93 94Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 95program memory space and less than 64K data space (MCU types: 96atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, 97atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, 98atxmega8e5, atxmega32e5, atxmega32x1). 99 100Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K 101of combined program memory and RAM, and with program memory 102visible in the RAM address space (MCU types: 103attiny212, attiny214, attiny412, attiny414, attiny416, attiny417, 104attiny814, attiny816, attiny817, attiny1614, attiny1616, attiny1617, 105attiny3214, attiny3216, attiny3217). 106 107Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 108program memory space and less than 64K data space (MCU types: 109atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, 110atxmega64c3, atxmega64d3, atxmega64d4). 111 112Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 113program memory space and greater than 64K data space (MCU types: 114atxmega64a1, atxmega64a1u). 115 116Instruction set avrxmega6 is for the XMEGA AVR core with larger than 11764K program memory space and less than 64K data space (MCU types: 118atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, 119atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, 120atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, 121atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, 122atxmega256d3). 123 124Instruction set avrxmega7 is for the XMEGA AVR core with larger than 12564K program memory space and greater than 64K data space (MCU types: 126atxmega128a1, atxmega128a1u, atxmega128a4u). 127 128Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 129microcontrollers. 130 131@cindex @code{-mall-opcodes} command-line option, AVR 132@item -mall-opcodes 133Accept all AVR opcodes, even if not supported by @code{-mmcu}. 134 135@cindex @code{-mno-skip-bug} command-line option, AVR 136@item -mno-skip-bug 137This option disable warnings for skipping two-word instructions. 138 139@cindex @code{-mno-wrap} command-line option, AVR 140@item -mno-wrap 141This option reject @code{rjmp/rcall} instructions with 8K wrap-around. 142 143@cindex @code{-mrmw} command-line option, AVR 144@item -mrmw 145Accept Read-Modify-Write (@code{XCH,LAC,LAS,LAT}) instructions. 146 147@cindex @code{-mlink-relax} command-line option, AVR 148@item -mlink-relax 149Enable support for link-time relaxation. This is now on by default 150and this flag no longer has any effect. 151 152@cindex @code{-mno-link-relax} command-line option, AVR 153@item -mno-link-relax 154Disable support for link-time relaxation. The assembler will resolve 155relocations when it can, and may be able to better compress some debug 156information. 157 158@cindex @code{-mgcc-isr} command-line option, AVR 159@item -mgcc-isr 160Enable the @code{__gcc_isr} pseudo instruction. 161 162@cindex @code{-mno-dollar-line-separator} command line option, AVR 163@item -mno-dollar-line-separator 164Do not treat the @code{$} character as a line separator character. 165This is for languages where @code{$} is valid character inside symbol 166names. 167 168@end table 169 170 171@node AVR Syntax 172@section Syntax 173@menu 174* AVR-Chars:: Special Characters 175* AVR-Regs:: Register Names 176* AVR-Modifiers:: Relocatable Expression Modifiers 177@end menu 178 179@node AVR-Chars 180@subsection Special Characters 181 182@cindex line comment character, AVR 183@cindex AVR line comment character 184 185The presence of a @samp{;} anywhere on a line indicates the start of a 186comment that extends to the end of that line. 187 188If a @samp{#} appears as the first character of a line, the whole line 189is treated as a comment, but in this case the line can also be a 190logical line number directive (@pxref{Comments}) or a preprocessor 191control command (@pxref{Preprocessing}). 192 193@cindex line separator, AVR 194@cindex statement separator, AVR 195@cindex AVR line separator 196 197The @samp{$} character can be used instead of a newline to separate 198statements. Note: the @option{-mno-dollar-line-separator} option 199disables this behaviour. 200 201@node AVR-Regs 202@subsection Register Names 203 204@cindex AVR register names 205@cindex register names, AVR 206 207The AVR has 32 x 8-bit general purpose working registers @samp{r0}, 208@samp{r1}, ... @samp{r31}. 209Six of the 32 registers can be used as three 16-bit indirect address 210register pointers for Data Space addressing. One of the these address 211pointers can also be used as an address pointer for look up tables in 212Flash program memory. These added function registers are the 16-bit 213@samp{X}, @samp{Y} and @samp{Z} - registers. 214 215@smallexample 216X = @r{r26:r27} 217Y = @r{r28:r29} 218Z = @r{r30:r31} 219@end smallexample 220 221@node AVR-Modifiers 222@subsection Relocatable Expression Modifiers 223 224@cindex AVR modifiers 225@cindex syntax, AVR 226 227The assembler supports several modifiers when using relocatable addresses 228in AVR instruction operands. The general syntax is the following: 229 230@smallexample 231modifier(relocatable-expression) 232@end smallexample 233 234@table @code 235@cindex symbol modifiers 236 237@item lo8 238 239This modifier allows you to use bits 0 through 7 of 240an address expression as an 8 bit relocatable expression. 241 242@item hi8 243 244This modifier allows you to use bits 7 through 15 of an address expression 245as an 8 bit relocatable expression. This is useful with, for example, the 246AVR @samp{ldi} instruction and @samp{lo8} modifier. 247 248For example 249 250@smallexample 251ldi r26, lo8(sym+10) 252ldi r27, hi8(sym+10) 253@end smallexample 254 255@item hh8 256 257This modifier allows you to use bits 16 through 23 of 258an address expression as an 8 bit relocatable expression. 259Also, can be useful for loading 32 bit constants. 260 261@item hlo8 262 263Synonym of @samp{hh8}. 264 265@item hhi8 266 267This modifier allows you to use bits 24 through 31 of 268an expression as an 8 bit expression. This is useful with, for example, the 269AVR @samp{ldi} instruction and @samp{lo8}, @samp{hi8}, @samp{hlo8}, 270@samp{hhi8}, modifier. 271 272For example 273 274@smallexample 275ldi r26, lo8(285774925) 276ldi r27, hi8(285774925) 277ldi r28, hlo8(285774925) 278ldi r29, hhi8(285774925) 279; r29,r28,r27,r26 = 285774925 280@end smallexample 281 282@item pm_lo8 283 284This modifier allows you to use bits 0 through 7 of 285an address expression as an 8 bit relocatable expression. 286This modifier is useful for addressing data or code from 287Flash/Program memory by two-byte words. The use of @samp{pm_lo8} 288is similar to @samp{lo8}. 289 290@item pm_hi8 291 292This modifier allows you to use bits 8 through 15 of 293an address expression as an 8 bit relocatable expression. 294This modifier is useful for addressing data or code from 295Flash/Program memory by two-byte words. 296 297For example, when setting the AVR @samp{Z} register with the @samp{ldi} 298instruction for subsequent use by the @samp{ijmp} instruction: 299 300@smallexample 301ldi r30, pm_lo8(sym) 302ldi r31, pm_hi8(sym) 303ijmp 304@end smallexample 305 306@item pm_hh8 307 308This modifier allows you to use bits 15 through 23 of 309an address expression as an 8 bit relocatable expression. 310This modifier is useful for addressing data or code from 311Flash/Program memory by two-byte words. 312 313@end table 314 315@node AVR Opcodes 316@section Opcodes 317 318@cindex AVR opcode summary 319@cindex opcode summary, AVR 320@cindex mnemonics, AVR 321@cindex instruction summary, AVR 322For detailed information on the AVR machine instruction set, see 323@url{www.atmel.com/products/AVR}. 324 325@code{@value{AS}} implements all the standard AVR opcodes. 326The following table summarizes the AVR opcodes, and their arguments. 327 328@smallexample 329@i{Legend:} 330 r @r{any register} 331 d @r{`ldi' register (r16-r31)} 332 v @r{`movw' even register (r0, r2, ..., r28, r30)} 333 a @r{`fmul' register (r16-r23)} 334 w @r{`adiw' register (r24,r26,r28,r30)} 335 e @r{pointer registers (X,Y,Z)} 336 b @r{base pointer register and displacement ([YZ]+disp)} 337 z @r{Z pointer register (for [e]lpm Rd,Z[+])} 338 M @r{immediate value from 0 to 255} 339 n @r{immediate value from 0 to 255 ( n = ~M ). Relocation impossible} 340 s @r{immediate value from 0 to 7} 341 P @r{Port address value from 0 to 63. (in, out)} 342 p @r{Port address value from 0 to 31. (cbi, sbi, sbic, sbis)} 343 K @r{immediate value from 0 to 63 (used in `adiw', `sbiw')} 344 i @r{immediate value} 345 l @r{signed pc relative offset from -64 to 63} 346 L @r{signed pc relative offset from -2048 to 2047} 347 h @r{absolute code address (call, jmp)} 348 S @r{immediate value from 0 to 7 (S = s << 4)} 349 ? @r{use this opcode entry if no parameters, else use next opcode entry} 350 3511001010010001000 clc 3521001010011011000 clh 3531001010011111000 cli 3541001010010101000 cln 3551001010011001000 cls 3561001010011101000 clt 3571001010010111000 clv 3581001010010011000 clz 3591001010000001000 sec 3601001010001011000 seh 3611001010001111000 sei 3621001010000101000 sen 3631001010001001000 ses 3641001010001101000 set 3651001010000111000 sev 3661001010000011000 sez 367100101001SSS1000 bclr S 368100101000SSS1000 bset S 3691001010100001001 icall 3701001010000001001 ijmp 3711001010111001000 lpm ? 3721001000ddddd010+ lpm r,z 3731001010111011000 elpm ? 3741001000ddddd011+ elpm r,z 3750000000000000000 nop 3761001010100001000 ret 3771001010100011000 reti 3781001010110001000 sleep 3791001010110011000 break 3801001010110101000 wdr 3811001010111101000 spm 382000111rdddddrrrr adc r,r 383000011rdddddrrrr add r,r 384001000rdddddrrrr and r,r 385000101rdddddrrrr cp r,r 386000001rdddddrrrr cpc r,r 387000100rdddddrrrr cpse r,r 388001001rdddddrrrr eor r,r 389001011rdddddrrrr mov r,r 390100111rdddddrrrr mul r,r 391001010rdddddrrrr or r,r 392000010rdddddrrrr sbc r,r 393000110rdddddrrrr sub r,r 394001001rdddddrrrr clr r 395000011rdddddrrrr lsl r 396000111rdddddrrrr rol r 397001000rdddddrrrr tst r 3980111KKKKddddKKKK andi d,M 3990111KKKKddddKKKK cbr d,n 4001110KKKKddddKKKK ldi d,M 40111101111dddd1111 ser d 4020110KKKKddddKKKK ori d,M 4030110KKKKddddKKKK sbr d,M 4040011KKKKddddKKKK cpi d,M 4050100KKKKddddKKKK sbci d,M 4060101KKKKddddKKKK subi d,M 4071111110rrrrr0sss sbrc r,s 4081111111rrrrr0sss sbrs r,s 4091111100ddddd0sss bld r,s 4101111101ddddd0sss bst r,s 41110110PPdddddPPPP in r,P 41210111PPrrrrrPPPP out P,r 41310010110KKddKKKK adiw w,K 41410010111KKddKKKK sbiw w,K 41510011000pppppsss cbi p,s 41610011010pppppsss sbi p,s 41710011001pppppsss sbic p,s 41810011011pppppsss sbis p,s 419111101lllllll000 brcc l 420111100lllllll000 brcs l 421111100lllllll001 breq l 422111101lllllll100 brge l 423111101lllllll101 brhc l 424111100lllllll101 brhs l 425111101lllllll111 brid l 426111100lllllll111 brie l 427111100lllllll000 brlo l 428111100lllllll100 brlt l 429111100lllllll010 brmi l 430111101lllllll001 brne l 431111101lllllll010 brpl l 432111101lllllll000 brsh l 433111101lllllll110 brtc l 434111100lllllll110 brts l 435111101lllllll011 brvc l 436111100lllllll011 brvs l 437111101lllllllsss brbc s,l 438111100lllllllsss brbs s,l 4391101LLLLLLLLLLLL rcall L 4401100LLLLLLLLLLLL rjmp L 4411001010hhhhh111h call h 4421001010hhhhh110h jmp h 4431001010rrrrr0101 asr r 4441001010rrrrr0000 com r 4451001010rrrrr1010 dec r 4461001010rrrrr0011 inc r 4471001010rrrrr0110 lsr r 4481001010rrrrr0001 neg r 4491001000rrrrr1111 pop r 4501001001rrrrr1111 push r 4511001010rrrrr0111 ror r 4521001010rrrrr0010 swap r 45300000001ddddrrrr movw v,v 45400000010ddddrrrr muls d,d 455000000110ddd0rrr mulsu a,a 456000000110ddd1rrr fmul a,a 457000000111ddd0rrr fmuls a,a 458000000111ddd1rrr fmulsu a,a 4591001001ddddd0000 sts i,r 4601001000ddddd0000 lds r,i 46110o0oo0dddddbooo ldd r,b 462100!000dddddee-+ ld r,e 46310o0oo1rrrrrbooo std b,r 464100!001rrrrree-+ st e,r 4651001010100011001 eicall 4661001010000011001 eijmp 467@end smallexample 468 469@node AVR Pseudo Instructions 470@section Pseudo Instructions 471 472The only available pseudo-instruction @code{__gcc_isr} can be activated by 473option @option{-mgcc-isr}. 474 475@table @code 476 477@item __gcc_isr 1 478Emit code chunk to be used in avr-gcc ISR prologue. 479It will expand to at most six 1-word instructions, all optional: 480push of @code{tmp_reg}, push of @code{SREG}, 481push and clear of @code{zero_reg}, push of @var{Reg}. 482 483@item __gcc_isr 2 484Emit code chunk to be used in an avr-gcc ISR epilogue. 485It will expand to at most five 1-word instructions, all optional: 486pop of @var{Reg}, pop of @code{zero_reg}, 487pop of @code{SREG}, pop of @code{tmp_reg}. 488 489@item __gcc_isr 0, @var{Reg} 490Finish avr-gcc ISR function. Scan code since the last prologue 491for usage of: @code{SREG}, @code{tmp_reg}, @code{zero_reg}. 492Prologue chunk and epilogue chunks will be replaced by appropriate code 493to save / restore @code{SREG}, @code{tmp_reg}, @code{zero_reg} and @var{Reg}. 494 495@end table 496 497Example input: 498 499@example 500__vector1: 501 __gcc_isr 1 502 lds r24, var 503 inc r24 504 sts var, r24 505 __gcc_isr 2 506 reti 507 __gcc_isr 0, r24 508@end example 509 510Example output: 511 512@example 51300000000 <__vector1>: 514 0: 8f 93 push r24 515 2: 8f b7 in r24, 0x3f 516 4: 8f 93 push r24 517 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> 518 a: 83 95 inc r24 519 c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> 520 10: 8f 91 pop r24 521 12: 8f bf out 0x3f, r24 522 14: 8f 91 pop r24 523 16: 18 95 reti 524@end example 525