1llvm-mca - LLVM Machine Code Analyzer 2===================================== 3 4.. program:: llvm-mca 5 6SYNOPSIS 7-------- 8 9:program:`llvm-mca` [*options*] [input] 10 11DESCRIPTION 12----------- 13 14:program:`llvm-mca` is a performance analysis tool that uses information 15available in LLVM (e.g. scheduling models) to statically measure the performance 16of machine code in a specific CPU. 17 18Performance is measured in terms of throughput as well as processor resource 19consumption. The tool currently works for processors with a backend for which 20there is a scheduling model available in LLVM. 21 22The main goal of this tool is not just to predict the performance of the code 23when run on the target, but also help with diagnosing potential performance 24issues. 25 26Given an assembly code sequence, :program:`llvm-mca` estimates the Instructions 27Per Cycle (IPC), as well as hardware resource pressure. The analysis and 28reporting style were inspired by the IACA tool from Intel. 29 30For example, you can compile code with clang, output assembly, and pipe it 31directly into :program:`llvm-mca` for analysis: 32 33.. code-block:: bash 34 35 $ clang foo.c -O2 -target x86_64-unknown-unknown -S -o - | llvm-mca -mcpu=btver2 36 37Or for Intel syntax: 38 39.. code-block:: bash 40 41 $ clang foo.c -O2 -target x86_64-unknown-unknown -mllvm -x86-asm-syntax=intel -S -o - | llvm-mca -mcpu=btver2 42 43(:program:`llvm-mca` detects Intel syntax by the presence of an `.intel_syntax` 44directive at the beginning of the input. By default its output syntax matches 45that of its input.) 46 47Scheduling models are not just used to compute instruction latencies and 48throughput, but also to understand what processor resources are available 49and how to simulate them. 50 51By design, the quality of the analysis conducted by :program:`llvm-mca` is 52inevitably affected by the quality of the scheduling models in LLVM. 53 54If you see that the performance report is not accurate for a processor, 55please `file a bug <https://bugs.llvm.org/enter_bug.cgi?product=libraries>`_ 56against the appropriate backend. 57 58OPTIONS 59------- 60 61If ``input`` is "``-``" or omitted, :program:`llvm-mca` reads from standard 62input. Otherwise, it will read from the specified filename. 63 64If the :option:`-o` option is omitted, then :program:`llvm-mca` will send its output 65to standard output if the input is from standard input. If the :option:`-o` 66option specifies "``-``", then the output will also be sent to standard output. 67 68 69.. option:: -help 70 71 Print a summary of command line options. 72 73.. option:: -o <filename> 74 75 Use ``<filename>`` as the output filename. See the summary above for more 76 details. 77 78.. option:: -mtriple=<target triple> 79 80 Specify a target triple string. 81 82.. option:: -march=<arch> 83 84 Specify the architecture for which to analyze the code. It defaults to the 85 host default target. 86 87.. option:: -mcpu=<cpuname> 88 89 Specify the processor for which to analyze the code. By default, the cpu name 90 is autodetected from the host. 91 92.. option:: -output-asm-variant=<variant id> 93 94 Specify the output assembly variant for the report generated by the tool. 95 On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables 96 the AT&T (vic. Intel) assembly format for the code printed out by the tool in 97 the analysis report. 98 99.. option:: -print-imm-hex 100 101 Prefer hex format for numeric literals in the output assembly printed as part 102 of the report. 103 104.. option:: -dispatch=<width> 105 106 Specify a different dispatch width for the processor. The dispatch width 107 defaults to field 'IssueWidth' in the processor scheduling model. If width is 108 zero, then the default dispatch width is used. 109 110.. option:: -register-file-size=<size> 111 112 Specify the size of the register file. When specified, this flag limits how 113 many physical registers are available for register renaming purposes. A value 114 of zero for this flag means "unlimited number of physical registers". 115 116.. option:: -iterations=<number of iterations> 117 118 Specify the number of iterations to run. If this flag is set to 0, then the 119 tool sets the number of iterations to a default value (i.e. 100). 120 121.. option:: -noalias=<bool> 122 123 If set, the tool assumes that loads and stores don't alias. This is the 124 default behavior. 125 126.. option:: -lqueue=<load queue size> 127 128 Specify the size of the load queue in the load/store unit emulated by the tool. 129 By default, the tool assumes an unbound number of entries in the load queue. 130 A value of zero for this flag is ignored, and the default load queue size is 131 used instead. 132 133.. option:: -squeue=<store queue size> 134 135 Specify the size of the store queue in the load/store unit emulated by the 136 tool. By default, the tool assumes an unbound number of entries in the store 137 queue. A value of zero for this flag is ignored, and the default store queue 138 size is used instead. 139 140.. option:: -timeline 141 142 Enable the timeline view. 143 144.. option:: -timeline-max-iterations=<iterations> 145 146 Limit the number of iterations to print in the timeline view. By default, the 147 timeline view prints information for up to 10 iterations. 148 149.. option:: -timeline-max-cycles=<cycles> 150 151 Limit the number of cycles in the timeline view. By default, the number of 152 cycles is set to 80. 153 154.. option:: -resource-pressure 155 156 Enable the resource pressure view. This is enabled by default. 157 158.. option:: -register-file-stats 159 160 Enable register file usage statistics. 161 162.. option:: -dispatch-stats 163 164 Enable extra dispatch statistics. This view collects and analyzes instruction 165 dispatch events, as well as static/dynamic dispatch stall events. This view 166 is disabled by default. 167 168.. option:: -scheduler-stats 169 170 Enable extra scheduler statistics. This view collects and analyzes instruction 171 issue events. This view is disabled by default. 172 173.. option:: -retire-stats 174 175 Enable extra retire control unit statistics. This view is disabled by default. 176 177.. option:: -instruction-info 178 179 Enable the instruction info view. This is enabled by default. 180 181.. option:: -show-encoding 182 183 Enable the printing of instruction encodings within the instruction info view. 184 185.. option:: -all-stats 186 187 Print all hardware statistics. This enables extra statistics related to the 188 dispatch logic, the hardware schedulers, the register file(s), and the retire 189 control unit. This option is disabled by default. 190 191.. option:: -all-views 192 193 Enable all the view. 194 195.. option:: -instruction-tables 196 197 Prints resource pressure information based on the static information 198 available from the processor model. This differs from the resource pressure 199 view because it doesn't require that the code is simulated. It instead prints 200 the theoretical uniform distribution of resource pressure for every 201 instruction in sequence. 202 203.. option:: -bottleneck-analysis 204 205 Print information about bottlenecks that affect the throughput. This analysis 206 can be expensive, and it is disabled by default. Bottlenecks are highlighted 207 in the summary view. Bottleneck analysis is currently not supported for 208 processors with an in-order backend. 209 210.. option:: -json 211 212 Print the requested views in JSON format. The instructions and the processor 213 resources are printed as members of special top level JSON objects. The 214 individual views refer to them by index. 215 216 217EXIT STATUS 218----------- 219 220:program:`llvm-mca` returns 0 on success. Otherwise, an error message is printed 221to standard error, and the tool returns 1. 222 223USING MARKERS TO ANALYZE SPECIFIC CODE BLOCKS 224--------------------------------------------- 225:program:`llvm-mca` allows for the optional usage of special code comments to 226mark regions of the assembly code to be analyzed. A comment starting with 227substring ``LLVM-MCA-BEGIN`` marks the beginning of a code region. A comment 228starting with substring ``LLVM-MCA-END`` marks the end of a code region. For 229example: 230 231.. code-block:: none 232 233 # LLVM-MCA-BEGIN 234 ... 235 # LLVM-MCA-END 236 237If no user-defined region is specified, then :program:`llvm-mca` assumes a 238default region which contains every instruction in the input file. Every region 239is analyzed in isolation, and the final performance report is the union of all 240the reports generated for every code region. 241 242Code regions can have names. For example: 243 244.. code-block:: none 245 246 # LLVM-MCA-BEGIN A simple example 247 add %eax, %eax 248 # LLVM-MCA-END 249 250The code from the example above defines a region named "A simple example" with a 251single instruction in it. Note how the region name doesn't have to be repeated 252in the ``LLVM-MCA-END`` directive. In the absence of overlapping regions, 253an anonymous ``LLVM-MCA-END`` directive always ends the currently active user 254defined region. 255 256Example of nesting regions: 257 258.. code-block:: none 259 260 # LLVM-MCA-BEGIN foo 261 add %eax, %edx 262 # LLVM-MCA-BEGIN bar 263 sub %eax, %edx 264 # LLVM-MCA-END bar 265 # LLVM-MCA-END foo 266 267Example of overlapping regions: 268 269.. code-block:: none 270 271 # LLVM-MCA-BEGIN foo 272 add %eax, %edx 273 # LLVM-MCA-BEGIN bar 274 sub %eax, %edx 275 # LLVM-MCA-END foo 276 add %eax, %edx 277 # LLVM-MCA-END bar 278 279Note that multiple anonymous regions cannot overlap. Also, overlapping regions 280cannot have the same name. 281 282There is no support for marking regions from high-level source code, like C or 283C++. As a workaround, inline assembly directives may be used: 284 285.. code-block:: c++ 286 287 int foo(int a, int b) { 288 __asm volatile("# LLVM-MCA-BEGIN foo"); 289 a += 42; 290 __asm volatile("# LLVM-MCA-END"); 291 a *= b; 292 return a; 293 } 294 295However, this interferes with optimizations like loop vectorization and may have 296an impact on the code generated. This is because the ``__asm`` statements are 297seen as real code having important side effects, which limits how the code 298around them can be transformed. If users want to make use of inline assembly 299to emit markers, then the recommendation is to always verify that the output 300assembly is equivalent to the assembly generated in the absence of markers. 301The `Clang options to emit optimization reports <https://clang.llvm.org/docs/UsersManual.html#options-to-emit-optimization-reports>`_ 302can also help in detecting missed optimizations. 303 304HOW LLVM-MCA WORKS 305------------------ 306 307:program:`llvm-mca` takes assembly code as input. The assembly code is parsed 308into a sequence of MCInst with the help of the existing LLVM target assembly 309parsers. The parsed sequence of MCInst is then analyzed by a ``Pipeline`` module 310to generate a performance report. 311 312The Pipeline module simulates the execution of the machine code sequence in a 313loop of iterations (default is 100). During this process, the pipeline collects 314a number of execution related statistics. At the end of this process, the 315pipeline generates and prints a report from the collected statistics. 316 317Here is an example of a performance report generated by the tool for a 318dot-product of two packed float vectors of four elements. The analysis is 319conducted for target x86, cpu btver2. The following result can be produced via 320the following command using the example located at 321``test/tools/llvm-mca/X86/BtVer2/dot-product.s``: 322 323.. code-block:: bash 324 325 $ llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=300 dot-product.s 326 327.. code-block:: none 328 329 Iterations: 300 330 Instructions: 900 331 Total Cycles: 610 332 Total uOps: 900 333 334 Dispatch Width: 2 335 uOps Per Cycle: 1.48 336 IPC: 1.48 337 Block RThroughput: 2.0 338 339 340 Instruction Info: 341 [1]: #uOps 342 [2]: Latency 343 [3]: RThroughput 344 [4]: MayLoad 345 [5]: MayStore 346 [6]: HasSideEffects (U) 347 348 [1] [2] [3] [4] [5] [6] Instructions: 349 1 2 1.00 vmulps %xmm0, %xmm1, %xmm2 350 1 3 1.00 vhaddps %xmm2, %xmm2, %xmm3 351 1 3 1.00 vhaddps %xmm3, %xmm3, %xmm4 352 353 354 Resources: 355 [0] - JALU0 356 [1] - JALU1 357 [2] - JDiv 358 [3] - JFPA 359 [4] - JFPM 360 [5] - JFPU0 361 [6] - JFPU1 362 [7] - JLAGU 363 [8] - JMul 364 [9] - JSAGU 365 [10] - JSTC 366 [11] - JVALU0 367 [12] - JVALU1 368 [13] - JVIMUL 369 370 371 Resource pressure per iteration: 372 [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] 373 - - - 2.00 1.00 2.00 1.00 - - - - - - - 374 375 Resource pressure by instruction: 376 [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: 377 - - - - 1.00 - 1.00 - - - - - - - vmulps %xmm0, %xmm1, %xmm2 378 - - - 1.00 - 1.00 - - - - - - - - vhaddps %xmm2, %xmm2, %xmm3 379 - - - 1.00 - 1.00 - - - - - - - - vhaddps %xmm3, %xmm3, %xmm4 380 381According to this report, the dot-product kernel has been executed 300 times, 382for a total of 900 simulated instructions. The total number of simulated micro 383opcodes (uOps) is also 900. 384 385The report is structured in three main sections. The first section collects a 386few performance numbers; the goal of this section is to give a very quick 387overview of the performance throughput. Important performance indicators are 388**IPC**, **uOps Per Cycle**, and **Block RThroughput** (Block Reciprocal 389Throughput). 390 391Field *DispatchWidth* is the maximum number of micro opcodes that are dispatched 392to the out-of-order backend every simulated cycle. For processors with an 393in-order backend, *DispatchWidth* is the maximum number of micro opcodes issued 394to the backend every simulated cycle. 395 396IPC is computed dividing the total number of simulated instructions by the total 397number of cycles. 398 399Field *Block RThroughput* is the reciprocal of the block throughput. Block 400throughput is a theoretical quantity computed as the maximum number of blocks 401(i.e. iterations) that can be executed per simulated clock cycle in the absence 402of loop carried dependencies. Block throughput is superiorly limited by the 403dispatch rate, and the availability of hardware resources. 404 405In the absence of loop-carried data dependencies, the observed IPC tends to a 406theoretical maximum which can be computed by dividing the number of instructions 407of a single iteration by the `Block RThroughput`. 408 409Field 'uOps Per Cycle' is computed dividing the total number of simulated micro 410opcodes by the total number of cycles. A delta between Dispatch Width and this 411field is an indicator of a performance issue. In the absence of loop-carried 412data dependencies, the observed 'uOps Per Cycle' should tend to a theoretical 413maximum throughput which can be computed by dividing the number of uOps of a 414single iteration by the `Block RThroughput`. 415 416Field *uOps Per Cycle* is bounded from above by the dispatch width. That is 417because the dispatch width limits the maximum size of a dispatch group. Both IPC 418and 'uOps Per Cycle' are limited by the amount of hardware parallelism. The 419availability of hardware resources affects the resource pressure distribution, 420and it limits the number of instructions that can be executed in parallel every 421cycle. A delta between Dispatch Width and the theoretical maximum uOps per 422Cycle (computed by dividing the number of uOps of a single iteration by the 423`Block RThroughput`) is an indicator of a performance bottleneck caused by the 424lack of hardware resources. 425In general, the lower the Block RThroughput, the better. 426 427In this example, ``uOps per iteration/Block RThroughput`` is 1.50. Since there 428are no loop-carried dependencies, the observed `uOps Per Cycle` is expected to 429approach 1.50 when the number of iterations tends to infinity. The delta between 430the Dispatch Width (2.00), and the theoretical maximum uOp throughput (1.50) is 431an indicator of a performance bottleneck caused by the lack of hardware 432resources, and the *Resource pressure view* can help to identify the problematic 433resource usage. 434 435The second section of the report is the `instruction info view`. It shows the 436latency and reciprocal throughput of every instruction in the sequence. It also 437reports extra information related to the number of micro opcodes, and opcode 438properties (i.e., 'MayLoad', 'MayStore', and 'HasSideEffects'). 439 440Field *RThroughput* is the reciprocal of the instruction throughput. Throughput 441is computed as the maximum number of instructions of a same type that can be 442executed per clock cycle in the absence of operand dependencies. In this 443example, the reciprocal throughput of a vector float multiply is 1 444cycles/instruction. That is because the FP multiplier JFPM is only available 445from pipeline JFPU1. 446 447Instruction encodings are displayed within the instruction info view when flag 448`-show-encoding` is specified. 449 450Below is an example of `-show-encoding` output for the dot-product kernel: 451 452.. code-block:: none 453 454 Instruction Info: 455 [1]: #uOps 456 [2]: Latency 457 [3]: RThroughput 458 [4]: MayLoad 459 [5]: MayStore 460 [6]: HasSideEffects (U) 461 [7]: Encoding Size 462 463 [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions: 464 1 2 1.00 4 c5 f0 59 d0 vmulps %xmm0, %xmm1, %xmm2 465 1 4 1.00 4 c5 eb 7c da vhaddps %xmm2, %xmm2, %xmm3 466 1 4 1.00 4 c5 e3 7c e3 vhaddps %xmm3, %xmm3, %xmm4 467 468The `Encoding Size` column shows the size in bytes of instructions. The 469`Encodings` column shows the actual instruction encodings (byte sequences in 470hex). 471 472The third section is the *Resource pressure view*. This view reports 473the average number of resource cycles consumed every iteration by instructions 474for every processor resource unit available on the target. Information is 475structured in two tables. The first table reports the number of resource cycles 476spent on average every iteration. The second table correlates the resource 477cycles to the machine instruction in the sequence. For example, every iteration 478of the instruction vmulps always executes on resource unit [6] 479(JFPU1 - floating point pipeline #1), consuming an average of 1 resource cycle 480per iteration. Note that on AMD Jaguar, vector floating-point multiply can 481only be issued to pipeline JFPU1, while horizontal floating-point additions can 482only be issued to pipeline JFPU0. 483 484The resource pressure view helps with identifying bottlenecks caused by high 485usage of specific hardware resources. Situations with resource pressure mainly 486concentrated on a few resources should, in general, be avoided. Ideally, 487pressure should be uniformly distributed between multiple resources. 488 489Timeline View 490^^^^^^^^^^^^^ 491The timeline view produces a detailed report of each instruction's state 492transitions through an instruction pipeline. This view is enabled by the 493command line option ``-timeline``. As instructions transition through the 494various stages of the pipeline, their states are depicted in the view report. 495These states are represented by the following characters: 496 497* D : Instruction dispatched. 498* e : Instruction executing. 499* E : Instruction executed. 500* R : Instruction retired. 501* = : Instruction already dispatched, waiting to be executed. 502* \- : Instruction executed, waiting to be retired. 503 504Below is the timeline view for a subset of the dot-product example located in 505``test/tools/llvm-mca/X86/BtVer2/dot-product.s`` and processed by 506:program:`llvm-mca` using the following command: 507 508.. code-block:: bash 509 510 $ llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=3 -timeline dot-product.s 511 512.. code-block:: none 513 514 Timeline view: 515 012345 516 Index 0123456789 517 518 [0,0] DeeER. . . vmulps %xmm0, %xmm1, %xmm2 519 [0,1] D==eeeER . . vhaddps %xmm2, %xmm2, %xmm3 520 [0,2] .D====eeeER . vhaddps %xmm3, %xmm3, %xmm4 521 [1,0] .DeeE-----R . vmulps %xmm0, %xmm1, %xmm2 522 [1,1] . D=eeeE---R . vhaddps %xmm2, %xmm2, %xmm3 523 [1,2] . D====eeeER . vhaddps %xmm3, %xmm3, %xmm4 524 [2,0] . DeeE-----R . vmulps %xmm0, %xmm1, %xmm2 525 [2,1] . D====eeeER . vhaddps %xmm2, %xmm2, %xmm3 526 [2,2] . D======eeeER vhaddps %xmm3, %xmm3, %xmm4 527 528 529 Average Wait times (based on the timeline view): 530 [0]: Executions 531 [1]: Average time spent waiting in a scheduler's queue 532 [2]: Average time spent waiting in a scheduler's queue while ready 533 [3]: Average time elapsed from WB until retire stage 534 535 [0] [1] [2] [3] 536 0. 3 1.0 1.0 3.3 vmulps %xmm0, %xmm1, %xmm2 537 1. 3 3.3 0.7 1.0 vhaddps %xmm2, %xmm2, %xmm3 538 2. 3 5.7 0.0 0.0 vhaddps %xmm3, %xmm3, %xmm4 539 3 3.3 0.5 1.4 <total> 540 541The timeline view is interesting because it shows instruction state changes 542during execution. It also gives an idea of how the tool processes instructions 543executed on the target, and how their timing information might be calculated. 544 545The timeline view is structured in two tables. The first table shows 546instructions changing state over time (measured in cycles); the second table 547(named *Average Wait times*) reports useful timing statistics, which should 548help diagnose performance bottlenecks caused by long data dependencies and 549sub-optimal usage of hardware resources. 550 551An instruction in the timeline view is identified by a pair of indices, where 552the first index identifies an iteration, and the second index is the 553instruction index (i.e., where it appears in the code sequence). Since this 554example was generated using 3 iterations: ``-iterations=3``, the iteration 555indices range from 0-2 inclusively. 556 557Excluding the first and last column, the remaining columns are in cycles. 558Cycles are numbered sequentially starting from 0. 559 560From the example output above, we know the following: 561 562* Instruction [1,0] was dispatched at cycle 1. 563* Instruction [1,0] started executing at cycle 2. 564* Instruction [1,0] reached the write back stage at cycle 4. 565* Instruction [1,0] was retired at cycle 10. 566 567Instruction [1,0] (i.e., vmulps from iteration #1) does not have to wait in the 568scheduler's queue for the operands to become available. By the time vmulps is 569dispatched, operands are already available, and pipeline JFPU1 is ready to 570serve another instruction. So the instruction can be immediately issued on the 571JFPU1 pipeline. That is demonstrated by the fact that the instruction only 572spent 1cy in the scheduler's queue. 573 574There is a gap of 5 cycles between the write-back stage and the retire event. 575That is because instructions must retire in program order, so [1,0] has to wait 576for [0,2] to be retired first (i.e., it has to wait until cycle 10). 577 578In the example, all instructions are in a RAW (Read After Write) dependency 579chain. Register %xmm2 written by vmulps is immediately used by the first 580vhaddps, and register %xmm3 written by the first vhaddps is used by the second 581vhaddps. Long data dependencies negatively impact the ILP (Instruction Level 582Parallelism). 583 584In the dot-product example, there are anti-dependencies introduced by 585instructions from different iterations. However, those dependencies can be 586removed at register renaming stage (at the cost of allocating register aliases, 587and therefore consuming physical registers). 588 589Table *Average Wait times* helps diagnose performance issues that are caused by 590the presence of long latency instructions and potentially long data dependencies 591which may limit the ILP. Last row, ``<total>``, shows a global average over all 592instructions measured. Note that :program:`llvm-mca`, by default, assumes at 593least 1cy between the dispatch event and the issue event. 594 595When the performance is limited by data dependencies and/or long latency 596instructions, the number of cycles spent while in the *ready* state is expected 597to be very small when compared with the total number of cycles spent in the 598scheduler's queue. The difference between the two counters is a good indicator 599of how large of an impact data dependencies had on the execution of the 600instructions. When performance is mostly limited by the lack of hardware 601resources, the delta between the two counters is small. However, the number of 602cycles spent in the queue tends to be larger (i.e., more than 1-3cy), 603especially when compared to other low latency instructions. 604 605Bottleneck Analysis 606^^^^^^^^^^^^^^^^^^^ 607The ``-bottleneck-analysis`` command line option enables the analysis of 608performance bottlenecks. 609 610This analysis is potentially expensive. It attempts to correlate increases in 611backend pressure (caused by pipeline resource pressure and data dependencies) to 612dynamic dispatch stalls. 613 614Below is an example of ``-bottleneck-analysis`` output generated by 615:program:`llvm-mca` for 500 iterations of the dot-product example on btver2. 616 617.. code-block:: none 618 619 620 Cycles with backend pressure increase [ 48.07% ] 621 Throughput Bottlenecks: 622 Resource Pressure [ 47.77% ] 623 - JFPA [ 47.77% ] 624 - JFPU0 [ 47.77% ] 625 Data Dependencies: [ 0.30% ] 626 - Register Dependencies [ 0.30% ] 627 - Memory Dependencies [ 0.00% ] 628 629 Critical sequence based on the simulation: 630 631 Instruction Dependency Information 632 +----< 2. vhaddps %xmm3, %xmm3, %xmm4 633 | 634 | < loop carried > 635 | 636 | 0. vmulps %xmm0, %xmm1, %xmm2 637 +----> 1. vhaddps %xmm2, %xmm2, %xmm3 ## RESOURCE interference: JFPA [ probability: 74% ] 638 +----> 2. vhaddps %xmm3, %xmm3, %xmm4 ## REGISTER dependency: %xmm3 639 | 640 | < loop carried > 641 | 642 +----> 1. vhaddps %xmm2, %xmm2, %xmm3 ## RESOURCE interference: JFPA [ probability: 74% ] 643 644 645According to the analysis, throughput is limited by resource pressure and not by 646data dependencies. The analysis observed increases in backend pressure during 64748.07% of the simulated run. Almost all those pressure increase events were 648caused by contention on processor resources JFPA/JFPU0. 649 650The `critical sequence` is the most expensive sequence of instructions according 651to the simulation. It is annotated to provide extra information about critical 652register dependencies and resource interferences between instructions. 653 654Instructions from the critical sequence are expected to significantly impact 655performance. By construction, the accuracy of this analysis is strongly 656dependent on the simulation and (as always) by the quality of the processor 657model in llvm. 658 659Bottleneck analysis is currently not supported for processors with an in-order 660backend. 661 662Extra Statistics to Further Diagnose Performance Issues 663^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 664The ``-all-stats`` command line option enables extra statistics and performance 665counters for the dispatch logic, the reorder buffer, the retire control unit, 666and the register file. 667 668Below is an example of ``-all-stats`` output generated by :program:`llvm-mca` 669for 300 iterations of the dot-product example discussed in the previous 670sections. 671 672.. code-block:: none 673 674 Dynamic Dispatch Stall Cycles: 675 RAT - Register unavailable: 0 676 RCU - Retire tokens unavailable: 0 677 SCHEDQ - Scheduler full: 272 (44.6%) 678 LQ - Load queue full: 0 679 SQ - Store queue full: 0 680 GROUP - Static restrictions on the dispatch group: 0 681 682 683 Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 684 [# dispatched], [# cycles] 685 0, 24 (3.9%) 686 1, 272 (44.6%) 687 2, 314 (51.5%) 688 689 690 Schedulers - number of cycles where we saw N micro opcodes issued: 691 [# issued], [# cycles] 692 0, 7 (1.1%) 693 1, 306 (50.2%) 694 2, 297 (48.7%) 695 696 Scheduler's queue usage: 697 [1] Resource name. 698 [2] Average number of used buffer entries. 699 [3] Maximum number of used buffer entries. 700 [4] Total number of buffer entries. 701 702 [1] [2] [3] [4] 703 JALU01 0 0 20 704 JFPU01 17 18 18 705 JLSAGU 0 0 12 706 707 708 Retire Control Unit - number of cycles where we saw N instructions retired: 709 [# retired], [# cycles] 710 0, 109 (17.9%) 711 1, 102 (16.7%) 712 2, 399 (65.4%) 713 714 Total ROB Entries: 64 715 Max Used ROB Entries: 35 ( 54.7% ) 716 Average Used ROB Entries per cy: 32 ( 50.0% ) 717 718 719 Register File statistics: 720 Total number of mappings created: 900 721 Max number of mappings used: 35 722 723 * Register File #1 -- JFpuPRF: 724 Number of physical registers: 72 725 Total number of mappings created: 900 726 Max number of mappings used: 35 727 728 * Register File #2 -- JIntegerPRF: 729 Number of physical registers: 64 730 Total number of mappings created: 0 731 Max number of mappings used: 0 732 733If we look at the *Dynamic Dispatch Stall Cycles* table, we see the counter for 734SCHEDQ reports 272 cycles. This counter is incremented every time the dispatch 735logic is unable to dispatch a full group because the scheduler's queue is full. 736 737Looking at the *Dispatch Logic* table, we see that the pipeline was only able to 738dispatch two micro opcodes 51.5% of the time. The dispatch group was limited to 739one micro opcode 44.6% of the cycles, which corresponds to 272 cycles. The 740dispatch statistics are displayed by either using the command option 741``-all-stats`` or ``-dispatch-stats``. 742 743The next table, *Schedulers*, presents a histogram displaying a count, 744representing the number of micro opcodes issued on some number of cycles. In 745this case, of the 610 simulated cycles, single opcodes were issued 306 times 746(50.2%) and there were 7 cycles where no opcodes were issued. 747 748The *Scheduler's queue usage* table shows that the average and maximum number of 749buffer entries (i.e., scheduler queue entries) used at runtime. Resource JFPU01 750reached its maximum (18 of 18 queue entries). Note that AMD Jaguar implements 751three schedulers: 752 753* JALU01 - A scheduler for ALU instructions. 754* JFPU01 - A scheduler floating point operations. 755* JLSAGU - A scheduler for address generation. 756 757The dot-product is a kernel of three floating point instructions (a vector 758multiply followed by two horizontal adds). That explains why only the floating 759point scheduler appears to be used. 760 761A full scheduler queue is either caused by data dependency chains or by a 762sub-optimal usage of hardware resources. Sometimes, resource pressure can be 763mitigated by rewriting the kernel using different instructions that consume 764different scheduler resources. Schedulers with a small queue are less resilient 765to bottlenecks caused by the presence of long data dependencies. The scheduler 766statistics are displayed by using the command option ``-all-stats`` or 767``-scheduler-stats``. 768 769The next table, *Retire Control Unit*, presents a histogram displaying a count, 770representing the number of instructions retired on some number of cycles. In 771this case, of the 610 simulated cycles, two instructions were retired during the 772same cycle 399 times (65.4%) and there were 109 cycles where no instructions 773were retired. The retire statistics are displayed by using the command option 774``-all-stats`` or ``-retire-stats``. 775 776The last table presented is *Register File statistics*. Each physical register 777file (PRF) used by the pipeline is presented in this table. In the case of AMD 778Jaguar, there are two register files, one for floating-point registers (JFpuPRF) 779and one for integer registers (JIntegerPRF). The table shows that of the 900 780instructions processed, there were 900 mappings created. Since this dot-product 781example utilized only floating point registers, the JFPuPRF was responsible for 782creating the 900 mappings. However, we see that the pipeline only used a 783maximum of 35 of 72 available register slots at any given time. We can conclude 784that the floating point PRF was the only register file used for the example, and 785that it was never resource constrained. The register file statistics are 786displayed by using the command option ``-all-stats`` or 787``-register-file-stats``. 788 789In this example, we can conclude that the IPC is mostly limited by data 790dependencies, and not by resource pressure. 791 792Instruction Flow 793^^^^^^^^^^^^^^^^ 794This section describes the instruction flow through the default pipeline of 795:program:`llvm-mca`, as well as the functional units involved in the process. 796 797The default pipeline implements the following sequence of stages used to 798process instructions. 799 800* Dispatch (Instruction is dispatched to the schedulers). 801* Issue (Instruction is issued to the processor pipelines). 802* Write Back (Instruction is executed, and results are written back). 803* Retire (Instruction is retired; writes are architecturally committed). 804 805The in-order pipeline implements the following sequence of stages: 806* InOrderIssue (Instruction is issued to the processor pipelines). 807* Retire (Instruction is retired; writes are architecturally committed). 808 809:program:`llvm-mca` assumes that instructions have all been decoded and placed 810into a queue before the simulation start. Therefore, the instruction fetch and 811decode stages are not modeled. Performance bottlenecks in the frontend are not 812diagnosed. Also, :program:`llvm-mca` does not model branch prediction. 813 814Instruction Dispatch 815"""""""""""""""""""" 816During the dispatch stage, instructions are picked in program order from a 817queue of already decoded instructions, and dispatched in groups to the 818simulated hardware schedulers. 819 820The size of a dispatch group depends on the availability of the simulated 821hardware resources. The processor dispatch width defaults to the value 822of the ``IssueWidth`` in LLVM's scheduling model. 823 824An instruction can be dispatched if: 825 826* The size of the dispatch group is smaller than processor's dispatch width. 827* There are enough entries in the reorder buffer. 828* There are enough physical registers to do register renaming. 829* The schedulers are not full. 830 831Scheduling models can optionally specify which register files are available on 832the processor. :program:`llvm-mca` uses that information to initialize register 833file descriptors. Users can limit the number of physical registers that are 834globally available for register renaming by using the command option 835``-register-file-size``. A value of zero for this option means *unbounded*. By 836knowing how many registers are available for renaming, the tool can predict 837dispatch stalls caused by the lack of physical registers. 838 839The number of reorder buffer entries consumed by an instruction depends on the 840number of micro-opcodes specified for that instruction by the target scheduling 841model. The reorder buffer is responsible for tracking the progress of 842instructions that are "in-flight", and retiring them in program order. The 843number of entries in the reorder buffer defaults to the value specified by field 844`MicroOpBufferSize` in the target scheduling model. 845 846Instructions that are dispatched to the schedulers consume scheduler buffer 847entries. :program:`llvm-mca` queries the scheduling model to determine the set 848of buffered resources consumed by an instruction. Buffered resources are 849treated like scheduler resources. 850 851Instruction Issue 852""""""""""""""""" 853Each processor scheduler implements a buffer of instructions. An instruction 854has to wait in the scheduler's buffer until input register operands become 855available. Only at that point, does the instruction becomes eligible for 856execution and may be issued (potentially out-of-order) for execution. 857Instruction latencies are computed by :program:`llvm-mca` with the help of the 858scheduling model. 859 860:program:`llvm-mca`'s scheduler is designed to simulate multiple processor 861schedulers. The scheduler is responsible for tracking data dependencies, and 862dynamically selecting which processor resources are consumed by instructions. 863It delegates the management of processor resource units and resource groups to a 864resource manager. The resource manager is responsible for selecting resource 865units that are consumed by instructions. For example, if an instruction 866consumes 1cy of a resource group, the resource manager selects one of the 867available units from the group; by default, the resource manager uses a 868round-robin selector to guarantee that resource usage is uniformly distributed 869between all units of a group. 870 871:program:`llvm-mca`'s scheduler internally groups instructions into three sets: 872 873* WaitSet: a set of instructions whose operands are not ready. 874* ReadySet: a set of instructions ready to execute. 875* IssuedSet: a set of instructions executing. 876 877Depending on the operands availability, instructions that are dispatched to the 878scheduler are either placed into the WaitSet or into the ReadySet. 879 880Every cycle, the scheduler checks if instructions can be moved from the WaitSet 881to the ReadySet, and if instructions from the ReadySet can be issued to the 882underlying pipelines. The algorithm prioritizes older instructions over younger 883instructions. 884 885Write-Back and Retire Stage 886""""""""""""""""""""""""""" 887Issued instructions are moved from the ReadySet to the IssuedSet. There, 888instructions wait until they reach the write-back stage. At that point, they 889get removed from the queue and the retire control unit is notified. 890 891When instructions are executed, the retire control unit flags the instruction as 892"ready to retire." 893 894Instructions are retired in program order. The register file is notified of the 895retirement so that it can free the physical registers that were allocated for 896the instruction during the register renaming stage. 897 898Load/Store Unit and Memory Consistency Model 899"""""""""""""""""""""""""""""""""""""""""""" 900To simulate an out-of-order execution of memory operations, :program:`llvm-mca` 901utilizes a simulated load/store unit (LSUnit) to simulate the speculative 902execution of loads and stores. 903 904Each load (or store) consumes an entry in the load (or store) queue. Users can 905specify flags ``-lqueue`` and ``-squeue`` to limit the number of entries in the 906load and store queues respectively. The queues are unbounded by default. 907 908The LSUnit implements a relaxed consistency model for memory loads and stores. 909The rules are: 910 9111. A younger load is allowed to pass an older load only if there are no 912 intervening stores or barriers between the two loads. 9132. A younger load is allowed to pass an older store provided that the load does 914 not alias with the store. 9153. A younger store is not allowed to pass an older store. 9164. A younger store is not allowed to pass an older load. 917 918By default, the LSUnit optimistically assumes that loads do not alias 919(`-noalias=true`) store operations. Under this assumption, younger loads are 920always allowed to pass older stores. Essentially, the LSUnit does not attempt 921to run any alias analysis to predict when loads and stores do not alias with 922each other. 923 924Note that, in the case of write-combining memory, rule 3 could be relaxed to 925allow reordering of non-aliasing store operations. That being said, at the 926moment, there is no way to further relax the memory model (``-noalias`` is the 927only option). Essentially, there is no option to specify a different memory 928type (e.g., write-back, write-combining, write-through; etc.) and consequently 929to weaken, or strengthen, the memory model. 930 931Other limitations are: 932 933* The LSUnit does not know when store-to-load forwarding may occur. 934* The LSUnit does not know anything about cache hierarchy and memory types. 935* The LSUnit does not know how to identify serializing operations and memory 936 fences. 937 938The LSUnit does not attempt to predict if a load or store hits or misses the L1 939cache. It only knows if an instruction "MayLoad" and/or "MayStore." For 940loads, the scheduling model provides an "optimistic" load-to-use latency (which 941usually matches the load-to-use latency for when there is a hit in the L1D). 942 943:program:`llvm-mca` does not know about serializing operations or memory-barrier 944like instructions. The LSUnit conservatively assumes that an instruction which 945has both "MayLoad" and unmodeled side effects behaves like a "soft" 946load-barrier. That means, it serializes loads without forcing a flush of the 947load queue. Similarly, instructions that "MayStore" and have unmodeled side 948effects are treated like store barriers. A full memory barrier is a "MayLoad" 949and "MayStore" instruction with unmodeled side effects. This is inaccurate, but 950it is the best that we can do at the moment with the current information 951available in LLVM. 952 953A load/store barrier consumes one entry of the load/store queue. A load/store 954barrier enforces ordering of loads/stores. A younger load cannot pass a load 955barrier. Also, a younger store cannot pass a store barrier. A younger load 956has to wait for the memory/load barrier to execute. A load/store barrier is 957"executed" when it becomes the oldest entry in the load/store queue(s). That 958also means, by construction, all of the older loads/stores have been executed. 959 960In conclusion, the full set of load/store consistency rules are: 961 962#. A store may not pass a previous store. 963#. A store may not pass a previous load (regardless of ``-noalias``). 964#. A store has to wait until an older store barrier is fully executed. 965#. A load may pass a previous load. 966#. A load may not pass a previous store unless ``-noalias`` is set. 967#. A load has to wait until an older load barrier is fully executed. 968 969In-order Issue and Execute 970"""""""""""""""""""""""""""""""""""" 971In-order processors are modelled as a single ``InOrderIssueStage`` stage. It 972bypasses Dispatch, Scheduler and Load/Store unit. Instructions are issued as 973soon as their operand registers are available and resource requirements are 974met. Multiple instructions can be issued in one cycle according to the value of 975the ``IssueWidth`` parameter in LLVM's scheduling model. 976 977Once issued, an instruction is moved to ``IssuedInst`` set until it is ready to 978retire. :program:`llvm-mca` ensures that writes are committed in-order. However, 979an instruction is allowed to commit writes and retire out-of-order if 980``RetireOOO`` property is true for at least one of its writes. 981