1 /* 2 * rtl8169.h 3 */ 4 5 #define RL_N_DESC 1024 /* Number of descriptors */ 6 #define N_RX_DESC RL_N_DESC /* Number of receive descriptors */ 7 #define N_TX_DESC RL_N_DESC /* Number of transmit descriptors */ 8 9 #define RX_BUFSIZE 1536 /* Maximum gigabit ethernet frame size */ 10 11 /* Transmit Descriptor control */ 12 #define DESC_RX_LGSEN 0x08000000 /* Large Send */ 13 #define DESC_RX_IPCS 0x00040000 /* IP Checksum Offload */ 14 #define DESC_RX_UDPCS 0x00020000 /* UDP Checksum Offload */ 15 #define DESC_RX_TCPCS 0x00010000 /* TCP Checksum Offload */ 16 #define DESC_TX_LENMASK 0x0000FFFF /* Transmit Frame Length Mask */ 17 18 /* Receive Descriptor control */ 19 #define DESC_RX_MAR 0x08000000 /* Multicast Address Received */ 20 #define DESC_RX_PAM 0x04000000 /* Physical Address Matched */ 21 #define DESC_RX_BAR 0x02000000 /* Broadcast Address Received */ 22 #define DESC_RX_BOVF 0x01000000 /* Buffer Overflow */ 23 #define DESC_RX_FOVF 0x00800000 /* FIFO Overflow */ 24 #define DESC_RX_RWT 0x00400000 /* Receive Watchdog Timer Expired */ 25 #define DESC_RX_RES 0x00200000 /* Receive Error Summary */ 26 #define DESC_RX_RUNT 0x00100000 /* Runt Packet */ 27 #define DESC_RX_CRC 0x00080000 /* CRC Error */ 28 #define DESC_RX_PID1 0x00040000 /* Protocol ID1 */ 29 #define DESC_RX_PID0 0x00020000 /* Protocol ID0 */ 30 #define DESC_RX_IPF 0x00010000 /* IP Checksum Failure */ 31 #define DESC_RX_UDPF 0x00008000 /* UDP Checksum Failure */ 32 #define DESC_RX_TCPF 0x00004000 /* TCP Checksum Failure */ 33 #define DESC_RX_LENMASK 0x00001FFF /* Receive Frame Length Mask */ 34 35 /* General Descriptor control */ 36 #define DESC_OWN 0x80000000 /* Ownership */ 37 #define DESC_EOR 0x40000000 /* End of Descriptor Ring */ 38 #define DESC_FS 0x20000000 /* First Segment Descriptor */ 39 #define DESC_LS 0x10000000 /* Last Segment Descriptor */ 40 41 42 #define RL_IDR 0x00 /* Ethernet address 43 * Note: RL_9346CR_EEM_CONFIG mode is 44 * required the change the ethernet address. 45 * Note: 4-byte write access only. 46 */ 47 #define RL_MAR 0x08 /* Multicast */ 48 #define RL_DTCCR_LO 0x10 /* Dump Tally Counter Command Register LOW */ 49 #define RL_DTCCR_HI 0x14 /* Dump Tally Counter Command Register HIGH */ 50 #define RL_DTCCR_CMD 0x08 /* Command */ 51 #define RL_TNPDS_LO 0x20 /* Transmit Normal Priority Descriptors Start Address LOW */ 52 #define RL_TNPDS_HI 0x24 /* Transmit Normal Priority Descriptors Start Address HIGH */ 53 #define RL_THPDS_LO 0x28 /* Transmit High Priority Descriptors Start Address LOW */ 54 #define RL_THPDS_HI 0x2C /* Transmit High Priority Descriptors Start Address HIGH */ 55 #define RL_FLASH 0x30 /* Flash Memory Read/Write Register */ 56 #define RL_ERBCR 0x34 /* Early Receive (Rx) Byte Count Register */ 57 #define RL_ERSR 0x36 /* Early Rx Status Register */ 58 #define RL_ERSR_RES 0xF0 /* Reserved */ 59 #define RL_ERSR_ERGOOD 0x08 /* Early Rx Good packet */ 60 #define RL_ERSR_ERBAD 0x04 /* Early Rx Bad packet */ 61 #define RL_ERSR_EROVW 0x02 /* Early Rx OverWrite */ 62 #define RL_ERSR_EROK 0x01 /* Early Rx OK */ 63 #define RL_CR 0x37 /* Command Register */ 64 #define RL_CR_RES0 0xE0 /* Reserved */ 65 #define RL_CR_RST 0x10 /* Reset */ 66 #define RL_CR_RE 0x08 /* Receiver Enable */ 67 #define RL_CR_TE 0x04 /* Transmitter Enable * 68 * Note: start with transmit buffer 69 * 0 after RL_CR_TE has been reset. 70 */ 71 #define RL_CR_RES1 0x02 /* Reserved */ 72 #define RL_CR_BUFE 0x01 /* Receive Buffer Empty */ 73 #define RL_TPPOLL 0x38 /* Transmit Priority Polling Register */ 74 #define RL_TPPOLL_HPQ 0x80 /* High Priority Queue Polling */ 75 #define RL_TPPOLL_NPQ 0x40 /* Normal Priority Queue Polling */ 76 #define RL_TPPOLL_FSW 0x01 /* Forced Software Interrupt */ 77 #define RL_IMR 0x3C /* Interrupt Mask Register */ 78 #define RL_IMR_SERR 0x8000 /* System Error */ 79 #define RL_IMR_TIMEOUT 0x4000 /* Time Out */ 80 #define RL_IMR_RES 0x3E00 /* Reserved */ 81 #define RL_IMR_SWINT 0x0100 /* Software Interrupt */ 82 #define RL_IMR_TDU 0x0080 /* Tx Descriptor Unavailable */ 83 #define RL_IMR_FOVW 0x0040 /* Rx FIFO Overflow */ 84 #define RL_IMR_PUN 0x0020 /* Packet Underrun / Link Change */ 85 #define RL_IMR_RDU 0x0010 /* Rx Descriptor Unavailable */ 86 #define RL_IMR_TER 0x0008 /* Transmit Error */ 87 #define RL_IMR_TOK 0x0004 /* Transmit OK */ 88 #define RL_IMR_RER 0x0002 /* Receive Error */ 89 #define RL_IMR_ROK 0x0001 /* Receive OK */ 90 #define RL_ISR 0x3E /* Interrupt Status Register */ 91 #define RL_ISR_SERR 0x8000 /* System Error */ 92 #define RL_ISR_TIMEOUT 0x4000 /* Time Out */ 93 #define RL_ISR_RES 0x3E00 /* Reserved */ 94 #define RL_ISR_SWINT 0x0100 /* Software Interrupt */ 95 #define RL_ISR_TDU 0x0080 /* Tx Descriptor Unavailable */ 96 #define RL_ISR_FOVW 0x0040 /* Rx FIFO Overflow */ 97 #define RL_ISR_PUN 0x0020 /* Packet Underrun / Link Change */ 98 #define RL_ISR_RDU 0x0010 /* Rx Descriptor Unavailable */ 99 #define RL_ISR_TER 0x0008 /* Transmit Error */ 100 #define RL_ISR_TOK 0x0004 /* Transmit OK */ 101 #define RL_ISR_RER 0x0002 /* Receive Error */ 102 #define RL_ISR_ROK 0x0001 /* Receive OK */ 103 #define RL_TCR 0x40 /* Transmit Configuration Register 104 * Note: RL_CR_TE has to be set to 105 * set/change RL_TCR. 106 */ 107 #define RL_TCR_RES0 0x80000000 /* Reserved */ 108 #define RL_TCR_HWVER_AM 0x7C000000 /* Hardware Version ID A */ 109 #define RL_TCR_IFG_M 0x03000000 /* Interframe Gap Time */ 110 #define RL_TCR_IFG_STD 0x03000000 /* IEEE 802.3 std */ 111 #define RL_TCR_HWVER_BM 0x00800000 /* Hardware Version ID B */ 112 #define RL_TCR_HWVER_RTL8169 0x00000000 /* RTL8169 */ 113 #define RL_TCR_HWVER_RTL8169S 0x00800000 /* RTL8169S */ 114 #define RL_TCR_HWVER_RTL8110S 0x04000000 /* RTL8110S */ 115 #define RL_TCR_HWVER_RTL8169SB 0x10000000 /* RTL8169sb/8110sb */ 116 #define RL_TCR_HWVER_RTL8110SCd 0x18000000 /* RTL8169sc/8110sc */ 117 #define RL_TCR_HWVER_RTL8105E 0x40800000 /* RTL8105E */ 118 #define RL_TCR_RES1 0x00380000 /* Reserved */ 119 #define RL_TCR_LBK_M 0x00060000 /* Loopback Test */ 120 #define RL_TCR_LBK_NORMAL 0x00000000 /* Normal */ 121 #define RL_TCR_LBK_LOOKBOCK 0x00060000 /* Loopback Mode */ 122 #define RL_TCR_CRC 0x00010000 /* (Do not) Append CRC */ 123 #define RL_TCR_RES2 0x0000F800 /* Reserved */ 124 #define RL_TCR_MXDMA_M 0x00000700 /* Max DMA Burst Size Tx */ 125 #define RL_TCR_MXDMA_16 0x00000000 /* 16 bytes */ 126 #define RL_TCR_MXDMA_32 0x00000100 /* 32 bytes */ 127 #define RL_TCR_MXDMA_64 0x00000200 /* 64 bytes */ 128 #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */ 129 #define RL_TCR_MXDMA_128 0x00000300 /* 128 bytes */ 130 #define RL_TCR_MXDMA_256 0x00000400 /* 256 bytes */ 131 #define RL_TCR_MXDMA_512 0x00000500 /* 512 bytes */ 132 #define RL_TCR_MXDMA_1024 0x00000600 /* 1024 bytes */ 133 #define RL_TCR_MXDMA_2048 0x00000700 /* 2048 bytes */ 134 #define RL_TCR_TXRR_M 0x000000F0 /* Tx Retry Count */ 135 #define RL_TCR_RES3 0x0000000E /* Reserved */ 136 #define RL_TCR_CLRABT 0x00000001 /* Clear Abort */ 137 #define RL_RCR 0x44 /* Receive Configuration Register 138 * Note: RL_CR_RE has to be set to 139 * set/change RL_RCR. 140 */ 141 #define RL_RCR_RES0 0xF0000000 /* Reserved */ 142 #define RL_RCR_ERTH_M 0x0F000000 /* Early Rx Threshold */ 143 #define RL_RCR_ERTH_0 0x00000000 /* No threshold */ 144 #define RL_RCR_ERTH_1 0x01000000 /* 1/16 */ 145 #define RL_RCR_ERTH_2 0x02000000 /* 2/16 */ 146 #define RL_RCR_ERTH_3 0x03000000 /* 3/16 */ 147 #define RL_RCR_ERTH_4 0x04000000 /* 4/16 */ 148 #define RL_RCR_ERTH_5 0x05000000 /* 5/16 */ 149 #define RL_RCR_ERTH_6 0x06000000 /* 6/16 */ 150 #define RL_RCR_ERTH_7 0x07000000 /* 7/16 */ 151 #define RL_RCR_ERTH_8 0x08000000 /* 8/16 */ 152 #define RL_RCR_ERTH_9 0x09000000 /* 9/16 */ 153 #define RL_RCR_ERTH_10 0x0A000000 /* 10/16 */ 154 #define RL_RCR_ERTH_11 0x0B000000 /* 11/16 */ 155 #define RL_RCR_ERTH_12 0x0C000000 /* 12/16 */ 156 #define RL_RCR_ERTH_13 0x0D000000 /* 13/16 */ 157 #define RL_RCR_ERTH_14 0x0E000000 /* 14/16 */ 158 #define RL_RCR_ERTH_15 0x0F000000 /* 15/16 */ 159 #define RL_RCR_RES1 0x00FC0000 /* Reserved */ 160 #define RL_RCR_MULERINT 0x00020000 /* Multiple Early Int Select */ 161 #define RL_RCR_RER8 0x00010000 /* Receive small error packet */ 162 #define RL_RCR_RXFTH_M 0x0000E000 /* Rx FIFO Threshold */ 163 #define RL_RCR_RXFTH_16 0x00000000 /* 16 bytes */ 164 #define RL_RCR_RXFTH_32 0x00002000 /* 32 bytes */ 165 #define RL_RCR_RXFTH_64 0x00004000 /* 64 bytes */ 166 #define RL_RCR_RXFTH_128 0x00006000 /* 128 bytes */ 167 #define RL_RCR_RXFTH_256 0x00008000 /* 256 bytes */ 168 #define RL_RCR_RXFTH_512 0x0000A000 /* 512 bytes */ 169 #define RL_RCR_RXFTH_1024 0x0000C000 /* 1024 bytes */ 170 #define RL_RCR_RXFTH_UNLIM 0x0000E000 /* unlimited */ 171 #define RL_RCR_RBLEM_M 0x00001800 /* Rx Buffer Length */ 172 #define RL_RCR_RBLEN_8K 0x00000000 /* 8KB + 16 bytes */ 173 #define RL_RCR_RBLEN_8K_SIZE (8*1024) 174 #define RL_RCR_RBLEN_16K 0x00000800 /* 16KB + 16 bytes */ 175 #define RL_RCR_RBLEN_16K_SIZE (16*1024) 176 #define RL_RCR_RBLEN_32K 0x00001000 /* 32KB + 16 bytes */ 177 #define RL_RCR_RBLEN_32K_SIZE (32*1024) 178 #define RL_RCR_RBLEN_64K 0x00001800 /* 64KB + 16 bytes */ 179 #define RL_RCR_RBLEN_64K_SIZE (64*1024) 180 #define RL_RCR_MXDMA_M 0x00000700 /* Rx DMA burst size */ 181 #define RL_RCR_MXDMA_16 0x00000000 /* 16 bytes */ 182 #define RL_RCR_MXDMA_32 0x00000100 /* 32 bytes */ 183 #define RL_RCR_MXDMA_64 0x00000200 /* 64 bytes */ 184 #define RL_RCR_MXDMA_128 0x00000300 /* 128 bytes */ 185 #define RL_RCR_MXDMA_256 0x00000400 /* 256 bytes */ 186 #define RL_RCR_MXDMA_512 0x00000500 /* 512 bytes */ 187 #define RL_RCR_MXDMA_1024 0x00000600 /* 1024 bytes */ 188 #define RL_RCR_MXDMA_UNLIM 0x00000700 /* unlimited */ 189 #define RL_RCR_WRAP 0x00000080 /* (Do not) Wrap on receive */ 190 #define RL_RCR_9356 0x00000040 /* EEPROM 1:9356 0:9346 */ 191 #define RL_RCR_AER 0x00000020 /* Accept Error Packets */ 192 #define RL_RCR_AR 0x00000010 /* Accept Runt Packets */ 193 #define RL_RCR_AB 0x00000008 /* Accept Broadcast Packets */ 194 #define RL_RCR_AM 0x00000004 /* Accept Multicast Packets */ 195 #define RL_RCR_APM 0x00000002 /* Accept Physical Match Packets */ 196 #define RL_RCR_AAP 0x00000001 /* Accept All Packets */ 197 #define RL_TCTR 0x48 /* Timer Count Register */ 198 #define RL_MPC 0x4C /* Missed Packet Counter */ 199 #define RL_9346CR 0x50 /* 93C46 Command Register */ 200 #define RL_9346CR_EEM_M 0xC0 /* Operating Mode */ 201 #define RL_9346CR_EEM_NORMAL 0x00 /* Normal Mode */ 202 #define RL_9346CR_EEM_AUTOLOAD 0x40 /* Load from 93C46 */ 203 #define RL_9346CR_EEM_PROG 0x80 /* 93C46 Programming */ 204 #define RL_9346CR_EEM_CONFIG 0xC0 /* Config Write Enable */ 205 #define RL_9346CR_RES 0x30 /* Reserved */ 206 #define RL_9346CR_EECS 0x08 /* EECS Pin */ 207 #define RL_9346CR_EESK 0x04 /* EESK Pin */ 208 #define RL_9346CR_EEDI 0x02 /* EEDI Pin */ 209 #define RL_9346CR_EEDO 0x01 /* EEDO Pin */ 210 #define RL_CONFIG0 0x51 /* Configuration Register 0 */ 211 #define RL_CFG0_RES 0x000000F8 /* Reserved */ 212 #define RL_CFG0_ROM 0x00000007 /* Select Boot ROM Size */ 213 #define RL_CFG0_ROM128K 0x00000005 /* 128K Boot ROM */ 214 #define RL_CFG0_ROM64K 0x00000004 /* 64K Boot ROM */ 215 #define RL_CFG0_ROM32K 0x00000003 /* 32K Boot ROM */ 216 #define RL_CFG0_ROM16K 0x00000002 /* 16K Boot ROM */ 217 #define RL_CFG0_ROM8K 0x00000001 /* 8K Boot ROM */ 218 #define RL_CFG0_ROMNO 0x00000000 /* No Boot ROM */ 219 #define RL_CONFIG1 0x52 /* Configuration Register 1 */ 220 #define RL_CFG1_LEDS1 0x00000080 /* LED1 */ 221 #define RL_CFG1_LEDS0 0x00000040 /* LED0 */ 222 #define RL_CFG1_DVRLOAD 0x00000020 /* Driver Load */ 223 #define RL_CFG1_LWACT 0x00000010 /* LWAKE Active Mode */ 224 #define RL_CFG1_MEMMAP 0x00000008 /* Memory Mapping */ 225 #define RL_CFG1_IOMAP 0x00000004 /* I/O Mapping */ 226 #define RL_CFG1_VPD 0x00000002 /* Enable Vital Product Data */ 227 #define RL_CFG1_PME 0x00000001 /* Power Management Enable */ 228 #define RL_CONFIG2 0x53 /* Configuration Register 2 */ 229 #define RL_CFG2_RES 0x000000E0 /* Reserved */ 230 #define RL_CFG2_AUX 0x00000010 /* Auxiliary Power Present Status */ 231 #define RL_CFG2_PCIBW 0x00000008 /* PCI Bus Width 1:64 0:32 */ 232 #define RL_CFG2_PCICLK 0x00000007 /* PCI Clock Frequency */ 233 #define RL_CFG2_66MHZ 0x00000001 /* 66 MHz */ 234 #define RL_CFG2_33MHZ 0x00000000 /* 33 MHz */ 235 #define RL_CONFIG3 0x54 /* Configuration Register 3 */ 236 #define RL_CFG3_MAGIC 0x00000020 /* Wake up when receives a Magic Packet */ 237 #define RL_CFG3_LINKUP 0x00000010 /* Wake up when the cable connection is re-established */ 238 #define RL_CFG3_BEACON 0x00000001 /* 8168 only, Reserved in the 8168b */ 239 #define RL_CONFIG4 0x55 /* Configuration Register 4 */ 240 #define RL_CONFIG5 0x56 /* Configuration Register 5 */ 241 #define RL_CFG5_BWF 0x00000040 /* Accept Broadcast Wakeup Frame */ 242 #define RL_CFG5_MWF 0x00000020 /* Accept Multicast Eakeup Frame */ 243 #define RL_CFG5_UWF 0x00000010 /* Accept Unicast Wakeup Frame */ 244 #define RL_CFG5_LAN 0x00000002 /* LANWake Singnal enable/disable */ 245 #define RL_CFG5_PME 0x00000001 /* PME status can be reset by PCI RST# */ 246 #define RL_TIMERINT 0x58 /* Timer Interrupt Select */ 247 #define RL_MULINT 0x5C /* Multiple Interrupt Select */ 248 /* 0x5E */ /* Reserved */ 249 /* 0x5F */ /* Reserved */ 250 #define RL_PHYAR 0x60 /* PHY Access */ 251 #define RL_TBICSR0 0x64 /* TBI Control and Status Register */ 252 #define RL_TBIANAR 0x68 /* TBI Auto-Negotiation Advertisement Register */ 253 #define RL_TBILPAR 0x6A /* TBI Auto-Negotiation Link Partner Ability Register */ 254 #define RL_PHYSTAT 0x6C /* MII PHY Status */ 255 #define RL_STAT_TBI 0x00000080 /* TBI Enable */ 256 #define RL_STAT_TXFLOW 0x00000040 /* Tx Flow Control */ 257 #define RL_STAT_RXFLOW 0x00000020 /* Rx Flow Control */ 258 #define RL_STAT_1000 0x00000010 /* 1000 Mbps */ 259 #define RL_STAT_100 0x00000008 /* 100 Mbps */ 260 #define RL_STAT_10 0x00000004 /* 10 Mbps */ 261 #define RL_STAT_LINK 0x00000002 /* Link Status */ 262 #define RL_STAT_FULLDUP 0x00000001 /* Full Duplex */ 263 264 #define RL_CCR_UNDOC 0x82 /* Undocumented C+ Command Register */ 265 266 #define RL_RMS 0xDA /* Rx Maximum Size */ 267 #define RL_CPLUSCMD 0xE0 /* C+ Command Register */ 268 #define RL_CPLUS_VLAN 0x00000040 /* Receive VLAN D-tagging Enable */ 269 #define RL_CPLUS_CHKSUM 0x00000020 /* Receive Checksum Offload Enable */ 270 #define RL_CPLUS_DAC 0x00000010 /* PCI Dual Address Cycles Enable */ 271 #define RL_CPLUS_MULRW 0x00000008 /* PCI Multiple Read/Write Enable */ 272 #define RL_INTRMITIGATE 0xE2 /* Interrupt Mitigate */ 273 #define RL_RDSAR_LO 0xE4 /* Receive Descriptor Start Address Register 274 * 256-byte alignment Low*/ 275 #define RL_RDSAR_HI 0xE8 /* Receive Descriptor Start Address High */ 276 #define RL_ETTHR 0xEC /* Early Transmit Threshold Register */ 277 #define RL_FER 0xF0 /* Function Event Register */ 278 #define RL_FEMR 0xF4 /* Function Event Mask Register */ 279 #define RL_FPSR 0xF8 /* Function Present State Register */ 280 #define RL_FFER 0xFC /* Function Force Event Register */ 281 282 /* 283 * Registers in the Machine Independent Interface (MII) to the PHY. 284 * IEEE 802.3 (2000 Edition) Clause 22. 285 */ 286 287 #define MII_CTRL 0x0 /* Control Register (basic) */ 288 #define MII_CTRL_RST 0x8000 /* Reset PHY */ 289 #define MII_CTRL_LB 0x4000 /* Enable Loopback Mode */ 290 #define MII_CTRL_SP_LSB 0x2000 /* Speed Selection (LSB) */ 291 #define MII_CTRL_ANE 0x1000 /* Auto Negotiation Enable */ 292 #define MII_CTRL_PD 0x0800 /* Power Down */ 293 #define MII_CTRL_ISO 0x0400 /* Isolate */ 294 #define MII_CTRL_RAN 0x0200 /* Restart Auto-Negotiation Process */ 295 #define MII_CTRL_DM 0x0100 /* Full Duplex */ 296 #define MII_CTRL_CT 0x0080 /* Enable COL Signal Test */ 297 #define MII_CTRL_SP_MSB 0x0040 /* Speed Selection (MSB) */ 298 #define MII_CTRL_SP_10 0x0000 /* 10 Mb/s */ 299 #define MII_CTRL_SP_100 0x2000 /* 100 Mb/s */ 300 #define MII_CTRL_SP_1000 0x0040 /* 1000 Mb/s */ 301 #define MII_CTRL_SP_RES 0x2040 /* Reserved */ 302 #define MII_CTRL_RES 0x003F /* Reserved */ 303 #define MII_STATUS 0x1 /* Status Register (basic) */ 304 #define MII_STATUS_100T4 0x8000 /* 100Base-T4 support */ 305 #define MII_STATUS_100XFD 0x4000 /* 100Base-X FD support */ 306 #define MII_STATUS_100XHD 0x2000 /* 100Base-X HD support */ 307 #define MII_STATUS_10FD 0x1000 /* 10 Mb/s FD support */ 308 #define MII_STATUS_10HD 0x0800 /* 10 Mb/s HD support */ 309 #define MII_STATUS_100T2FD 0x0400 /* 100Base-T2 FD support */ 310 #define MII_STATUS_100T2HD 0x0200 /* 100Base-T2 HD support */ 311 #define MII_STATUS_EXT_STAT 0x0100 /* Supports MII_EXT_STATUS */ 312 #define MII_STATUS_RES 0x0080 /* Reserved */ 313 #define MII_STATUS_MFPS 0x0040 /* MF Preamble Suppression */ 314 #define MII_STATUS_ANC 0x0020 /* Auto-Negotiation Completed */ 315 #define MII_STATUS_RF 0x0010 /* Remote Fault Detected */ 316 #define MII_STATUS_ANA 0x0008 /* Auto-Negotiation Ability */ 317 #define MII_STATUS_LS 0x0004 /* Link Up */ 318 #define MII_STATUS_JD 0x0002 /* Jabber Condition Detected */ 319 #define MII_STATUS_EC 0x0001 /* Ext Register Capabilities */ 320 #define MII_PHYID_H 0x2 /* PHY ID (high) */ 321 #define MII_PHYID_L 0x3 /* PHY ID (low) */ 322 #define MII_ANA 0x4 /* Auto-Negotiation Advertisement */ 323 #define MII_ANA_NP 0x8000 /* Next PAge */ 324 #define MII_ANA_RES 0x4000 /* Reserved */ 325 #define MII_ANA_RF 0x2000 /* Remote Fault */ 326 #define MII_ANA_TAF_M 0x1FE0 /* Technology Ability Field */ 327 #define MII_ANA_TAF_S 5 /* Shift */ 328 #define MII_ANA_TAF_RES 0x1000 /* Reserved */ 329 #define MII_ANA_PAUSE_ASYM 0x0800 /* Asym. Pause */ 330 #define MII_ANA_PAUSE_SYM 0x0400 /* Sym. Pause */ 331 #define MII_ANA_100T4 0x0200 /* 100Base-T4 */ 332 #define MII_ANA_100TXFD 0x0100 /* 100Base-TX FD */ 333 #define MII_ANA_100TXHD 0x0080 /* 100Base-TX HD */ 334 #define MII_ANA_10TFD 0x0040 /* 10Base-T FD */ 335 #define MII_ANA_10THD 0x0020 /* 10Base-T HD */ 336 #define MII_ANA_SEL_M 0x001F /* Selector Field */ 337 #define MII_ANA_SEL_802_3 0x0001 /* 802.3 */ 338 #define MII_ANLPA 0x5 /* Auto-Neg Link Partner Ability Register */ 339 #define MII_ANLPA_NP 0x8000 /* Next Page */ 340 #define MII_ANLPA_ACK 0x4000 /* Acknowledge */ 341 #define MII_ANLPA_RF 0x2000 /* Remote Fault */ 342 #define MII_ANLPA_TAF_M 0x1FC0 /* Technology Ability Field */ 343 #define MII_ANLPA_SEL_M 0x001F /* Selector Field */ 344 #define MII_ANE 0x6 /* Auto-Negotiation Expansion */ 345 #define MII_ANE_RES 0xFFE0 /* Reserved */ 346 #define MII_ANE_PDF 0x0010 /* Parallel Detection Fault */ 347 #define MII_ANE_LPNPA 0x0008 /* Link Partner is Next Page Able */ 348 #define MII_ANE_NPA 0x0002 /* Local Device is Next Page Able */ 349 #define MII_ANE_PR 0x0002 /* New Page has been received */ 350 #define MII_ANE_LPANA 0x0001 /* Link Partner is Auto-Neg.able */ 351 #define MII_ANNPT 0x7 /* Auto-Negotiation Next Page Transmit */ 352 #define MII_ANLPRNP 0x8 /* Auto-Neg Link Partner Received Next Page */ 353 #define MII_1000_CTRL 0x9 /* 1000BASE-T Control Register */ 354 #define MII_1000C_FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 355 #define MII_1000C_HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 356 #define MII_1000_STATUS 0xA /* 1000BASE-T Status Register */ 357 #define MII_1000S_LRXOK 0x2000 /* Link partner local receiver status */ 358 #define MII_1000S_RRXOK 0x1000 /* Link partner remote receiver status */ 359 #define MII_1000S_FULL 0x0800 /* Link partner 1000BASE-T full duplex */ 360 #define MII_1000S_HALF 0x0400 /* Link partner 1000BASE-T half duplex */ 361 /* 0xB ... 0xE */ /* Reserved */ 362 #define MII_EXT_STATUS 0xF /* Extended Status */ 363 #define MII_ESTAT_1000XFD 0x8000 /* 1000Base-X Full Duplex */ 364 #define MII_ESTAT_1000XHD 0x4000 /* 1000Base-X Half Duplex */ 365 #define MII_ESTAT_1000TFD 0x2000 /* 1000Base-T Full Duplex */ 366 #define MII_ESTAT_1000THD 0x1000 /* 1000Base-T Half Duplex */ 367 #define MII_ESTAT_RES 0x0FFF /* Reserved */ 368 /* 0x10 ... 0x1F */ /* Vendor Specific */ 369