1 /* A device driver for Intel Pro/1000 Gigabit Ethernet Controllers. */
2
3 #include <minix/drivers.h>
4 #include <minix/netdriver.h>
5 #include <machine/pci.h>
6 #include <sys/mman.h>
7 #include "assert.h"
8 #include "e1000.h"
9 #include "e1000_hw.h"
10 #include "e1000_reg.h"
11 #include "e1000_pci.h"
12
13 static int e1000_init(unsigned int instance, netdriver_addr_t *addr,
14 uint32_t *caps, unsigned int *ticks);
15 static void e1000_stop(void);
16 static void e1000_set_mode(unsigned int, const netdriver_addr_t *,
17 unsigned int);
18 static void e1000_set_hwaddr(const netdriver_addr_t *);
19 static int e1000_send(struct netdriver_data *data, size_t size);
20 static ssize_t e1000_recv(struct netdriver_data *data, size_t max);
21 static unsigned int e1000_get_link(uint32_t *);
22 static void e1000_intr(unsigned int mask);
23 static void e1000_tick(void);
24 static int e1000_probe(e1000_t *e, int skip);
25 static void e1000_init_hw(e1000_t *e, netdriver_addr_t *addr);
26 static uint32_t e1000_reg_read(e1000_t *e, uint32_t reg);
27 static void e1000_reg_write(e1000_t *e, uint32_t reg, uint32_t value);
28 static void e1000_reg_set(e1000_t *e, uint32_t reg, uint32_t value);
29 static void e1000_reg_unset(e1000_t *e, uint32_t reg, uint32_t value);
30 static u16_t eeprom_eerd(e1000_t *e, int reg);
31 static u16_t eeprom_ich(e1000_t *e, int reg);
32 static int eeprom_ich_init(e1000_t *e);
33 static int eeprom_ich_cycle(e1000_t *e, u32_t timeout);
34
35 static int e1000_instance;
36 static e1000_t e1000_state;
37
38 static const struct netdriver e1000_table = {
39 .ndr_name = "em",
40 .ndr_init = e1000_init,
41 .ndr_stop = e1000_stop,
42 .ndr_set_mode = e1000_set_mode,
43 .ndr_set_hwaddr = e1000_set_hwaddr,
44 .ndr_recv = e1000_recv,
45 .ndr_send = e1000_send,
46 .ndr_get_link = e1000_get_link,
47 .ndr_intr = e1000_intr,
48 .ndr_tick = e1000_tick
49 };
50
51 /*
52 * The e1000 driver.
53 */
54 int
main(int argc,char * argv[])55 main(int argc, char * argv[])
56 {
57
58 env_setargs(argc, argv);
59
60 /* Let the netdriver library take control. */
61 netdriver_task(&e1000_table);
62
63 return 0;
64 }
65
66 /*
67 * Initialize the e1000 driver and device.
68 */
69 static int
e1000_init(unsigned int instance,netdriver_addr_t * addr,uint32_t * caps,unsigned int * ticks)70 e1000_init(unsigned int instance, netdriver_addr_t * addr, uint32_t * caps,
71 unsigned int * ticks)
72 {
73 e1000_t *e;
74 int r;
75
76 e1000_instance = instance;
77
78 /* Clear state. */
79 memset(&e1000_state, 0, sizeof(e1000_state));
80
81 e = &e1000_state;
82
83 /* Perform calibration. */
84 if ((r = tsc_calibrate()) != OK)
85 panic("tsc_calibrate failed: %d", r);
86
87 /* See if we can find a matching device. */
88 if (!e1000_probe(e, instance))
89 return ENXIO;
90
91 /* Initialize the hardware, and return its ethernet address. */
92 e1000_init_hw(e, addr);
93
94 *caps = NDEV_CAP_MCAST | NDEV_CAP_BCAST | NDEV_CAP_HWADDR;
95 *ticks = sys_hz() / 10; /* update statistics 10x/sec */
96 return OK;
97 }
98
99 /*
100 * Map flash memory. This step is optional.
101 */
102 static void
e1000_map_flash(e1000_t * e,int devind,int did)103 e1000_map_flash(e1000_t * e, int devind, int did)
104 {
105 u32_t flash_addr, gfpreg, sector_base_addr;
106 size_t flash_size;
107
108 /* The flash memory is pointed to by BAR2. It may not be present. */
109 if ((flash_addr = pci_attr_r32(devind, PCI_BAR_2)) == 0)
110 return;
111
112 /* The default flash size. */
113 flash_size = 0x10000;
114
115 switch (did) {
116 case E1000_DEV_ID_82540EM:
117 case E1000_DEV_ID_82545EM:
118 case E1000_DEV_ID_82540EP:
119 case E1000_DEV_ID_82540EP_LP:
120 return; /* don't even try */
121
122 /* 82566/82567/82562V series support mapping 4kB of flash memory. */
123 case E1000_DEV_ID_ICH10_D_BM_LM:
124 case E1000_DEV_ID_ICH10_R_BM_LF:
125 flash_size = 0x1000;
126 break;
127 }
128
129 e->flash = vm_map_phys(SELF, (void *)flash_addr, flash_size);
130 if (e->flash == MAP_FAILED)
131 panic("e1000: couldn't map in flash");
132
133 /* sector_base_addr is a "sector"-aligned address (4096 bytes). */
134 gfpreg = E1000_READ_FLASH_REG(e, ICH_FLASH_GFPREG);
135 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
136
137 /* flash_base_addr is byte-aligned. */
138 e->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
139 }
140
141 /*
142 * Find a matching device. Return TRUE on success.
143 */
144 static int
e1000_probe(e1000_t * e,int skip)145 e1000_probe(e1000_t * e, int skip)
146 {
147 int r, devind, ioflag;
148 u16_t vid, did, cr;
149 u32_t status;
150 u32_t base, size;
151 const char *dname;
152
153 E1000_DEBUG(3, ("%s: probe()\n", netdriver_name()));
154
155 /* Initialize communication to the PCI driver. */
156 pci_init();
157
158 /* Attempt to iterate the PCI bus. Start at the beginning. */
159 if ((r = pci_first_dev(&devind, &vid, &did)) == 0)
160 return FALSE;
161
162 /* Loop devices on the PCI bus. */
163 while (skip--) {
164 E1000_DEBUG(3, ("%s: probe() devind %d vid 0x%x did 0x%x\n",
165 netdriver_name(), devind, vid, did));
166
167 if (!(r = pci_next_dev(&devind, &vid, &did)))
168 return FALSE;
169 }
170
171 /* We found a matching card. Set card-specific properties. */
172 e->eeprom_read = eeprom_eerd;
173
174 switch (did) {
175 case E1000_DEV_ID_ICH10_D_BM_LM:
176 case E1000_DEV_ID_ICH10_R_BM_LF:
177 e->eeprom_read = eeprom_ich;
178 break;
179
180 case E1000_DEV_ID_82540EM:
181 case E1000_DEV_ID_82545EM:
182 case E1000_DEV_ID_82540EP_LP:
183 e->eeprom_done_bit = (1 << 4);
184 e->eeprom_addr_off = 8;
185 break;
186
187 default:
188 e->eeprom_done_bit = (1 << 1);
189 e->eeprom_addr_off = 2;
190 break;
191 }
192
193 /* Inform the user about the new card. */
194 if (!(dname = pci_dev_name(vid, did)))
195 dname = "Intel Pro/1000 Gigabit Ethernet Card";
196 E1000_DEBUG(1, ("%s: %s (%04x/%04x) at %s\n",
197 netdriver_name(), dname, vid, did, pci_slot_name(devind)));
198
199 /* Reserve PCI resources found. */
200 pci_reserve(devind);
201
202 /* Read PCI configuration. */
203 e->irq = pci_attr_r8(devind, PCI_ILR);
204
205 if ((r = pci_get_bar(devind, PCI_BAR, &base, &size, &ioflag)) != OK)
206 panic("failed to get PCI BAR: %d", r);
207 if (ioflag)
208 panic("PCI BAR is not for memory");
209
210 if ((e->regs = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED)
211 panic("failed to map hardware registers from PCI");
212
213 /* Enable DMA bus mastering if necessary. */
214 cr = pci_attr_r16(devind, PCI_CR);
215 if (!(cr & PCI_CR_MAST_EN))
216 pci_attr_w16(devind, PCI_CR, cr | PCI_CR_MAST_EN);
217
218 /* Optionally map flash memory. */
219 e1000_map_flash(e, devind, did);
220
221 /* Output debug information. */
222 status = e1000_reg_read(e, E1000_REG_STATUS);
223 E1000_DEBUG(3, ("%s: MEM at %p, IRQ %d\n", netdriver_name(),
224 e->regs, e->irq));
225 E1000_DEBUG(3, ("%s: link %s, %s duplex\n", netdriver_name(),
226 status & 3 ? "up" : "down", status & 1 ? "full" : "half"));
227
228 return TRUE;
229 }
230
231 /*
232 * Reset the card.
233 */
234 static void
e1000_reset_hw(e1000_t * e)235 e1000_reset_hw(e1000_t * e)
236 {
237
238 /* Assert a Device Reset signal. */
239 e1000_reg_set(e, E1000_REG_CTRL, E1000_REG_CTRL_RST);
240
241 /* Wait one microsecond. */
242 micro_delay(16000);
243 }
244
245 /*
246 * Initialize and return the card's ethernet address.
247 */
248 static void
e1000_init_addr(e1000_t * e,netdriver_addr_t * addr)249 e1000_init_addr(e1000_t * e, netdriver_addr_t * addr)
250 {
251 static char eakey[] = E1000_ENVVAR "#_EA";
252 static char eafmt[] = "x:x:x:x:x:x";
253 u16_t word;
254 int i;
255 long v;
256
257 /* Do we have a user defined ethernet address? */
258 eakey[sizeof(E1000_ENVVAR)-1] = '0' + e1000_instance;
259
260 for (i = 0; i < 6; i++) {
261 if (env_parse(eakey, eafmt, i, &v, 0x00L, 0xFFL) != EP_SET)
262 break;
263 else
264 addr->na_addr[i] = v;
265 }
266
267 /* If that fails, read Ethernet Address from EEPROM. */
268 if (i != 6) {
269 for (i = 0; i < 3; i++) {
270 word = e->eeprom_read(e, i);
271 addr->na_addr[i * 2] = (word & 0x00ff);
272 addr->na_addr[i * 2 + 1] = (word & 0xff00) >> 8;
273 }
274 }
275
276 /* Set Receive Address. */
277 e1000_set_hwaddr(addr);
278
279 E1000_DEBUG(3, ("%s: Ethernet Address %x:%x:%x:%x:%x:%x\n",
280 netdriver_name(),
281 addr->na_addr[0], addr->na_addr[1], addr->na_addr[2],
282 addr->na_addr[3], addr->na_addr[4], addr->na_addr[5]));
283 }
284
285 /*
286 * Initialize receive and transmit buffers.
287 */
288 static void
e1000_init_buf(e1000_t * e)289 e1000_init_buf(e1000_t * e)
290 {
291 phys_bytes rx_desc_p, rx_buff_p;
292 phys_bytes tx_desc_p, tx_buff_p;
293 int i;
294
295 /* Number of descriptors. */
296 e->rx_desc_count = E1000_RXDESC_NR;
297 e->tx_desc_count = E1000_TXDESC_NR;
298
299 /* Allocate receive descriptors. */
300 if ((e->rx_desc = alloc_contig(sizeof(e1000_rx_desc_t) *
301 e->rx_desc_count, AC_ALIGN4K, &rx_desc_p)) == NULL)
302 panic("failed to allocate RX descriptors");
303
304 memset(e->rx_desc, 0, sizeof(e1000_rx_desc_t) * e->rx_desc_count);
305
306 /* Allocate receive buffers. */
307 e->rx_buffer_size = E1000_RXDESC_NR * E1000_IOBUF_SIZE;
308
309 if ((e->rx_buffer = alloc_contig(e->rx_buffer_size, AC_ALIGN4K,
310 &rx_buff_p)) == NULL)
311 panic("failed to allocate RX buffers");
312
313 /* Set up receive descriptors. */
314 for (i = 0; i < E1000_RXDESC_NR; i++)
315 e->rx_desc[i].buffer = rx_buff_p + i * E1000_IOBUF_SIZE;
316
317 /* Allocate transmit descriptors. */
318 if ((e->tx_desc = alloc_contig(sizeof(e1000_tx_desc_t) *
319 e->tx_desc_count, AC_ALIGN4K, &tx_desc_p)) == NULL)
320 panic("failed to allocate TX descriptors");
321
322 memset(e->tx_desc, 0, sizeof(e1000_tx_desc_t) * e->tx_desc_count);
323
324 /* Allocate transmit buffers. */
325 e->tx_buffer_size = E1000_TXDESC_NR * E1000_IOBUF_SIZE;
326
327 if ((e->tx_buffer = alloc_contig(e->tx_buffer_size, AC_ALIGN4K,
328 &tx_buff_p)) == NULL)
329 panic("failed to allocate TX buffers");
330
331 /* Set up transmit descriptors. */
332 for (i = 0; i < E1000_TXDESC_NR; i++)
333 e->tx_desc[i].buffer = tx_buff_p + i * E1000_IOBUF_SIZE;
334
335 /* Set up the receive ring registers. */
336 e1000_reg_write(e, E1000_REG_RDBAL, rx_desc_p);
337 e1000_reg_write(e, E1000_REG_RDBAH, 0);
338 e1000_reg_write(e, E1000_REG_RDLEN,
339 e->rx_desc_count * sizeof(e1000_rx_desc_t));
340 e1000_reg_write(e, E1000_REG_RDH, 0);
341 e1000_reg_write(e, E1000_REG_RDT, e->rx_desc_count - 1);
342 e1000_reg_unset(e, E1000_REG_RCTL, E1000_REG_RCTL_BSIZE);
343 e1000_reg_set(e, E1000_REG_RCTL, E1000_REG_RCTL_EN);
344
345 /* Set up the transmit ring registers. */
346 e1000_reg_write(e, E1000_REG_TDBAL, tx_desc_p);
347 e1000_reg_write(e, E1000_REG_TDBAH, 0);
348 e1000_reg_write(e, E1000_REG_TDLEN,
349 e->tx_desc_count * sizeof(e1000_tx_desc_t));
350 e1000_reg_write(e, E1000_REG_TDH, 0);
351 e1000_reg_write(e, E1000_REG_TDT, 0);
352 e1000_reg_set(e, E1000_REG_TCTL,
353 E1000_REG_TCTL_EN | E1000_REG_TCTL_PSP);
354 }
355
356 /*
357 * Initialize the hardware. Return the ethernet address.
358 */
359 static void
e1000_init_hw(e1000_t * e,netdriver_addr_t * addr)360 e1000_init_hw(e1000_t * e, netdriver_addr_t * addr)
361 {
362 int r, i;
363
364 e->irq_hook = e->irq;
365
366 /*
367 * Set the interrupt handler and policy. Do not automatically
368 * reenable interrupts. Return the IRQ line number on interrupts.
369 */
370 if ((r = sys_irqsetpolicy(e->irq, 0, &e->irq_hook)) != OK)
371 panic("sys_irqsetpolicy failed: %d", r);
372 if ((r = sys_irqenable(&e->irq_hook)) != OK)
373 panic("sys_irqenable failed: %d", r);
374
375 /* Reset hardware. */
376 e1000_reset_hw(e);
377
378 /*
379 * Initialize appropriately, according to section 14.3 General
380 * Configuration of Intel's Gigabit Ethernet Controllers Software
381 * Developer's Manual.
382 */
383 e1000_reg_set(e, E1000_REG_CTRL,
384 E1000_REG_CTRL_ASDE | E1000_REG_CTRL_SLU);
385 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_LRST);
386 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_PHY_RST);
387 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_ILOS);
388 e1000_reg_write(e, E1000_REG_FCAL, 0);
389 e1000_reg_write(e, E1000_REG_FCAH, 0);
390 e1000_reg_write(e, E1000_REG_FCT, 0);
391 e1000_reg_write(e, E1000_REG_FCTTV, 0);
392 e1000_reg_unset(e, E1000_REG_CTRL, E1000_REG_CTRL_VME);
393
394 /* Clear Multicast Table Array (MTA). */
395 for (i = 0; i < 128; i++)
396 e1000_reg_write(e, E1000_REG_MTA + i * 4, 0);
397
398 /* Initialize statistics registers. */
399 for (i = 0; i < 64; i++)
400 e1000_reg_write(e, E1000_REG_CRCERRS + i * 4, 0);
401
402 /* Acquire MAC address and set up RX/TX buffers. */
403 e1000_init_addr(e, addr);
404 e1000_init_buf(e);
405
406 /* Enable interrupts. */
407 e1000_reg_set(e, E1000_REG_IMS, E1000_REG_IMS_LSC | E1000_REG_IMS_RXO |
408 E1000_REG_IMS_RXT | E1000_REG_IMS_TXQE | E1000_REG_IMS_TXDW);
409 }
410
411 /*
412 * Set receive mode.
413 */
414 static void
e1000_set_mode(unsigned int mode,const netdriver_addr_t * mcast_list __unused,unsigned int mcast_count __unused)415 e1000_set_mode(unsigned int mode, const netdriver_addr_t * mcast_list __unused,
416 unsigned int mcast_count __unused)
417 {
418 e1000_t *e;
419 uint32_t rctl;
420
421 e = &e1000_state;
422
423 rctl = e1000_reg_read(e, E1000_REG_RCTL);
424
425 rctl &= ~(E1000_REG_RCTL_BAM | E1000_REG_RCTL_MPE |
426 E1000_REG_RCTL_UPE);
427
428 /* TODO: support for NDEV_MODE_DOWN and multicast lists */
429 if (mode & NDEV_MODE_BCAST)
430 rctl |= E1000_REG_RCTL_BAM;
431 if (mode & (NDEV_MODE_MCAST_LIST | NDEV_MODE_MCAST_ALL))
432 rctl |= E1000_REG_RCTL_MPE;
433 if (mode & NDEV_MODE_PROMISC)
434 rctl |= E1000_REG_RCTL_BAM | E1000_REG_RCTL_MPE |
435 E1000_REG_RCTL_UPE;
436
437 e1000_reg_write(e, E1000_REG_RCTL, rctl);
438 }
439
440 /*
441 * Set hardware address.
442 */
443 static void
e1000_set_hwaddr(const netdriver_addr_t * hwaddr)444 e1000_set_hwaddr(const netdriver_addr_t * hwaddr)
445 {
446 e1000_t *e;
447
448 e = &e1000_state;
449
450 e1000_reg_write(e, E1000_REG_RAL,
451 *(const u32_t *)(&hwaddr->na_addr[0]));
452 e1000_reg_write(e, E1000_REG_RAH,
453 *(const u16_t *)(&hwaddr->na_addr[4]));
454 e1000_reg_set(e, E1000_REG_RAH, E1000_REG_RAH_AV);
455 }
456
457 /*
458 * Try to send a packet.
459 */
460 static int
e1000_send(struct netdriver_data * data,size_t size)461 e1000_send(struct netdriver_data * data, size_t size)
462 {
463 e1000_t *e;
464 e1000_tx_desc_t *desc;
465 unsigned int head, tail, next;
466 char *ptr;
467
468 e = &e1000_state;
469
470 if (size > E1000_IOBUF_SIZE)
471 panic("packet too large to send");
472
473 /*
474 * The queue tail must not advance to the point that it is equal to the
475 * queue head, since this condition indicates that the queue is empty.
476 */
477 head = e1000_reg_read(e, E1000_REG_TDH);
478 tail = e1000_reg_read(e, E1000_REG_TDT);
479 next = (tail + 1) % e->tx_desc_count;
480
481 if (next == head)
482 return SUSPEND;
483
484 /* The descriptor to use is the one pointed to by the current tail. */
485 desc = &e->tx_desc[tail];
486
487 /* Copy the packet from the caller. */
488 ptr = e->tx_buffer + tail * E1000_IOBUF_SIZE;
489
490 netdriver_copyin(data, 0, ptr, size);
491
492 /* Mark this descriptor ready. */
493 desc->status = 0;
494 desc->length = size;
495 desc->command = E1000_TX_CMD_EOP | E1000_TX_CMD_FCS | E1000_TX_CMD_RS;
496
497 /* Increment tail. Start transmission. */
498 e1000_reg_write(e, E1000_REG_TDT, next);
499
500 return OK;
501 }
502
503 /*
504 * Try to receive a packet.
505 */
506 static ssize_t
e1000_recv(struct netdriver_data * data,size_t max)507 e1000_recv(struct netdriver_data * data, size_t max)
508 {
509 e1000_t *e;
510 e1000_rx_desc_t *desc;
511 unsigned int head, tail, cur;
512 char *ptr;
513 size_t size;
514
515 e = &e1000_state;
516
517 /* If the queue head and tail are equal, the queue is empty. */
518 head = e1000_reg_read(e, E1000_REG_RDH);
519 tail = e1000_reg_read(e, E1000_REG_RDT);
520
521 E1000_DEBUG(4, ("%s: head=%u, tail=%u\n",
522 netdriver_name(), head, tail));
523
524 if (head == tail)
525 return SUSPEND;
526
527 /* Has a packet been received? */
528 cur = (tail + 1) % e->rx_desc_count;
529 desc = &e->rx_desc[cur];
530
531 if (!(desc->status & E1000_RX_STATUS_DONE))
532 return SUSPEND;
533
534 /*
535 * HACK: we expect all packets to fit in a single receive buffer.
536 * Eventually, some sort of support to deal with packets spanning
537 * multiple receive descriptors should be added. For now, we panic,
538 * so that we can continue after the restart; this is already an
539 * improvement over freezing (the old behavior of this driver).
540 */
541 size = desc->length;
542
543 if (!(desc->status & E1000_RX_STATUS_EOP))
544 panic("received packet too large");
545
546 /* Copy the packet to the caller. */
547 ptr = e->rx_buffer + cur * E1000_IOBUF_SIZE;
548
549 if (size > max)
550 size = max;
551
552 netdriver_copyout(data, 0, ptr, size);
553
554 /* Reset the descriptor. */
555 desc->status = 0;
556
557 /* Increment tail. */
558 e1000_reg_write(e, E1000_REG_RDT, cur);
559
560 /* Return the size of the received packet. */
561 return size;
562 }
563
564 /*
565 * Return the link and media status.
566 */
567 static unsigned int
e1000_get_link(uint32_t * media)568 e1000_get_link(uint32_t * media)
569 {
570 uint32_t status, type;
571
572 status = e1000_reg_read(&e1000_state, E1000_REG_STATUS);
573
574 if (!(status & E1000_REG_STATUS_LU))
575 return NDEV_LINK_DOWN;
576
577 if (status & E1000_REG_STATUS_FD)
578 type = IFM_ETHER | IFM_FDX;
579 else
580 type = IFM_ETHER | IFM_HDX;
581
582 switch (status & E1000_REG_STATUS_SPEED) {
583 case E1000_REG_STATUS_SPEED_10:
584 type |= IFM_10_T;
585 break;
586 case E1000_REG_STATUS_SPEED_100:
587 type |= IFM_100_TX;
588 break;
589 case E1000_REG_STATUS_SPEED_1000_A:
590 case E1000_REG_STATUS_SPEED_1000_B:
591 type |= IFM_1000_T;
592 break;
593 }
594
595 *media = type;
596 return NDEV_LINK_UP;
597 }
598
599 /*
600 * Handle an interrupt.
601 */
602 static void
e1000_intr(unsigned int __unused mask)603 e1000_intr(unsigned int __unused mask)
604 {
605 e1000_t *e;
606 u32_t cause;
607
608 E1000_DEBUG(3, ("e1000: interrupt\n"));
609
610 e = &e1000_state;
611
612 /* Reenable interrupts. */
613 if (sys_irqenable(&e->irq_hook) != OK)
614 panic("failed to re-enable IRQ");
615
616 /* Read the Interrupt Cause Read register. */
617 if ((cause = e1000_reg_read(e, E1000_REG_ICR)) != 0) {
618 if (cause & E1000_REG_ICR_LSC)
619 netdriver_link();
620
621 if (cause & (E1000_REG_ICR_RXO | E1000_REG_ICR_RXT))
622 netdriver_recv();
623
624 if (cause & (E1000_REG_ICR_TXQE | E1000_REG_ICR_TXDW))
625 netdriver_send();
626 }
627 }
628
629 /*
630 * Do regular processing.
631 */
632 static void
e1000_tick(void)633 e1000_tick(void)
634 {
635 e1000_t *e;
636
637 e = &e1000_state;
638
639 /* Update statistics. */
640 netdriver_stat_ierror(e1000_reg_read(e, E1000_REG_RXERRC));
641 netdriver_stat_ierror(e1000_reg_read(e, E1000_REG_CRCERRS));
642 netdriver_stat_ierror(e1000_reg_read(e, E1000_REG_MPC));
643 netdriver_stat_coll(e1000_reg_read(e, E1000_REG_COLC));
644 }
645
646 /*
647 * Stop the card.
648 */
649 static void
e1000_stop(void)650 e1000_stop(void)
651 {
652 e1000_t *e;
653
654 e = &e1000_state;
655
656 E1000_DEBUG(3, ("%s: stop()\n", netdriver_name()));
657
658 e1000_reset_hw(e);
659 }
660
661 /*
662 * Read from a register.
663 */
664 static uint32_t
e1000_reg_read(e1000_t * e,uint32_t reg)665 e1000_reg_read(e1000_t * e, uint32_t reg)
666 {
667 uint32_t value;
668
669 /* Assume a sane register. */
670 assert(reg < 0x1ffff);
671
672 /* Read from memory mapped register. */
673 value = *(volatile uint32_t *)(e->regs + reg);
674
675 /* Return the result. */
676 return value;
677 }
678
679 /*
680 * Write to a register.
681 */
682 static void
e1000_reg_write(e1000_t * e,uint32_t reg,uint32_t value)683 e1000_reg_write(e1000_t * e, uint32_t reg, uint32_t value)
684 {
685
686 /* Assume a sane register. */
687 assert(reg < 0x1ffff);
688
689 /* Write to memory mapped register. */
690 *(volatile u32_t *)(e->regs + reg) = value;
691 }
692
693 /*
694 * Set bits in a register.
695 */
696 static void
e1000_reg_set(e1000_t * e,uint32_t reg,uint32_t value)697 e1000_reg_set(e1000_t * e, uint32_t reg, uint32_t value)
698 {
699 uint32_t data;
700
701 /* First read the current value. */
702 data = e1000_reg_read(e, reg);
703
704 /* Set bits, and write back. */
705 e1000_reg_write(e, reg, data | value);
706 }
707
708 /*
709 * Clear bits in a register.
710 */
711 static void
e1000_reg_unset(e1000_t * e,uint32_t reg,uint32_t value)712 e1000_reg_unset(e1000_t * e, uint32_t reg, uint32_t value)
713 {
714 uint32_t data;
715
716 /* First read the current value. */
717 data = e1000_reg_read(e, reg);
718
719 /* Unset bits, and write back. */
720 e1000_reg_write(e, reg, data & ~value);
721 }
722
723 /*
724 * Read from EEPROM.
725 */
726 static u16_t
eeprom_eerd(e1000_t * e,int reg)727 eeprom_eerd(e1000_t * e, int reg)
728 {
729 u32_t data;
730
731 /* Request EEPROM read. */
732 e1000_reg_write(e, E1000_REG_EERD,
733 (reg << e->eeprom_addr_off) | (E1000_REG_EERD_START));
734
735 /* Wait until ready. */
736 while (!((data = (e1000_reg_read(e, E1000_REG_EERD))) &
737 e->eeprom_done_bit));
738
739 return data >> 16;
740 }
741
742 /*
743 * Initialize ICH8 flash.
744 */
745 static int
eeprom_ich_init(e1000_t * e)746 eeprom_ich_init(e1000_t * e)
747 {
748 union ich8_hws_flash_status hsfsts;
749 int ret_val = -1;
750 int i = 0;
751
752 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS);
753
754 /* Check if the flash descriptor is valid */
755 if (hsfsts.hsf_status.fldesvalid == 0) {
756 E1000_DEBUG(3, ("Flash descriptor invalid. "
757 "SW Sequencing must be used."));
758 return ret_val;
759 }
760
761 /* Clear FCERR and DAEL in hw status by writing 1 */
762 hsfsts.hsf_status.flcerr = 1;
763 hsfsts.hsf_status.dael = 1;
764
765 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, hsfsts.regval);
766
767 /*
768 * Either we should have a hardware SPI cycle in progress bit to check
769 * against, in order to start a new cycle or FDONE bit should be
770 * changed in the hardware so that it is 1 after hardware reset, which
771 * can then be used as an indication whether a cycle is in progress or
772 * has been completed.
773 */
774 if (hsfsts.hsf_status.flcinprog == 0) {
775 /*
776 * There is no cycle running at present, so we can start a
777 * cycle. Begin by setting Flash Cycle Done.
778 */
779 hsfsts.hsf_status.flcdone = 1;
780 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS, hsfsts.regval);
781 ret_val = 0;
782 } else {
783 /*
784 * Otherwise poll for sometime so the current cycle has a
785 * chance to end before giving up.
786 */
787 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
788 hsfsts.regval = E1000_READ_FLASH_REG16(e,
789 ICH_FLASH_HSFSTS);
790
791 if (hsfsts.hsf_status.flcinprog == 0) {
792 ret_val = 0;
793 break;
794 }
795 micro_delay(16000);
796 }
797 if (ret_val == 0) {
798 /*
799 * Successful in waiting for previous cycle to timeout,
800 * now set the Flash Cycle Done.
801 */
802 hsfsts.hsf_status.flcdone = 1;
803 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFSTS,
804 hsfsts.regval);
805 } else {
806 E1000_DEBUG(3,
807 ("Flash controller busy, cannot get access"));
808 }
809 }
810
811 return ret_val;
812 }
813
814 /*
815 * Start ICH8 flash cycle.
816 */
817 static int
eeprom_ich_cycle(e1000_t * e,u32_t timeout)818 eeprom_ich_cycle(e1000_t * e, u32_t timeout)
819 {
820 union ich8_hws_flash_ctrl hsflctl;
821 union ich8_hws_flash_status hsfsts;
822 int ret_val = -1;
823 u32_t i = 0;
824
825 E1000_DEBUG(3, ("e1000_flash_cycle_ich8lan"));
826
827 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
828 hsflctl.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFCTL);
829 hsflctl.hsf_ctrl.flcgo = 1;
830 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFCTL, hsflctl.regval);
831
832 /* Wait till the FDONE bit is set to 1 */
833 do {
834 hsfsts.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFSTS);
835 if (hsfsts.hsf_status.flcdone == 1)
836 break;
837 micro_delay(16000);
838 } while (i++ < timeout);
839
840 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
841 ret_val = 0;
842
843 return ret_val;
844 }
845
846 /*
847 * Read from ICH8 flash.
848 */
849 static u16_t
eeprom_ich(e1000_t * e,int reg)850 eeprom_ich(e1000_t * e, int reg)
851 {
852 union ich8_hws_flash_status hsfsts;
853 union ich8_hws_flash_ctrl hsflctl;
854 u32_t flash_linear_addr;
855 u32_t flash_data = 0;
856 int ret_val = -1;
857 u8_t count = 0;
858 u16_t data = 0;
859
860 E1000_DEBUG(3, ("e1000_read_flash_data_ich8lan"));
861
862 if (reg > ICH_FLASH_LINEAR_ADDR_MASK)
863 return data;
864
865 reg *= sizeof(u16_t);
866 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & reg) +
867 e->flash_base_addr;
868
869 do {
870 micro_delay(16000);
871
872 /* Steps */
873 ret_val = eeprom_ich_init(e);
874 if (ret_val != 0)
875 break;
876
877 hsflctl.regval = E1000_READ_FLASH_REG16(e, ICH_FLASH_HSFCTL);
878 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
879 hsflctl.hsf_ctrl.fldbcount = 1;
880 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
881 E1000_WRITE_FLASH_REG16(e, ICH_FLASH_HSFCTL, hsflctl.regval);
882 E1000_WRITE_FLASH_REG(e, ICH_FLASH_FADDR, flash_linear_addr);
883
884 ret_val = eeprom_ich_cycle(e, ICH_FLASH_READ_COMMAND_TIMEOUT);
885
886 /*
887 * Check if FCERR is set to 1, if set to 1, clear it and try
888 * the whole sequence a few more times, else read in (shift in)
889 * the Flash Data0, the order is least significant byte first
890 * msb to lsb.
891 */
892 if (ret_val == 0) {
893 flash_data = E1000_READ_FLASH_REG(e, ICH_FLASH_FDATA0);
894 data = (u16_t)(flash_data & 0x0000FFFF);
895 break;
896 } else {
897 /*
898 * If we've gotten here, then things are probably
899 * completely hosed, but if the error condition is
900 * detected, it won't hurt to give it another try...
901 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
902 */
903 hsfsts.regval = E1000_READ_FLASH_REG16(e,
904 ICH_FLASH_HSFSTS);
905
906 if (hsfsts.hsf_status.flcerr == 1) {
907 /* Repeat for some time before giving up. */
908 continue;
909 } else if (hsfsts.hsf_status.flcdone == 0) {
910 E1000_DEBUG(3, ("Timeout error - flash cycle "
911 "did not complete."));
912 break;
913 }
914 }
915 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
916
917 return data;
918 }
919