1 /* 2 ** File: wd.h 3 ** 4 ** Created: before Dec 28, 1992 by Philip Homburg 5 ** $PchId: wdeth.h,v 1.4 1995/12/22 08:36:57 philip Exp $ 6 ** 7 ** $Log$ 8 ** Revision 1.2 2005/08/22 15:17:40 beng 9 ** Remove double-blank lines (Al) 10 ** 11 ** Revision 1.1 2005/06/29 10:16:46 beng 12 ** Import of dpeth 3c501/3c509b/.. ethernet driver by 13 ** Giovanni Falzoni <fgalzoni@inwind.it>. 14 ** 15 ** Revision 2.0 2005/06/26 16:16:46 lsodgf0 16 ** Initial revision for Minix 3.0.6 17 */ 18 19 #ifndef WDETH_H 20 #define WDETH_H 21 22 /* Western Digital Ethercard Plus, or WD8003E card. */ 23 24 #define EPL_REG0 0x0 /* Control(write) and status(read) */ 25 #define EPL_REG1 0x1 26 #define EPL_REG2 0x2 27 #define EPL_REG3 0x3 28 #define EPL_REG4 0x4 29 #define EPL_REG5 0x5 30 #define EPL_REG6 0x6 31 #define EPL_REG7 0x7 32 #define EPL_EA0 0x8 /* Most significant eaddr byte */ 33 #define EPL_EA1 0x9 34 #define EPL_EA2 0xA 35 #define EPL_EA3 0xB 36 #define EPL_EA4 0xC 37 #define EPL_EA5 0xD /* Least significant eaddr byte */ 38 #define EPL_TLB 0xE 39 #define EPL_CHKSUM 0xF /* sum from epl_ea0 upto here is 0xFF */ 40 #define EPL_DP8390 0x10 /* NatSemi chip */ 41 42 #define EPL_MSR EPL_REG0/* memory select register */ 43 #define EPL_ICR EPL_REG1/* interface configuration register */ 44 #define EPL_IRR EPL_REG4/* interrupt request register (IRR) */ 45 #define EPL_790_HWR EPL_REG4/* '790 hardware support register */ 46 #define EPL_LAAR EPL_REG5/* LA address register (write only) */ 47 #define EPL_790_ICR EPL_REG6/* '790 interrupt control register */ 48 #define EPL_GP2 EPL_REG7/* general purpose register 2 */ 49 #define EPL_790_B EPL_EA3 /* '790 memory register */ 50 #define EPL_790_GCR EPL_EA5 /* '790 General Control Register */ 51 52 /* Bits in EPL_MSR */ 53 #define E_MSR_MEMADDR 0x3F /* Bits SA18-SA13, SA19 implicit 1 */ 54 #define E_MSR_MENABLE 0x40 /* Memory Enable */ 55 #define E_MSR_RESET 0x80 /* Software Reset */ 56 57 /* Bits in EPL_ICR */ 58 #define E_ICR_16BIT 0x01 /* 16 bit bus */ 59 #define E_ICR_IR2 0x04 /* bit 2 of encoded IRQ */ 60 #define E_ICR_MEMBIT 0x08 /* 583 mem size mask */ 61 62 /* Bits in EPL_IRR */ 63 #define E_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 64 #define E_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 65 #define E_IRR_IEN 0x80 /* enable interrupts */ 66 67 /* Bits in EPL_LAAR */ 68 #define E_LAAR_A19 0x01 /* address lines for above 1M ram */ 69 #define E_LAAR_A20 0x02 /* address lines for above 1M ram */ 70 #define E_LAAR_A21 0x04 /* address lines for above 1M ram */ 71 #define E_LAAR_A22 0x08 /* address lines for above 1M ram */ 72 #define E_LAAR_A23 0x10 /* address lines for above 1M ram */ 73 #define E_LAAR_SOFTINT 0x20 /* enable software interrupt */ 74 #define E_LAAR_LAN16E 0x40 /* enables 16 bit RAM for LAN */ 75 #define E_LAAR_MEM16E 0x80 /* enables 16 bit RAM for host */ 76 77 /* Bits and values in EPL_TLB */ 78 #define E_TLB_EB 0x05 /* WD8013EB */ 79 #define E_TLB_E 0x27 /* WD8013 Elite */ 80 #define E_TLB_SMCE 0x29 /* SMC Elite 16 */ 81 #define E_TLB_SMC8216C 0x2B /* SMC 8216 C */ 82 83 #define E_TLB_REV 0x1F /* revision mask */ 84 #define E_TLB_SOFT 0x20 /* soft config */ 85 #define E_TLB_RAM 0x40 /* extra ram bit */ 86 87 /* Bits in EPL_790_HWR */ 88 #define E_790_HWR_SWH 0x80 /* switch register set */ 89 90 /* Bits in EPL_790_ICR */ 91 #define E_790_ICR_EIL 0x01 /* enable interrupts */ 92 93 /* Bits in EPL_790_GCR when E_790_HWR_SWH is set in EPL_790_HWR */ 94 #define E_790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 95 #define E_790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 96 #define E_790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 97 98 #define inb_we(dep, reg) (inb(dep->de_base_port+reg)) 99 #define outb_we(dep, reg, data) (outb(dep->de_base_port+reg, data)) 100 101 #endif /* WDETH_H */ 102 103 /** wd.h **/ 104