1 /* 2 ** File: 3c501.h Jan. 14, 1997 3 ** 4 ** Author: Giovanni Falzoni <gfalzoni@inwind.it> 5 ** 6 ** Interface description for 3Com Etherlink boards 7 ** 8 ** $Log$ 9 ** Revision 1.1 2005/06/29 10:16:46 beng 10 ** Import of dpeth 3c501/3c509b/.. ethernet driver by 11 ** Giovanni Falzoni <fgalzoni@inwind.it>. 12 ** 13 ** Revision 2.0 2005/06/26 16:16:46 lsodgf0 14 ** Initial revision for Minix 3.0.6 15 */ 16 17 /* The various board command registers */ 18 #define EL1_ADDRESS 0x00 /* Board station address, 6 bytes */ 19 #define EL1_RECV 0x06 /* Board Receive Config/Status Reg. */ 20 #define EL1_XMIT 0x07 /* Board Transmit Config/Status Reg. */ 21 #define EL1_XMITPTR 0x08 /* Transmit buffer pointer (word access) */ 22 #define EL1_RECVPTR 0x0A /* Receive buffer pointer (word access) */ 23 #define EL1_SAPROM 0x0C /* Window on Station Addr prom */ 24 #define EL1_CSR 0x0E /* Board Command/Status Register */ 25 #define EL1_DATAPORT 0x0F /* Window on packet buffer (Data Port) */ 26 27 /* Bits in EL1_RECV, interrupt enable on write, status when read */ 28 #define ERSR_NONE 0x00 /* Match mode in bits 5-6 (wo) */ 29 #define ERSR_ALL 0x40 /* Promiscuous receive (wo) */ 30 #define ERSR_BROAD 0x80 /* Station address plus broadcast (wo) */ 31 #define ERSR_MULTI 0x80 /* Station address plus multicast 0xC0 */ 32 #define ERSR_STALE 0x80 /* Receive status previously read (ro) */ 33 #define ERSR_GOOD 0x20 /* Well formed packets only (rw) */ 34 #define ERSR_ANY 0x10 /* Any packet, even with errors (rw) */ 35 #define ERSR_SHORT 0x08 /* Short frame (rw) */ 36 #define ERSR_DRIBBLE 0x04 /* Dribble error (rw) */ 37 #define ERSR_FCS 0x02 /* CRC error (rw) */ 38 #define ERSR_OVER 0x01 /* Data overflow (rw) */ 39 40 #define ERSR_RERROR (ERSR_SHORT|ERSR_DRIBBLE|ERSR_FCS|ERSR_OVER) 41 #define ERSR_RMASK (ERSR_GOOD|ERSR_RERROR)/*(ERSR_GOOD|ERSR_ANY|ERSR_RERROR)*/ 42 43 /* Bits in EL1_XMIT, interrupt enable on write, status when read */ 44 #define EXSR_IDLE 0x08 /* Transmit idle (send completed) */ 45 #define EXSR_16JAM 0x04 /* Packet sending got 16 collisions */ 46 #define EXSR_JAM 0x02 /* Packet sending got a collision */ 47 #define EXSR_UNDER 0x01 /* Data underflow in sending */ 48 49 /* Bits in EL1_CSR (Configuration Status Register) */ 50 #define ECSR_RESET 0x80 /* Reset the controller (wo) */ 51 #define ECSR_XMTBSY 0x80 /* Transmitter busy (ro) */ 52 #define ECSR_RIDE 0x01 /* Request interrupt/DMA enable (rw) */ 53 #define ECSR_DMA 0x20 /* DMA request (rw) */ 54 #define ECSR_EDMA 0x10 /* DMA done (ro) */ 55 #define ECSR_CRC 0x02 /* Causes CRC error on transmit (wo) */ 56 #define ECSR_RCVBSY 0x01 /* Receive in progress (ro) */ 57 #define ECSR_LOOP (3<<2) /* 2 bit field in bits 2,3, loopback */ 58 #define ECSR_RECV (2<<2) /* Gives buffer to receiver (rw) */ 59 #define ECSR_XMIT (1<<2) /* Gives buffer to transmit (rw) */ 60 #define ECSR_SYS (0<<2) /* Gives buffer to processor (wo) */ 61 62 #define EL1_BFRSIZ 2048 /* Number of bytes in board buffer */ 63 64 #define inb_el1(dep,reg) (inb(dep->de_base_port+(reg))) 65 #define inw_el1(dep,reg) (inw(dep->de_base_port+(reg))) 66 #define outb_el1(dep,reg,data) (outb(dep->de_base_port+(reg),data)) 67 #define outw_el1(dep,reg,data) (outw(dep->de_base_port+(reg),data)) 68 69 /** 3c501.h **/ 70