xref: /minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/AMDGPU.td (revision 0a6a1f1d05b60e214de2f05a7310ddd1f0e590e7) 
1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===----------------------------------------------------------------------===//
13// Subtarget Features
14//===----------------------------------------------------------------------===//
15
16// Debugging Features
17
18def FeatureDumpCode : SubtargetFeature <"DumpCode",
19        "DumpCode",
20        "true",
21        "Dump MachineInstrs in the CodeEmitter">;
22
23def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
24        "EnableIRStructurizer",
25        "false",
26        "Disable IR Structurizer">;
27
28def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29        "EnablePromoteAlloca",
30        "true",
31        "Enable promote alloca pass">;
32
33// Target features
34
35def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
36        "EnableIfCvt",
37        "false",
38        "Disable the if conversion pass">;
39
40def FeatureFP64 : SubtargetFeature<"fp64",
41        "FP64",
42        "true",
43        "Enable double precision operations">;
44
45def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
46        "FP64Denormals",
47        "true",
48        "Enable double precision denormal handling",
49        [FeatureFP64]>;
50
51// Some instructions do not support denormals despite this flag. Using
52// fp32 denormals also causes instructions to run at the double
53// precision rate for the device.
54def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
55        "FP32Denormals",
56        "true",
57        "Enable single precision denormal handling">;
58
59def Feature64BitPtr : SubtargetFeature<"64BitPtr",
60        "Is64bit",
61        "true",
62        "Specify if 64-bit addressing should be used">;
63
64def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
65        "R600ALUInst",
66        "false",
67        "Older version of ALU instructions encoding">;
68
69def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
70        "HasVertexCache",
71        "true",
72        "Specify use of dedicated vertex cache">;
73
74def FeatureCaymanISA : SubtargetFeature<"caymanISA",
75        "CaymanISA",
76        "true",
77        "Use Cayman ISA">;
78
79def FeatureCFALUBug : SubtargetFeature<"cfalubug",
80        "CFALUBug",
81        "true",
82        "GPU has CF_ALU bug">;
83
84// XXX - This should probably be removed once enabled by default
85def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
86        "EnableLoadStoreOpt",
87        "true",
88        "Enable SI load/store optimizer pass">;
89
90def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
91        "FlatAddressSpace",
92        "true",
93        "Support flat address space">;
94
95def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
96        "EnableVGPRSpilling",
97        "true",
98        "Enable spilling of VGPRs to scratch memory">;
99
100def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
101        "SGPRInitBug",
102        "true",
103        "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
104
105class SubtargetFeatureFetchLimit <string Value> :
106                          SubtargetFeature <"fetch"#Value,
107        "TexVTXClauseSize",
108        Value,
109        "Limit the maximum number of fetches in a clause to "#Value>;
110
111def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
112def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
113
114class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
115        "wavefrontsize"#Value,
116        "WavefrontSize",
117        !cast<string>(Value),
118        "The number of threads per wavefront">;
119
120def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
121def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
122def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
123
124class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
125        "localmemorysize"#Value,
126        "LocalMemorySize",
127        !cast<string>(Value),
128        "The size of local memory in bytes">;
129
130class SubtargetFeatureGeneration <string Value,
131                                  list<SubtargetFeature> Implies> :
132        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
133                          Value#" GPU generation", Implies>;
134
135def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
136def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
137def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
138
139def FeatureR600 : SubtargetFeatureGeneration<"R600",
140        [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
141
142def FeatureR700 : SubtargetFeatureGeneration<"R700",
143        [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
144
145def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
146        [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
147
148def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
149        [FeatureFetchLimit16, FeatureWavefrontSize64,
150         FeatureLocalMemorySize32768]
151>;
152
153def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
154        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
155         FeatureWavefrontSize64]>;
156
157def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
158        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
159         FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
160
161def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
162        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
163         FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
164
165//===----------------------------------------------------------------------===//
166
167def AMDGPUInstrInfo : InstrInfo {
168  let guessInstructionProperties = 1;
169}
170
171def AMDGPUAsmParser : AsmParser {
172  // Some of the R600 registers have the same name, so this crashes.
173  // For example T0_XYZW and T0_XY both have the asm name T0.
174  let ShouldEmitMatchRegisterName = 0;
175}
176
177def AMDGPU : Target {
178  // Pull in Instruction Info:
179  let InstructionSet = AMDGPUInstrInfo;
180  let AssemblyParsers = [AMDGPUAsmParser];
181}
182
183// Dummy Instruction itineraries for pseudo instructions
184def ALU_NULL : FuncUnit;
185def NullALU : InstrItinClass;
186
187//===----------------------------------------------------------------------===//
188// Predicate helper class
189//===----------------------------------------------------------------------===//
190
191class PredicateControl {
192  Predicate SubtargetPredicate;
193  list<Predicate> OtherPredicates = [];
194  list<Predicate> Predicates = !listconcat([SubtargetPredicate],
195                                            OtherPredicates);
196}
197
198// Include AMDGPU TD files
199include "R600Schedule.td"
200include "SISchedule.td"
201include "Processors.td"
202include "AMDGPUInstrInfo.td"
203include "AMDGPUIntrinsics.td"
204include "AMDGPURegisterInfo.td"
205include "AMDGPUInstructions.td"
206include "AMDGPUCallingConv.td"
207