xref: /minix3/common/lib/libc/arch/mips/atomic/atomic_inc.S (revision 0a6a1f1d05b60e214de2f05a7310ddd1f0e590e7)
1/*	$NetBSD: atomic_inc.S,v 1.5 2015/06/01 23:16:54 matt Exp $	*/
2
3/*-
4 * Copyright (c) 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <machine/asm.h>
30#include "atomic_op_asm.h"
31
32RCSID("$NetBSD: atomic_inc.S,v 1.5 2015/06/01 23:16:54 matt Exp $")
33
34	.text
35	.set	noreorder
36#ifdef _KERNEL_OPT
37#include "opt_cputype.h"
38#ifndef MIPS3_LOONGSON2F
39	.set	noat
40	.set	nomacro
41#endif
42#else /* _KERNEL_OPT */
43	.set	noat
44	.set	nomacro
45#endif /* _KERNEL_OPT */
46
47
48LEAF(_atomic_inc_32)
49#if defined(_MIPS_ARCH_OCTEONP) || defined(_MIPS_ARCH_OCTEON2)
50	li		t0, 1
51	saa		t0, (a0)
52#else
531:	INT_LL		t0, 0(a0)
54	 nop
55	INT_ADDU	t0, 1
56	INT_SC		t0, 0(a0)
57	beq		t0, zero, 1b
58 	 nop
59#endif
60	j		ra
61	 nop
62END(_atomic_inc_32)
63ATOMIC_OP_ALIAS(atomic_inc_32, _atomic_inc_32)
64
65LEAF(_atomic_inc_32_nv)
661:	INT_LL		v0, 0(a0)
67	 nop
68	INT_ADDU	v0, 1
69	move		t0, v0
70	INT_SC		t0, 0(a0)
71	beq		t0, zero, 1b
72 	 nop
73	j		ra
74	 nop
75END(_atomic_inc_32_nv)
76ATOMIC_OP_ALIAS(atomic_inc_32_nv, _atomic_inc_32_nv)
77
78#if !defined(__mips_o32)
79LEAF(_atomic_inc_64)
80#if defined(_MIPS_ARCH_OCTEONP) || defined(_MIPS_ARCH_OCTEON2)
81	li		t0, 1
82	saad		t0, (a0)
83#else
841:	REG_LL		t0, 0(a0)
85	 nop
86	REG_ADDU	t0, 1
87	REG_SC		t0, 0(a0)
88	beq		t0, zero, 1b
89 	 nop
90#endif
91	j		ra
92	 nop
93END(_atomic_inc_64)
94ATOMIC_OP_ALIAS(atomic_inc_64, _atomic_inc_64)
95
96LEAF(_atomic_inc_64_nv)
971:	REG_LL		v0, 0(a0)
98	 nop
99	REG_ADDU	v0, 1
100	move		t0, v0
101	REG_SC		t0, 0(a0)
102	beq		t0, zero, 1b
103 	 nop
104	j		ra
105	 nop
106END(_atomic_inc_64_nv)
107ATOMIC_OP_ALIAS(atomic_inc_64_nv, _atomic_inc_64_nv)
108#endif
109
110#ifdef _LP64
111STRONG_ALIAS(_atomic_inc_ptr,		_atomic_inc_64)
112STRONG_ALIAS(_atomic_inc_ptr_nv,	_atomic_inc_64_nv)
113STRONG_ALIAS(_atomic_inc_ulong,		_atomic_inc_64)
114STRONG_ALIAS(_atomic_inc_ulong_nv,	_atomic_inc_64_nv)
115#else
116STRONG_ALIAS(_atomic_inc_ptr,		_atomic_inc_32)
117STRONG_ALIAS(_atomic_inc_ptr_nv,	_atomic_inc_32_nv)
118STRONG_ALIAS(_atomic_inc_ulong,		_atomic_inc_32)
119STRONG_ALIAS(_atomic_inc_ulong_nv,	_atomic_inc_32_nv)
120#endif
121STRONG_ALIAS(_atomic_inc_uint,		_atomic_inc_32)
122STRONG_ALIAS(_atomic_inc_uint_nv,	_atomic_inc_32_nv)
123
124ATOMIC_OP_ALIAS(atomic_inc_ptr,		_atomic_inc_ptr)
125ATOMIC_OP_ALIAS(atomic_inc_ptr_nv,	_atomic_inc_ptr_nv)
126ATOMIC_OP_ALIAS(atomic_inc_uint,	_atomic_inc_uint)
127ATOMIC_OP_ALIAS(atomic_inc_uint_nv,	_atomic_inc_uint_nv)
128ATOMIC_OP_ALIAS(atomic_inc_ulong,	_atomic_inc_ulong)
129ATOMIC_OP_ALIAS(atomic_inc_ulong_nv,	_atomic_inc_ulong_nv)
130