1; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s 2 3; Verify the import works if the blocks are not topologically sorted. 4; CHECK-LABEL: @dominance_order 5; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] 6define i64 @dominance_order(i64 %arg1) { 7 ; CHECK: llvm.br ^[[BB2:.+]] 8 br label %bb2 9bb1: 10 ; CHECK: ^[[BB1:[a-zA-Z0-9]+]]: 11 ; CHECK: llvm.return %[[VAL1:.+]] : i64 12 ret i64 %1 13bb2: 14 ; CHECK: ^[[BB2]]: 15 ; CHECK: %[[VAL1]] = llvm.add %[[ARG1]] 16 %1 = add i64 %arg1, 3 17 ; CHECK: llvm.br ^[[BB1]] 18 br label %bb1 19} 20 21; // ----- 22 23; CHECK-LABEL: @block_argument 24; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] 25; CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]] 26define i64 @block_argument(i1 %arg1, i64 %arg2) { 27entry: 28 ; CHECK: llvm.cond_br %[[ARG1]] 29 ; CHECK-SAME: ^[[BB1:.+]](%[[ARG2]] : i64) 30 ; CHECK-SAME: ^[[BB2:.+]] 31 br i1 %arg1, label %bb1, label %bb2 32bb1: 33 ; CHECK: ^[[BB1]](%[[BA1:.+]]: i64): 34 ; CHECK: llvm.return %[[BA1]] : i64 35 %0 = phi i64 [ %arg2, %entry ], [ %1, %bb2 ] 36 ret i64 %0 37bb2: 38 ; CHECK: ^[[BB2]]: 39 ; CHECK: %[[VAL1:.+]] = llvm.add %[[ARG2]] 40 ; CHECK: llvm.br ^[[BB1]](%[[VAL1]] 41 %1 = add i64 %arg2, 3 42 br label %bb1 43} 44 45; // ----- 46 47; CHECK-LABEL: @simple_switch( 48; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] 49define i64 @simple_switch(i64 %arg1) { 50 ; CHECK: %[[VAL1:.+]] = llvm.add 51 ; CHECK: %[[VAL2:.+]] = llvm.sub 52 ; CHECK: %[[VAL3:.+]] = llvm.mul 53 %1 = add i64 %arg1, 42 54 %2 = sub i64 %arg1, 42 55 %3 = mul i64 %arg1, 42 56 ; CHECK: llvm.switch %[[ARG1]] : i64, ^[[BBD:.+]] [ 57 ; CHECK: 0: ^[[BB1:.+]], 58 ; CHECK: 9: ^[[BB2:.+]] 59 ; CHECK: ] 60 switch i64 %arg1, label %bbd [ 61 i64 0, label %bb1 62 i64 9, label %bb2 63 ] 64bb1: 65 ; CHECK: ^[[BB1]]: 66 ; CHECK: llvm.return %[[VAL1]] 67 ret i64 %1 68bb2: 69 ; CHECK: ^[[BB2]]: 70 ; CHECK: llvm.return %[[VAL2]] 71 ret i64 %2 72bbd: 73 ; CHECK: ^[[BBD]]: 74 ; CHECK: llvm.return %[[VAL3]] 75 ret i64 %3 76} 77 78; // ----- 79 80; CHECK-LABEL: @switch_args 81; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]] 82define i32 @switch_args(i32 %arg1) { 83entry: 84 ; CHECK: %[[VAL1:.+]] = llvm.add 85 ; CHECK: %[[VAL2:.+]] = llvm.sub 86 ; CHECK: %[[VAL3:.+]] = llvm.mul 87 %0 = add i32 %arg1, 42 88 %1 = sub i32 %arg1, 42 89 %2 = mul i32 %arg1, 42 90 ; CHECK: llvm.switch %[[ARG1]] : i32, ^[[BBD:.+]](%[[VAL3]] : i32) [ 91 ; CHECK: 0: ^[[BB1:.+]](%[[VAL1]], %[[VAL2]] : i32, i32) 92 ; CHECK: ] 93 switch i32 %arg1, label %bbd [ 94 i32 0, label %bb1 95 ] 96bb1: 97 ; CHECK: ^[[BB1]](%[[BA1:.+]]: i32, %[[BA2:.+]]: i32): 98 ; CHECK: %[[VAL1:.*]] = llvm.add %[[BA1]], %[[BA2]] : i32 99 %3 = phi i32 [%0, %entry] 100 %4 = phi i32 [%1, %entry] 101 %5 = add i32 %3, %4 102 ; CHECK: llvm.br ^[[BBD]](%[[VAL1]] 103 br label %bbd 104bbd: 105 ; CHECK: ^[[BBD]](%[[BA3:.+]]: i32): 106 ; CHECK: llvm.return %[[BA3]] 107 %6 = phi i32 [%2, %entry], [%5, %bb1] 108 ret i32 %6 109} 110