1// RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s 2 3//===----------------------------------------------------------------------===// 4// spirv.ShiftRightArithmetic 5//===----------------------------------------------------------------------===// 6 7// CHECK-LABEL: @shift_right_arithmetic_scalar 8spirv.func @shift_right_arithmetic_scalar(%arg0: i32, %arg1: si32, %arg2 : i16, %arg3 : ui16) "None" { 9 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : i32 10 %0 = spirv.ShiftRightArithmetic %arg0, %arg0 : i32, i32 11 12 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : i32 13 %1 = spirv.ShiftRightArithmetic %arg0, %arg1 : i32, si32 14 15 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32 16 // CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : i32 17 %2 = spirv.ShiftRightArithmetic %arg0, %arg2 : i32, i16 18 19 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32 20 // CHECK: llvm.ashr %{{.*}}, %[[ZEXT]] : i32 21 %3 = spirv.ShiftRightArithmetic %arg0, %arg3 : i32, ui16 22 spirv.Return 23} 24 25// CHECK-LABEL: @shift_right_arithmetic_vector 26spirv.func @shift_right_arithmetic_vector(%arg0: vector<4xi64>, %arg1: vector<4xui64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" { 27 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : vector<4xi64> 28 %0 = spirv.ShiftRightArithmetic %arg0, %arg0 : vector<4xi64>, vector<4xi64> 29 30 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : vector<4xi64> 31 %1 = spirv.ShiftRightArithmetic %arg0, %arg1 : vector<4xi64>, vector<4xui64> 32 33 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64> 34 // CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : vector<4xi64> 35 %2 = spirv.ShiftRightArithmetic %arg0, %arg2 : vector<4xi64>, vector<4xi32> 36 37 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64> 38 // CHECK: llvm.ashr %{{.*}}, %[[ZEXT]] : vector<4xi64> 39 %3 = spirv.ShiftRightArithmetic %arg0, %arg3 : vector<4xi64>, vector<4xui32> 40 spirv.Return 41} 42 43//===----------------------------------------------------------------------===// 44// spirv.ShiftRightLogical 45//===----------------------------------------------------------------------===// 46 47// CHECK-LABEL: @shift_right_logical_scalar 48spirv.func @shift_right_logical_scalar(%arg0: i32, %arg1: si32, %arg2 : si16, %arg3 : ui16) "None" { 49 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : i32 50 %0 = spirv.ShiftRightLogical %arg0, %arg0 : i32, i32 51 52 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : i32 53 %1 = spirv.ShiftRightLogical %arg0, %arg1 : i32, si32 54 55 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32 56 // CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : i32 57 %2 = spirv.ShiftRightLogical %arg0, %arg2 : i32, si16 58 59 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32 60 // CHECK: llvm.lshr %{{.*}}, %[[ZEXT]] : i32 61 %3 = spirv.ShiftRightLogical %arg0, %arg3 : i32, ui16 62 spirv.Return 63} 64 65// CHECK-LABEL: @shift_right_logical_vector 66spirv.func @shift_right_logical_vector(%arg0: vector<4xi64>, %arg1: vector<4xsi64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" { 67 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : vector<4xi64> 68 %0 = spirv.ShiftRightLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64> 69 70 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : vector<4xi64> 71 %1 = spirv.ShiftRightLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64> 72 73 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64> 74 // CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : vector<4xi64> 75 %2 = spirv.ShiftRightLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32> 76 77 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64> 78 // CHECK: llvm.lshr %{{.*}}, %[[ZEXT]] : vector<4xi64> 79 %3 = spirv.ShiftRightLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32> 80 spirv.Return 81} 82 83//===----------------------------------------------------------------------===// 84// spirv.ShiftLeftLogical 85//===----------------------------------------------------------------------===// 86 87// CHECK-LABEL: @shift_left_logical_scalar 88spirv.func @shift_left_logical_scalar(%arg0: i32, %arg1: si32, %arg2 : i16, %arg3 : ui16) "None" { 89 // CHECK: llvm.shl %{{.*}}, %{{.*}} : i32 90 %0 = spirv.ShiftLeftLogical %arg0, %arg0 : i32, i32 91 92 // CHECK: llvm.shl %{{.*}}, %{{.*}} : i32 93 %1 = spirv.ShiftLeftLogical %arg0, %arg1 : i32, si32 94 95 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32 96 // CHECK: llvm.shl %{{.*}}, %[[SEXT]] : i32 97 %2 = spirv.ShiftLeftLogical %arg0, %arg2 : i32, i16 98 99 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32 100 // CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : i32 101 %3 = spirv.ShiftLeftLogical %arg0, %arg3 : i32, ui16 102 spirv.Return 103} 104 105// CHECK-LABEL: @shift_left_logical_vector 106spirv.func @shift_left_logical_vector(%arg0: vector<4xi64>, %arg1: vector<4xsi64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" { 107 // CHECK: llvm.shl %{{.*}}, %{{.*}} : vector<4xi64> 108 %0 = spirv.ShiftLeftLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64> 109 110 // CHECK: llvm.shl %{{.*}}, %{{.*}} : vector<4xi64> 111 %1 = spirv.ShiftLeftLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64> 112 113 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64> 114 // CHECK: llvm.shl %{{.*}}, %[[SEXT]] : vector<4xi64> 115 %2 = spirv.ShiftLeftLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32> 116 117 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64> 118 // CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : vector<4xi64> 119 %3 = spirv.ShiftLeftLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32> 120 spirv.Return 121} 122