1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting a description of a target 10 // register file for a code generator. It uses instances of the Register, 11 // RegisterAliases, and RegisterClass classes to gather this information. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "Basic/SequenceToOffsetTable.h" 16 #include "Common/CodeGenHwModes.h" 17 #include "Common/CodeGenRegisters.h" 18 #include "Common/CodeGenTarget.h" 19 #include "Common/InfoByHwMode.h" 20 #include "Common/Types.h" 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/SetVector.h" 25 #include "llvm/ADT/SmallVector.h" 26 #include "llvm/ADT/SparseBitVector.h" 27 #include "llvm/ADT/Twine.h" 28 #include "llvm/CodeGenTypes/MachineValueType.h" 29 #include "llvm/Support/Casting.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/Format.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/TableGen/Error.h" 34 #include "llvm/TableGen/Record.h" 35 #include "llvm/TableGen/SetTheory.h" 36 #include "llvm/TableGen/TGTimer.h" 37 #include "llvm/TableGen/TableGenBackend.h" 38 #include <algorithm> 39 #include <cassert> 40 #include <cstddef> 41 #include <cstdint> 42 #include <deque> 43 #include <iterator> 44 #include <set> 45 #include <string> 46 #include <vector> 47 48 using namespace llvm; 49 50 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 51 52 static cl::opt<bool> 53 RegisterInfoDebug("register-info-debug", cl::init(false), 54 cl::desc("Dump register information to help debugging"), 55 cl::cat(RegisterInfoCat)); 56 57 namespace { 58 59 class RegisterInfoEmitter { 60 const RecordKeeper &Records; 61 const CodeGenTarget Target; 62 CodeGenRegBank &RegBank; 63 64 public: 65 RegisterInfoEmitter(const RecordKeeper &R) 66 : Records(R), Target(R), RegBank(Target.getRegBank()) { 67 RegBank.computeDerivedInfo(); 68 } 69 70 // runEnums - Print out enum values for all of the registers. 71 void runEnums(raw_ostream &OS); 72 73 // runMCDesc - Print out MC register descriptions. 74 void runMCDesc(raw_ostream &OS); 75 76 // runTargetHeader - Emit a header fragment for the register info emitter. 77 void runTargetHeader(raw_ostream &OS); 78 79 // runTargetDesc - Output the target register and register file descriptions. 80 void runTargetDesc(raw_ostream &OS); 81 82 // run - Output the register file description. 83 void run(raw_ostream &OS); 84 85 void debugDump(raw_ostream &OS); 86 87 private: 88 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, 89 bool isCtor); 90 void EmitRegMappingTables(raw_ostream &OS, 91 const std::deque<CodeGenRegister> &Regs, 92 bool isCtor); 93 void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName); 94 void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName); 95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName); 96 }; 97 98 } // end anonymous namespace 99 100 // runEnums - Print out enum values for all of the registers. 101 void RegisterInfoEmitter::runEnums(raw_ostream &OS) { 102 const auto &Registers = RegBank.getRegisters(); 103 104 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 105 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 106 107 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 108 109 emitSourceFileHeader("Target Register Enum Values", OS); 110 111 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 112 OS << "#undef GET_REGINFO_ENUM\n\n"; 113 114 OS << "namespace llvm {\n\n"; 115 116 OS << "class MCRegisterClass;\n" 117 << "extern const MCRegisterClass " << Target.getName() 118 << "MCRegisterClasses[];\n\n"; 119 120 if (!Namespace.empty()) 121 OS << "namespace " << Namespace << " {\n"; 122 OS << "enum : unsigned {\n NoRegister,\n"; 123 124 for (const auto &Reg : Registers) 125 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 126 assert(Registers.size() == Registers.back().EnumValue && 127 "Register enum value mismatch!"); 128 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n"; 129 OS << "};\n"; 130 if (!Namespace.empty()) 131 OS << "} // end namespace " << Namespace << "\n"; 132 133 const auto &RegisterClasses = RegBank.getRegClasses(); 134 if (!RegisterClasses.empty()) { 135 136 // RegisterClass enums are stored as uint16_t in the tables. 137 assert(RegisterClasses.size() <= 0xffff && 138 "Too many register classes to fit in tables"); 139 140 OS << "\n// Register classes\n\n"; 141 if (!Namespace.empty()) 142 OS << "namespace " << Namespace << " {\n"; 143 OS << "enum {\n"; 144 for (const auto &RC : RegisterClasses) 145 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; 146 OS << "\n};\n"; 147 if (!Namespace.empty()) 148 OS << "} // end namespace " << Namespace << "\n\n"; 149 } 150 151 ArrayRef<const Record *> RegAltNameIndices = Target.getRegAltNameIndices(); 152 // If the only definition is the default NoRegAltName, we don't need to 153 // emit anything. 154 if (RegAltNameIndices.size() > 1) { 155 OS << "\n// Register alternate name indices\n\n"; 156 if (!Namespace.empty()) 157 OS << "namespace " << Namespace << " {\n"; 158 OS << "enum {\n"; 159 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 160 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 161 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 162 OS << "};\n"; 163 if (!Namespace.empty()) 164 OS << "} // end namespace " << Namespace << "\n\n"; 165 } 166 167 auto &SubRegIndices = RegBank.getSubRegIndices(); 168 if (!SubRegIndices.empty()) { 169 OS << "\n// Subregister indices\n\n"; 170 std::string Namespace = SubRegIndices.front().getNamespace(); 171 if (!Namespace.empty()) 172 OS << "namespace " << Namespace << " {\n"; 173 OS << "enum : uint16_t {\n NoSubRegister,\n"; 174 unsigned i = 0; 175 for (const auto &Idx : SubRegIndices) 176 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 177 OS << " NUM_TARGET_SUBREGS\n};\n"; 178 if (!Namespace.empty()) 179 OS << "} // end namespace " << Namespace << "\n\n"; 180 } 181 182 OS << "// Register pressure sets enum.\n"; 183 if (!Namespace.empty()) 184 OS << "namespace " << Namespace << " {\n"; 185 OS << "enum RegisterPressureSets {\n"; 186 unsigned NumSets = RegBank.getNumRegPressureSets(); 187 for (unsigned i = 0; i < NumSets; ++i) { 188 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 189 OS << " " << RegUnits.Name << " = " << i << ",\n"; 190 } 191 OS << "};\n"; 192 if (!Namespace.empty()) 193 OS << "} // end namespace " << Namespace << '\n'; 194 OS << '\n'; 195 196 OS << "} // end namespace llvm\n\n"; 197 OS << "#endif // GET_REGINFO_ENUM\n\n"; 198 } 199 200 static void printInt(raw_ostream &OS, int Val) { OS << Val; } 201 202 void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS, 203 StringRef ClassName) { 204 unsigned NumRCs = RegBank.getRegClasses().size(); 205 unsigned NumSets = RegBank.getNumRegPressureSets(); 206 207 OS << "/// Get the weight in units of pressure for this register class.\n" 208 << "const RegClassWeight &" << ClassName << "::\n" 209 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 210 << " static const RegClassWeight RCWeightTable[] = {\n"; 211 for (const auto &RC : RegBank.getRegClasses()) { 212 const CodeGenRegister::Vec &Regs = RC.getMembers(); 213 OS << " {" << RC.getWeight(RegBank) << ", "; 214 if (Regs.empty() || RC.Artificial) 215 OS << '0'; 216 else { 217 std::vector<unsigned> RegUnits; 218 RC.buildRegUnitSet(RegBank, RegUnits); 219 OS << RegBank.getRegUnitSetWeight(RegUnits); 220 } 221 OS << "}, \t// " << RC.getName() << "\n"; 222 } 223 OS << " };\n" 224 << " return RCWeightTable[RC->getID()];\n" 225 << "}\n\n"; 226 227 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 228 // bother generating a table. 229 bool RegUnitsHaveUnitWeight = true; 230 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 231 UnitIdx < UnitEnd; ++UnitIdx) { 232 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 233 RegUnitsHaveUnitWeight = false; 234 } 235 OS << "/// Get the weight in units of pressure for this register unit.\n" 236 << "unsigned " << ClassName << "::\n" 237 << "getRegUnitWeight(unsigned RegUnit) const {\n" 238 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 239 << " && \"invalid register unit\");\n"; 240 if (!RegUnitsHaveUnitWeight) { 241 OS << " static const uint8_t RUWeightTable[] = {\n "; 242 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 243 UnitIdx < UnitEnd; ++UnitIdx) { 244 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 245 assert(RU.Weight < 256 && "RegUnit too heavy"); 246 OS << RU.Weight << ", "; 247 } 248 OS << "};\n" 249 << " return RUWeightTable[RegUnit];\n"; 250 } else { 251 OS << " // All register units have unit weight.\n" 252 << " return 1;\n"; 253 } 254 OS << "}\n\n"; 255 256 OS << "\n" 257 << "// Get the number of dimensions of register pressure.\n" 258 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 259 << " return " << NumSets << ";\n}\n\n"; 260 261 OS << "// Get the name of this register unit pressure set.\n" 262 << "const char *" << ClassName << "::\n" 263 << "getRegPressureSetName(unsigned Idx) const {\n" 264 << " static const char *PressureNameTable[] = {\n"; 265 unsigned MaxRegUnitWeight = 0; 266 for (unsigned i = 0; i < NumSets; ++i) { 267 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 268 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 269 OS << " \"" << RegUnits.Name << "\",\n"; 270 } 271 OS << " };\n" 272 << " return PressureNameTable[Idx];\n" 273 << "}\n\n"; 274 275 OS << "// Get the register unit pressure limit for this dimension.\n" 276 << "// This limit must be adjusted dynamically for reserved registers.\n" 277 << "unsigned " << ClassName << "::\n" 278 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 279 "{\n" 280 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 281 << " PressureLimitTable[] = {\n"; 282 for (unsigned i = 0; i < NumSets; ++i) { 283 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 284 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name 285 << "\n"; 286 } 287 OS << " };\n" 288 << " return PressureLimitTable[Idx];\n" 289 << "}\n\n"; 290 291 SequenceToOffsetTable<std::vector<int>> PSetsSeqs(/*Terminator=*/-1); 292 293 // This table may be larger than NumRCs if some register units needed a list 294 // of unit sets that did not correspond to a register class. 295 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 296 std::vector<std::vector<int>> PSets(NumRCUnitSets); 297 298 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 299 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 300 PSets[i].reserve(PSetIDs.size()); 301 for (unsigned PSetID : PSetIDs) { 302 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order); 303 } 304 llvm::sort(PSets[i]); 305 PSetsSeqs.add(PSets[i]); 306 } 307 308 PSetsSeqs.layout(); 309 310 OS << "/// Table of pressure sets per register class or unit.\n" 311 << "static const int RCSetsTable[] = {\n"; 312 PSetsSeqs.emit(OS, printInt); 313 OS << "};\n\n"; 314 315 OS << "/// Get the dimensions of register pressure impacted by this " 316 << "register class.\n" 317 << "/// Returns a -1 terminated array of pressure set IDs\n" 318 << "const int *" << ClassName << "::\n" 319 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 320 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 321 << " RCSetStartTable[] = {\n "; 322 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 323 OS << PSetsSeqs.get(PSets[i]) << ","; 324 } 325 OS << "};\n" 326 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 327 << "}\n\n"; 328 329 OS << "/// Get the dimensions of register pressure impacted by this " 330 << "register unit.\n" 331 << "/// Returns a -1 terminated array of pressure set IDs\n" 332 << "const int *" << ClassName << "::\n" 333 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 334 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 335 << " && \"invalid register unit\");\n"; 336 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 337 << " RUSetStartTable[] = {\n "; 338 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 339 UnitIdx < UnitEnd; ++UnitIdx) { 340 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 341 << ","; 342 } 343 OS << "};\n" 344 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 345 << "}\n\n"; 346 } 347 348 using DwarfRegNumsMapPair = std::pair<const Record *, std::vector<int64_t>>; 349 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 350 351 static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 352 // Sort and unique to get a map-like vector. We want the last assignment to 353 // match previous behaviour. 354 llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>()); 355 // Warn about duplicate assignments. 356 const Record *LastSeenReg = nullptr; 357 for (const auto &X : DwarfRegNums) { 358 const auto &Reg = X.first; 359 // The only way LessRecordRegister can return equal is if they're the same 360 // string. Use simple equality instead. 361 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 362 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 363 getQualifiedName(Reg) + 364 "specified multiple times"); 365 LastSeenReg = Reg; 366 } 367 auto Last = llvm::unique(DwarfRegNums, [](const DwarfRegNumsMapPair &A, 368 const DwarfRegNumsMapPair &B) { 369 return A.first->getName() == B.first->getName(); 370 }); 371 DwarfRegNums.erase(Last, DwarfRegNums.end()); 372 } 373 374 void RegisterInfoEmitter::EmitRegMappingTables( 375 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 376 // Collect all information about dwarf register numbers 377 DwarfRegNumsVecTy DwarfRegNums; 378 379 // First, just pull all provided information to the map 380 unsigned maxLength = 0; 381 for (auto &RE : Regs) { 382 const Record *Reg = RE.TheDef; 383 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 384 maxLength = std::max((size_t)maxLength, RegNums.size()); 385 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 386 } 387 finalizeDwarfRegNumsKeys(DwarfRegNums); 388 389 if (!maxLength) 390 return; 391 392 // Now we know maximal length of number list. Append -1's, where needed 393 for (auto &DwarfRegNum : DwarfRegNums) 394 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) 395 DwarfRegNum.second.push_back(-1); 396 397 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 398 399 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 400 401 // Emit reverse information about the dwarf register numbers. 402 for (unsigned j = 0; j < 2; ++j) { 403 for (unsigned I = 0, E = maxLength; I != E; ++I) { 404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 406 OS << I << "Dwarf2L[]"; 407 408 if (!isCtor) { 409 OS << " = {\n"; 410 411 // Store the mapping sorted by the LLVM reg num so lookup can be done 412 // with a binary search. 413 std::map<uint64_t, const Record *> Dwarf2LMap; 414 for (auto &DwarfRegNum : DwarfRegNums) { 415 int DwarfRegNo = DwarfRegNum.second[I]; 416 if (DwarfRegNo < 0) 417 continue; 418 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; 419 } 420 421 for (auto &I : Dwarf2LMap) 422 OS << " { " << I.first << "U, " << getQualifiedName(I.second) 423 << " },\n"; 424 425 OS << "};\n"; 426 } else { 427 OS << ";\n"; 428 } 429 430 // We have to store the size in a const global, it's used in multiple 431 // places. 432 OS << "extern const unsigned " << Namespace 433 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize"; 434 if (!isCtor) 435 OS << " = std::size(" << Namespace 436 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n"; 437 else 438 OS << ";\n\n"; 439 } 440 } 441 442 for (auto &RE : Regs) { 443 const Record *Reg = RE.TheDef; 444 const RecordVal *V = Reg->getValue("DwarfAlias"); 445 if (!V || !V->getValue()) 446 continue; 447 448 const DefInit *DI = cast<DefInit>(V->getValue()); 449 const Record *Alias = DI->getDef(); 450 const auto &AliasIter = llvm::lower_bound( 451 DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) { 452 return LessRecordRegister()(A.first, B); 453 }); 454 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 455 "Expected Alias to be present in map"); 456 const auto &RegIter = llvm::lower_bound( 457 DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) { 458 return LessRecordRegister()(A.first, B); 459 }); 460 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 461 "Expected Reg to be present in map"); 462 RegIter->second = AliasIter->second; 463 } 464 465 // Emit information about the dwarf register numbers. 466 for (unsigned j = 0; j < 2; ++j) { 467 for (unsigned i = 0, e = maxLength; i != e; ++i) { 468 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 469 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 470 OS << i << "L2Dwarf[]"; 471 if (!isCtor) { 472 OS << " = {\n"; 473 // Store the mapping sorted by the Dwarf reg num so lookup can be done 474 // with a binary search. 475 for (auto &DwarfRegNum : DwarfRegNums) { 476 int RegNo = DwarfRegNum.second[i]; 477 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 478 continue; 479 480 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo 481 << "U },\n"; 482 } 483 OS << "};\n"; 484 } else { 485 OS << ";\n"; 486 } 487 488 // We have to store the size in a const global, it's used in multiple 489 // places. 490 OS << "extern const unsigned " << Namespace 491 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 492 if (!isCtor) 493 OS << " = std::size(" << Namespace 494 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 495 else 496 OS << ";\n\n"; 497 } 498 } 499 } 500 501 void RegisterInfoEmitter::EmitRegMapping( 502 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 503 // Emit the initializer so the tables from EmitRegMappingTables get wired up 504 // to the MCRegisterInfo object. 505 unsigned maxLength = 0; 506 for (auto &RE : Regs) { 507 const Record *Reg = RE.TheDef; 508 maxLength = std::max((size_t)maxLength, 509 Reg->getValueAsListOfInts("DwarfNumbers").size()); 510 } 511 512 if (!maxLength) 513 return; 514 515 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 516 517 // Emit reverse information about the dwarf register numbers. 518 for (unsigned j = 0; j < 2; ++j) { 519 OS << " switch ("; 520 if (j == 0) 521 OS << "DwarfFlavour"; 522 else 523 OS << "EHFlavour"; 524 OS << ") {\n" 525 << " default:\n" 526 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 527 528 for (unsigned i = 0, e = maxLength; i != e; ++i) { 529 OS << " case " << i << ":\n"; 530 OS << " "; 531 if (!isCtor) 532 OS << "RI->"; 533 std::string Tmp; 534 raw_string_ostream(Tmp) 535 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 536 << "Dwarf2L"; 537 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 538 if (j == 0) 539 OS << "false"; 540 else 541 OS << "true"; 542 OS << ");\n"; 543 OS << " break;\n"; 544 } 545 OS << " }\n"; 546 } 547 548 // Emit information about the dwarf register numbers. 549 for (unsigned j = 0; j < 2; ++j) { 550 OS << " switch ("; 551 if (j == 0) 552 OS << "DwarfFlavour"; 553 else 554 OS << "EHFlavour"; 555 OS << ") {\n" 556 << " default:\n" 557 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 558 559 for (unsigned i = 0, e = maxLength; i != e; ++i) { 560 OS << " case " << i << ":\n"; 561 OS << " "; 562 if (!isCtor) 563 OS << "RI->"; 564 std::string Tmp; 565 raw_string_ostream(Tmp) 566 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 567 << "L2Dwarf"; 568 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 569 if (j == 0) 570 OS << "false"; 571 else 572 OS << "true"; 573 OS << ");\n"; 574 OS << " break;\n"; 575 } 576 OS << " }\n"; 577 } 578 } 579 580 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 581 // Width is the number of bits per hex number. 582 static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits, 583 unsigned Width) { 584 assert(Width <= 32 && "Width too large"); 585 unsigned Digits = (Width + 3) / 4; 586 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 587 unsigned Value = 0; 588 for (unsigned j = 0; j != Width && i + j != e; ++j) 589 Value |= Bits.test(i + j) << j; 590 OS << format("0x%0*x, ", Digits, Value); 591 } 592 } 593 594 // Helper to emit a set of bits into a constant byte array. 595 class BitVectorEmitter { 596 BitVector Values; 597 598 public: 599 void add(unsigned v) { 600 if (v >= Values.size()) 601 Values.resize(((v / 8) + 1) * 8); // Round up to the next byte. 602 Values[v] = true; 603 } 604 605 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Values, 8); } 606 }; 607 608 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 609 OS << getEnumName(VT); 610 } 611 612 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 613 OS << (Idx ? Idx->EnumValue : 0); 614 } 615 616 // Differentially encoded register and regunit lists allow for better 617 // compression on regular register banks. The sequence is computed from the 618 // differential list as: 619 // 620 // out[0] = InitVal; 621 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 622 // 623 // The initial value depends on the specific list. The list is terminated by a 624 // 0 differential which means we can't encode repeated elements. 625 626 typedef SmallVector<int16_t, 4> DiffVec; 627 typedef SmallVector<LaneBitmask, 4> MaskVec; 628 629 // Fills V with differentials between every two consecutive elements of List. 630 static DiffVec &diffEncode(DiffVec &V, SparseBitVector<> List) { 631 assert(V.empty() && "Clear DiffVec before diffEncode."); 632 SparseBitVector<>::iterator I = List.begin(), E = List.end(); 633 unsigned Val = *I; 634 while (++I != E) { 635 unsigned Cur = *I; 636 V.push_back(Cur - Val); 637 Val = Cur; 638 } 639 return V; 640 } 641 642 template <typename Iter> 643 static DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 644 assert(V.empty() && "Clear DiffVec before diffEncode."); 645 unsigned Val = InitVal; 646 for (Iter I = Begin; I != End; ++I) { 647 unsigned Cur = (*I)->EnumValue; 648 V.push_back(Cur - Val); 649 Val = Cur; 650 } 651 return V; 652 } 653 654 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; } 655 656 static void printMask(raw_ostream &OS, LaneBitmask Val) { 657 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 658 } 659 660 // Try to combine Idx's compose map into Vec if it is compatible. 661 // Return false if it's not possible. 662 static bool combine(const CodeGenSubRegIndex *Idx, 663 SmallVectorImpl<CodeGenSubRegIndex *> &Vec) { 664 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 665 for (const auto &I : Map) { 666 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 667 if (Entry && Entry != I.second) 668 return false; 669 } 670 671 // All entries are compatible. Make it so. 672 for (const auto &I : Map) { 673 auto *&Entry = Vec[I.first->EnumValue - 1]; 674 assert((!Entry || Entry == I.second) && "Expected EnumValue to be unique"); 675 Entry = I.second; 676 } 677 return true; 678 } 679 680 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 681 StringRef ClassName) { 682 const auto &SubRegIndices = RegBank.getSubRegIndices(); 683 OS << "unsigned " << ClassName 684 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 685 686 // Many sub-register indexes are composition-compatible, meaning that 687 // 688 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 689 // 690 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 691 // The illegal entries can be use as wildcards to compress the table further. 692 693 // Map each Sub-register index to a compatible table row. 694 SmallVector<unsigned, 4> RowMap; 695 SmallVector<SmallVector<CodeGenSubRegIndex *, 4>, 4> Rows; 696 697 auto SubRegIndicesSize = 698 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 699 for (const auto &Idx : SubRegIndices) { 700 unsigned Found = ~0u; 701 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 702 if (combine(&Idx, Rows[r])) { 703 Found = r; 704 break; 705 } 706 } 707 if (Found == ~0u) { 708 Found = Rows.size(); 709 Rows.resize(Found + 1); 710 Rows.back().resize(SubRegIndicesSize); 711 combine(&Idx, Rows.back()); 712 } 713 RowMap.push_back(Found); 714 } 715 716 // Output the row map if there is multiple rows. 717 if (Rows.size() > 1) { 718 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 719 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 720 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 721 OS << RowMap[i] << ", "; 722 OS << "\n };\n"; 723 } 724 725 // Output the rows. 726 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 727 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 728 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 729 OS << " { "; 730 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 731 if (Rows[r][i]) 732 OS << Rows[r][i]->getQualifiedName() << ", "; 733 else 734 OS << "0, "; 735 OS << "},\n"; 736 } 737 OS << " };\n\n"; 738 739 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" 740 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 741 if (Rows.size() > 1) 742 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 743 else 744 OS << " return Rows[0][IdxB];\n"; 745 OS << "}\n\n"; 746 } 747 748 void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 749 StringRef ClassName) { 750 // See the comments in computeSubRegLaneMasks() for our goal here. 751 const auto &SubRegIndices = RegBank.getSubRegIndices(); 752 753 // Create a list of Mask+Rotate operations, with equivalent entries merged. 754 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 755 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 756 for (const auto &Idx : SubRegIndices) { 757 const SmallVector<MaskRolPair, 1> &IdxSequence = 758 Idx.CompositionLaneMaskTransform; 759 760 unsigned Found = ~0u; 761 unsigned SIdx = 0; 762 unsigned NextSIdx; 763 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 764 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 765 NextSIdx = SIdx + Sequence.size() + 1; 766 if (Sequence == IdxSequence) { 767 Found = SIdx; 768 break; 769 } 770 } 771 if (Found == ~0u) { 772 Sequences.push_back(IdxSequence); 773 Found = SIdx; 774 } 775 SubReg2SequenceIndexMap.push_back(Found); 776 } 777 778 OS << " struct MaskRolOp {\n" 779 " LaneBitmask Mask;\n" 780 " uint8_t RotateLeft;\n" 781 " };\n" 782 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 783 unsigned Idx = 0; 784 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 785 OS << " "; 786 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 787 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 788 const MaskRolPair &P = Sequence[p]; 789 printMask(OS << "{ ", P.Mask); 790 OS << format(", %2u }, ", P.RotateLeft); 791 } 792 OS << "{ LaneBitmask::getNone(), 0 }"; 793 if (s + 1 != se) 794 OS << ", "; 795 OS << " // Sequence " << Idx << "\n"; 796 Idx += Sequence.size() + 1; 797 } 798 auto *IntType = 799 getMinimalTypeForRange(*llvm::max_element(SubReg2SequenceIndexMap)); 800 OS << " };\n" 801 " static const " 802 << IntType << " CompositeSequences[] = {\n"; 803 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 804 OS << " "; 805 OS << SubReg2SequenceIndexMap[i]; 806 if (i + 1 != e) 807 OS << ","; 808 OS << " // to " << SubRegIndices[i].getName() << "\n"; 809 } 810 OS << " };\n\n"; 811 812 OS << "LaneBitmask " << ClassName 813 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 814 " const {\n" 815 " --IdxA; assert(IdxA < " 816 << SubRegIndices.size() 817 << " && \"Subregister index out of bounds\");\n" 818 " LaneBitmask Result;\n" 819 " for (const MaskRolOp *Ops =\n" 820 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 821 " Ops->Mask.any(); ++Ops) {\n" 822 " LaneBitmask::Type M = LaneMask.getAsInteger() & " 823 "Ops->Mask.getAsInteger();\n" 824 " if (unsigned S = Ops->RotateLeft)\n" 825 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - " 826 "S)));\n" 827 " else\n" 828 " Result |= LaneBitmask(M);\n" 829 " }\n" 830 " return Result;\n" 831 "}\n\n"; 832 833 OS << "LaneBitmask " << ClassName 834 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 835 " LaneBitmask LaneMask) const {\n" 836 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 837 " --IdxA; assert(IdxA < " 838 << SubRegIndices.size() 839 << " && \"Subregister index out of bounds\");\n" 840 " LaneBitmask Result;\n" 841 " for (const MaskRolOp *Ops =\n" 842 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 843 " Ops->Mask.any(); ++Ops) {\n" 844 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 845 " if (unsigned S = Ops->RotateLeft)\n" 846 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - " 847 "S)));\n" 848 " else\n" 849 " Result |= LaneBitmask(M);\n" 850 " }\n" 851 " return Result;\n" 852 "}\n\n"; 853 } 854 855 // 856 // runMCDesc - Print out MC register descriptions. 857 // 858 void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { 859 emitSourceFileHeader("MC Register Information", OS); 860 861 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 862 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 863 864 const auto &Regs = RegBank.getRegisters(); 865 866 auto &SubRegIndices = RegBank.getSubRegIndices(); 867 // The lists of sub-registers and super-registers go in the same array. That 868 // allows us to share suffixes. 869 typedef std::vector<const CodeGenRegister *> RegVec; 870 871 // Differentially encoded lists. 872 SequenceToOffsetTable<DiffVec> DiffSeqs; 873 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 874 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 875 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 876 877 // List of lane masks accompanying register unit sequences. 878 SequenceToOffsetTable<MaskVec> LaneMaskSeqs(/*Terminator=*/std::nullopt); 879 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 880 881 // Keep track of sub-register names as well. These are not differentially 882 // encoded. 883 typedef SmallVector<const CodeGenSubRegIndex *, 4> SubRegIdxVec; 884 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs( 885 /*Terminator=*/std::nullopt); 886 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 887 888 SequenceToOffsetTable<std::string> RegStrings; 889 890 // Precompute register lists for the SequenceToOffsetTable. 891 unsigned i = 0; 892 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 893 const auto &Reg = *I; 894 RegStrings.add(std::string(Reg.getName())); 895 896 // Compute the ordered sub-register list. 897 SetVector<const CodeGenRegister *> SR; 898 Reg.addSubRegsPreOrder(SR, RegBank); 899 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 900 DiffSeqs.add(SubRegLists[i]); 901 902 // Compute the corresponding sub-register indexes. 903 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 904 for (const CodeGenRegister *S : SR) 905 SRIs.push_back(Reg.getSubRegIndex(S)); 906 SubRegIdxSeqs.add(SRIs); 907 908 // Super-registers are already computed. 909 const RegVec &SuperRegList = Reg.getSuperRegs(); 910 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 911 SuperRegList.end()); 912 DiffSeqs.add(SuperRegLists[i]); 913 914 const SparseBitVector<> &RUs = Reg.getNativeRegUnits(); 915 DiffSeqs.add(diffEncode(RegUnitLists[i], RUs)); 916 917 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 918 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 919 assert(LaneMaskVec.empty()); 920 llvm::append_range(LaneMaskVec, RUMasks); 921 LaneMaskSeqs.add(LaneMaskVec); 922 } 923 924 // Compute the final layout of the sequence table. 925 DiffSeqs.layout(); 926 LaneMaskSeqs.layout(); 927 SubRegIdxSeqs.layout(); 928 929 OS << "namespace llvm {\n\n"; 930 931 const std::string &TargetName = std::string(Target.getName()); 932 933 // Emit the shared table of differential lists. 934 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n"; 935 DiffSeqs.emit(OS, printDiff16); 936 OS << "};\n\n"; 937 938 // Emit the shared table of regunit lane mask sequences. 939 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 940 LaneMaskSeqs.emit(OS, printMask); 941 OS << "};\n\n"; 942 943 // Emit the table of sub-register indexes. 944 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 945 SubRegIdxSeqs.emit(OS, printSubRegIndex); 946 OS << "};\n\n"; 947 948 // Emit the string table. 949 RegStrings.layout(); 950 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + 951 "RegStrings[]"); 952 953 OS << "extern const MCRegisterDesc " << TargetName 954 << "RegDesc[] = { // Descriptors\n"; 955 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0, 0 },\n"; 956 957 // Emit the register descriptors now. 958 i = 0; 959 for (const auto &Reg : Regs) { 960 unsigned FirstRU = Reg.getNativeRegUnits().find_first(); 961 unsigned Offset = DiffSeqs.get(RegUnitLists[i]); 962 // The value must be kept in sync with MCRegisterInfo.h. 963 constexpr unsigned RegUnitBits = 12; 964 assert(isUInt<RegUnitBits>(FirstRU) && "Too many regunits"); 965 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big"); 966 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " 967 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 968 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 969 << (Offset << RegUnitBits | FirstRU) << ", " 970 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << ", " << Reg.Constant << ", " 971 << Reg.Artificial << " },\n"; 972 ++i; 973 } 974 OS << "};\n\n"; // End of register descriptors... 975 976 // Emit the table of register unit roots. Each regunit has one or two root 977 // registers. 978 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 979 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 980 ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(i).getRoots(); 981 assert(!Roots.empty() && "All regunits must have a root register."); 982 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 983 OS << " { "; 984 ListSeparator LS; 985 for (const CodeGenRegister *R : Roots) 986 OS << LS << getQualifiedName(R->TheDef); 987 OS << " },\n"; 988 } 989 OS << "};\n\n"; 990 991 const auto &RegisterClasses = RegBank.getRegClasses(); 992 993 // Loop over all of the register classes... emitting each one. 994 OS << "namespace { // Register classes...\n"; 995 996 SequenceToOffsetTable<std::string> RegClassStrings; 997 998 // Emit the register enum value arrays for each RegisterClass 999 for (const auto &RC : RegisterClasses) { 1000 ArrayRef<const Record *> Order = RC.getOrder(); 1001 1002 // Give the register class a legal C name if it's anonymous. 1003 const std::string &Name = RC.getName(); 1004 1005 RegClassStrings.add(Name); 1006 1007 // Emit the register list now (unless it would be a zero-length array). 1008 if (!Order.empty()) { 1009 OS << " // " << Name << " Register Class...\n" 1010 << " const MCPhysReg " << Name << "[] = {\n "; 1011 for (const Record *Reg : Order) { 1012 OS << getQualifiedName(Reg) << ", "; 1013 } 1014 OS << "\n };\n\n"; 1015 1016 OS << " // " << Name << " Bit set.\n" 1017 << " const uint8_t " << Name << "Bits[] = {\n "; 1018 BitVectorEmitter BVE; 1019 for (const Record *Reg : Order) { 1020 BVE.add(RegBank.getReg(Reg)->EnumValue); 1021 } 1022 BVE.print(OS); 1023 OS << "\n };\n\n"; 1024 } 1025 } 1026 OS << "} // end anonymous namespace\n\n"; 1027 1028 RegClassStrings.layout(); 1029 RegClassStrings.emitStringLiteralDef( 1030 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); 1031 1032 OS << "extern const MCRegisterClass " << TargetName 1033 << "MCRegisterClasses[] = {\n"; 1034 1035 for (const auto &RC : RegisterClasses) { 1036 ArrayRef<const Record *> Order = RC.getOrder(); 1037 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); 1038 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; 1039 std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")"; 1040 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1041 uint32_t RegSize = 0; 1042 if (RC.RSI.isSimple()) 1043 RegSize = RC.RSI.getSimple().RegSize; 1044 OS << " { " << RCName << ", " << RCBitsName << ", " 1045 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() 1046 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", " 1047 << RegSize << ", " << RC.CopyCost << ", " 1048 << (RC.Allocatable ? "true" : "false") << ", " 1049 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n"; 1050 } 1051 1052 OS << "};\n\n"; 1053 1054 EmitRegMappingTables(OS, Regs, false); 1055 1056 // Emit Reg encoding table 1057 OS << "extern const uint16_t " << TargetName; 1058 OS << "RegEncodingTable[] = {\n"; 1059 // Add entry for NoRegister 1060 OS << " 0,\n"; 1061 for (const auto &RE : Regs) { 1062 const Record *Reg = RE.TheDef; 1063 const BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1064 uint64_t Value = 0; 1065 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1066 if (const BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1067 Value |= (uint64_t)B->getValue() << b; 1068 } 1069 OS << " " << Value << ",\n"; 1070 } 1071 OS << "};\n"; // End of HW encoding table 1072 1073 // MCRegisterInfo initialization routine. 1074 OS << "static inline void Init" << TargetName 1075 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1076 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1077 "{\n" 1078 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1079 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1080 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1081 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1082 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1083 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1084 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1085 << TargetName << "RegEncodingTable);\n\n"; 1086 1087 EmitRegMapping(OS, Regs, false); 1088 1089 OS << "}\n\n"; 1090 1091 OS << "} // end namespace llvm\n\n"; 1092 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1093 } 1094 1095 void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) { 1096 emitSourceFileHeader("Register Information Header Fragment", OS); 1097 1098 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1099 OS << "#undef GET_REGINFO_HEADER\n\n"; 1100 1101 const std::string &TargetName = std::string(Target.getName()); 1102 std::string ClassName = TargetName + "GenRegisterInfo"; 1103 1104 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1105 1106 OS << "namespace llvm {\n\n"; 1107 1108 OS << "class " << TargetName << "FrameLowering;\n\n"; 1109 1110 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1111 << " explicit " << ClassName 1112 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1113 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1114 if (!RegBank.getSubRegIndices().empty()) { 1115 OS << " unsigned composeSubRegIndicesImpl" 1116 << "(unsigned, unsigned) const override;\n" 1117 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1118 << "(unsigned, LaneBitmask) const override;\n" 1119 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1120 << "(unsigned, LaneBitmask) const override;\n" 1121 << " const TargetRegisterClass *getSubClassWithSubReg" 1122 << "(const TargetRegisterClass *, unsigned) const override;\n" 1123 << " const TargetRegisterClass *getSubRegisterClass" 1124 << "(const TargetRegisterClass *, unsigned) const override;\n"; 1125 } 1126 OS << " const RegClassWeight &getRegClassWeight(" 1127 << "const TargetRegisterClass *RC) const override;\n" 1128 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1129 << " unsigned getNumRegPressureSets() const override;\n" 1130 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1131 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1132 "Idx) const override;\n" 1133 << " const int *getRegClassPressureSets(" 1134 << "const TargetRegisterClass *RC) const override;\n" 1135 << " const int *getRegUnitPressureSets(" 1136 << "unsigned RegUnit) const override;\n" 1137 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1138 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1139 << " bool isGeneralPurposeRegister(const MachineFunction &, " 1140 << "MCRegister) const override;\n" 1141 << " bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)" 1142 << " const override;\n" 1143 << " bool isFixedRegister(const MachineFunction &, " 1144 << "MCRegister) const override;\n" 1145 << " bool isArgumentRegister(const MachineFunction &, " 1146 << "MCRegister) const override;\n" 1147 << " bool isConstantPhysReg(MCRegister PhysReg) const override final;\n" 1148 << " /// Devirtualized TargetFrameLowering.\n" 1149 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1150 << " const MachineFunction &MF);\n"; 1151 1152 const auto &RegisterClasses = RegBank.getRegClasses(); 1153 if (llvm::any_of(RegisterClasses, 1154 [](const auto &RC) { return RC.getBaseClassOrder(); })) { 1155 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) " 1156 "const override;\n"; 1157 } 1158 1159 OS << "};\n\n"; 1160 1161 if (!RegisterClasses.empty()) { 1162 OS << "namespace " << RegisterClasses.front().Namespace 1163 << " { // Register classes\n"; 1164 1165 for (const auto &RC : RegisterClasses) { 1166 const std::string &Name = RC.getName(); 1167 1168 // Output the extern for the instance. 1169 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1170 } 1171 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1172 } 1173 OS << "} // end namespace llvm\n\n"; 1174 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1175 } 1176 1177 // 1178 // runTargetDesc - Output the target register and register file descriptions. 1179 // 1180 void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { 1181 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1182 1183 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1184 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1185 1186 OS << "namespace llvm {\n\n"; 1187 1188 // Get access to MCRegisterClass data. 1189 OS << "extern const MCRegisterClass " << Target.getName() 1190 << "MCRegisterClasses[];\n"; 1191 1192 // Start out by emitting each of the register classes. 1193 const auto &RegisterClasses = RegBank.getRegClasses(); 1194 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1195 1196 // Collect all registers belonging to any allocatable class. 1197 std::set<const Record *> AllocatableRegs; 1198 1199 // Collect allocatable registers. 1200 for (const auto &RC : RegisterClasses) { 1201 ArrayRef<const Record *> Order = RC.getOrder(); 1202 1203 if (RC.Allocatable) 1204 AllocatableRegs.insert(Order.begin(), Order.end()); 1205 } 1206 1207 const CodeGenHwModes &CGH = Target.getHwModes(); 1208 unsigned NumModes = CGH.getNumModeIds(); 1209 1210 // Build a shared array of value types. 1211 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs( 1212 /*Terminator=*/MVT::Other); 1213 for (unsigned M = 0; M < NumModes; ++M) { 1214 for (const auto &RC : RegisterClasses) { 1215 std::vector<MVT::SimpleValueType> S; 1216 for (const ValueTypeByHwMode &VVT : RC.VTs) 1217 if (VVT.hasDefault() || VVT.hasMode(M)) 1218 S.push_back(VVT.get(M).SimpleTy); 1219 VTSeqs.add(S); 1220 } 1221 } 1222 VTSeqs.layout(); 1223 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1224 VTSeqs.emit(OS, printSimpleValueType); 1225 OS << "};\n"; 1226 1227 // Emit SubRegIndex names, skipping 0. 1228 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; 1229 1230 for (const auto &Idx : SubRegIndices) { 1231 OS << Idx.getName(); 1232 OS << "\", \""; 1233 } 1234 OS << "\" };\n\n"; 1235 1236 // Emit the table of sub-register index sizes. 1237 OS << "static const TargetRegisterInfo::SubRegCoveredBits " 1238 "SubRegIdxRangeTable[] = {\n"; 1239 for (unsigned M = 0; M < NumModes; ++M) { 1240 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 1241 for (const auto &Idx : SubRegIndices) { 1242 const SubRegRange &Range = Idx.Range.get(M); 1243 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// " 1244 << Idx.getName() << "\n"; 1245 } 1246 } 1247 OS << "};\n\n"; 1248 1249 // Emit SubRegIndex lane masks, including 0. 1250 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1251 "LaneBitmask::getAll(),\n"; 1252 for (const auto &Idx : SubRegIndices) { 1253 printMask(OS << " ", Idx.LaneMask); 1254 OS << ", // " << Idx.getName() << '\n'; 1255 } 1256 OS << " };\n\n"; 1257 1258 OS << "\n"; 1259 1260 // Now that all of the structs have been emitted, emit the instances. 1261 if (!RegisterClasses.empty()) { 1262 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1263 << " = {\n"; 1264 for (unsigned M = 0; M < NumModes; ++M) { 1265 unsigned EV = 0; 1266 OS << " // Mode = " << M << " ("; 1267 if (M == 0) 1268 OS << "Default"; 1269 else 1270 OS << CGH.getMode(M).Name; 1271 OS << ")\n"; 1272 for (const auto &RC : RegisterClasses) { 1273 assert(RC.EnumValue == EV && "Unexpected order of register classes"); 1274 ++EV; 1275 (void)EV; 1276 const RegSizeInfo &RI = RC.RSI.get(M); 1277 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1278 << RI.SpillAlignment; 1279 std::vector<MVT::SimpleValueType> VTs; 1280 for (const ValueTypeByHwMode &VVT : RC.VTs) 1281 if (VVT.hasDefault() || VVT.hasMode(M)) 1282 VTs.push_back(VVT.get(M).SimpleTy); 1283 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // " 1284 << RC.getName() << '\n'; 1285 } 1286 } 1287 OS << "};\n"; 1288 1289 // Emit register class bit mask tables. The first bit mask emitted for a 1290 // register class, RC, is the set of sub-classes, including RC itself. 1291 // 1292 // If RC has super-registers, also create a list of subreg indices and bit 1293 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1294 // SuperRC, that satisfies: 1295 // 1296 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1297 // 1298 // The 0-terminated list of subreg indices starts at: 1299 // 1300 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1301 // 1302 // The corresponding bitmasks follow the sub-class mask in memory. Each 1303 // mask has RCMaskWords uint32_t entries. 1304 // 1305 // Every bit mask present in the list has at least one bit set. 1306 1307 // Compress the sub-reg index lists. 1308 typedef std::vector<const CodeGenSubRegIndex *> IdxList; 1309 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1310 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1311 BitVector MaskBV(RegisterClasses.size()); 1312 1313 for (const auto &RC : RegisterClasses) { 1314 OS << "static const uint32_t " << RC.getName() 1315 << "SubClassMask[] = {\n "; 1316 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1317 1318 // Emit super-reg class masks for any relevant SubRegIndices that can 1319 // project into RC. 1320 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1321 for (auto &Idx : SubRegIndices) { 1322 MaskBV.reset(); 1323 RC.getSuperRegClasses(&Idx, MaskBV); 1324 if (MaskBV.none()) 1325 continue; 1326 SRIList.push_back(&Idx); 1327 OS << "\n "; 1328 printBitVectorAsHex(OS, MaskBV, 32); 1329 OS << "// " << Idx.getName(); 1330 } 1331 SuperRegIdxSeqs.add(SRIList); 1332 OS << "\n};\n\n"; 1333 } 1334 1335 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1336 SuperRegIdxSeqs.layout(); 1337 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1338 OS << "};\n\n"; 1339 1340 // Emit super-class lists. 1341 for (const auto &RC : RegisterClasses) { 1342 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses(); 1343 1344 // Skip classes without supers. 1345 if (Supers.empty()) 1346 continue; 1347 1348 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n"; 1349 for (const auto *Super : Supers) 1350 OS << " " << Super->getQualifiedIdName() << ",\n"; 1351 OS << "};\n\n"; 1352 } 1353 1354 // Emit methods. 1355 for (const auto &RC : RegisterClasses) { 1356 if (!RC.AltOrderSelect.empty()) { 1357 OS << "\nstatic inline unsigned " << RC.getName() 1358 << "AltOrderSelect(const MachineFunction &MF) {" << RC.AltOrderSelect 1359 << "}\n\n" 1360 << "static ArrayRef<MCPhysReg> " << RC.getName() 1361 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1362 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) { 1363 ArrayRef<const Record *> Elems = RC.getOrder(oi); 1364 if (!Elems.empty()) { 1365 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1366 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1367 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1368 OS << " };\n"; 1369 } 1370 } 1371 OS << " const MCRegisterClass &MCR = " << Target.getName() 1372 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1373 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1374 << " ArrayRef(MCR.begin(), MCR.getNumRegs()"; 1375 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1376 if (RC.getOrder(oi).empty()) 1377 OS << "),\n ArrayRef<MCPhysReg>("; 1378 else 1379 OS << "),\n ArrayRef(AltOrder" << oi; 1380 OS << ")\n };\n const unsigned Select = " << RC.getName() 1381 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1382 << ");\n return Order[Select];\n}\n"; 1383 } 1384 } 1385 1386 // Now emit the actual value-initialized register class instances. 1387 OS << "\nnamespace " << RegisterClasses.front().Namespace 1388 << " { // Register class instances\n"; 1389 1390 for (const auto &RC : RegisterClasses) { 1391 OS << " extern const TargetRegisterClass " << RC.getName() 1392 << "RegClass = {\n " << '&' << Target.getName() 1393 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1394 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1395 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1396 printMask(OS, RC.LaneMask); 1397 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1398 << (RC.GlobalPriority ? "true" : "false") << ",\n " 1399 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n " 1400 << (RC.HasDisjunctSubRegs ? "true" : "false") 1401 << ", /* HasDisjunctSubRegs */\n " 1402 << (RC.CoveredBySubRegs ? "true" : "false") 1403 << ", /* CoveredBySubRegs */\n "; 1404 if (RC.getSuperClasses().empty()) 1405 OS << "nullptr, "; 1406 else 1407 OS << RC.getName() << "Superclasses, "; 1408 OS << RC.getSuperClasses().size() << ",\n "; 1409 if (RC.AltOrderSelect.empty()) 1410 OS << "nullptr\n"; 1411 else 1412 OS << RC.getName() << "GetRawAllocationOrder\n"; 1413 OS << " };\n\n"; 1414 } 1415 1416 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1417 } 1418 1419 OS << "\nnamespace {\n"; 1420 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; 1421 for (const auto &RC : RegisterClasses) 1422 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1423 OS << " };\n"; 1424 OS << "} // end anonymous namespace\n"; 1425 1426 // Emit extra information about registers. 1427 const std::string &TargetName = std::string(Target.getName()); 1428 const auto &Regs = RegBank.getRegisters(); 1429 unsigned NumRegCosts = 1; 1430 for (const auto &Reg : Regs) 1431 NumRegCosts = std::max((size_t)NumRegCosts, Reg.CostPerUse.size()); 1432 1433 std::vector<unsigned> AllRegCostPerUse; 1434 llvm::BitVector InAllocClass(Regs.size() + 1, false); 1435 AllRegCostPerUse.insert(AllRegCostPerUse.end(), NumRegCosts, 0); 1436 1437 // Populate the vector RegCosts with the CostPerUse list of the registers 1438 // in the order they are read. Have at most NumRegCosts entries for 1439 // each register. Fill with zero for values which are not explicitly given. 1440 for (const auto &Reg : Regs) { 1441 auto Costs = Reg.CostPerUse; 1442 AllRegCostPerUse.insert(AllRegCostPerUse.end(), Costs.begin(), Costs.end()); 1443 if (NumRegCosts > Costs.size()) 1444 AllRegCostPerUse.insert(AllRegCostPerUse.end(), 1445 NumRegCosts - Costs.size(), 0); 1446 1447 if (AllocatableRegs.count(Reg.TheDef)) 1448 InAllocClass.set(Reg.EnumValue); 1449 } 1450 1451 // Emit the cost values as a 1D-array after grouping them by their indices, 1452 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc. 1453 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1). 1454 OS << "\nstatic const uint8_t " 1455 << "CostPerUseTable[] = { \n"; 1456 for (unsigned int I = 0; I < NumRegCosts; ++I) { 1457 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts) 1458 OS << AllRegCostPerUse[J] << ", "; 1459 } 1460 OS << "};\n\n"; 1461 1462 OS << "\nstatic const bool " 1463 << "InAllocatableClassTable[] = { \n"; 1464 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) { 1465 OS << (InAllocClass[I] ? "true" : "false") << ", "; 1466 } 1467 OS << "};\n\n"; 1468 1469 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName 1470 << "RegInfoDesc = { // Extra Descriptors\n"; 1471 OS << "CostPerUseTable, " << NumRegCosts << ", " 1472 << "InAllocatableClassTable"; 1473 OS << "};\n\n"; // End of register descriptors... 1474 1475 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1476 1477 auto SubRegIndicesSize = 1478 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1479 1480 if (!SubRegIndices.empty()) { 1481 emitComposeSubRegIndices(OS, ClassName); 1482 emitComposeSubRegIndexLaneMask(OS, ClassName); 1483 } 1484 1485 if (!SubRegIndices.empty()) { 1486 // Emit getSubClassWithSubReg. 1487 OS << "const TargetRegisterClass *" << ClassName 1488 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1489 << " const {\n"; 1490 // Use the smallest type that can hold a regclass ID with room for a 1491 // sentinel. 1492 if (RegisterClasses.size() <= UINT8_MAX) 1493 OS << " static const uint8_t Table["; 1494 else if (RegisterClasses.size() <= UINT16_MAX) 1495 OS << " static const uint16_t Table["; 1496 else 1497 PrintFatalError("Too many register classes."); 1498 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1499 for (const auto &RC : RegisterClasses) { 1500 OS << " {\t// " << RC.getName() << "\n"; 1501 for (auto &Idx : SubRegIndices) { 1502 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1503 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1504 << " -> " << SRC->getName() << "\n"; 1505 else 1506 OS << " 0,\t// " << Idx.getName() << "\n"; 1507 } 1508 OS << " },\n"; 1509 } 1510 OS << " };\n assert(RC && \"Missing regclass\");\n" 1511 << " if (!Idx) return RC;\n --Idx;\n" 1512 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1513 << " unsigned TV = Table[RC->getID()][Idx];\n" 1514 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1515 1516 // Emit getSubRegisterClass 1517 OS << "const TargetRegisterClass *" << ClassName 1518 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)" 1519 << " const {\n"; 1520 1521 // Use the smallest type that can hold a regclass ID with room for a 1522 // sentinel. 1523 if (RegisterClasses.size() <= UINT8_MAX) 1524 OS << " static const uint8_t Table["; 1525 else if (RegisterClasses.size() <= UINT16_MAX) 1526 OS << " static const uint16_t Table["; 1527 else 1528 PrintFatalError("Too many register classes."); 1529 1530 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1531 1532 for (const auto &RC : RegisterClasses) { 1533 OS << " {\t// " << RC.getName() << '\n'; 1534 for (auto &Idx : SubRegIndices) { 1535 std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> 1536 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx); 1537 1538 unsigned EnumValue = 0; 1539 if (MatchingSubClass) { 1540 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; 1541 EnumValue = SubRegClass->EnumValue + 1; 1542 } 1543 1544 OS << " " << EnumValue << ",\t// " << RC.getName() << ':' 1545 << Idx.getName(); 1546 1547 if (MatchingSubClass) { 1548 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; 1549 OS << " -> " << SubRegClass->getName(); 1550 } 1551 1552 OS << '\n'; 1553 } 1554 1555 OS << " },\n"; 1556 } 1557 OS << " };\n assert(RC && \"Missing regclass\");\n" 1558 << " if (!Idx) return RC;\n --Idx;\n" 1559 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1560 << " unsigned TV = Table[RC->getID()][Idx];\n" 1561 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1562 } 1563 1564 EmitRegUnitPressure(OS, ClassName); 1565 1566 // Emit register base class mapper 1567 if (!RegisterClasses.empty()) { 1568 // Collect base classes 1569 SmallVector<const CodeGenRegisterClass *> BaseClasses; 1570 for (const auto &RC : RegisterClasses) { 1571 if (RC.getBaseClassOrder()) 1572 BaseClasses.push_back(&RC); 1573 } 1574 if (!BaseClasses.empty()) { 1575 assert(BaseClasses.size() < UINT16_MAX && 1576 "Too many base register classes"); 1577 1578 // Apply order 1579 struct BaseClassOrdering { 1580 bool operator()(const CodeGenRegisterClass *LHS, 1581 const CodeGenRegisterClass *RHS) const { 1582 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) < 1583 std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue); 1584 } 1585 }; 1586 llvm::stable_sort(BaseClasses, BaseClassOrdering()); 1587 1588 OS << "\n// Register to base register class mapping\n\n"; 1589 OS << "\n"; 1590 OS << "const TargetRegisterClass *" << ClassName 1591 << "::getPhysRegBaseClass(MCRegister Reg)" 1592 << " const {\n"; 1593 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n"; 1594 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n"; 1595 OS << " InvalidRegClassID, // NoRegister\n"; 1596 for (const CodeGenRegister &Reg : Regs) { 1597 const CodeGenRegisterClass *BaseRC = nullptr; 1598 for (const CodeGenRegisterClass *RC : BaseClasses) { 1599 if (is_contained(RC->getMembers(), &Reg)) { 1600 BaseRC = RC; 1601 break; 1602 } 1603 } 1604 1605 OS << " " 1606 << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID") 1607 << ", // " << Reg.getName() << "\n"; 1608 } 1609 OS << " };\n\n" 1610 " assert(Reg < ArrayRef(Mapping).size());\n" 1611 " unsigned RCID = Mapping[Reg.id()];\n" 1612 " if (RCID == InvalidRegClassID)\n" 1613 " return nullptr;\n" 1614 " return RegisterClasses[RCID];\n" 1615 "}\n"; 1616 } 1617 } 1618 1619 // Emit the constructor of the class... 1620 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1621 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n"; 1622 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1623 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1624 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1625 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1626 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1627 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1628 1629 EmitRegMappingTables(OS, Regs, true); 1630 1631 OS << ClassName << "::\n" 1632 << ClassName 1633 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1634 " unsigned PC, unsigned HwMode)\n" 1635 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc" 1636 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1637 << " SubRegIndexNameTable, SubRegIdxRangeTable, " 1638 "SubRegIndexLaneMaskTable,\n" 1639 << " "; 1640 printMask(OS, RegBank.CoveringLanes); 1641 OS << ", RegClassInfos, VTLists, HwMode) {\n" 1642 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1643 << ", RA, PC,\n " << TargetName 1644 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1645 << " " << TargetName << "RegUnitRoots,\n" 1646 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1647 << " " << TargetName << "RegDiffLists,\n" 1648 << " " << TargetName << "LaneMaskLists,\n" 1649 << " " << TargetName << "RegStrings,\n" 1650 << " " << TargetName << "RegClassStrings,\n" 1651 << " " << TargetName << "SubRegIdxLists,\n" 1652 << " " << SubRegIndicesSize + 1 << ",\n" 1653 << " " << TargetName << "RegEncodingTable);\n\n"; 1654 1655 EmitRegMapping(OS, Regs, true); 1656 1657 OS << "}\n\n"; 1658 1659 // Emit CalleeSavedRegs information. 1660 ArrayRef<const Record *> CSRSets = 1661 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1662 for (const Record *CSRSet : CSRSets) { 1663 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1664 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1665 1666 // Emit the *_SaveList list of callee-saved registers. 1667 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; 1668 for (const Record *Reg : *Regs) 1669 OS << getQualifiedName(Reg) << ", "; 1670 OS << "0 };\n"; 1671 1672 // Emit the *_RegMask bit mask of call-preserved registers. 1673 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1674 1675 // Check for an optional OtherPreserved set. 1676 // Add those registers to RegMask, but not to SaveList. 1677 if (const DagInit *OPDag = 1678 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1679 SetTheory::RecSet OPSet; 1680 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1681 Covered |= RegBank.computeCoveredRegisters(OPSet.getArrayRef()); 1682 } 1683 1684 // Add all constant physical registers to the preserved mask: 1685 SetTheory::RecSet ConstantSet; 1686 for (const auto &Reg : RegBank.getRegisters()) { 1687 if (Reg.Constant) 1688 ConstantSet.insert(Reg.TheDef); 1689 } 1690 Covered |= RegBank.computeCoveredRegisters(ConstantSet.getArrayRef()); 1691 1692 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; 1693 printBitVectorAsHex(OS, Covered, 32); 1694 OS << "};\n"; 1695 } 1696 OS << "\n\n"; 1697 1698 OS << "ArrayRef<const uint32_t *> " << ClassName 1699 << "::getRegMasks() const {\n"; 1700 if (!CSRSets.empty()) { 1701 OS << " static const uint32_t *const Masks[] = {\n"; 1702 for (const Record *CSRSet : CSRSets) 1703 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1704 OS << " };\n"; 1705 OS << " return ArrayRef(Masks);\n"; 1706 } else { 1707 OS << " return {};\n"; 1708 } 1709 OS << "}\n\n"; 1710 1711 const std::list<CodeGenRegisterCategory> &RegCategories = 1712 RegBank.getRegCategories(); 1713 OS << "bool " << ClassName << "::\n" 1714 << "isGeneralPurposeRegister(const MachineFunction &MF, " 1715 << "MCRegister PhysReg) const {\n" 1716 << " return\n"; 1717 for (const CodeGenRegisterCategory &Category : RegCategories) 1718 if (Category.getName() == "GeneralPurposeRegisters") { 1719 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1720 OS << " " << RC->getQualifiedName() 1721 << "RegClass.contains(PhysReg) ||\n"; 1722 break; 1723 } 1724 OS << " false;\n"; 1725 OS << "}\n\n"; 1726 1727 OS << "bool " << ClassName << "::\n" 1728 << "isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)" 1729 << " const {\n" 1730 << " return\n"; 1731 for (const CodeGenRegisterCategory &Category : RegCategories) 1732 if (Category.getName() == "GeneralPurposeRegisters") { 1733 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1734 OS << " " << RC->getQualifiedName() 1735 << "RegClass.hasSubClassEq(RC) ||\n"; 1736 break; 1737 } 1738 OS << " false;\n"; 1739 OS << "}\n\n"; 1740 1741 OS << "bool " << ClassName << "::\n" 1742 << "isFixedRegister(const MachineFunction &MF, " 1743 << "MCRegister PhysReg) const {\n" 1744 << " return\n"; 1745 for (const CodeGenRegisterCategory &Category : RegCategories) 1746 if (Category.getName() == "FixedRegisters") { 1747 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1748 OS << " " << RC->getQualifiedName() 1749 << "RegClass.contains(PhysReg) ||\n"; 1750 break; 1751 } 1752 OS << " false;\n"; 1753 OS << "}\n\n"; 1754 1755 OS << "bool " << ClassName << "::\n" 1756 << "isArgumentRegister(const MachineFunction &MF, " 1757 << "MCRegister PhysReg) const {\n" 1758 << " return\n"; 1759 for (const CodeGenRegisterCategory &Category : RegCategories) 1760 if (Category.getName() == "ArgumentRegisters") { 1761 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1762 OS << " " << RC->getQualifiedName() 1763 << "RegClass.contains(PhysReg) ||\n"; 1764 break; 1765 } 1766 OS << " false;\n"; 1767 OS << "}\n\n"; 1768 1769 OS << "bool " << ClassName << "::\n" 1770 << "isConstantPhysReg(MCRegister PhysReg) const {\n" 1771 << " return\n"; 1772 for (const auto &Reg : Regs) 1773 if (Reg.Constant) 1774 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n"; 1775 OS << " false;\n"; 1776 OS << "}\n\n"; 1777 1778 OS << "ArrayRef<const char *> " << ClassName 1779 << "::getRegMaskNames() const {\n"; 1780 if (!CSRSets.empty()) { 1781 OS << " static const char *Names[] = {\n"; 1782 for (const Record *CSRSet : CSRSets) 1783 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1784 OS << " };\n"; 1785 OS << " return ArrayRef(Names);\n"; 1786 } else { 1787 OS << " return {};\n"; 1788 } 1789 OS << "}\n\n"; 1790 1791 OS << "const " << TargetName << "FrameLowering *\n" 1792 << TargetName 1793 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1794 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1795 << " MF.getSubtarget().getFrameLowering());\n" 1796 << "}\n\n"; 1797 1798 OS << "} // end namespace llvm\n\n"; 1799 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1800 } 1801 1802 void RegisterInfoEmitter::run(raw_ostream &OS) { 1803 TGTimer &Timer = Records.getTimer(); 1804 Timer.startTimer("Print enums"); 1805 runEnums(OS); 1806 1807 Timer.startTimer("Print MC registers"); 1808 runMCDesc(OS); 1809 1810 Timer.startTimer("Print header fragment"); 1811 runTargetHeader(OS); 1812 1813 Timer.startTimer("Print target registers"); 1814 runTargetDesc(OS); 1815 1816 if (RegisterInfoDebug) 1817 debugDump(errs()); 1818 } 1819 1820 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1821 const CodeGenHwModes &CGH = Target.getHwModes(); 1822 unsigned NumModes = CGH.getNumModeIds(); 1823 auto getModeName = [CGH](unsigned M) -> StringRef { 1824 if (M == 0) 1825 return "Default"; 1826 return CGH.getMode(M).Name; 1827 }; 1828 1829 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1830 OS << "RegisterClass " << RC.getName() << ":\n"; 1831 OS << "\tSpillSize: {"; 1832 for (unsigned M = 0; M != NumModes; ++M) 1833 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1834 OS << " }\n\tSpillAlignment: {"; 1835 for (unsigned M = 0; M != NumModes; ++M) 1836 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1837 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1838 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1839 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1840 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1841 OS << "\tAllocatable: " << RC.Allocatable << '\n'; 1842 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; 1843 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n'; 1844 OS << "\tRegs:"; 1845 for (const CodeGenRegister *R : RC.getMembers()) { 1846 OS << " " << R->getName(); 1847 } 1848 OS << '\n'; 1849 OS << "\tSubClasses:"; 1850 const BitVector &SubClasses = RC.getSubClasses(); 1851 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1852 if (!SubClasses.test(SRC.EnumValue)) 1853 continue; 1854 OS << " " << SRC.getName(); 1855 } 1856 OS << '\n'; 1857 OS << "\tSuperClasses:"; 1858 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1859 OS << " " << SRC->getName(); 1860 } 1861 OS << '\n'; 1862 } 1863 1864 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1865 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1866 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1867 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1868 OS << "\tOffset: {"; 1869 for (unsigned M = 0; M != NumModes; ++M) 1870 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset; 1871 OS << " }\n\tSize: {"; 1872 for (unsigned M = 0; M != NumModes; ++M) 1873 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size; 1874 OS << " }\n"; 1875 } 1876 1877 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1878 OS << "Register " << R.getName() << ":\n"; 1879 OS << "\tCostPerUse: "; 1880 for (const auto &Cost : R.CostPerUse) 1881 OS << Cost << " "; 1882 OS << '\n'; 1883 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1884 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1885 for (auto &[SubIdx, SubReg] : R.getSubRegs()) { 1886 OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName() 1887 << '\n'; 1888 } 1889 } 1890 } 1891 1892 static TableGen::Emitter::OptClass<RegisterInfoEmitter> 1893 X("gen-register-info", "Generate registers and register classes info"); 1894