1 //===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "../Common/AssemblerUtils.h"
10 #include "LlvmState.h"
11 #include "MCInstrDescView.h"
12 #include "PPCInstrInfo.h"
13 #include "ParallelSnippetGenerator.h"
14 #include "RegisterAliasing.h"
15 #include "SerialSnippetGenerator.h"
16 #include "TestBase.h"
17
18 namespace llvm {
19 namespace exegesis {
20 namespace {
21
22 using testing::AnyOf;
23 using testing::ElementsAre;
24 using testing::HasSubstr;
25 using testing::SizeIs;
26
27 MATCHER(IsInvalid, "") { return !arg.isValid(); }
28 MATCHER(IsReg, "") { return arg.isReg(); }
29
30 template <typename SnippetGeneratorT>
31 class PPCSnippetGeneratorTest : public PPCTestBase {
32 protected:
PPCSnippetGeneratorTest()33 PPCSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
34
checkAndGetCodeTemplates(unsigned Opcode)35 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
36 randomGenerator().seed(0); // Initialize seed.
37 const Instruction &Instr = State.getIC().getInstr(Opcode);
38 auto CodeTemplateOrError = Generator.generateCodeTemplates(
39 &Instr, State.getRATC().emptyRegisters());
40 EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
41 return std::move(CodeTemplateOrError.get());
42 }
43
44 SnippetGeneratorT Generator;
45 };
46
47 using PPCSerialSnippetGeneratorTest = PPCSnippetGeneratorTest<SerialSnippetGenerator>;
48
49 using PPCParallelSnippetGeneratorTest =
50 PPCSnippetGeneratorTest<ParallelSnippetGenerator>;
51
TEST_F(PPCSerialSnippetGeneratorTest,ImplicitSelfDependencyThroughExplicitRegs)52 TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
53 // - ADD8
54 // - Op0 Explicit Def RegClass(G8RC)
55 // - Op1 Explicit Use RegClass(G8RC)
56 // - Op2 Explicit Use RegClass(G8RC)
57 // - Var0 [Op0]
58 // - Var1 [Op1]
59 // - Var2 [Op2]
60 // - hasAliasingRegisters
61 const unsigned Opcode = PPC::ADD8;
62 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
63 ASSERT_THAT(CodeTemplates, SizeIs(1));
64 const auto &CT = CodeTemplates[0];
65 EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
66 ASSERT_THAT(CT.Instructions, SizeIs(1));
67 const InstructionTemplate &IT = CT.Instructions[0];
68 EXPECT_THAT(IT.getOpcode(), Opcode);
69 ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
70 EXPECT_THAT(IT.getVariableValues(),
71 AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
72 ElementsAre(IsReg(), IsReg(), IsInvalid())))
73 << "Op0 is either set to Op1 or to Op2";
74 }
75
TEST_F(PPCSerialSnippetGeneratorTest,ImplicitSelfDependencyThroughTiedRegs)76 TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
77
78 // - RLDIMI
79 // - Op0 Explicit Def RegClass(G8RC)
80 // - Op1 Explicit Use RegClass(G8RC) TiedToOp0
81 // - Op2 Explicit Use RegClass(G8RC)
82 // - Op3 Explicit Use Immediate
83 // - Op4 Explicit Use Immediate
84 // - Var0 [Op0,Op1]
85 // - Var1 [Op2]
86 // - Var2 [Op3]
87 // - Var3 [Op4]
88 // - hasTiedRegisters (execution is always serial)
89 // - hasAliasingRegisters
90 // - RLDIMI
91 const unsigned Opcode = PPC::RLDIMI;
92 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
93 ASSERT_THAT(CodeTemplates, SizeIs(1));
94 const auto &CT = CodeTemplates[0];
95 EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
96 ASSERT_THAT(CT.Instructions, SizeIs(1));
97 const InstructionTemplate &IT = CT.Instructions[0];
98 EXPECT_THAT(IT.getOpcode(), Opcode);
99 ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
100 EXPECT_THAT(IT.getVariableValues()[2], IsInvalid()) << "Operand 1 is not set";
101 EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set";
102 }
103
TEST_F(PPCParallelSnippetGeneratorTest,MemoryUse)104 TEST_F(PPCParallelSnippetGeneratorTest, MemoryUse) {
105 // - LDX
106 // - Op0 Explicit Def RegClass(G8RC)
107 // - Op1 Explicit Use Memory RegClass(GPRC)
108 // - Op2 Explicit Use Memory RegClass(VSSRC)
109 // - Var0 [Op0]
110 // - Var1 [Op1]
111 // - Var2 [Op2]
112 // - hasMemoryOperands
113 // - hasAliasingRegisters
114 const unsigned Opcode = PPC::LDX;
115 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
116 ASSERT_THAT(CodeTemplates, SizeIs(1));
117 for (const auto &CT : CodeTemplates) {
118 EXPECT_THAT(CT.Info, HasSubstr("instruction has no tied variables"));
119 EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
120 ASSERT_THAT(CT.Instructions,
121 SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
122 const InstructionTemplate &IT = CT.Instructions[0];
123 EXPECT_THAT(IT.getOpcode(), Opcode);
124 ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
125 EXPECT_EQ(IT.getVariableValues()[1].getReg(), PPC::X1);
126 EXPECT_EQ(IT.getVariableValues()[2].getReg(), PPC::X13);
127 }
128 }
129
130 } // namespace
131 } // namespace exegesis
132 } // namespace llvm
133