1 //===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "AMDGPUTargetMachine.h" 10 #include "AMDGPUUnitTests.h" 11 #include "gtest/gtest.h" 12 13 using namespace llvm; 14 15 TEST(AMDGPU, TestWave64DwarfRegMapping) { 16 for (auto Triple : 17 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) { 18 auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize64"); 19 if (TM) { 20 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), 21 std::string(TM->getTargetFeatureString()), *TM); 22 auto MRI = ST.getRegisterInfo(); 23 if (MRI) { 24 // Wave64 Dwarf register mapping test numbers 25 // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95, 26 // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815, 27 // A0 => 3072, A255 => 3327 28 for (int DwarfEncoding : 29 {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) { 30 MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false); 31 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false)); 32 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true)); 33 } 34 35 // We should get the correct LLVM register when round tripping through 36 // the dwarf encoding. 37 for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) { 38 int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false); 39 EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false)); 40 } 41 42 // Verify that subregisters have no dwarf encoding. 43 for (MCRegister LLSubReg : 44 {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) { 45 EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1); 46 } 47 } 48 } 49 } 50 } 51 52 TEST(AMDGPU, TestWave32DwarfRegMapping) { 53 for (auto Triple : 54 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) { 55 auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize32"); 56 if (TM) { 57 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), 58 std::string(TM->getTargetFeatureString()), *TM); 59 auto MRI = ST.getRegisterInfo(); 60 if (MRI) { 61 // Wave32 Dwarf register mapping test numbers 62 // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95, 63 // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791, 64 // A0 => 2048, A255 => 2303 65 for (int DwarfEncoding : 66 {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) { 67 MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false); 68 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false)); 69 EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true)); 70 } 71 72 // We should get the correct LLVM register when round tripping through 73 // the dwarf encoding. 74 for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) { 75 int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false); 76 EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false)); 77 } 78 79 // Verify that subregisters have no dwarf encoding. 80 for (MCRegister LLSubReg : 81 {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) { 82 EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1); 83 } 84 } 85 } 86 } 87 } 88