1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=3 --noalias=true < %s | FileCheck %s 3 4str x1, [x10] 5str x1, [x10] 6ldr x2, [x10] 7nop 8ldr x2, [x10] 9ldr x3, [x10] 10 11# CHECK: Iterations: 3 12# CHECK-NEXT: Instructions: 18 13# CHECK-NEXT: Total Cycles: 16 14# CHECK-NEXT: Total uOps: 18 15 16# CHECK: Dispatch Width: 2 17# CHECK-NEXT: uOps Per Cycle: 1.13 18# CHECK-NEXT: IPC: 1.13 19# CHECK-NEXT: Block RThroughput: 3.0 20 21# CHECK: Instruction Info: 22# CHECK-NEXT: [1]: #uOps 23# CHECK-NEXT: [2]: Latency 24# CHECK-NEXT: [3]: RThroughput 25# CHECK-NEXT: [4]: MayLoad 26# CHECK-NEXT: [5]: MayStore 27# CHECK-NEXT: [6]: HasSideEffects (U) 28 29# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 30# CHECK-NEXT: 1 1 1.00 * str x1, [x10] 31# CHECK-NEXT: 1 1 1.00 * str x1, [x10] 32# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10] 33# CHECK-NEXT: 1 1 1.00 * * U nop 34# CHECK-NEXT: 1 3 1.00 * ldr x2, [x10] 35# CHECK-NEXT: 1 3 1.00 * ldr x3, [x10] 36 37# CHECK: Resources: 38# CHECK-NEXT: [0.0] - CortexA55UnitALU 39# CHECK-NEXT: [0.1] - CortexA55UnitALU 40# CHECK-NEXT: [1] - CortexA55UnitB 41# CHECK-NEXT: [2] - CortexA55UnitDiv 42# CHECK-NEXT: [3.0] - CortexA55UnitFPALU 43# CHECK-NEXT: [3.1] - CortexA55UnitFPALU 44# CHECK-NEXT: [4] - CortexA55UnitFPDIV 45# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC 46# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC 47# CHECK-NEXT: [6] - CortexA55UnitLd 48# CHECK-NEXT: [7] - CortexA55UnitMAC 49# CHECK-NEXT: [8] - CortexA55UnitSt 50 51# CHECK: Resource pressure per iteration: 52# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] 53# CHECK-NEXT: - - 1.00 - - - - - - 3.00 - 2.00 54 55# CHECK: Resource pressure by instruction: 56# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions: 57# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10] 58# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x10] 59# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10] 60# CHECK-NEXT: - - 1.00 - - - - - - - - - nop 61# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x10] 62# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10] 63 64# CHECK: Timeline view: 65# CHECK-NEXT: 012345 66# CHECK-NEXT: Index 0123456789 67 68# CHECK: [0,0] DE . . . str x1, [x10] 69# CHECK-NEXT: [0,1] .DE . . . str x1, [x10] 70# CHECK-NEXT: [0,2] .DeeE. . . ldr x2, [x10] 71# CHECK-NEXT: [0,3] . DE. . . nop 72# CHECK-NEXT: [0,4] . DeeE . . ldr x2, [x10] 73# CHECK-NEXT: [0,5] . DeeE . . ldr x3, [x10] 74# CHECK-NEXT: [1,0] . DE . . str x1, [x10] 75# CHECK-NEXT: [1,1] . DE . . str x1, [x10] 76# CHECK-NEXT: [1,2] . DeeE . . ldr x2, [x10] 77# CHECK-NEXT: [1,3] . . DE . . nop 78# CHECK-NEXT: [1,4] . . DeeE . ldr x2, [x10] 79# CHECK-NEXT: [1,5] . . DeeE . ldr x3, [x10] 80# CHECK-NEXT: [2,0] . . DE. . str x1, [x10] 81# CHECK-NEXT: [2,1] . . DE . str x1, [x10] 82# CHECK-NEXT: [2,2] . . DeeE . ldr x2, [x10] 83# CHECK-NEXT: [2,3] . . .DE . nop 84# CHECK-NEXT: [2,4] . . .DeeE. ldr x2, [x10] 85# CHECK-NEXT: [2,5] . . . DeeE ldr x3, [x10] 86 87# CHECK: Average Wait times (based on the timeline view): 88# CHECK-NEXT: [0]: Executions 89# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 90# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 91# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 92 93# CHECK: [0] [1] [2] [3] 94# CHECK-NEXT: 0. 3 0.0 0.0 0.0 str x1, [x10] 95# CHECK-NEXT: 1. 3 0.0 0.0 0.0 str x1, [x10] 96# CHECK-NEXT: 2. 3 0.0 0.0 0.0 ldr x2, [x10] 97# CHECK-NEXT: 3. 3 0.0 0.0 0.0 nop 98# CHECK-NEXT: 4. 3 0.0 0.0 0.0 ldr x2, [x10] 99# CHECK-NEXT: 5. 3 0.0 0.0 0.0 ldr x3, [x10] 100# CHECK-NEXT: 3 0.0 0.0 0.0 <total> 101