xref: /llvm-project/llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll (revision 035e64c0ec02b237a266ebc672718037fdd53eb2) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=CHECK,SSE
3; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE
4; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX2
5; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX512
6
7define i32 @movmsk_i32_v32i8_v16i8(<16 x i8> %v0, <16 x i8> %v1) {
8; CHECK-LABEL: @movmsk_i32_v32i8_v16i8(
9; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> [[V0:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
10; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <32 x i8> [[TMP1]], zeroinitializer
11; CHECK-NEXT:    [[OR:%.*]] = bitcast <32 x i1> [[TMP2]] to i32
12; CHECK-NEXT:    ret i32 [[OR]]
13;
14  %c0 = icmp slt <16 x i8> %v0, zeroinitializer
15  %c1 = icmp slt <16 x i8> %v1, zeroinitializer
16  %b0 = bitcast <16 x i1> %c0 to i16
17  %b1 = bitcast <16 x i1> %c1 to i16
18  %z0 = zext i16 %b0 to i32
19  %z1 = zext i16 %b1 to i32
20  %s0 = shl nuw i32 %z0, 16
21  %or = or disjoint i32 %s0, %z1
22  ret i32 %or
23}
24
25define i32 @movmsk_i32_v8i32_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
26; CHECK-LABEL: @movmsk_i32_v8i32_v4i32(
27; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
28; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <8 x i32> [[TMP1]], zeroinitializer
29; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i1> [[TMP2]] to i8
30; CHECK-NEXT:    [[OR:%.*]] = zext i8 [[TMP3]] to i32
31; CHECK-NEXT:    ret i32 [[OR]]
32;
33  %c0 = icmp slt <4 x i32> %v0, zeroinitializer
34  %c1 = icmp slt <4 x i32> %v1, zeroinitializer
35  %b0 = bitcast <4 x i1> %c0 to i4
36  %b1 = bitcast <4 x i1> %c1 to i4
37  %z0 = zext i4 %b0 to i32
38  %z1 = zext i4 %b1 to i32
39  %s0 = shl nuw i32 %z0, 4
40  %or = or disjoint i32 %s0, %z1
41  ret i32 %or
42}
43
44define i64 @movmsk_i64_v32i8_v16i8(<16 x i8> %v0, <16 x i8> %v1) {
45; CHECK-LABEL: @movmsk_i64_v32i8_v16i8(
46; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> [[V0:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
47; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <32 x i8> [[TMP1]], zeroinitializer
48; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <32 x i1> [[TMP2]] to i32
49; CHECK-NEXT:    [[OR:%.*]] = zext i32 [[TMP3]] to i64
50; CHECK-NEXT:    ret i64 [[OR]]
51;
52  %c0 = icmp slt <16 x i8> %v0, zeroinitializer
53  %c1 = icmp slt <16 x i8> %v1, zeroinitializer
54  %b0 = bitcast <16 x i1> %c0 to i16
55  %b1 = bitcast <16 x i1> %c1 to i16
56  %z0 = zext i16 %b0 to i64
57  %z1 = zext i16 %b1 to i64
58  %s0 = shl nuw i64 %z0, 16
59  %or = or disjoint i64 %s0, %z1
60  ret i64 %or
61}
62
63define i64 @movmsk_i64_v8i32_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
64; CHECK-LABEL: @movmsk_i64_v8i32_v4i32(
65; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
66; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <8 x i32> [[TMP1]], zeroinitializer
67; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i1> [[TMP2]] to i8
68; CHECK-NEXT:    [[OR:%.*]] = zext i8 [[TMP3]] to i64
69; CHECK-NEXT:    ret i64 [[OR]]
70;
71  %c0 = icmp slt <4 x i32> %v0, zeroinitializer
72  %c1 = icmp slt <4 x i32> %v1, zeroinitializer
73  %b0 = bitcast <4 x i1> %c0 to i4
74  %b1 = bitcast <4 x i1> %c1 to i4
75  %z0 = zext i4 %b0 to i64
76  %z1 = zext i4 %b1 to i64
77  %s0 = shl nuw i64 %z0, 4
78  %or = or disjoint i64 %s0, %z1
79  ret i64 %or
80}
81
82define i64 @movmsk_i64_v64i8_v16i8(<16 x i8> %v0, <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
83; SSE-LABEL: @movmsk_i64_v64i8_v16i8(
84; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[V3:%.*]], <16 x i8> [[V2:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
85; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> [[V0:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
86; SSE-NEXT:    [[TMP3:%.*]] = shufflevector <32 x i8> [[TMP1]], <32 x i8> [[TMP2]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
87; SSE-NEXT:    [[TMP4:%.*]] = icmp slt <64 x i8> [[TMP3]], zeroinitializer
88; SSE-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP4]] to i64
89; SSE-NEXT:    ret i64 [[OR]]
90;
91; AVX2-LABEL: @movmsk_i64_v64i8_v16i8(
92; AVX2-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> [[V0:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
93; AVX2-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[V3:%.*]], <16 x i8> [[V2:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
94; AVX2-NEXT:    [[TMP3:%.*]] = shufflevector <32 x i8> [[TMP2]], <32 x i8> [[TMP1]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
95; AVX2-NEXT:    [[TMP4:%.*]] = icmp slt <64 x i8> [[TMP3]], zeroinitializer
96; AVX2-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP4]] to i64
97; AVX2-NEXT:    ret i64 [[OR]]
98;
99; AVX512-LABEL: @movmsk_i64_v64i8_v16i8(
100; AVX512-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> [[V0:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
101; AVX512-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[V3:%.*]], <16 x i8> [[V2:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
102; AVX512-NEXT:    [[TMP3:%.*]] = shufflevector <32 x i8> [[TMP2]], <32 x i8> [[TMP1]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
103; AVX512-NEXT:    [[TMP4:%.*]] = icmp slt <64 x i8> [[TMP3]], zeroinitializer
104; AVX512-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP4]] to i64
105; AVX512-NEXT:    ret i64 [[OR]]
106;
107  %c0 = icmp slt <16 x i8> %v0, zeroinitializer
108  %c1 = icmp slt <16 x i8> %v1, zeroinitializer
109  %c2 = icmp slt <16 x i8> %v2, zeroinitializer
110  %c3 = icmp slt <16 x i8> %v3, zeroinitializer
111  %b0 = bitcast <16 x i1> %c0 to i16
112  %b1 = bitcast <16 x i1> %c1 to i16
113  %b2 = bitcast <16 x i1> %c2 to i16
114  %b3 = bitcast <16 x i1> %c3 to i16
115  %z0 = zext i16 %b0 to i64
116  %z1 = zext i16 %b1 to i64
117  %z2 = zext i16 %b2 to i64
118  %z3 = zext i16 %b3 to i64
119  %s0 = shl nuw i64 %z0, 48
120  %s1 = shl nuw i64 %z1, 32
121  %s2 = shl nuw i64 %z2, 16
122  %or0 = or disjoint i64 %s0, %s1
123  %or1 = or disjoint i64 %s2, %z3
124  %or = or disjoint i64 %or0, %or1
125  ret i64 %or
126}
127
128define i64 @movmsk_i64_v32i32_v4i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
129; SSE-LABEL: @movmsk_i64_v32i32_v4i32(
130; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V3:%.*]], <4 x i32> [[V2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
131; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
132; SSE-NEXT:    [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
133; SSE-NEXT:    [[TMP4:%.*]] = icmp slt <16 x i32> [[TMP3]], zeroinitializer
134; SSE-NEXT:    [[TMP5:%.*]] = bitcast <16 x i1> [[TMP4]] to i16
135; SSE-NEXT:    [[OR:%.*]] = zext i16 [[TMP5]] to i64
136; SSE-NEXT:    ret i64 [[OR]]
137;
138; AVX2-LABEL: @movmsk_i64_v32i32_v4i32(
139; AVX2-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
140; AVX2-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V3:%.*]], <4 x i32> [[V2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
141; AVX2-NEXT:    [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> [[TMP1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
142; AVX2-NEXT:    [[TMP4:%.*]] = icmp slt <16 x i32> [[TMP3]], zeroinitializer
143; AVX2-NEXT:    [[TMP5:%.*]] = bitcast <16 x i1> [[TMP4]] to i16
144; AVX2-NEXT:    [[OR:%.*]] = zext i16 [[TMP5]] to i64
145; AVX2-NEXT:    ret i64 [[OR]]
146;
147; AVX512-LABEL: @movmsk_i64_v32i32_v4i32(
148; AVX512-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> [[V0:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
149; AVX512-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V3:%.*]], <4 x i32> [[V2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
150; AVX512-NEXT:    [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> [[TMP1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
151; AVX512-NEXT:    [[TMP4:%.*]] = icmp slt <16 x i32> [[TMP3]], zeroinitializer
152; AVX512-NEXT:    [[TMP5:%.*]] = bitcast <16 x i1> [[TMP4]] to i16
153; AVX512-NEXT:    [[OR:%.*]] = zext i16 [[TMP5]] to i64
154; AVX512-NEXT:    ret i64 [[OR]]
155;
156  %c0 = icmp slt <4 x i32> %v0, zeroinitializer
157  %c1 = icmp slt <4 x i32> %v1, zeroinitializer
158  %c2 = icmp slt <4 x i32> %v2, zeroinitializer
159  %c3 = icmp slt <4 x i32> %v3, zeroinitializer
160  %b0 = bitcast <4 x i1> %c0 to i4
161  %b1 = bitcast <4 x i1> %c1 to i4
162  %b2 = bitcast <4 x i1> %c2 to i4
163  %b3 = bitcast <4 x i1> %c3 to i4
164  %z0 = zext i4 %b0 to i64
165  %z1 = zext i4 %b1 to i64
166  %z2 = zext i4 %b2 to i64
167  %z3 = zext i4 %b3 to i64
168  %s0 = shl nuw i64 %z0, 12
169  %s1 = shl nuw i64 %z1, 8
170  %s2 = shl nuw i64 %z2, 4
171  %or0 = or disjoint i64 %s0, %s1
172  %or1 = or disjoint i64 %s2, %z3
173  %or = or disjoint i64 %or0, %or1
174  ret i64 %or
175}
176
177define i64 @movmsk_i64_v64i8_v32i8(<32 x i8> %v0, <32 x i8> %v1) {
178; CHECK-LABEL: @movmsk_i64_v64i8_v32i8(
179; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[V1:%.*]], <32 x i8> [[V0:%.*]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
180; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <64 x i8> [[TMP1]], zeroinitializer
181; CHECK-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP2]] to i64
182; CHECK-NEXT:    ret i64 [[OR]]
183;
184  %c0 = icmp slt <32 x i8> %v0, zeroinitializer
185  %c1 = icmp slt <32 x i8> %v1, zeroinitializer
186  %b0 = bitcast <32 x i1> %c0 to i32
187  %b1 = bitcast <32 x i1> %c1 to i32
188  %z0 = zext i32 %b0 to i64
189  %z1 = zext i32 %b1 to i64
190  %s0 = shl nuw i64 %z0, 32
191  %or = or disjoint i64 %s0, %z1
192  ret i64 %or
193}
194
195define i32 @movmsk_i32_v16i32_v8i32(<8 x i32> %v0, <8 x i32> %v1) {
196; CHECK-LABEL: @movmsk_i32_v16i32_v8i32(
197; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[V1:%.*]], <8 x i32> [[V0:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
198; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <16 x i32> [[TMP1]], zeroinitializer
199; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i1> [[TMP2]] to i16
200; CHECK-NEXT:    [[OR:%.*]] = zext i16 [[TMP3]] to i32
201; CHECK-NEXT:    ret i32 [[OR]]
202;
203  %c0 = icmp slt <8 x i32> %v0, zeroinitializer
204  %c1 = icmp slt <8 x i32> %v1, zeroinitializer
205  %b0 = bitcast <8 x i1> %c0 to i8
206  %b1 = bitcast <8 x i1> %c1 to i8
207  %z0 = zext i8 %b0 to i32
208  %z1 = zext i8 %b1 to i32
209  %s0 = shl nuw i32 %z0, 8
210  %or = or disjoint i32 %s0, %z1
211  ret i32 %or
212}
213
214define i64 @PR111431(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) {
215; SSE-LABEL: @PR111431(
216; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> [[A0]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
217; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <32 x i8> [[A2:%.*]], <32 x i8> [[A1:%.*]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
218; SSE-NEXT:    [[TMP3:%.*]] = icmp eq <64 x i8> [[TMP1]], [[TMP2]]
219; SSE-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP3]] to i64
220; SSE-NEXT:    ret i64 [[OR]]
221;
222; AVX2-LABEL: @PR111431(
223; AVX2-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> [[A0]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
224; AVX2-NEXT:    [[TMP2:%.*]] = shufflevector <32 x i8> [[A2:%.*]], <32 x i8> [[A1:%.*]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
225; AVX2-NEXT:    [[TMP3:%.*]] = icmp eq <64 x i8> [[TMP1]], [[TMP2]]
226; AVX2-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP3]] to i64
227; AVX2-NEXT:    ret i64 [[OR]]
228;
229; AVX512-LABEL: @PR111431(
230; AVX512-NEXT:    [[C01:%.*]] = icmp eq <32 x i8> [[A0:%.*]], [[A1:%.*]]
231; AVX512-NEXT:    [[C02:%.*]] = icmp eq <32 x i8> [[A0]], [[A2:%.*]]
232; AVX512-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i1> [[C02]], <32 x i1> [[C01]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
233; AVX512-NEXT:    [[OR:%.*]] = bitcast <64 x i1> [[TMP1]] to i64
234; AVX512-NEXT:    ret i64 [[OR]]
235;
236  %c01 = icmp eq <32 x i8> %a0, %a1
237  %c02 = icmp eq <32 x i8> %a0, %a2
238  %b01 = bitcast <32 x i1> %c01 to i32
239  %b02 = bitcast <32 x i1> %c02 to i32
240  %z01 = zext i32 %b01 to i64
241  %z02 = zext i32 %b02 to i64
242  %shl = shl nuw i64 %z01, 32
243  %or = or disjoint i64 %shl, %z02
244  ret i64 %or
245}
246