1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt < %s -passes=vector-combine -S -mtriple=riscv32 -mattr=+v | FileCheck %s 3; RUN: opt < %s -passes=vector-combine -S -mtriple=riscv64 -mattr=+v | FileCheck %s 4 5define void @fixed_load_scalable_src(ptr %p) { 6; CHECK-LABEL: define void @fixed_load_scalable_src( 7; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { 8; CHECK-NEXT: entry: 9; CHECK-NEXT: store <vscale x 4 x i16> zeroinitializer, ptr [[P]], align 8 10; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[P]], align 8 11; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison> 12; CHECK-NEXT: ret void 13; 14entry: 15 store <vscale x 4 x i16> zeroinitializer, ptr %p 16 %0 = load <4 x i16>, ptr %p 17 %1 = shufflevector <4 x i16> %0, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison> 18 ret void 19} 20