1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s 3 4define i32 @test1(i32 %x) nounwind { 5; CHECK-LABEL: @test1( 6; CHECK-NEXT: common.ret: 7; CHECK-NEXT: [[I:%.*]] = shl i32 [[X:%.*]], 1 8; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I]], 24 9; CHECK-NEXT: [[DOT:%.*]] = select i1 [[COND]], i32 5, i32 0 10; CHECK-NEXT: ret i32 [[DOT]] 11; 12 %i = shl i32 %x, 1 13 switch i32 %i, label %a [ 14 i32 21, label %b 15 i32 24, label %c 16 ] 17 18a: 19 ret i32 0 20b: 21 ret i32 3 22c: 23 ret i32 5 24} 25 26 27define i32 @test2(i32 %x) nounwind { 28; CHECK-LABEL: @test2( 29; CHECK-NEXT: a: 30; CHECK-NEXT: ret i32 0 31; 32 %i = shl i32 %x, 1 33 switch i32 %i, label %a [ 34 i32 21, label %b 35 i32 23, label %c 36 ] 37 38a: 39 ret i32 0 40b: 41 ret i32 3 42c: 43 ret i32 5 44} 45 46; We're sign extending an 8-bit value. 47; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead. 48 49define i1 @repeated_signbits(i8 %condition) { 50; CHECK-LABEL: @repeated_signbits( 51; CHECK-NEXT: entry: 52; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32 53; CHECK-NEXT: switch i32 [[SEXT]], label [[DEFAULT:%.*]] [ 54; CHECK-NEXT: i32 0, label [[COMMON_RET:%.*]] 55; CHECK-NEXT: i32 127, label [[COMMON_RET]] 56; CHECK-NEXT: i32 -128, label [[COMMON_RET]] 57; CHECK-NEXT: i32 -1, label [[COMMON_RET]] 58; CHECK-NEXT: ] 59; CHECK: common.ret: 60; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ] 61; CHECK-NEXT: ret i1 [[COMMON_RET_OP]] 62; CHECK: default: 63; CHECK-NEXT: br label [[COMMON_RET]] 64; 65entry: 66 %sext = sext i8 %condition to i32 67 switch i32 %sext, label %default [ 68 i32 -2147483648, label %a 69 i32 -129, label %a 70 i32 -128, label %a 71 i32 -1, label %a 72 i32 0, label %a 73 i32 127, label %a 74 i32 128, label %a 75 i32 2147483647, label %a 76 ] 77 78a: 79 ret i1 1 80 81default: 82 ret i1 0 83} 84 85