xref: /llvm-project/llvm/test/Transforms/SimplifyCFG/speculate-vector-insert-extract.ll (revision d1d129356909af2f6fefd6f1b9335a39fe172e9a) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=simplifycfg -S | FileCheck %s
3
4declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64 immarg)
5declare <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64 immarg)
6
7define <vscale x 4 x i32> @speculate_vector_insert(i32 %c, <4 x i32> %v1, <4 x i32> %v2) {
8; CHECK-LABEL: @speculate_vector_insert(
9; CHECK-NEXT:  entry:
10; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[C:%.*]], 0
11; CHECK-NEXT:    [[T1:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> [[V1:%.*]], i64 0)
12; CHECK-NEXT:    [[T2:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> [[V2:%.*]], i64 0)
13; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], <vscale x 4 x i32> [[T2]], <vscale x 4 x i32> [[T1]]
14; CHECK-NEXT:    ret <vscale x 4 x i32> [[COND]]
15;
16entry:
17  %tobool = icmp eq i32 %c, 0
18  br i1 %tobool, label %cond.else, label %cond.then
19
20cond.then:                                        ; preds = %entry
21  %t1 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> %v1, i64 0)
22  br label %cond.end
23
24cond.else:                                        ; preds = %entry
25  %t2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> %v2, i64 0)
26  br label %cond.end
27
28cond.end:                                         ; preds = %cond.else, %cond.then
29  %cond = phi <vscale x 4 x i32> [ %t1, %cond.then ], [ %t2, %cond.else ]
30  br label %return
31
32return:                                           ; preds = %cond.end
33  ret <vscale x 4 x i32> %cond
34}
35
36define <4 x i32> @speculate_vector_extract(i32 %c, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2) {
37; CHECK-LABEL: @speculate_vector_extract(
38; CHECK-NEXT:  entry:
39; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[C:%.*]], 0
40; CHECK-NEXT:    [[T1:%.*]] = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[V1:%.*]], i64 0)
41; CHECK-NEXT:    [[T2:%.*]] = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[V2:%.*]], i64 0)
42; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], <4 x i32> [[T2]], <4 x i32> [[T1]]
43; CHECK-NEXT:    ret <4 x i32> [[COND]]
44;
45entry:
46  %tobool = icmp eq i32 %c, 0
47  br i1 %tobool, label %cond.else, label %cond.then
48
49cond.then:                                        ; preds = %entry
50  %t1 = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %v1, i64 0)
51  br label %cond.end
52
53cond.else:                                        ; preds = %entry
54  %t2 = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %v2, i64 0)
55  br label %cond.end
56
57cond.end:                                         ; preds = %cond.else, %cond.then
58  %cond = phi <4 x i32> [ %t1, %cond.then ], [ %t2, %cond.else ]
59  br label %return
60
61return:                                           ; preds = %cond.end
62  ret <4 x i32> %cond
63}
64