xref: /llvm-project/llvm/test/Transforms/SimpleLoopUnswitch/pr60736.ll (revision c270aafb182c61123daa55ab53794af7f4ff9757)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -simple-loop-unswitch-inject-invariant-conditions=true -passes='loop(simple-loop-unswitch<nontrivial>,loop-instsimplify)' -S | FileCheck %s
3
4define void @test() {
5; CHECK-LABEL: @test(
6; CHECK-NEXT:  bb:
7; CHECK-NEXT:    [[TMP:%.*]] = call i1 @llvm.experimental.widenable.condition()
8; CHECK-NEXT:    [[TMP1:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8
9; CHECK-NEXT:    [[TMP2:%.*]] = load atomic i32, ptr addrspace(1) poison unordered, align 8
10; CHECK-NEXT:    br i1 [[TMP]], label [[BB_SPLIT:%.*]], label [[BB3_SPLIT_US:%.*]]
11; CHECK:       bb.split:
12; CHECK-NEXT:    br label [[BB3:%.*]]
13; CHECK:       bb3:
14; CHECK-NEXT:    br label [[BB3_SPLIT:%.*]]
15; CHECK:       bb3.split.us:
16; CHECK-NEXT:    br label [[BB4_US:%.*]]
17; CHECK:       bb4.us:
18; CHECK-NEXT:    [[TMP5_US:%.*]] = phi i32 [ poison, [[BB3_SPLIT_US]] ]
19; CHECK-NEXT:    [[TMP6_US:%.*]] = phi i32 [ poison, [[BB3_SPLIT_US]] ]
20; CHECK-NEXT:    [[TMP7_US:%.*]] = add nuw nsw i32 [[TMP6_US]], 2
21; CHECK-NEXT:    [[TMP8_US:%.*]] = icmp ult i32 [[TMP7_US]], [[TMP2]]
22; CHECK-NEXT:    br i1 [[TMP8_US]], label [[BB9_US:%.*]], label [[BB16_SPLIT_US:%.*]], !prof [[PROF0:![0-9]+]]
23; CHECK:       bb9.us:
24; CHECK-NEXT:    br label [[BB17_SPLIT_US:%.*]]
25; CHECK:       bb16.split.us:
26; CHECK-NEXT:    br label [[BB16:%.*]]
27; CHECK:       bb17.split.us:
28; CHECK-NEXT:    br label [[BB17:%.*]]
29; CHECK:       bb3.split:
30; CHECK-NEXT:    br label [[BB4:%.*]]
31; CHECK:       bb4:
32; CHECK-NEXT:    [[TMP5:%.*]] = phi i32 [ poison, [[BB3_SPLIT]] ], [ [[TMP14:%.*]], [[BB13:%.*]] ]
33; CHECK-NEXT:    [[TMP6:%.*]] = phi i32 [ poison, [[BB3_SPLIT]] ], [ [[TMP5]], [[BB13]] ]
34; CHECK-NEXT:    [[TMP7:%.*]] = add nuw nsw i32 [[TMP6]], 2
35; CHECK-NEXT:    [[TMP8:%.*]] = icmp ult i32 [[TMP7]], [[TMP2]]
36; CHECK-NEXT:    br i1 [[TMP8]], label [[BB9:%.*]], label [[BB16_SPLIT:%.*]], !prof [[PROF0]]
37; CHECK:       bb9:
38; CHECK-NEXT:    [[TMP10:%.*]] = icmp ult i32 [[TMP7]], [[TMP1]]
39; CHECK-NEXT:    br i1 [[TMP10]], label [[BB12:%.*]], label [[BB17_SPLIT:%.*]], !prof [[PROF0]]
40; CHECK:       bb12:
41; CHECK-NEXT:    br i1 true, label [[BB15:%.*]], label [[BB13]]
42; CHECK:       bb13:
43; CHECK-NEXT:    [[TMP14]] = add nuw nsw i32 [[TMP5]], 1
44; CHECK-NEXT:    br label [[BB4]]
45; CHECK:       bb15:
46; CHECK-NEXT:    br label [[BB3]]
47; CHECK:       bb16.split:
48; CHECK-NEXT:    br label [[BB16]]
49; CHECK:       bb16:
50; CHECK-NEXT:    ret void
51; CHECK:       bb17.split:
52; CHECK-NEXT:    br label [[BB17]]
53; CHECK:       bb17:
54; CHECK-NEXT:    ret void
55;
56bb:
57  %tmp = call i1 @llvm.experimental.widenable.condition()
58  %tmp1 = load atomic i32, ptr addrspace(1) poison unordered, align 8
59  %tmp2 = load atomic i32, ptr addrspace(1) poison unordered, align 8
60  br label %bb3
61
62bb3:                                              ; preds = %bb15, %bb
63  br label %bb4
64
65bb4:                                              ; preds = %bb13, %bb3
66  %tmp5 = phi i32 [ poison, %bb3 ], [ %tmp14, %bb13 ]
67  %tmp6 = phi i32 [ poison, %bb3 ], [ %tmp5, %bb13 ]
68  %tmp7 = add nuw nsw i32 %tmp6, 2
69  %tmp8 = icmp ult i32 %tmp7, %tmp2
70  br i1 %tmp8, label %bb9, label %bb16, !prof !0
71
72bb9:                                              ; preds = %bb4
73  %tmp10 = icmp ult i32 %tmp7, %tmp1
74  %tmp11 = and i1 %tmp10, %tmp
75  br i1 %tmp11, label %bb12, label %bb17, !prof !0
76
77bb12:                                             ; preds = %bb9
78  br i1 poison, label %bb15, label %bb13
79
80bb13:                                             ; preds = %bb12
81  %tmp14 = add nuw nsw i32 %tmp5, 1
82  br label %bb4
83
84bb15:                                             ; preds = %bb12
85  br label %bb3
86
87bb16:                                             ; preds = %bb4
88  ret void
89
90bb17:                                             ; preds = %bb9
91  ret void
92}
93
94; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite)
95declare i1 @llvm.experimental.widenable.condition()
96
97!0 = !{!"branch_weights", i32 1048576, i32 1}
98
99