1*c7d65e44SPaul Walker; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2*c7d65e44SPaul Walker; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s 3*c7d65e44SPaul Walker; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s 4*c7d65e44SPaul Walker 5*c7d65e44SPaul Walker; This test checks that SROA runs mem2reg on arrays of scalable vectors. 6*c7d65e44SPaul Walker 7*c7d65e44SPaul Walkerdefine [ 2 x <vscale x 4 x i32> ] @alloca(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 8*c7d65e44SPaul Walker; CHECK-LABEL: define [2 x <vscale x 4 x i32>] @alloca 9*c7d65e44SPaul Walker; CHECK-SAME: (<vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> [[Y:%.*]]) { 10*c7d65e44SPaul Walker; CHECK-NEXT: [[AGG0:%.*]] = insertvalue [2 x <vscale x 4 x i32>] poison, <vscale x 4 x i32> [[X]], 0 11*c7d65e44SPaul Walker; CHECK-NEXT: [[AGG1:%.*]] = insertvalue [2 x <vscale x 4 x i32>] [[AGG0]], <vscale x 4 x i32> [[Y]], 1 12*c7d65e44SPaul Walker; CHECK-NEXT: ret [2 x <vscale x 4 x i32>] [[AGG1]] 13*c7d65e44SPaul Walker; 14*c7d65e44SPaul Walker %addr = alloca [ 2 x <vscale x 4 x i32> ], align 4 15*c7d65e44SPaul Walker %agg0 = insertvalue [ 2 x <vscale x 4 x i32> ] poison, <vscale x 4 x i32> %x, 0 16*c7d65e44SPaul Walker %agg1 = insertvalue [ 2 x <vscale x 4 x i32> ] %agg0, <vscale x 4 x i32> %y, 1 17*c7d65e44SPaul Walker store [ 2 x <vscale x 4 x i32> ] %agg1, ptr %addr, align 4 18*c7d65e44SPaul Walker %val = load [ 2 x <vscale x 4 x i32> ], ptr %addr, align 4 19*c7d65e44SPaul Walker ret [ 2 x <vscale x 4 x i32> ] %val 20*c7d65e44SPaul Walker} 21