1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s 3; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s 4 5; This test checks that SROA runs mem2reg on arrays of scalable vectors. 6 7define [ 2 x <vscale x 4 x i32> ] @alloca(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) { 8; CHECK-LABEL: define [2 x <vscale x 4 x i32>] @alloca 9; CHECK-SAME: (<vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> [[Y:%.*]]) { 10; CHECK-NEXT: [[AGG0:%.*]] = insertvalue [2 x <vscale x 4 x i32>] poison, <vscale x 4 x i32> [[X]], 0 11; CHECK-NEXT: [[AGG1:%.*]] = insertvalue [2 x <vscale x 4 x i32>] [[AGG0]], <vscale x 4 x i32> [[Y]], 1 12; CHECK-NEXT: ret [2 x <vscale x 4 x i32>] [[AGG1]] 13; 14 %addr = alloca [ 2 x <vscale x 4 x i32> ], align 4 15 %agg0 = insertvalue [ 2 x <vscale x 4 x i32> ] poison, <vscale x 4 x i32> %x, 0 16 %agg1 = insertvalue [ 2 x <vscale x 4 x i32> ] %agg0, <vscale x 4 x i32> %y, 1 17 store [ 2 x <vscale x 4 x i32> ] %agg1, ptr %addr, align 4 18 %val = load [ 2 x <vscale x 4 x i32> ], ptr %addr, align 4 19 ret [ 2 x <vscale x 4 x i32> ] %val 20} 21